DS90CP22 [NSC]
2X2 800 Mbps LVDS Crosspoint Switch; 2X2 800Mbps的LVDS交叉点开关
| 型号： | DS90CP22 |
| 厂家： | 
National Semiconductor |
| 描述： | 2X2 800 Mbps LVDS Crosspoint Switch |
| 文件： | 总10页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2003
DS90CP22
2X2 800 Mbps LVDS Crosspoint Switch
General Description
Features
n Low jitter 800 Mbps fully differential data path
n 75 ps (typ) of pk-pk jitter with PRBS = 223−1 data
pattern at 800 Mbps
DS90CP22 is a 2x2 crosspoint switch utilizing LVDS (Low
Voltage Differential Signaling) technology for low power, high
speed operation. Data paths are fully differential from input
to output for low noise generation and low pulse width dis-
tortion. The non-blocking design allows connection of any
input to any output or outputs. LVDS I/O enable high speed
data transmission for point-to-point interconnects. This de-
vice can be used as a high speed differential crosspoint, 2:1
mux, 1:2 demux, repeater or 1:2 signal splitter. The mux and
demux functions are useful for switching between primary
and backup circuits in fault tolerant systems. The 1:2 signal
splitter and 2:1 mux functions are useful for distribution of
serial bus across several rack-mounted backplanes.
n Single +3.3 V Supply
n Less than 330 mW (typ) total power dissipation
n Non-blocking "’Switch Architecture"’
n Balanced output impedance
n Output channel-to-channel skew is 35 ps (typ)
n Configurable as 2:1 mux, 1:2 demux, repeater or 1:2
signal splitter
n LVDS receiver inputs accept LVPECL signals
n Fast switch time of 1.2ns (typ)
n Fast propagation delay of 1.3ns (typ)
The DS90CP22 accepts LVDS signal levels, LVPECL levels
directly or PECL with attenuation networks.
<
n Receiver input threshold
100 mV
n Available in 16 lead TSSOP and SOIC packages
n Inter-operates with ANSI/TIA/EIA-644-1995 LVDS
standard
The individual LVDS outputs can be put into TRI-STATE by
use of the enable pins.
For more details, please refer to the Application Information
section of this datasheet.
n Operating Temperature: −40˚C to +85˚C
Connection Diagrams
10105305
Order Number DS90CP22M-8 (SOIC)
Order Number DS90CP22MT (TSSOP)
10105310
@
Diff. Output Eye-Pattern in 1:2 split mode 800 Mbps
Conditions: 3.3 V, PRBS = 223−1 data pattern,
VID = 300mV, VCM = +1.2 V, 200 ps/div, 100 mV/div
© 2003 National Semiconductor Corporation
DS101053
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Maximum Package Power Dissipation at 25˚C
16L SOIC
1.435 W
16L SOIC Package Derating
16L TSSOP
11.48 mW/˚C above +25˚C
0.866 W
Supply Voltage (VCC
)
−0.3V to +4V
16L TSSOP Package Derating
ESD Rating:
9.6 mW/˚C above +25˚C
CMOS/TTL Input Voltage (EN0,
EN1, SEL0, SEL1)
−0.3V to (VCC + 0.3V)
>
(HBM, 1.5kΩ, 100pF)
(EIAJ, 0Ω, 200pF)
5 kV
LVDS Receiver Input Voltage
(IN+, IN−)
>
250 V
−0.3V to +4V
LVDS Driver Output Voltage
(OUT+, OUT−)
Recommended Operating
Conditions
−0.3V to +4V
Continuous
LVDS Output Short Circuit
Current
Min Typ Max Units
Junction Temperature
Storage Temperature Range
Lead Temperature
+150˚C
Supply Voltage (VCC
)
3.0 3.3 3.6
VCC
V
V
−65˚C to +150˚C
Receiver Input Voltage
0
Operating Free Air Temperature
-40 +25 +85 ˚C
(Soldering, 4 sec.)
+260˚C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS (EN0,EN1,SEL0,SEL1)
VIH
VIL
IIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Clamp Voltage
2.0
VCC
0.8
V
V
GND
VIN = 3.6V or 2.0V; VCC = 3.6V
VIN = 0V or 0.8V; VCC = 3.6V
ICL = −18 mA
+7
1
+20
10
µA
µA
V
IIL
VCL
−0.8
−1.5
LVDS OUTPUT DC SPECIFICATIONS (OUT0,OUT1)
VOD
Differential Output Voltage
RL = 75Ω
270
285
365
365
475
440
35
mV
mV
mV
V
RL = 75Ω, VCC = 3.3V, TA = 25˚C
∆VOD
VOS
Change in VOD between Complimentary Output States
Offset Voltage (Note 3)
1.0
1.2
1
1.45
35
∆VOS
IOZ
Change in VOS between Complimentary Output States
Output TRI-STATE® Current
mV
µA
TRI-STATE Output,
10
VOUT = VCC or GND
IOFF
IOS
Power-Off Leakage Current
Output Short Circuit Current
Both Outputs Short Circuit Current
VCC = 0V; VOUT = 3.6V or GND
VOUT+ OR VOUT− = 0V
VOUT+ AND VOUT− = 0V
1
−15
−30
10
−25
−50
µA
mA
mA
IOSB
LVDS RECEIVER DC SPECIFICATIONS (IN0,IN1)
VTH
VTL
VCMR
IIN
Differential Input High Threshold
Differential Input Low Threshold
Common Mode Voltage Range
Input Current
VCM = +0.05V or +1.2V or +3.25V,
Vcc = 3.3V
0
0
+100
mV
mV
V
−100
0.05
VID = 100mV, Vcc = 3.3V
VIN = +3.0V, VCC = 3.6V or 0V
VIN = 0V, VCC = 3.6V or 0V
3.25
10
1
1
µA
µA
10
SUPPLY CURRENT
ICCD Total Supply Current
RL = 75Ω, CL = 5 pF,
EN0 = EN1 = High
EN0 = EN1 = Low
98
43
125
55
mA
mA
ICCZ
TRI-STATE Supply Current
Note 1: “Absolute Maximum Ratings” are these beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2: All typical are given for V
= +3.3V and T = +25˚C, unless otherwise stated.
A
CC
Note 3: V
is defined and measured on the ATE as (V
+ V ) / 2.
OH OL
OS
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2
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified (Note 4)
Symbol
TSET
Parameter
Conditions
Min
Typ
Max
Units
Input to SEL Setup Time, Figures 1, 2
(Note 5)
0.7
0.5
ns
THOLD
Input to SEL Hold Time, Figures 1, 2
(Note 5)
1.0
0.9
0.5
ns
TSWITCH
TPHZ
TPLZ
SEL to Switched Output, Figures 1, 2
Disable Time (Active to TRI-STATE) High to Z, Figure 3
Disable Time (Active to TRI-STATE) Low to Z, Figure 3
Enable Time (TRI-STATE to Active) Z to High, Figure 3
Enable Time (TRI-STATE to Active) Z to Low, Figure 3
1.2
2.1
1.7
4.0
ns
ns
ns
ns
ns
ps
ps
ps
3.0
4.5
TPZH
TPZL
25.5
25.5
400
400
40
55.0
55.0
580
580
90
TLHT
THLT
TJIT
Output Low-to-High Transition Time, 20% to 80%, Figure 5
Output High-to-Low Transition Time, 80% to 20%, Figure 5
290
290
LVDS Data Path Peak to Peak Jitter,
(Note 6)
VID = 300mV; 50% Duty Cycle;
VCM = 1.2V at 800Mbps
VID = 300mV; PRBS=223-1 data
75
190
ps
pattern; VCM = 1.2V at 800Mbps
TPLHD
TPHLD
Propagation Low to High Delay, Figure 6
0.9
1.0
0.9
1.0
1.3
1.3
1.3
1.3
0
1.6
1.5
1.6
1.5
225
80
ns
ns
ns
ns
ps
ps
Propagation Low to High Delay, Figure 6 VCC = 3.3V, TA = 25˚C
Propagation High to Low Delay, Figure 6
Propagation High to Low Delay, Figure 6 VCC = 3.3V, TA = 25˚C
TSKEW
TCCS
Pulse Skew |TPLHD - TPHLD
|
Output Channel-to-Channel Skew, Figure 7
35
Note 4: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage and
temperature) range.
Note 5: T
and T
time specify that data must be in a stable state before and after the SEL transition.
HOLD
SET
Note 6: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT range with the following
equipment test setup: HP70004A (display mainframe) with HP70841B (pattern generator), 5 feet of RG-142 cable with DUT test board and HP83480A (digital scope
mainframe) with HP83483A (20GHz scope module).
3
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AC Timing Diagrams
10105302
FIGURE 1. Input-to-Select rising edge setup and hold times and mux switch time
10105303
FIGURE 2. Input-to-Select falling edge setup and hold times and mux switch time
10105304
FIGURE 3. Output active to TRI-STATE and TRI-STATE to active output time
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4
AC Timing Diagrams (Continued)
10105306
FIGURE 4. LVDS Output Load
10105309
FIGURE 5. LVDS Output Transition Time
10105307
FIGURE 6. Propagation Delay Low-to-High and High-to-Low
10105308
FIGURE 7. Output Channel-to-Channel Skew in 1:2 splitter mode
5
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DS90CP22 Pin Description
Pin Name
IN+
# of Pin
Input/Output
Description
Non-inverting LVDS input
2
2
2
2
2
I
I
IN -
Inverting LVDS input
OUT+
OUT -
EN
O
O
I
Non-inverting LVDS Output
Inverting LVDS Output
A logic low on the Enable puts the LVDS output into
TRI-STATE and reduces the supply current
2:1 mux input select
SEL
GND
VCC
NC
2
1
1
2
I
P
P
Ground
Power Supply
No Connect
PCB LAYOUT AND POWER SYSTEM BYPASS
Application Information
Circuit board layout and stack-up for the DS90CP22 should
be designed to provide noise-free power to the device. Good
layout practice also will separate high frequency or high level
inputs and outputs to minimize unwanted stray noise pickup,
feedback and interference. Power system performance may
be greatly improved by using thin dielectrics (4 to 10 mils) for
power/ground sandwiches. This increases the intrinsic ca-
pacitance of the PCB power system which improves power
supply filtering, especially at high frequencies, and makes
the value and placement of external bypass capacitors less
critical. External bypass capacitors should include both RF
ceramic and tantalum electrolytic types. RF capacitors may
use values in the range 0.01 µF to 0.1 µF. It is recommended
practice to use two vias at each power pin of the DS90CP22
as well as all RF bypass capacitor terminals. Dual vias
reduce the interconnect inductance by up to half, thereby
reducing interconnect inductance and extending the effec-
tive frequency range of the bypass components.
MODES OF OPERATION
The DS90CP22 provides three modes of operation. In the
1:2 splitter mode, the two outputs are copies of the same
single input. This is useful for distribution / fan-out applica-
tions. In the repeater mode, the device operates as a 2
channel LVDS buffer. Repeating the signal restores the
LVDS amplitude, allowing it to drive another media segment.
This allows for isolation of segments or long distance appli-
cations. The switch mode provides a crosspoint function.
This can be used in a system when primary and redundant
paths are supported in fault tolerant applications.
INPUT FAIL-SAFE
The receiver inputs of the DS90CP22 do not have internal
fail-safe biasing. For point-to-point and multidrop applica-
tions with a single source, fail-safe biasing may not be
required. When the driver is off, the link is in-active. If fail-
safe biasing is required, this can be accomplished with ex-
ternal high value resistors. The IN+ should be pull to Vcc with
10kΩ and the IN− should be pull to Gnd with 10kΩ. This
provides a slight positive differential bias, and sets a known
HIGH state on the link with a minimum amount of distortion.
The outer layers of the PCB may be flooded with additional
ground plane. These planes will improve shielding and iso-
lation as well as increase the intrinsic capacitance of the
power supply plane system. Naturally, to be effective, these
planes must be tied to the ground supply plane at frequent
intervals with vias. Frequent via placement also improves
signal integrity on signal transmission lines by providing
short paths for image currents which reduces signal distor-
tion.
UNUSED LVDS INPUTS
Unused LVDS Receiver inputs should be tied off to prevent
the high-speed sensitive input stage from picking up noise
signals. The open input to IN+ should be pull to Vcc with
10kΩ and the open input to IN− should be pull to Gnd with
10kΩ.
There are more common practices which should be followed
when designing PCBs for LVDS signaling. Please see Appli-
cation Note: AN-1108 for additional information.
COMPATIBILITY WITH LVDS STANDARD
UNUSED CONTROL INPUTS
The DS90CP22 is compatible with LVDS and Bus LVDS
Interface devices. It is enhanced over standard LVDS drivers
in that it is able to driver lower impedance loads with stan-
dard LVDS levels. Standard LVDS drivers provide 330mV
differential output with a 100Ω load. The DS90CP22 pro-
vides 365mV with a 75Ω load or 400mV with 100Ω loads.
This extra drive capability is useful in certain multidrop ap-
plications.
The SEL and EN control input pins have internal pull down
devices. Unused pins may be tied off or left as no-connect (if
a LOW state is desired).
EXPANDING THE NUMBER OF OUTPUT PORTS
To expand the number of output ports, more than one
DS90CP22 can be used. Total propagation delay through the
devices should be considered to determine the maximum
expansion. For example, if 2 X 4 is desired, than three of the
DS90CP22 are required. A minimum of two device propaga-
tion delays (2 x 1.3ns = 2.6ns (typ)) can be achieved. For a
2 X 8, a total of 7 devices must be used with propagation
delay of 3 x 1.3ns = 3.9ns (typ). The power consumption will
increase proportional to the number of devices used.
In backplane multidrop configurations, with closely spaced
loads, the effective differential impedance of the line is re-
duced. If the mainline has been designed for 100Ω differen-
tial impedance, the loading effects may reduce this to the
70Ω range depending upon spacing and capacitance load.
Terminating the line with a 75Ω load is a better match than
with 100Ω and reflections are reduced.
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6
Block Diagram
10105301
Function Table
SEL0
SEL1
OUT0
IN0
OUT1
IN0
Mode
0
0
1
1
0
1
0
1
1:2 splitter
repeater
switch
IN0
IN1
IN1
IN0
IN1
IN1
1:2 splitter
Note: 0 = low, 1 = high
EN0 = EN1 = 1 for enable
Typical Performance Characteristics
Diff. Output Voltage (VOD) vs. Resistive Load (RT)
10105311
7
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Typical Performance Characteristics (Continued)
Peak-to-Peak Output Jitter at VCM = +0.4V vs. VID
10105312
Peak-to-Peak Output Jitter at VCM = +1.2V vs. VID
10105313
Peak-to-Peak Output Jitter at VCM = +1.6V vs. VID
10105314
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8
Physical Dimensions inches (millimeters)
unless otherwise noted
Order Number DS90CP22M-8
See NS Package Number M16A
16-Lead (4.4mm Wide) Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90CP22MT
Order Number DS90CP22MTX (Tape and Reel)
See NS Package Number MTC16
9
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