DS90CR213 [NSC]
21-Bit Channel LinkΑ66 MHz; 21位通道链接-66 MHz的
| 型号： | DS90CR213 |
| 厂家： | 
National Semiconductor |
| 描述： | 21-Bit Channel LinkΑ66 MHz |
| 文件： | 总14页 (文件大小：267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1997
DS90CR213/DS90CR214
21-Bit Channel Link—66 MHz
width, which provides a system cost savings, reduces con-
nector physical size and cost, and reduces shielding require-
ments due to the cable’s smaller form factor.
General Description
The DS90CR213 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CR214 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 66 MHz, 21 bits of TTL data are
transmitted at a rate of 462 Mbps per LVDS data channel.
Using a 66 MHz clock, the data throughput is 1.386 Gbit/s
(173 Mbytes/s).
The 21 CMOS/TTL inputs can support a variety of signal
combinations. For example, 5 4-bit nibbles (byte + parity) or
2 9-bit (byte + 3 parity) and 1 control.
Features
n 66 MHz Clock Support
n Up to 173 Mbytes/s bandwidth
<
n Low power CMOS design ( 610 mW)
<
n Power-down mode ( 0.5 mW total)
The multiplexing of the data lines provides a substantial
cable reduction. Long distance parallel single-ended buses
typically require a ground wire per active signal (and have
very limited noise rejection capability). Thus, for a 21-bit wide
data and one clock, up to 44 conductors are required. With
the Channel Link chipset as few as 9 conductors (3 data
pairs, 1 clock pair and a minimum of one ground) are
needed. This provides an 80% reduction in required cable
n Up to 1.386 Gbit/s data throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 48-lead TSSOP package
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS Standard
Block Diagrams
DS90CR213
DS90CR214
DS012888-27
DS012888-1
Order Number DS90CR213MTD
See NS Package Number MTD48
Order Number DS90CR214MTD
See NS Package Number MTD48
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS012888
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Pin Diagrams
DS90CR213
DS90CR214
DS012888-21
DS012888-22
Typical Application
DS012888-23
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Package Derating:
DS90CR213
16 mW/˚C above +25˚C
15 mW/˚C above +25˚C
DS90CR214
ESD Rating (Note 4)
This device does not meet 2000V
Supply Voltage (VCC
)
−0.3V to +6V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
Recommended Operating
Conditions
Min Nom Max
Units
LVDS Output Short Circuit
Duration
Supply Voltage (VCC
Operating Free Air
Temperature (TA)
)
4.75 5.0
5.25
V
Continuous
+150˚C
Junction Temperature
Storage Temperature
−10 +25
0
+70
2.4
˚C
V
−65˚C to +150˚C
Receiver Input Range
Lead Temperature
(Soldering, 4 sec)
Supply Noise Voltage (VCC
)
100 mVP-P
+260˚C
Maximum Package Power
Dissipation Capacity
@
25˚C
MTD48 (TSSOP) Package:
DS90CR213
DS90CR214
1.98W
1.89W
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Clamp Voltage
2.0
GND
3.8
VCC
V
V
0.8
=
VOH
VOL
VCL
IIN
IOH −0.4 mA
4.9
0.1
V
=
IOL 2 mA
0.3
V
=
ICL −18 mA
−0.79
−1.5
V
=
±
±
10
Input Current
VIN VCC, GND, 2.5V or 0.4V
5.1
µA
mA
=
IOS
Output Short Circuit Current
VOUT 0V
−120
LVDS DRIVER DC SPECIFICATIONS
=
VOD
Differential Output Voltage
RL 100Ω
250
1.1
290
450
35
mV
mV
∆VOD
Change in VOD between
Complimentary Output States
VOS
Offset Voltage
1.25
1.375
35
V
∆VOS
Change in Magnitude of VOS
between Complimentary Output
States
mV
=
=
100Ω
IOS
IOZ
Output Short Circuit Current
Output TRI-STATE® Current
VOUT 0V, R
−2.9
−5
mA
µA
L
=
=
±
±
10
Powerdown 0V, VOUT 0V or VCC
1
LVDS RECEIVER DC SPECIFICATIONS
=
VTH
VTL
IIN
Differential Input High Threshold
Differential Input Low Threshold
Input Current
VCM +1.2V
+100
mV
mV
µA
−100
=
=
±
±
VIN +2.4V, VCC 5.0V
10
10
=
=
VIN 0V, VCC 5.0V
µA
TRANSMITTER SUPPLY CURRENT
=
=
=
=
=
ICCTW
Transmitter Supply Current
Worst Case
RL 100Ω, C
5 pF,
f
f
f
32.5 MHz
37.5 MHz
66 MHz
49
51
70
63
mA
mA
mA
L
Worst Case Pattern
64
84
(Figure 1 and Figure 2 )
=
Powerdown Low
ICCTZ
Transmitter Supply Current
Power Down
Driver Outputs in TRI-STATE under
Powerdown Mode
1
25
µA
3
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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RECEIVER SUPPLY CURRENT
=
=
=
=
ICCRW
Receiver Supply Current
Worst Case
CL 8 pF,
f
f
f
32.5 MHz
37.5 MHz
66 MHz
64
70
77
85
mA
mA
mA
Worst Case Pattern
(Figure 1 and Figure 3 )
110
140
=
Powerdown Low
ICCRZ
Receiver Supply Current
Power Down
Receiver Outputs in Previous State during
Power Down Mode.
1
10
µA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
=
=
+25˚C.
Note 2: Typical values are given for V
CC
5.0V and T
A
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V and ∆V ).
OD
OD
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)
PLL V ≥ 1000V
CC
All Other Pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V
Note 5:
V
previously referred as V .
CM
OS
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
Parameter
LVDS Low-to-High Transition Time (Figure 2 )
LVDS High-to-Low Transition Time (Figure 2 )
TxCLK IN Transition Time (Figure 4 )
Min
Typ
0.75
0.75
Max
1.5
Units
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
LHLT
1.5
TCIT
8
TCCS
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TCIP
TxOUT Channel-to-Channel Skew (Note 6) (Figure 5)
Transmitter Output Pulse Position for Bit 0 (Figure 16 )
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxCLK IN Period (Figure 6 )
350
−0.30
1.70
3.60
5.90
8.30
10.40
12.70
15
0
0.30
2.50
4.50
6.75
9.00
11.10
13.40
50
(1/7)Tclk
(2/7)Tclk
(3/7)Tclk
(4/7)Tclk
(5/7)Tclk
(6/7)Tclk
T
=
f
66 MHz
TCIH
TxCLK IN High Time (Figure 6 )
0.35T
0.35T
5
0.5T
0.65T
0.65T
TCIL
TxCLK IN Low Time (Figure 6 )
0.5T
TSTC
TxIN Setup to TxCLK IN (Figure 6 )
3.5
THTC
TxIN Hold to TxCLK IN (Figure 6 )
2.5
1.5
=
@
TCCD
TPLLS
TPDD
TxCLK IN to TxCLK OUT Delay 25˚C, VCC 5.0V (Figure 8 )
Transmitter Phase Lock Loop Set (Figure 10 )
Transmitter Powerdown Delay (Figure 14 )
3.5
8.5
10
100
Note 6: This limit based on bench characterization.
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 3 )
CMOS/TTL High-to-Low Transition Time (Figure 3 )
Min
Typ
2.5
2.0
Max
4.0
Units
ns
CHLT
4.0
ns
=
=
=
=
RSKM
RxIN Skew Margin (Note 7) V
5V,TA 25˚C(Figure 17)
f
f
40 MHz
66 MHz
700
600
ps
CC
ps
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Receiver Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
RCOP
Parameter
Min
15
Typ
Max
Units
ns
RxCLK OUT Period (Figure 7 )
T
50
=
=
=
=
=
=
=
=
RCOH
RxCLK OUT High Time (Figure 7 )
RxCLK OUT Low Time (Figure 7 )
RxOUT Setup to RxCLK OUT (Figure 7 )
RxOUT Hold to RxCLK OUT (Figure 7 )
f
f
f
f
f
f
f
f
40 MHz
66 MHz
40 MHz
66 MHz
40 MHz
66 MHz
40 MHz
66 MHz
6
ns
4.3
10.5
7.0
4.5
2.5
6.5
4
5
ns
RCOL
RSRC
RHRC
ns
9
ns
ns
4.2
5.2
ns
ns
ns
=
@
RCCD
RPLLS
RPDD
RxCLK IN to RxCLK OUT Delay 25˚C, VCC 5.0V (Figure 9 )
6.4
10.7
10
1
ns
Receiver Phase Lock Loop Set (Figure 11 )
ms
µs
Receiver Powerdown Delay (Figure 15 )
Note 7: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
DS012888-2
FIGURE 1. “Worst Case” Test Pattern
DS012888-3
DS012888-4
FIGURE 2. DS90CR213 (Transmitter) LVDS Output Load and Transition Times
DS012888-5
DS012888-6
FIGURE 3. DS90CR214 (Receiver) CMOS/TTL Output Load and Transition Times
5
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AC Timing Diagrams (Continued)
DS012888-7
FIGURE 4. DS90CR213 (Transmitter) Input Clock Transition Time
DS012888-8
=
Note 8: Measurements at V
0V
diff
Note 9: TCSS measured between earliest and latest LVDS edges.
→
Note 10: TxCLK Differential Low High Edge
FIGURE 5. DS90CR213 (Transmitter) Channel-to-Channel Skew
DS012888-9
FIGURE 6. DS90CR213 (Transmitter) Setup/Hold and High/Low Times
DS012888-10
FIGURE 7. DS90CR214 (Receiver) Setup/Hold and High/Low Times
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AC Timing Diagrams (Continued)
DS012888-11
FIGURE 8. DS90CR213 (Transmitter) Clock In to Clock Out Delay
DS012888-12
FIGURE 9. DS90CR214 (Receiver) Clock In to Clock Out Delay
DS012888-13
FIGURE 10. DS90CR213 (Transmitter) Phase Lock Loop Set Time
DS012888-14
FIGURE 11. DS90CR214 (Receiver) Phase Lock Loop Set Time
7
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AC Timing Diagrams (Continued)
DS012888-15
FIGURE 12. Seven Bits of LVDS in Once Clock Cycle
DS012888-16
FIGURE 13. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR283)
DS012888-17
FIGURE 14. Transmitter Powerdown Delay
DS012888-18
FIGURE 15. Receiver Powerdown Delay
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AC Timing Diagrams (Continued)
DS012888-19
FIGURE 16. Transmitter LVDS Output Pulse Position Measurement
DS012888-20
SW—Setup and Hold Time (Internal Data Sampling Window)
TCCS—Transmitter Output Skew
RSKM ≥ Cable Skew (Type, Length) + Source Clock Jitter (Cycle to Cycle)
Cable Skew—Typically 10 ps–40 ps per foot
FIGURE 17. Receiver LVDS Input Skew Margin
DS90CR213 Pin Description—Channel Link Transmitter
Pin Name
TxIN
I/O
I
No.
21
3
Description
TTL level inputs.
TxOUT+
O
O
I
Positive LVDS differential data output.
Negative LVDS differentiaI data output.
TxOUT−
3
TxCLK IN
1
TTL level clock input. The rising edge acts as data strobe.
Positive LVDS differential clock output.
TxCLK OUT+
TxCLK OUT−
PWR DOWN
O
O
I
1
1
Negative LVDS differential clock output.
1
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down.
VCC
I
I
4
5
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
GND
9
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DS90CR213 Pin Description—Channel Link Transmitter (Continued)
Pin Name
PLL VCC
I/O
No.
1
Description
I
I
I
I
Power supply pin for PLL.
Ground pins for PLL.
PLL GND
LVDS VCC
LVDS GND
2
1
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
3
DS90CR214 Pin Description—Channel Link Receiver
Pin Name
RxIN+
I/O
No.
3
Description
I
I
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
TTL level outputs.
RxIN−
3
RxOUT
O
I
21
1
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
VCC
Positive LVDS differential clock input.
Negative LVDS differentiaI clock input.
I
1
O
I
1
TTL level clock output. The rising edge acts as data strobe.
TTL Ievel input. Locks the previous receiver output state.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
1
I
4
GND
I
5
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I
1
Power supply for PLL.
I
2
Ground pin for PLL.
I
1
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
I
3
Applications Information
@
The Channel Link devices are intended to be used in a wide
variety of data transmission applications. Depending upon
the application the interconnecting media may vary. For ex-
ample, for lower data rate (clock rate) and shorter cable
recommended that cable skew remain below 350 ps ( 66
MHz clock rate) to maintain a sufficient data sampling win-
dow at the receiver.
In addition to the four or five cable pairs that carry data and
clock, it is recommended to provide at least one additional
conductor (or pair) which connects ground between the
transmitter and receiver. This low impedance ground pro-
vides a common mode return path for the two devices. Some
of the more commonly used cable types for point-to-point ap-
plications include flat ribbon, flex, twisted pair and
Twin-Coax. All are available in a variety of configurations and
options. Flat ribbon cable, flex and twisted pair generally per-
form well in short point-to-point applications while Twin-Coax
is good for short and long applications. When using ribbon
cable, it is recommended to place a ground line between
each differential pair to act as a barrier to noise coupling be-
tween adjacent pairs. For Twin-Coax cable applications, it is
recommended to utilize a shield on each cable pair. All ex-
tended point-to-point applications should also employ an
overall shield surrounding all cable pairs regardless of the
cable type. This overall shield results in improved transmis-
sion parameters such as faster attainable speeds, longer
distances between transmitter and receiver and reduced
problems associated with EMS or EMI.
<
lengths ( 2m), the media electrical performance is less criti-
cal. For higher speed/long distance applications the media’s
performance becomes more critical. Certain cable construc-
tions provide tighter skew (matched electrical length be-
tween the conductors and pairs). Twin-coax for example, has
been demonstrated at distances as great as 5 meters and
with the maximum data transfer of 1.38 Gbit/s. Additional ap-
plications information can be found in the following National
Interface Application Notes:
=
AN ####
Topic
AN-1041
AN-1035
Introduction to Channel Link
PCB Design Guidelines for LVDS and
Link Devices
AN-806
AN-905
Transmission Line Theory
Transmission Line Calculations and
Differential Impedance
AN-916
Cable Information
CABLES: A cable interface between the transmitter and re-
ceiver needs to support the differential LVDS pairs. The
21-bit CHANNEL LINK chipset (DS90CR213/214) requires
four pairs of signal wires and the 28-bit CHANNEL LINK
chipset (DS90CR283/284) requires five pairs of signal wires.
The ideal cable/connector interface would have a constant
100Ω differential impedance throughout the path. It is also
The high-speed transport of LVDS signals has been demon-
strated on several types of cables with excellent results.
However, the best overall performance has been seen when
using Twin-Coax cable. Twin-Coax has very low cable skew
and EMI due to its construction and double shielding. All of
the design considerations discussed here and listed in the
supplemental application notes provide the subsystem com-
munications designer with many useful guidelines. It is rec-
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TERMINATION: Use of current mode drivers requires a ter-
minating resistor across the receiver inputs. The CHANNEL
LINK chipset will normally require a single 100Ω resistor be-
tween the true and complement lines on each differential
pair of the receiver input. The actual value of the termination
resistor should be selected to match the differential mode
characteristic impedance (90Ω to 120Ω typical) of the cable.
Figure 18 shows an example. No additional pull-up or
pull-down resistors are necessary as with some other differ-
ential technologies such as PECL. Surface mount resistors
are recommended to avoid the additional inductance that ac-
companies leaded resistors. These resistors should be
placed as close as possible to the receiver input pins to re-
duce stubs and effectively terminate the differential lines.
Applications Information (Continued)
ommended that the designer assess the tradeoffs of each
application thoroughly to arrive at a reliable and economical
cable solution.
BOARD LAYOUT: To obtain the maximum benefit from the
noise and EMI reductions of LVDS, attention should be paid
to the layout of differential lines. Lines of a differential pair
should always be adjacent to eliminate noise interference
from other signals and take full advantage of the noise can-
celing of the differential signals. The board designer should
also try to maintain equal length on signal traces for a given
differential pair. As with any high speed design, the imped-
ance discontinuities should be limited (reduce the numbers
of vias and no 90 degree angles on traces). Any discontinui-
ties which do occur on one signal line should be mirrored in
the other line of the differential pair. Care should be taken to
ensure that the differential trace impedance match the differ-
ential impedance of the selected physical media (this imped-
ance should also match the value of the termination resistor
that is connected across the differential pair at the receiver’s
input). Finally, the location of the CHANNEL LINK TxOUT/
RxIN pins should be as close as possible to the board edge
so as to eliminate excessive pcb runs. All of these consider-
ations will limit reflections and crosstalk which adversely ef-
fect high frequency performance and EMI.
DECOUPLING CAPACITORS: Bypassing capacitors are
needed to reduce the impact of switching noise which could
limit performance. For
a conservative approach three
parallel-connected decoupling capacitors (Multi-Layered Ce-
ramic type in surface mount form factor) between each VCC
and the ground plane(s) are recommended. The three ca-
pacitor values are 0.1 µF, 0.01µF and 0.001 µF. An example
is shown in Figure 19. The designer should employ wide
traces for power and ground and ensure each capacitor has
its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL VCC should receive
the most filtering/bypassing. Next would be the LVDS VCC
pins and finally the logic VCC pins.
UNUSED INPUTS: All unused inputs at the TxIN inputs of
the transmitter must be tied to ground. All unused outputs at
the RxOUT outputs of the receiver must then be left floating.
DS012888-24
FIGURE 18. LVDS Serialized Link Termination
width of 2.16 ns. Differential skew (∆t within one differential
pair), interconnect skew (∆t of one differential pair to an-
other) and clock jitter will all reduce the available window for
sampling the LVDS serial data streams. Care must be taken
to ensure that the clock input to the transmitter be a clean
low noise signal. Individual bypassing of each VCC to ground
will minimize the noise passed on to the PLL, thus creating a
low jitter LVDS clock. These measures provide more margin
for channel-to-channel skew and interconnect skew as a part
of the overall jitter/skew budget.
COMMON MODE vs. DIFFERENTIAL MODE NOISE MAR-
GIN: The typical signal swing for LVDS is 300 mV centered
at +1.2V. The CHANNEL LINK receiver supports a 100 mV
threshold therefore providing approximately 200 mV of differ-
ential noise margin. Common mode protection is of more im-
portance to the system’s operation due to the differential
data transmission. LVDS supports an input voltage range of
DS012888-25
FIGURE 19. CHANNEL LINK
Decoupling Configuration
CLOCK JITTER: The CHANNEL LINK devices employ a
PLL to generate and recover the clock transmitted across the
LVDS interface. The width of each bit in the serialized LVDS
data stream is one-seventh the clock period. For example, a
66 MHz clock has a period of 15 ns which results in a data bit
±
Ground to +2.4V. This allows for a 1.0V shifting of the cen-
ter point due to ground potential differences and common
mode noise.
11
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11
The CHANNEL LINK chipset is designed to protect itself
from accidental loss of power to either the transmitter or re-
ceiver. If power to the transmit board is lost, the receiver
clocks (input and output) stop. The data outputs (RxOUT) re-
tain the states they were in when the clocks stopped. When
the receiver board loses power, the receiver inputs are
Applications Information (Continued)
POWER SEQUENCING AND POWERDOWN MODE: Out-
puts of the CHANNEL LINK transmitter remain in TRI-STATE
until the power supply reaches 3V. Clock and data outputs
will begin to toggle 10 ms after VCC has reached 4.5V and
the Powerdown pin is above 2V. Either device may be placed
into a powerdown mode at any time by asserting the Power-
down pin (active low). Total power dissipation for each de-
vice will decrease to 5 µW (typical).
shorted to V
through an internal diode. Current is limited
CC
(5 mA per input) by the fixed current mode drivers, thus
avoiding the potential for latchup when powering the device.
DS012888-26
FIGURE 20. Single-Ended and Differential Waveforms
Book
Extract
End
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THIS PAGE IS IGNORED IN THE DATABOOK
13
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Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Molded Thin Shrink Small Outline Package, JEDEC
NS Package Number MTD48
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
Email: sea.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
PrintDate=1998/01/07 PrintTime=09:53:22 28561 ds012888 Rev. No. 5 cmserv Proof
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