DS90UB903QSQ_技术文档

January 14, 2011

DS90UB903Q/DS90UB904Q

10 - 43MHz 18 Bit Color FPD-Link III Serializer and

Deserializer with Bidirectional Control Channel

Single differential pair interconnect

Bidirectional control interface channel with I²C support

■

General Description

The DS90UB903Q/DS90UB904Q chipset offers a FPD-Link

III interface with a high-speed forward channel and a bidirec-

tional control channel for data transmission over a single

differential pair. The DS90UB903Q/904Q incorporates differ-

ential signaling on both the high-speed forward channel and

bidirectional control channel data paths. The Serializer/ De-

serializer pair is targeted for direct connections between

graphics host controller and displays modules. This chipset is

ideally suited for driving video data to displays requiring 18-

bit color depth (RGB666 + HS, VS, and DE) along with

bidirectional control channel bus. The primary transport con-

verts 21 bit data over a single high-speed serial stream, along

with a separate low latency bidirectional control channel

transport that accepts control information from an I²C port.

Using National’s embedded clock technology allows trans-

parent full-duplex communication over a single differential

pair, carrying asymmetrical bidirectional control channel in-

formation in both directions. This single serial stream simpli-

fies transferring a wide data bus over PCB traces and cable

by eliminating the skew problems between parallel data and

clock paths. This significantly saves system cost by narrowing

data paths that in turn reduce PCB layers, cable width, and

connector size and pins.

Embedded clock with DC Balanced coding to support AC-

coupled interconnects

Capable to drive up to 10 meters shielded twisted-pair

I²C compatible serial interface

■

Single hardware device addressing pin

Up to 4 General Purpose Input (GPI)/ Output (GPO)

LOCK output reporting pin and AT-SPEED BIST diagnosis

feature to validate link integrity

Integrated termination resistors

■

1.8V- or 3.3V-compatible parallel bus interface

Single power supply at 1.8V

ISO 10605 ESD and IEC 61000-4-2 ESD compliant

Automotive grade product: AEC-Q100 Grade 2 qualified

Temperature range −40°C to +105°C

No reference clock required on Deserializer

Programmable Receive Equalization

EMI/EMC Mitigation

DES Programmable Spread Spectrum (SSCG)

outputs

—

DES Receiver staggered outputs

—

In addition, the Deserializer inputs provide equalization con-

trol to compensate for loss from the media over longer dis-

tances. Internal DC balanced encoding/decoding is used to

support AC-Coupled interconnects.

Applications

Automotive Display Systems

■

The Serializer is offered in a 40-pin lead in LLP and Deseri-

alizer is offered in a 48-pin LLP packages.

Central Information Displays

Navigation Displays

—

Rear Seat Entertainment

Touch Screen Displays

Features

10 MHz to 43 MHz input PCLK support

■

210 Mbps to 903 Mbps data throughput

Typical Application Diagram

30125427

FIGURE 1. Typical Application Circuit

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

301254

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Block Diagrams

30125428

FIGURE 2. Block Diagram

30125429

FIGURE 3. Application Block Diagram

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2

Ordering Information

NSID

DS90UB903QSQE

Package Description

Quantity

250

SPEC

NOPB

Package ID

SQA40A

SQA48A

40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch

48-pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch

DS90UB903QSQ

DS90UB903QSQX

DS90UB904QSQE

DS90UB904QSQ

DS90UB904QSQX

1000

4500

250

1000

4500

Note: Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market,

including defect detection methodologies. Reliability qualification is compliant with the requirements and temperature grades

defined in the AEC Q100 standard. Automotive Grade products are identified with the letter Q. For more information go to

http://www.national.com/automotive.

DS90UB903Q Pin Diagram

30125419

Serializer - DS90UB903Q — Top View

3

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DS90UB903Q Serializer Pin Descriptions

Pin Name

Pin No.

I/O, Type

Description

LVCMOS PARALLEL INTERFACE

DIN[20:0]

5, 4, 3, 2, 1, Inputs, LVCMOS Parallel data inputs.

40, 39, 38, 37,

36, 35, 33, 32,

30, 29, 28, 27,

26, 25, 24, 23

w/ pull down

PCLK

6

Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register.

w/ pull down

GENERAL PURPOSE OUTPUT (GPO)

GPO[3:0]

22, 21, 20, 19

Output,

LVCMOS

General-purpose output pins can be used to control and respond to various

commands.

BIDIRECTIONAL CONTROL BUS - I²C COMPATIBLE

Clock line for the bidirectional control bus communication

SCL requires an external pull-up resistor to V_DDIO

Data line for the bidirectional control bus communication

Input/Output,

Open Drain

SCL

SDA

7

8

.

Input/Output,

Open Drain

SDA requires an external pull-up resistor to V_DDIO

I²C Mode select

.

MODE = L, Master mode (default); Device generates and drives the SCL clock line.

Device is connected to slave peripheral on the bus. (Serializer initially starts up in

Standby mode and is enabled through remote wakeup by Deserializer)

MODE = H, Slave mode; Device accepts SCL clock input and attached to an I²C

controller master on the bus. Slave mode does not generate the SCL clock, but

uses the clock generated by the Master for the data transfers.

Input, LVCMOS

w/ pull down

MODE

12

Device ID Address Select

ID[x]

9

Input, analog

Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 3

CONTROL AND CONFIGURATION

Power down Mode Input Pin.

PDB = H, Serializer is enabled and is ON.

Input, LVCMOS

w/ pull down

PDB

RES

13

PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,

the PLL is shutdown, and IDD is minimized. Programmed control register data are

NOT retained and reset to default values

Input, LVCMOS Reserved.

10, 11

w/ pull down

This pin MUST be tied LOW.

FPD-LINK III INTERFACE

Input/Output, Non-inverting differential output, bidirectional control channel input. The

DOUT+

DOUT-

17

16

CML

Input/Output, Inverting differential output, bidirectional control channel input. The interconnect

CML must be AC Coupled with a 100 nF capacitor.

interconnect must be AC Coupled with a 100 nF capacitor.

POWER AND GROUND

VDDPLL

VDDT

14

Power, Analog PLL Power, 1.8V ±5%

15

18

34

Power, Analog Tx Analog Power, 1.8V ±5%

Power, Analog CML & Bidirectional Channel Driver Power, 1.8V ±5%

Power, Digital Digital Power, 1.8V ±5%

VDDCML

VDDD

Power, Digital Power for I/O stage. The single-ended inputs and SDA, SCL are powered from

V_DDIO. V_DDIOcan be connected to a 1.8V ±5% or 3.3V ±10%

VDDIO

31

Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located

at the center of the LLP package. Connected to the ground plane (GND) with at

least 16 vias.

VSS

DAP

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DS90UB904Q Pin Diagram

30125420

Deserializer - DS90UB904Q — Top View

5

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DS90UB904Q Deserializer Pin Descriptions

Pin Name

Pin No.

I/O, Type

Description

LVCMOS PARALLEL INTERFACE

ROUT[20:0]

5, 6, 8, 9, 10,

11, 12, 13, 14,

15, 16, 18, 19,

21, 22, 23, 24,

25, 26, 27, 28

Outputs,

LVCMOS

Parallel data outputs.

Output,

LVCMOS

Pixel Clock Output Pin.

Strobe edge set by RRFB control register.

PCLK

4

GENERAL PURPOSE INPUT (GPI)

General-purpose input pins can be used to control and respond to various

commands.

GPI[3:0]

30, 31, 32, 33 Input, LVCMOS

BIDIRECTIONAL CONTROL BUS - I²C COMPATIBLE

Clock line for the bidirectional control bus communication

SCL requires an external pull-up resistor to V_DDIO

Data line for bidirectional control bus communication

Input/Output,

Open Drain

SCL

SDA

2

1

.

Input/Output,

Open Drain

SDA requires an external pull-up resistor to V_DDIO

I²C Mode select

.

MODE = L, Master mode; Device generates and drives the SCL clock line, where

Input, LVCMOS required such as Read. Device is connected to slave peripheral on the bus.

MODE

47

w/ pull up

MODE = H, Slave mode (default); Device accepts SCL clock input and attached to

an I²C controller master on the bus. Slave mode does not generate the SCL clock,

but uses the clock generated by the Master for the data transfers.

Device ID Address Select

ID[x]

48

Input, analog

Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 4

CONTROL AND CONFIGURATION

Power down Mode Input Pin.

PDB = H, Deserializer is enabled and is ON.

PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power

Down. Programmed control register data are NOT retained and reset to default

values.

Input, LVCMOS

w/ pull down

PDB

35

LOCK Status Output Pin.

Output,

LVCMOS

LOCK = H, PLL is Locked, outputs are active

LOCK

RES

34

LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by

OSS_SEL control register. May be used as Link Status.

Reserved.

Pin 46: This pin MUST be tied LOW.

Pin 43: Leave pin open.

38, 39, 43, 46

-

Pins 38, 39: Route to test point or leave open if unused.

BIST MODE

BIST Enable Pin.

Input, LVCMOS

w/ pull down

BISTEN

44

37

BISTEN = H, BIST Mode is enabled.

BISTEN = L, BIST Mode is disabled.

PASS Output Pin for BIST mode.

PASS = H, ERROR FREE Transmission

PASS = L, one or more errors were detected in the received payload.

Leave Open if unused. Route to test point (pad) recommended.

Output,

LVCOMS

PASS

FPD-LINK III INTERFACE

Input/Output, Noninverting differential input, bidirectional control channel output. The

CML interconnect must be AC Coupled with a 100 nF capacitor.

Input/Output, Inverting differential input, bidirectional control channel output. The interconnect

RIN+

RIN-

41

42

CML

must be AC Coupled with a 100 nF capacitor.

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Pin Name

Pin No.

I/O, Type

Description

POWER AND GROUND

SSCG Power, 1.8V ±5%

Power supply must be connected regardless if SSCG function is in operation.

VDDSSCG

VDDIO1/2/3

3

Power, Digital

LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered

from V_DDIO. V_DDIOcan be connected to a 1.8V ±5% or 3.3V ±10%

29, 20, 7

VDDD

17

36

40

45

Power, Digital Digital Core Power, 1.8V ±5%

Power, Analog Rx Analog Power, 1.8V ±5%

Power, Analog Bidirectional Channel Driver Power, 1.8V ±5%

Power, Analog PLL Power, 1.8V ±5%

VDDR

VDDCML

VDDPLL

DAP must be grounded. DAP is the large metal contact at the bottom side, located

VSS

DAP

Ground, DAP at the center of the LLP package. Connected to the ground plane (GND) with at

least 16 vias.

7

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ESD Rating (ISO10605)

R_D= 330Ω, C_S= 150/330pF

R_D= 2KΩ, C_S= 150/330pF

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Air Discharge

(DOUT+, DOUT-, RIN+, RIN-)

≥±15 kV

Contact Discharge

(DOUT+, DOUT-, RIN+, RIN-)

ESD Rating (HBM)

Supply Voltage – V_DDn(1.8V)

Supply Voltage – V_DDIO

−0.3V to +2.5V

−0.3V to +4.0V

≥±10 kV

≥±8 kV

LVCMOS Input Voltage I/O

Voltage

−0.3V to + (VDDIO + 0.3V)

−0.3V to +(V_DD+ 0.3V)

For soldering specifications:

see product folder at www.national.com and

www.national.com/ms/MS/MS-SOLDERING.pdf

CML Driver I/O Voltage (V_DD

)

CML Receiver I/O Voltage

(V_DD

)

−0.3V to (V_DD+ 0.3V)

+150°C

Junction Temperature

Storage Temperature

Maximum Package Power

Recommended Operating

Conditions

−65°C to +150°C

1/θ_JA°C/W above +25°

Min

Nom

Max

Units

Dissipation Capacity Package

Supply Voltage

(V_DDn

LVCMOS Supply

1.71

1.8

1.89

V

Package Derating:

DS90UB903Q 40L LLP

)

30.7 °C/W

6.8 °C/W

1.71

3.0

1.8

3.3

1.89

3.6

V

ꢀ θ_JA

Voltage (V_DDIO

)

(based on 16 thermal vias)

OR

ꢀθ_JC

LVCMOS Supply

(based on 16 thermal vias)

DS90UB904Q 48L LLP

ꢀθ_JA

Voltage (V_DDIO

Supply Noise

V_DDn(1.8V)

)

26.9 °C/W

4.4 °C/W

25

50

mVp-p

(based on 16 thermal vias)

V_DDIO(1.8V)

V_DDIO(3.3V)

ꢀθ_JC

(based on 16 thermal vias)

ESD Rating (IEC 61000-4-2)

Operating Free Air

Temperature (T_A)

-40

10

+25

+105

43

°C

R_D= 330Ω, C_S= 150pF

≥±25 kV

Air Discharge

(DOUT+, DOUT-, RIN+, RIN-)

Contact Discharge

(DOUT+, DOUT-, RIN+, RIN-)

PCLK Clock

Frequency

MHz

≥±10 kV

Electrical Characteristics (Note 2, Note 3, Note 4)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min

Typ

Max

Units

LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)

V_IH

V_IL

I_IN

High Level Input Voltage

Low Level Input Voltage

Input Current

V_IN= 3.0V to 3.6V

V_IN

0.8

2.0

V

GND

V_IN= 0V or 3.6V

-20

2.4

±1

+20

V_DDIO

0.4

µA

V

V_IN= 3.0V to 3.6V

V_OH

V_OL

High Level Output Voltage

Low Level Output Voltage

V_DDIO= 3.0V to 3.6V

I_OH= +4 mA

GND

V

I_OS

Output Short Circuit Current V_OUT= 0V

Serializer

GPO Outputs

-24

-39

±1

mA

µA

Deserializer

LVCMOS Outputs

PDB = 0V,

I_OZ

TRI-STATE® Output Current

LVCMOS Outputs

-20

+20

V_OUT= 0V or V_DD

LVCMOS DC SPECIFICATIONS 1.8V I/O (SER INPUTS, DES OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)

V_IH

V_IL

I_IN

High Level Input Voltage

Low Level Input Voltage

Input Current

V_IN= 1.71V to 1.89V

0.65 V_IN

GND

V_IN+0.3

0.35 V_IN

V

V_IN= 0V or 1.89V

-20

±1

+20

µA

V_IN= 1.71V to 1.89V

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Symbol

Parameter

Conditions

V_DDIO= 1.71V to 1.89V

Min

Typ

Max

Units

V_OH

High Level Output Voltage

V_DDIO

0.45

-

V_DDIO

V

I_OH= −4 mA

V_OL

I_OS

Low Level Output Voltage

V_DDIO= 1.71V to 1.89V

I_OL= +4 mA

Deserializer

LVCMOS Outputs

GND

0.45

V

Output Short Circuit Current V_OUT= 0V

Serializer

GPO Outputs

-11

-20

±1

mA

µA

Deserializer

LVCMOS Outputs

I_OZ

TRI-STATE® Output Current PDB = 0V,

LVCMOS Outputs

-20

+20

V_OUT= 0V or V_DD

CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)

|V_OD

|

Output Differential Voltage

R_T= 100Ω (Figure 7)

R_L= 100Ω

268

340

1

412

50

mV

Output Differential Voltage

Unbalance

ΔV_OD

V_OS

Output Differential Offset

Voltage

V_{DD (MIN)}

-

V_{DD (MAX)}-

R_L= 100Ω

(Figure 7)

V_DD- V_OD

V

V_{OD (MAX)}

V_{OD (MIN)}

Offset Voltage Unbalance

ΔV_OS

I_OS

R_L= 100Ω

1

50

mV

mA

Output Short Circuit Current DOUT+/- = 0V

-27

R_T

Differential Internal

Termination Resistance

Differential across DOUT+ and DOUT-

80

100

120

Ω

CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-)

Differential Threshold High

Voltage

(Figure 8)

V_TH

V_TL

+90

mV

Differential Threshold Low

Voltage

-90

180

-20

80

V_IN

Differential Input Voltage

Range

RIN+ - RIN-

mV

µA

Ω

Input Current

V_IN= V_DDor 0V,

V_DD= 1.89V

I_IN

±1

+20

120

R_T

Differential Internal

Termination Resistance

Differential across RIN+ and RIN-

100

SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD

I_DDT

Serializer (Tx)

VDDn = 1.89V

R_T= 100Ω

VDDn Supply Current

(includes load current)

PCLK = 43 MHz

Default Registers

62

55

2

90

WORST CASE pattern

(Figure 5)

mA

R_T= 100Ω

RANDOM PRBS-7 pattern

I_DDIOT

Serializer (Tx)

VDDIO Supply Current

(includes load current)

VDDIO = 1.89V

PCLK = 43 MHz

Default Registers

R_T= 100Ω

WORST CASE pattern

(Figure 5)

5

mA

µA

VDDIO = 3.6V

PCLK = 43 MHz

Default Registers

7

15

I_DDTZ

Serializer (Tx) Supply Current PDB = 0V; All other

Power-down LVCMOS Inputs = 0V

V_DDn= 1.89V

V_DDIO= 1.89V

V_DDIO= 3.6V

370

55

775

125

135

I_DDIOTZ

65

9

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Symbol

Parameter

Conditions

PCLK = 43 MHz

Min

Typ

Max

Units

I_DDR

Deserializer (Rx) VDDn

Supply Current (includes load

current)

V_DDn= 1.89V

C_L= 8 pF

SSCG[3:0] = ON

Default Registers

60

96

WORST CASE Pattern

(Figure 5)

V_DDn= 1.89V

PCLK = 43 MHz

Default Registers

C_L= 8 pF

53

21

49

RANDOM PRBS-7 Pattern

mA

I_DDIOR

Deserializer (Rx) VDDIO

Supply Current (includes load

current)

V_DDIO= 1.89V

C_L= 8 pF

PCLK = 43 MHz

Default Registers

32

83

WORST CASE Pattern

(Figure 5)

V_DDIO= 3.6V

PCLK = 43 MHz

Default Registers

C_L= 8 pF

WORST CASE Pattern

I_DDRZ

Deserializer (Rx) Supply

Current Power-down

PDB = 0V; All other

LVCMOS Inputs = 0V

V_DDn= 1.89V

V_DDIO= 1.89V

V_DDIO= 3.6V

42

8

400

40

I_DDIORZ

µA

350

800

Recommended Serializer Timing for PCLK (Note 12)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

t_TCP

Parameter

Conditions

10 MHz – 43 MHz

Min

Typ

Max

Units

Transmit Clock Period

23.3

T

100

ns

t_TCIH

t_TCIL

t_CLKT

f_OSC

Transmit Clock Input High

Time

0.4T

0.5T

0.6T

ns

Transmit Clock Input Low

Time

0.4T

0.5

0.5T

25

0.6T

3

ns

PCLK Input Transition Time

(Figure 9)

Internal oscillator clock

source

MHz

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Serializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

t_LHT

Parameter

Conditions

R_L= 100Ω (Figure 6)

Min

Typ

Max

Units

CML Low-to-High

Transition Time

150

330

ps

t_HLT

CML High-to-Low

Transition Time

R_L= 100Ω (Figure 6)

150

330

ps

t_DIS

t_DIH

t_PLD

t_SD

Data Input Setup to PCLK Serializer Data Inputs

2.0

ns

(Figure 10)

Data Input Hold from PCLK

Serializer PLL Lock Time

Serializer Delay

R_L= 100Ω (Note 5, Note 11)

1

2

ms

R_T= 100Ω

6.386T

+ 5

6.386T

+ 12

6.386T

+ 19.7

PCLK = 10–43 MHz

Register 0x03h b[0] (TRFB = 1)

(Figure 12)

ns

UI

t_JIND

Serializer Output

Deterministic Jitter

Serializer output intrinsic deterministic

jitter . Measured (cycle-cycle) with

PRBS-7 test pattern

PCLK = 43 MHz

(Note 4, Note 13)

0.13

0.04

t_JINR

Serializer Output Random Serializer output intrinsic random jitter

Jitter

(cycle-cycle). Alternating-1,0 pattern.

PCLK = 43 MHz

(Note 4, Note 13)

t_JINT

Peak-to-peak Serializer

Output Jitter

Serializer output peak-to-peak jitter

includes deterministic jitter, random

jitter, and jitter transfer from serializer

input. Measured (cycle-cycle) with

PRBS-7 test pattern.

0.396

UI

PCLK = 43 MHz

(Note 4, Note 13)

Serializer Jitter Transfer

Function -3 dB Bandwidth Default Registers

PCLK = 43 MHz

λ_STXBW

1.90

0.944

500

MHz

dB

(Figure 18) (Note 4)

Serializer Jitter Transfer

Function (Peaking)

PCLK = 43 MHz

Default Registers

(Figure 18 ) (Note 4)

δ_STX

Serializer Jitter Transfer

Function (Peaking

Frequency)

PCLK = 43 MHz

Default Registers

(Figure 18) (Note 4)

δ_STXf

kHz

11

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Deserializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

t_RCP

Parameter

Receiver Output Clock Period

PCLK Duty Cycle

Conditions

t_RCP= t_TCP

Pin/Freq.

PCLK

Min

Typ

Max

Units

23.3

T

100

ns

t_PDC

Default Registers

SSCG[3:0] = OFF

45

50

55

%

LVCMOS Low-to-High Transition V_DDIO: 1.71V to 1.89V or PCLK

t_CLH

t_CHL

1.3

2.0

2.8

Time

3.0 to 3.6V,

C_L= 8 pF (lumped load)

Default Registers

(Figure 14) (Note 10)

ns

LVCMOS High-to-Low Transition

Time

1.3

1.6

2.0

2.4

2.8

3.3

LVCMOS Low-to-High Transition V_DDIO: 1.71V to 1.89V or Deserializer ROUTn

t_CLH

t_CHL

Time

Data Outputs

3.0 to 3.6V,

C_L= 8 pF (lumped load)

Default Registers

(Figure 14) (Note 10)

ns

LVCMOS High-to-Low Transition

Time

1.6

2.4

t_ROS

t_ROH

V_DDIO: 1.71V to 1.89V or Deserializer ROUTn

ROUT Setup Data to PCLK

ROUT Hold Data to PCLK

0.38T

0.5T

Data Outputs

3.0V to 3.6V,

ns

C_L= 8 pF (lumped load)

Default Registers

Register 0x03h b[0]

(RRFB = 1)

10 MHz–43 MHz

4.571T

+ 8

4.571T 4.571T

+ 12

t_DD

Deserializer Delay

+ 16

(Figure 15)

t_DDLT

t_RJIT

(Figure 13) (Note 5)

10 MHz–43 MHz

43 MHz

Deserializer Data Lock Time

Receiver Input Jitter Tolerance

10

ms

UI

(Figure 17, Figure 19)

(Note 13, Note 14)

0.53

300

120

425

320

300

t_RCJ

Receiver Clock Jitter

PCLK

SSCG[3:0] = OFF

(Note 6, Note 10)

10 MHz

43 MHz

550

250

600

480

500

ps

t_DPJ

Deserializer Period Jitter

PCLK

SSCG[3:0] = OFF

(Note 7, Note 10)

10 MHz

43 MHz

t_DCCJ

Deserializer Cycle-to-Cycle Clock PCLK

10 MHz

43 MHz

Jitter

SSCG[3:0] = OFF

(Note 8, Note 10)

fdev

Spread Spectrum Clocking

Deviation Frequency

LVCMOS Output Bus

SSC[3:0] = ON

(Figure 20)

20 MHz–43 MHz

±0.5% to

±2.0%

%

fmod

Spread Spectrum Clocking

Modulation Frequency

9 kHz to

66 kHz

kHz

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12

Bidirectional Control Bus AC Timing Specifications (SCL, SDA) - I²C

Compliant (Figure 4)

Over recommended supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

RECOMMENDED INPUT TIMING REQUIREMENTS (Note 12)

f_SCL

SCL Clock Frequency

SCL Low Period

>0

4.7

4.0

100

kHz

µs

t_LOW

t_HIGH

f_SCL= 100 kHz

SCL High Period

µs

Hold time for a start or a repeated start

condition

t_HD:STA

t_SU:STA

4.0

4.7

µs

Set Up time for a start or a repeated

start condition

t_HD:DAT

t_SU:DAT

t_SU:STO

t_r

Data Hold Time

0

3.45

µs

ns

µs

ns

pF

Data Set Up Time

250

4.0

Set Up Time for STOP Condition

SCL & SDA Rise Time

SCL & SDA Fall Time

Capacitive load for bus

1000

300

t_f

C_b

400

SWITCHING CHARACTERISTICS (Note 11)

Serializer MODE = 0 – R/W

Register 0x05 = 0x40'h

100

f_SCL

SCL Clock Frequency

SCL Low Period

kHz

µs

Deserializer MODE = 0 – READ

Register 0x06 b[6:4] = 0x00'h

Serializer MODE = 0 – R/W

Register 0x05 = 0x40'h

t_LOW

4.7

4.0

Deserializer MODE = 0 – READ

Register 0x06 b[6:4] = 0x00'h

Serializer MODE = 0 – R/W

Register 0x05 = 0x40'h

t_HIGH

SCL High Period

µs

Deserializer MODE = 0 – READ

Register 0x06 b[6:4] = 0x00'h

Hold time for a start or a repeated start Serializer MODE = 0

t_HD:STA

t_SU:STA

4.0

4.7

µs

condition

Register 0x05 = 0x40'h

Set Up time for a start or a repeated

start condition

Serializer MODE = 0

Register 0x05 = 0x40'h

t_HD:DAT

t_SU:DAT

t_SU:STO

t_f

Data Hold Time

0

3.45

300

µs

ns

µs

ns

Data Set Up Time

250

4.0

Serializer MODE = 0

Set Up Time for STOP Condition

SCL & SDA Fall Time

Bus free time between a stop and start Serializer MODE = 0

condition

t_BUF

4.7

µs

Serializer MODE = 1

1

t_TIMEOUT

NACK Time out

ms

Deserializer MODE = 1

Register 0x06 b[2:0]=111'b

25

13

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30125436

FIGURE 4. Bidirectional Control Bus Timing

Bidirectional Control Bus DC Characteristics (SCL, SDA) - I²C Compliant

Over recommended supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Input High Level

Conditions

SDA and SCL

Min

Typ

Max

Units

V_IH

V_IL

0.7 x

V_DDIO

V

Input Low Level Voltage

SDA and SCL

0.3 x

V_DDIO

GND

V

V_HY

I_OZ

Input Hysteresis

SDA and SCL

>50

±1

mV

µA

TRI-STATE Output Current PDB = 0V

V_OUT= 0V or V_DD

SDA or SCL,

Vin = V_DDIOor GND

-20

+20

I_IN

Input Current

±1

<5

µA

pF

C_IN

Input Pin Capacitance

V_OL

Low Level Output Voltage SCL and SDA

V_DDIO= 3.0V

0.36

V

I_OL= 1.5 mA

SCL and SDA

V_DDIO= 1.71V

I_OL= 1 mA

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional; the device

should not be operated beyond such conditions.

Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 3: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,

VTH and VTL which are differential voltages.

Note 4: Typical values represent most likely parametric norms at 1.8V or 3.3V, T_A= +25°C, and at the Recommended Operation Conditions at the time of product

characterization and are not guaranteed.

Note 5: t_PLDand t_DDLTis the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK

Note 6: t_DCJis the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).

Note 7: t_DPJis the maximum amount the period is allowed to deviate measured over 30,000 samples.

Note 8: t_DCCJis the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.

Note 9: Supply noise testing was done with minimum capacitors (as shown on Figures 35, 36) on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V)

supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows

no error when the noise frequency on the Ser is less than 1 MHz. The Des on the other hand shows no error when the noise frequency is less than 750 kHz.

Note 10: Specification is guaranteed by characterization and is not tested in production.

Note 11: Specification is guaranteed by design.

Note 12: Recommended Input Timing Requirements are input specifications and not tested in production.

Note 13: UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.

Note 14: t_RJITmax (0.61UI) is limited by instrumentation and actual t_RJITof in-band jitter at low frequency (<2 MHz) is greater 1 UI.

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14

AC Timing Diagrams and Test Circuits

30125452

FIGURE 5. “Worst Case” Test Pattern

30125446

30125447

FIGURE 6. Serializer CML Output Load and Transition Times

15

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30125448

30125430

FIGURE 7. Serializer VOD DC Diagram

30125434

FIGURE 8. Differential VTH/VTL Definition Diagram

30125416

FIGURE 9. Serializer Input Clock Transition Times

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16

30125449

FIGURE 10. Serializer Setup/Hold Times

30125432

FIGURE 11. Serializer Data Lock Time

30125450

FIGURE 12. Serializer Delay

30125413

FIGURE 13. Deserializer Data Lock Time

17

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30125414

FIGURE 14. Deserializer LVCMOS Output Load and Transition Times

30125411

FIGURE 15. Deserializer Delay

30125431

FIGURE 16. Deserializer Output Setup/Hold Times

30125458

FIGURE 17. Receiver Input Jitter Tolerance

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18

30125462

FIGURE 18. Typical Serializer Jitter Transfer Function Curve at 43 MHz

30125459

FIGURE 19. Typical Deserializer Input Jitter Tolerance Curve at 43 MHz

30125435

FIGURE 20. Spread Spectrum Clock Output Profile

19

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TABLE 1. DS90UB903Q Control Registers

Addr

(Hex)

Name

Bits Field

R/W

Default Description

7-bit address of Serializer; 0x58'h

7:1 DEVICE ID

(1011_000X'b) default

I²C Device ID

0

RW

0xB0'h

0: Device ID is from ID[x]

0

SER ID SEL

1: Register I²C Device ID overrides ID[x]

7:3 RESERVED

0x00'h Reserved

Standby mode control. Retains control register data.

Supported only when MODE = 0

2

STANDBY

RW

0

0: Enabled. Low-current Standby mode with wake-up

capability. Suspends all clocks and functions.

1: Disabled. Standby and wake-up disabled

1

2

Reset

1: Resets the device to default register values. Does not

affect device I²C Bus or Device ID

DIGITAL

RESET0

0

1

0

RW

self clear

0

1: Digital Reset, retains all register values

DIGITAL RESET1

self clear

Reserved

7:0 RESERVED

7:6 RESERVED

0x20'h Reserved

11'b

Reserved

Auto V_DDIOdetect

Allows manual setting of VDDIO by register.

0: Disable

1: Enable (auto detect mode)

VDDIO Control

VDDIO Mode

5

4

VDDIO CONTOL

RW

1

VDDIO voltage set

Only used when VDDIOCONTROL = 0

0: 1.8V

1: 3.3V

I²C Pass-Through

0: Disabled

VDDIO MODE

RW

1

I²C Pass-

Through

I²C PASS-

THROUGH

3

2

1

0

3

1: Enabled

RESERVED

Reserved

Switch over to internal 25 MHz Oscillator clock in the

absence of PCLK

0: Disable

1: Enable

PCLK_AUTO

1

PCLK_AUTO

RW

1

Pixel Clock Edge Select:

0: Parallel Interface Data is strobed on the Falling Clock

Edge.

TRFB

0

TRFB

1

1: Parallel Interface Data is strobed on the Rising Clock

Edge.

4

5

RESERVED

I²C Bus Rate

7:0 RESERVED

0x80'h Reserved

I²C SCL frequency is determined by the following:

f_SCL= 6.25 MHz / Register value (in decimal)

0x40'h = ~100 kHz SCL (default)

I²C BUS RATE

7:0

RW

0x40'h

Note: Register values <0x32'h are NOT supported.

0xC0'h Deserializer Device ID = 0x60'h

(1100_000X'b) default

7:1 DES DEV ID

6

7

DES ID

0

RESERVED

7:1 SLAVE DEV ID

RESERVED

Reserved

RW

0x00'h Slave Device ID. Sets remote slave I²C address.

Slave ID

0

Reserved

8

9

A

Reserved

7:0 RESERVED

0x00'h Reserved

0x01'h Reserved

0x00'h Reserved

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20

Addr

(Hex)

Name

Bits Field

R/W

Default Description

B

Reserved

7:0 RESERVED

7:3 RESERVED

0x00'h Reserved

1: Valid PCLK detected

0: Valid PCLK not detected

Reserved

PCLK Detect

2

3

0

PCLK DETECT

RESERVED

R

0

C

Reserved

Cable Link

Detect Status

0: Cable link not detected

1: Cable link detected

LINK DETECT

D

E

Reserved

7:0 RESERVED

GPCR[7]

0x11'h Reserved

0x01'h Reserved

0x03'h Reserved

0: LOW

F

10

11

12

GPCR[6]

1: HIGH

GPCR[5]

GPCR[4]

7:0

General Purpose

Control Reg

13

RW

0x00'h

GPCR[3]

GPCR[2]

GPCR[1]

GPCR[0]

21

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TABLE 2. DS90UB904Q Control Registers

Addr

(Hex)

Name

Bits

Field

R/W

Default

Description

RW

0xC0'h 7-bit address of Deserializer;

0x60h

7:1 DEVICE ID

I²C Device ID

(1100_000X) default

0

0: Device ID is from ID[x]

1: Register I²C Device ID overrides ID[x]

0

DES ID SEL

7:3 RESERVED

0x00'h

0

Reserved

Remote Wake-up Select

1: Enable

Generate remote wakeup signal automatically wake-up

the Serializer in Standby mode

0: Disable

2

REM_WAKEUP

RW

1

Reset

Puts the Serializer in Standby mode

1: Resets the device to default register values. Does not

affect device I²C Bus or Device ID

0

1

0

DIGITALRESET0

DIGITALRESET1

RW

self clear

0

1: Digital Reset, retains all register values

self clear

RESERVED

Auto Clock

7:6 RESERVED

00'b

Reserved

1: Output PCLK or Internal 25 MHz Oscillator clock

0: Only PCLK when valid PCLK present

5

AUTO_CLOCK

RW

0

Output Sleep State Select

0: Outputs = TRI-STATE, when LOCK = L

1: Outputs = LOW , when LOCK = L

OSS Select

4

OSS_SEL

0

SSCG Select

0000: Normal Operation, SSCG OFF (default)

0001: fmod (kHz) PCLK/2168, fdev ±0.50%

0010: fmod (kHz) PCLK/2168, fdev ±1.00%

0011: fmod (kHz) PCLK/2168, fdev ±1.50%

0100: fmod (kHz) PCLK/2168, fdev ±2.00%

0101: fmod (kHz) PCLK/1300, fdev ±0.50%

0110: fmod (kHz) PCLK/1300, fdev ±1.00%

2

SSCG

3:0 SSCG

0000'b 0111: fmod (kHz) PCLK/1300, fdev ±1.50%

1000: fmod (kHz) PCLK/1300, fdev ±2.00%

1001: fmod (kHz) PCLK/868, fdev ±0.50%

1010: fmod (kHz) PCLK/868, fdev ±1.00%

1011: fmod (kHz) PCLK/868, fdev ±1.50%

1100: fmod (kHz) PCLK/868, fdev ±2.00%

1101: fmod (kHz) PCLK/650, fdev ±0.50%

1110: fmod (kHz) PCLK/650, fdev ±1.00%

1111: fmod (kHz) PCLK/650, fdev ±1.50%

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22

Addr

(Hex)

Name

Bits

Field

R/W

Default

Description

RESERVED

7:6 RESERVED

11'b

Reserved

Auto voltage control

0: Disable

1: Enable (auto detect mode)

VDDIO

5

VDDIO Control

VDDIO Mode

RW

1

0

1

CONTROL

VDDIO voltage set

0: 1.8V

1: 3.3V

I²C Pass-Through Mode

0: Disabled

1: Enabled

4

3

VDDIO MODE

I²C PASS-

THROUGH

I²C Pass-Through

RW

3

0: Disable

1: Enable

Auto ACK

2

1

AUTO ACK

RESERVED

0

RESERVED

Reserved

Pixel Clock Edge Select

0: Parallel Interface Data is strobed on the Falling Clock

RRFB

0

RRFB

RW

1

Edge

1: Parallel Interface Data is strobed on the Rising Clock

Edge.

EQ Gain

00'h = ~0.0 dB

01'h = ~4.5 dB

03'h = ~6.5 dB

4

5

EQ Control

7:0 EQ

0x00'h 07'h = ~7.5 dB

0F'h = ~8.0 dB

1F'h = ~11.0 dB

3F'h = ~12.5 dB

FF'h = ~14.0 dB

RESERVED

7:0 RESERVED

0x00'h Reserved

7

RESERVED

0

Reserved

Prescales the SCL clock line when reading data byte

from a slave device (MODE = 0)

000 : ~100 kHz SCL (default)

001 : ~125 kHz SCL

101 : ~11 kHz SCL

110 : ~33 kHz SCL

SCL Prescale

6:4 SCL_PRESCALE

RW

000'b

111 : ~50 kHz SCL

Other values are NOT supported.

Remote NACK Timer Enable

In slave mode (MODE = 1) if bit is set the I²C core will

REM_NACK_TIM

automatically timeout when no acknowledge condition

was detected.

1: Enable

6

Remote NACK

3

1

ER

0: Disable

Remote NACK Timeout.

000: 2.0 ms

001: 5.2 ms

010: 8.6 ms

Remote NACK

2:0 NACK_TIMEOUT

RW

111'b

011: 11.8 ms

100: 14.4 ms

101: 18.4 ms

110: 21.6 ms

111: 25.0 ms

23

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Addr

(Hex)

Name

Bits

Field

R/W

Default

Description

RW

0xB0'h Serializer Device ID = 0x58'h

(1011_000X'b) default

7:1 SER DEV ID

7

SER ID

0

RESERVED

7:1 ID[0] INDEX

RESERVED

7:1 ID[1] INDEX

RESERVED

7:1 ID[2] INDEX

RESERVED

7:1 ID[3] INDEX

RESERVED

7:1 ID[4] INDEX

RESERVED

7:1 ID[5] INDEX

RESERVED

7:1 ID[6] INDEX

RESERVED

7:1 ID[7] INDEX

RESERVED

7:1 ID[0] MATCH

RESERVED

7:1 ID[1] MATCH

RESERVED

7:1 ID[2] MATCH

RESERVED

7:1 ID[3] MATCH

RESERVED

7:1 ID[4] MATCH

RESERVED

7:1 ID[5] MATCH

RESERVED

7:1 ID[6] MATCH

RESERVED

7:1 ID[7] MATCH

RESERVED

Reserved

RW

0x00'h Target slave Device ID slv_id0 [7:1]

Reserved

8

9

ID[0] Index

ID[1] Index

ID[2] Index

ID[3] Index

ID[4] Index

ID[5] Index

ID[6] Index

ID[7] Index

ID[0] Match

ID[1] Match

ID[2] Match

ID[3] Match

ID[4] Match

ID[5] Match

ID[6] Match

ID[7] Match

0

Target slave Device ID slv_id1 [7:1]

RW

0x00'h

0

Reserved

Target slave Device ID slv_id2 [7:1]

A

0x00'h

0

Reserved

Target slave Device ID slv_id3 [7:1]

B

0x00'h

0

Reserved

Target slave Device ID slv_id4 [7:1]

C

0x00'h

0

Reserved

Target slave Device ID slv_id5 [7:1]

D

0x00'h

0

Reserved

Target slave Device ID slv_id6 [7:1]

E

0x00'h

0

Reserved

Target slave Device ID slv_id7 [7:1]

F

0x00'h

0

Reserved

Alias to match Device ID slv_id0 [7:1]

10

11

12

13

14

15

16

17

0x00'h

0

Reserved

Alias to match Device ID slv_id1 [7:1]

0x00'h

0

Reserved

Alias to match Device ID slv_id2 [7:1]

0x00'h

0

Reserved

Alias to match Device ID slv_id3 [7:1]

0x00'h

0

Reserved

Alias to match Device ID slv_id4 [7:1]

0x00'h

0

Reserved

Alias to match Device ID slv_id5 [7:1]

0x00'h

0

Reserved

Alias to match Device ID slv_id6 [7:1]

0x00'h

0

Reserved

Alias to match Device ID slv_id [7:1]

0x00'h

0

Reserved

18

19

1A

1B

RESERVED

7:0 RESERVED

7:3 RESERVED

0x00'h Reserved

0x01'h Reserved

0x00'h Reserved

2

RESERVED

0

Reserved

Signal Detect

Status

0: Active signal not detected

1: Active signal detected

1C

1

R

0

0: CDR/PLL Unlocked

1: CDR/PLL Locked

LOCK Pin Status

0

1D

1E

1F

20

Reserved

7:0 RESERVED

0x17'h Reserved

0x07'h Reserved

0x01'h Reserved

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24

Addr

(Hex)

Name

Bits

Field

R/W

Default

Description

21

22

Reserved

7:0 RESERVED

0x01'h Reserved

GPCR[7]

GPCR[6]

GPCR[5]

0: LOW

1: HIGH

General Purpose

Control Reg

GPCR[4]

GPCR[3]

23

7:0

RW

0x00'h

GPCR[2]

GPCR[1]

GPCR[0]

BIST Enable

24

25

BIST

0

BIST_EN

RW

R

0

0: Normal operation

1: Bist Enable

0x00'h Bist Error Counter

BIST_ERR

7:0 BIST_ERR

11: Enable remote wake up mode

00: Normal operation mode

Other values are NOT supported

REM_WAKEUP_

EN

7:6

RW

00'b

0

Remote Wake

Enable

26

5:0 RESERVED

Reserved

25

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bidirectional control channel offers asymmetrical communi-

cation and is not dependent on video blanking intervals.

Functional Description

The DS90UB903Q/904Q FPD-Link III chipset is intended for

video display applications. The Serializer/ Deserializer

chipset operates from a 10 MHz to 43 MHz pixel clock fre-

quency. The DS90UB903Q transforms a 21-bit wide parallel

LVCMOS data bus along with a bidirectional control bus into

a single high-speed differential pair. The high-speed serial bit

stream contains an embedded clock and DC-balance infor-

mation which enhances signal quality to support AC coupling.

The DS90UB904Q receives the single serial data stream and

converts it back into a 21-bit wide parallel data bus together

with the bidirectional control channel data bus.

DISPLAY APPLICATION

The DS90UB903Q/904Q chipset is intended for interface be-

tween a host (graphics processor) and a Display. It supports

a 21 bit parallel video bus for 18-bit color depth (RGB666)

display format. In a RGB666 configuration, 18 color bits (R

[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits

(VS, HS and DE) are supported across the serial link.

The DS90UB903Q Serializer accepts a 21-bit parallel data

bus along with a bidirectional control bus. The parallel data

and bidirectional control channel information is converted into

a single differential link. The integrated bidirectional control

channel bus supports I2C compatible operation for controlling

auxiliary data transport to and from host processor and dis-

play module. The DS90UB904Q Deserializer extracts the

clock/control information from the incoming data stream and

reconstructs the 21-bit data with control channel data.

The control channel function of the DS90UB903Q/904Q pro-

vides bidirectional communication between the host proces-

sor and display. The integrated control channel transfers data

simultaneously over the same differential pair used for video

data interface. This interface offers advantages over other

chipsets by eliminating the need for additional wires for pro-

gramming and control. The control supports I²C port. The

30125406

FIGURE 21. Typical Display System Diagram

SERIAL FRAME FORMAT

The DS90UB903Q/904Q chipset will transmit and receive a

pixel of data in the following format:

30125461

FIGURE 22. Serial Bitstream for 28-bit Symbol

The High Speed Forward Channel is a 28-bit symbol com-

posed of 21 bits of data containing video data & control

information transmitted from Serializer to Deserializer. CLK1

and CLK0 represent the embedded clock in the serial stream.

CLK1 is always HIGH and CLK0 is always LOW. This data

payload is optimized for signal transmission over an AC cou-

pled link. Data is randomized, balanced and scrambled.

DESCRIPTION OF BIDIRECTIONAL CONTROL BUS AND

I2C MODES

The I²C compatible interface allows programming of the

DS90UB903Q, DS90UB904Q, or an external remote device

(such as a display) through the bidirectional control channel.

Register

programming

transactions

to/from

the

DS90UB903Q/904Q chipset are employed through the clock

(SCL) and data (SDA) lines. These two signals have open-

drain I/Os and both lines must be pulled-up to VDDIO by

external resistor. Figure 4 shows the timing relationships of

the clock (SCL) and data (SDA) signals. Pull-up resistors or

current sources are required on the SCL and SDA busses to

pull them high when they are not being driven low. A logic zero

is transmitted by driving the output low. A logic high is trans-

The bidirectional control channel data is transferred along

with the high-speed forward data over the same serial link.

This architecture provides a full duplex low speed forward

channel across the serial link together with a high speed for-

ward channel without the dependence of the video blanking

phase.

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26

mitted by releasing the output and allowing it to be pulled-up

externally. The appropriate pull-up resistor values will depend

upon the total bus capacitance and operating speed. The

DS90UB903Q/904Q I²C bus data rate supports up to 100

kbps according to I²C specification.

is treated as a slave proxy; acts as a slave on behalf of the

remote slave. When addressing a remote peripheral or Seri-

alizer/Deserializer (not wired directly to the MCU), the slave

proxy will forward any byte transactions sent by the Master

controller to the target device. When MODE pin is set to Low,

the device will function as a master proxy device; acts as a

master on behalf of the I²C master controller. Note that the

devices must have complementary settings for the MODE

configuration. For example, if the Serializer MODE pin is set

to High then the Deserializer MODE pin must be set to Low

and vice-versa.

To start any data transfer, the DS90UB903Q/904Q must be

configured in the proper I²C mode. Each device can function

as an I²C slave proxy or master proxy depending on the mode

determined by MODE pin. The Ser/Des interface acts as a

virtual bridge between Master Controller Unit (MCU) and the

remote device. When the MODE pin is set to High, the device

30125460

FIGURE 23. Write Byte

30125410

FIGURE 24. Read Byte

30125441

FIGURE 25. Basic Operation

27

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30125442

FIGURE 26. START and STOP Conditions

SLAVE CLOCK STRETCHING

ID[X] ADDRESS DECODER

In order to communicate and synchronize with remote de-

vices on the I²C bus through the bidirectional control channel,

slave clock stretching must be supported by the I²C master

controller/MCU. The chipset utilizes bus clock stretching

(holding the SCL line low) during data transmission; where

the I²C slave pulls the SCL line low on the 9th clock of every

I²C data transfer (before the ACK signal). The slave device

will not control the clock and only stretches it until the remote

peripheral has responded; which is typically in the order of 12

us (typical).

The ID[x] pin is used to decode and set the physical slave

address of the Serializer/Deserializer (I²C only) to allow up to

six devices on the bus using only a single pin. The pin sets

one of six possible addresses for each Serializer/Deserializer

device. The pin must be pulled to VDD (1.8V, NOT VDDIO))

with a 10 kΩ resistor and a pull down resistor (RID) of the

recommended value to set the physical device address. The

recommended maximum resistor tolerance is 0.1% worst

case (0.2% total tolerance).

30125443

FIGURE 27. Bidirectional Control Bus Connection

TABLE 3. ID[x] Resistor Value – DS90UB903Q

ID[x] Resistor Value - DS90UB903Q Ser

TABLE 4. ID[x] Resistor Value – DS90UB904Q

ID[x] Resistor Value - DS90UB904Q Des

Resistor

RID Ω

Address 7'b

(Note 11)

Address 8'b 0

appended (WRITE)

Resistor

RID Ω

Address 7'b

(Note 11)

Address 8'b 0

appended (WRITE)

(±0.1%)

0

7b' 101 1000 (h'58) 8b' 1011 0000 (h'B0)

0

7b' 110 0000 (h'60) 8b' 1100 0000 (h'C0)

GND

2.0k

4.7k

7b' 101 1001 (h'59) 8b' 1011 0010 (h'B2)

7b' 101 1010 (h'5A) 8b' 1011 0100 (h'B4)

7b' 101 1011 (h'5B) 8b' 1011 0110 (h'B6)

7b' 101 1100 (h'5C) 8b' 1011 1000 (h'B8)

7b' 101 1110 (h'5E) 8b' 1011 1100 (h'BC)

2.0k

4.7k

7b' 110 0001 (h'61) 8b' 1100 0010 (h'C2)

7b' 110 0010 (h'62) 8b' 1100 0100 (h'C4)

7b' 110 0011 (h'63) 8b' 1101 0110 (h'C6)

7b' 110 0100 (h'64) 8b' 1101 1000 (h'C8)

7b' 110 0110 (h'66) 8b' 1100 1100 (h'CC)

8.2k

12.1k

39.0k

12.1k

39.0k

www.national.com

28

CAMERA MODE OPERATION

to High. Before initiating any I²C commands, the Deserializer

needs to be programmed with the target slave device ad-

dresses and Serializer device address. SER_DEV_ID Regis-

ter 0x07h sets the Serializer device address and

In Camera mode, I²C transactions originate from the Deseri-

alizer from the Master controller (Figure 28). The I²C slave

core in the Deserializer will detect if a transaction is intended

for the Serializer or a slave at the Serializer. Commands are

sent over the bidirectional control channel to initiate the trans-

actions. The Serializer will receive the command and gener-

ate an I²C transaction on its local I²C bus. At the same time,

the Serializer will capture the response on the I²C bus and

return the response as a command on the forward channel

link. The Deserializer parses the response and passes the

appropriate response to the Deserializer I²C bus.

SLAVE_x_MATCH/SLAVE_x_INDEX

registers

0x08h~0x17h set the remote target slave addresses. The

slave address match registers must also be set. In slave mode

the address register is compared with the address byte sent

by the I²C master. If the addresses are equal to any of regis-

ters values, the I²C slave will acknowledge the transaction to

the I²C master allowing reads or writes to target device.

To configure the devices for camera mode operation, set the

Serializer MODE pin to Low and the Deserializer MODE pin

30125440

FIGURE 28. Typical Camera System Diagram

DISPLAY MODE OPERATION

PROGRAMMABLE CONTROLLER

In Display mode, I²C transactions originate from the controller

attached to the Serializer. The I²C slave core in the Serializer

will detect if a transaction targets (local) registers within the

Serialier or the (remote) registers within the Deserializer or a

remote slave connected to the I²C master interface of the De-

serializer. Commands are sent over the forward channel link

to initiate the transactions. The Deserializer will receive the

command and generate an I²C transaction on its local I²C

bus. At the same time, the Deserializer will capture the re-

sponse on the I²C bus and return the response as a command

on the bidirectional control channel. The Serializer parses the

response and passes the appropriate response to the Serial-

izer I²C bus.

The physical device ID of the I²C slave in the Serializer is

determined by the analog voltage on the ID[x] input. It can be

reprogrammed by using the SER_DEV_ID register and set-

ting the bit . The device ID of the logical I²C slave in the

Deserializer is determined by programming the DES ID in the

Serializer. The state of the ID[x] input on the Deserializer is

used to set the device ID. The I²C transactions between Ser/

Des will be bridged between the host to the remote slave.

An integrated I²C slave controller is embedded in each of the

DS90UB903Q Serializer and DS90UB904Q Deserializer. It

must be used to access and program the extra features em-

bedded within the configuration registers. Refer to Table 1

and Table 2 for details of control registers.

I²C PASS THROUGH

I²C pass-through provides an alternative means to indepen-

dently address slave devices. The mode enables or disables

I²C bidirectional control channel communication to the remote

I²C bus. This option is used to determine whether or not an

I²C instruction is to be transferred over to the remote I²C de-

vice. When enabled, the I²C bus traffic will continue to pass

through and will be received by I²C devices downstream. If

disabled, I²C commands will be excluded to the remote I²C

device. The pass through function also provides access and

communication to only specific devices on the remote bus.

The feature is effective for both Camera mode and Display

mode.

SYNCHRONIZING MULTIPLE LINKS

For applications requiring synchronization across multiple

links, it is recommended to utilize the General Purpose Input/

Output (GPI/GPO) pins to transmit control signals to synchro-

nize slave peripherals together. To synchronize the periph-

erals properly, the system controller needs to provide a sync

signal output. Note this form of synchronization timing rela-

tionship has a non-deterministic latency. After the control data

is reconstructed from the birectional control channel, there will

be a time variation of the GPI/GPO signals arriving at the dif-

ferent target devices (between the parallel links). The maxi-

mum latency delta (t1) of the GPI/GPO data transmitted

across multiple links is 25 us.

To configure the devices for display mode operation, set the

Serializer MODE pin to High and the Deserializer MODE pin

to Low. Before initiating any I²C commands, the Serializer

needs to be programmed with the target slave device address

and Serializer device address. DES_DEV_ID Register 0x06h

sets the Deserializer device address and SLAVE_DEV_ID

register 0x7h sets the remote target slave address. If the I²C

slave address matches any of registers values, the I²C slave

will acknowledge the transaction allowing read or write to tar-

get device. Note: In Display mode operation, registers

0x08h~0x17h on Deserializer must be reset to 0x00.

29

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Note: The user must verify that the timing variations between

the different links are within their system and timing specifi-

cations.

The maximum time (t1) between the rising edge of GPI/GPO

(i.e. sync signal) arriving at SER A and SER B is 25 us.

30125454

FIGURE 29. GPI/GPO Delta Latency

GENERAL PURPOSE I/O (GPI/GPO)

free during the BIST duration test. A LOW on this pin at the

conclusion of the test indicates that one or more payloads

were detected with errors.

The DS90UB903Q/904Q has up to 4 GPO and 4 GPI on the

Serializer and Deserializer respectively. The GPI/GPO max-

imum switching rate is up to 66 kHz for communication be-

tween Deserializer GPI to Serializer GPO.

The BIST duration is defined by the width of BISTEN. BIST

starts when Deserializer LOCK goes HIGH and BISTEN is set

HIGH. BIST ends when BISTEN goes LOW. Any errors de-

tected after the BIST Duration are not included in PASS logic.

AT-SPEED BIST (BISTEN, PASS)

An optional AT SPEED Built in Self Test (BIST) feature sup-

ports at speed testing of the high-speed serial and the bidi-

rectional control channel link. Control pins at the Deserializer

are used to enable the BIST test mode and allow the system

to initiate the test and set the duration. A HIGH on PASS pin

indicates that all payloads received during the test were error

Note: AT-SPEED BIST is only available in the Camera mode

and not the Display mode

The following diagram shows how to perform system AT

SPEED BIST:

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30

30125445

FIGURE 30. AT-SPEED BIST System Flow Diagram

Step 1: Place the Deserializer in BIST Mode.

Deserializer will communicate through the bidirectional con-

trol channel to configure Serializer into BIST mode. Once the

BIST mode is set, the Serializer will initiate BIST transmission

to the Deserializer.

Serializer and Deserializer power supply must be supplied.

Enable the AT SPEED BIST mode on the Deserializer by set-

ting the BISTEN pin High. The 904 GPI[1:0] pins are used to

select the PCLK frequency of the on-chip oscillator for the

BIST test on high speed data path.

Wait 10 ms for Deserializer to acquire lock and then monitor

the LOCK pin transition from LOW to HIGH. At this point, AT

SPEED BIST is operational and the BIST process has begun.

The Serializer will start transfer of an internally generated

PRBS data pattern through the high speed serial link. This

pattern traverses across the interconnecting link to the De-

serializer. Check the status of the PASS pin; a HIGH indicates

a pass, a LOW indicates a fail. A fail will stay LOW for ½ a

clock cycle. If two or more bits in the serial frame fail, the

PASS pin will toggle ½ clock cycle HIGH and ½ clock cycle

low. The user can use the PASS pin to count the number of

fails on the high speed link. In addition, there is a defined SER

and DES register that will keep track of the accumulated error

count. The Serializer 903 GPO[0] pin will be assigned as a

PASS flag error indicator for the bidirectional control channel

link.

TABLE 5. BIST Oscillator Frequency Select

Des GPI

[1:0]

Oscillator

Source

min

typ

max

(MHz) (MHz) (MHz )

00

01

10

11

External PCLK

Internal

10

43

50

25

Internal

12.5

The Deserializer GPI[1:0] set to 00 will bypass the on-chip

oscillator and an external oscillator to Serializer PCLK input

is required. This allows the user to operate BIST under dif-

ferent frequencies other than the predefined ranges.

Step 2: Enable AT SPEED BIST by placing the Serializer into

BIST mode.

31

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30125464

FIGURE 31. BIST Timing Diagram

Step 3: Stop at SPEED BIST by turning off BIST mode in the

Deserializer to determine Pass/Fail.

TEN width and Deserializer LOCK is HIGH; thus the Bit Error

Rate is determined by how long the system holds BISTEN

HIGH.

To end BIST, the system must pull BISTEN pin of the Dese-

rializer LOW. The BIST duration is fully defined by the BIS-

30125405

FIGURE 32. BIST BER Calculation

Step 4: Place system in Normal Operating Mode by disabling

BIST at the Serializer.

LVCMOS VDDIO OPTION

1.8V or 3.3V SER Inputs and DES Outputs are user seletable

to provide compatibility with 1.8V and 3.3V system interfaces.

Once Step 3 is complete, AT SPEED BIST is over and the

Deserializer is out of BIST mode. To fully return to Normal

mode, apply Normal input data into the Serializer.

REMOTE WAKE UP (Camera Mode)

After initial power up, the Serializer is in a low-power Standby

mode. The Deserializer (controlled by ECU/MCU) 'Remote

Wake-up' register allows the Deserializer side to generate a

signal across the link to remotely wake-up the Serializer.

Once the Serializer detects the wake-up signal Serializer

switches from Standby mode to active mode. In active mode,

the Serializer locks onto PCLK input (if present), otherwise

the on-chip oscillator is used as the input clock source. Note

the MCU controller should monitor the Deserializer LOCK pin

and confirm LOCK = H before performing any I²C communi-

cation across the link.

Any PASS result will remain unless it is changed by a new

BIST session or cleared by asserting and releasing PDB. The

default state of PASS after a PDB toggle is HIGH.

It is important to note that AT SPEED BIST will only determine

if there is an issue on the link that is not related to the clock

and data recovery of the link (whose status is flagged with

LOCK pin).

www.national.com

32

For Remote Wake-up to function properly:

EMI REDUCTION

•

The chipset needs to be configured in Camera mode:

Serializer MODE = 0 and Deserializer MODE = 1

Des - Receiver Staggered Output

The Receiver staggered outputs allows for outputs to switch

in a random distribution of transitions within a defined window.

Outputs transitions are distributed randomly. This minimizes

the number of outputs switching simultaneously and helps to

reduce supply noise. In addition it spreads the noise spectrum

out reducing overall EMI.

•

Serializer expects remote wake-up by default at power on.

Configure the control channel driver of the Deserializer to

be in remote wake-up mode by setting Deserializer

Register 0x26h = 0xC0h.

Perform remote wake-up on Serializer by setting

Deserializer Register 0x01 b[2] = 1

Return the control channel driver of the Deserializer to the

normal operation mode by setting Deserializer Register

0x26h = 0x00h

•

Des Spread Spectrum Clocking

The DS90UB904Q parallel data and clock outputs have pro-

grammable SSCG ranges from 9 kHz–66 kHz and ±0.5%–

±2% from 20 MHz to 43 MHz. The modulation rate and mod-

ulation frequency variation of output spread is controlled

through the SSC control registers.

Serializer can also be put into standby mode by programming

the Deserializer remote wake-up control register 0x01 b[2]

REM_WAKEUP to 0.

PIXEL CLOCK EDGE SELECT (TRFB/RRFB)

POWERDOWN

The TRFB/RRFB selects which edge of the Pixel Clock is

used. For the SER, this register determines the edge that the

data is latched on. If TRFB register is 1, data is latched on the

Rising edge of the PCLK. If TRFB register is 0, data is latched

on the Falling edge of the PCLK. For the DES, this register

determines the edge that the data is strobed on. If RRFB reg-

ister is 1, data is strobed on the Rising edge of the PCLK. If

RRFB register is 0, data is strobed on the Falling edge of the

PCLK.

The SER has a PDB input pin to ENABLE or Powerdown the

device. The modes can be controlled by the host and is used

to disable the Link to save power when the remote device is

not operational. An auto mode is also available. In this mode,

the PDB pin is tied High and the SER switches over to an

internal oscillator when the PCLK stops or not present. When

a PCLK starts again, the SER will then lock to the valid input

PCLK and transmits the data to the DES. In powerdown

mode, the high-speed driver outputs are static (High).

The DES has a PDB input pin to ENABLE or Powerdown the

device. This pin can be controlled by the system and is used

to disable the DES to save power. An auto mode is also avail-

able. In this mode, the PDB pin is tied High and the DES will

enter powerdown when the serial stream stops. When the

serial stream starts up again, the DES will lock to the input

stream and assert the LOCK pin and output valid data. In

powerdown mode, the Data and PCLK outputs are set by the

OSS_SEL control register.

30125451

FIGURE 33. Programmable PCLK Strobe Select

POWER UP REQUIREMENTS AND PDB PIN

It is required to delay and release the PDB input signal after

VDD (VDDn and VDDIO) power supplies have settled to the

recommended operating voltages. A external RC network can

be connected to the PDB pin to ensure PDB arrives after all

the VDD have stabilized.

SIGNAL QUALITY ENHANCERS

Des - Receiver Input Equalization (EQ)

The receiver inputs provided input equalization filter in order

to compensate for loss from the media. The level of equal-

ization is controlled via register setting.

33

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nal AC coupling capacitors must be placed in series in the

FPD-Link III signal path as illustrated in Figure 34.

Applications Information

AC COUPLING

The SER/DES supports only AC-coupled interconnects

through an integrated DC balanced decoding scheme. Exter-

30125438

FIGURE 34. AC-Coupled Connection

For high-speed FPD-Link III transmissions, the smallest avail-

able package should be used for the AC coupling capacitor.

This will help minimize degradation of signal quality due to

package parasitics. The I/O’s require a 100 nF AC coupling

capacitors to the line.

TYPICAL APPLICATION CONNECTION

Figure 35 shows a typical connection of the DS90UB903Q

Serializer.

30125455

FIGURE 35. DS90UB903Q Typical Connection Diagram — Pin Control

www.national.com

34

Figure 36 shows a typical connection of the DS90UB904Q

Deserializer.

30125456

FIGURE 36. DS90UB904Q Typical Connection Diagram — Pin Control

35

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TRANSMISSION MEDIA

Other cable parameters that may limit the cable's perfor-

mance boundaries are: cable attenuation, near-end crosstalk

and pair-to-pair skew.

The Ser/Des chipset is intended to be used over a wide variety

of balanced cables depending on distance and signal quality

requirements. The Ser/Des employ internal termination pro-

viding a clean signaling environment. The interconnect for

FPD-Link III interface should present a differential impedance

of 100 Ohms. Use of cables and connectors that have

matched differential impedance will minimize impedance dis-

continuities. Shielded or un-shielded cables may be used

depending upon the noise environment and application re-

quirements. The chipset's optimum cable drive performance

is achieved at 43 MHz at 10 meters length. The maximum

signaling rate increases as the cable length decreases.

Therefore, the chipset supports 50 MHz at shorter distances.

For obtaining optimal performance, we recommend:

•

Use Shielded Twisted Pair (STP) cable

100Ω differential impedance and 24 AWG (or lower AWG)

cable

•

Low skew, impedance matched

Ground and/or terminate unused conductors

Figure 37 shows the Typical Performance Characteristics

demonstrating various lengths and data rates using Rosen-

berger HSD and Leoni DACAR 538 Cable.

30125457

*Note: Equalization is enabled for cable lengths greater than 7 meters

FIGURE 37. Rosenberger HSD & Leoni DACAR 538 Cable Performance

PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS

A small body size X7R chip capacitor, such as 0603, is rec-

ommended for external bypass. Its small body size reduces

the parasitic inductance of the capacitor. The user must pay

attention to the resonance frequency of these external bypass

capacitors, usually in the range of 20-30 MHz. To provide ef-

fective bypassing, multiple capacitors are often used to

achieve low impedance between the supply rails over the fre-

quency of interest. At high frequency, it is also a common

practice to use two vias from power and ground pins to the

planes, reducing the impedance at high frequency.

Circuit board layout and stack-up for the Ser/Des devices

should be designed to provide low-noise power feed to the

device. Good layout practice will also separate high frequency

or high-level inputs and outputs to minimize unwanted stray

noise pickup, feedback and interference. Power system per-

formance may be greatly improved by using thin dielectrics (2

to 4 mils) for power / ground sandwiches. This arrangement

provides plane capacitance for the PCB power system with

low-inductance parasitics, which has proven especially effec-

tive at high frequencies, and makes the value and placement

of external bypass capacitors less critical. External bypass

capacitors should include both RF ceramic and tantalum elec-

trolytic types. RF capacitors may use values in the range of

0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF

to 10 uF range. Voltage rating of the tantalum capacitors

should be at least 5X the power supply voltage being used.

Some devices provide separate power for different portions

of the circuit. This is done to isolate switching noise effects

between different sections of the circuit. Separate planes on

the PCB are typically not required. Pin Description tables typ-

ically provide guidance on which circuit blocks are connected

to which power pin pairs. In some cases, an external filter

many be used to provide clean power to sensitive circuits

such as PLLs.

Surface mount capacitors are recommended due to their

smaller parasitics. When using multiple capacitors per supply

pin, locate the smaller value closer to the pin. A large bulk

capacitor is recommend at the point of power entry. This is

typically in the 50uF to 100uF range and will smooth low fre-

quency switching noise. It is recommended to connect power

and ground pins directly to the power and ground planes with

bypass capacitors connected to the plane with via on both

ends of the capacitor. Connecting power or ground pins to an

external bypass capacitor will increase the inductance of the

path.

Use at least a four layer board with a power and ground plane.

Locate LVCMOS signals away from the differential lines to

prevent coupling from the LVCMOS lines to the differential

lines. Closely-coupled differential lines of 100 Ohms are typ-

ically recommended for differential interconnect. The closely

coupled lines help to ensure that coupled noise will appear as

common-mode and thus is rejected by the receivers. The

tightly coupled lines will also radiate less.

Information on the LLP style package is provided in National

Application Note: AN-1187.

www.national.com

36

INTERCONNECT GUIDELINES

•

Use differential connectors when operating above

500Mbps line speed

Maintain balance of the traces

Minimize skew within the pair

See AN-1108 and AN-905 for full details.

•

Use 100Ω coupled differential pairs

Use the S/2S/3S rule in spacings

– S = space between the pair

– 2S = space between pairs

– 3S = space to LVCMOS signal

Additional general guidance can be found in the LVDS

Owner’s Manual - available in PDF format from the National

web site at: www.national.com/lvds

•

Minimize the number of Vias

37

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Physical Dimensions inches (millimeters) unless otherwise noted

DS90UB903Q Serializer

NS Package Number SQA40A

DS90UB904Q Deserializer

NS Package Number SQA48A

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38

Notes

39

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Notes

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型号：	DS90UB903QSQ
厂家：	National Semiconductor
描述：	IC LINE DRIVER, QCC40, 6 X 6 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-40, Line Driver or Receiver 驱动接口集成电路
文件：	总41页 (文件大小：949K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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