DS92LV3241TVSX [NSC]
20-85 MHz 32-Bit Channel Link II Serializer/Deserializer; 20-85 MHz的32位通道链接II串行器/解串器
| 型号： | DS92LV3241TVSX |
| 厂家： | 
National Semiconductor |
| 描述： | 20-85 MHz 32-Bit Channel Link II Serializer/Deserializer |
| 文件： | 总30页 (文件大小：1796K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 17, 2009
DS92LV3241/DS92LV3242
20-85 MHz 32-Bit Channel Link II Serializer/Deserializer
Dual Lane Mode (20 to 50 MHz)
Quad Lane Mode (40 to 85 MHz)
—
—
General Description
The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or
4 (selectable) embedded clock LVDS serial channels for a
data payload rate up to 2.72 Gbps over cables such as CATx,
or backplanes FR-4 traces. The companion DS92LV3242
(DES) deserializes the 2 or 4 LVDS serial data channels, de-
skews channel-to-channel delay variations and converts the
LVDS data stream back into a 32-bit LVCMOS parallel data
bus.
Simplified Clocking Architecture
■
No separate serial clock line
No reference clock required
Receiver locks to random data
—
—
—
On-chip Signal Conditioning for Robust Serial
Connectivity
■
Transmit Pre-Emphasis
Data randomization
—
—
—
—
—
On-chip data Randomization/Scrambling and DC balance en-
coding and selectable serializer Pre-emphasis ensure a ro-
bust, low-EMI transmission over longer, lossy cables and
backplanes. The Deserializer automatically locks to incoming
data without an external reference clock or special sync pat-
terns, providing an easy “plug-and-lock” operation.
DC-balance encoding
Receive channel deskew
Supports up to 10m CAT-5 at 2.7 Gbps
Integrated LVDS Terminations
■
■
■
■
■
■
By embedding the clock in the data payload and including
signal conditioning functions, the Channel-Link II SerDes de-
vices reduce trace count, eliminate skew issues, simplify
design effort and lower cable/connector cost for a wide variety
of video, control and imaging applications. A built-in AT-
SPEED BIST feature validates link integrity and may be used
for system diagnostics.
Built-in AT-SPEED BIST for end-to-end system testing
AC-coupled interconnect for isolation and fault protection
> 4KV HBM ESD protection
Space-saving 64-pin TQFP package
Full industrial temperature range : -40° to +85°C
Applications
Features
Industrial imaging (Machine-vision) and control
■
■
■
■
Wide Operating Range Embedded Clock SER/DES
■
Security & Surveillance cameras and infrastructure
Up to 32-bit parallel LVCMOS data
20 to 85 MHz parallel clock
—
—
—
Medical imaging
Up to 30 bits per pixel, VGA to HD video transport and
Up to 2.72 Gbps application data paylod
display
Selectable Serial LVDS Bus Width
■
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2009 National Semiconductor Corporation
301036
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Block Diagram
30103627
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General Block Diagram
30103628
FIGURE 1. Dual Mode
3
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30103629
FIGURE 2. Quad Mode
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DS92LV3241 Pin Diagram
30103630
FIGURE 3. DS92LV3241 Pin Diagram— Top View
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DS92LV3241 Serializer Pin Descriptions
Pin #
Pin Name
I/O, Type
Description
LVCMOS PARALLEL INTERFACE PINS
10–8,
5–1,
TxIN[31:29], I, LVCMOS
TxIN[28:24],
Serializer Parallel Interface Data Input Pins.
64–57, TxIN[23:16],
52–51, TxIN[15:14],
48–44. TxIN[13:9],
41–33
11
TxIN[8:0]
TxCLKIN
I, LVCMOS
Serializer Parallel Interface Clock Input Pin. Strobe edge set by R_FB configuration pin.
CONTROL AND CONFIGURATION PINS
12
PDB
I, LVCMOS
Serializer Power Down Bar (ACTIVE LOW)
PDB = L; Device Disabled, Differential serial outputs are put into TRI-STATE® stand-by mode,
PLL is shutdown
PDB = H; Device Enabled
15
19
14
20
13
16
MODE
PRE
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
Dual or Quad mode select (ACTIVE H)
MODE = L (default); Dual Mode,
MODE = H; Quad Mode
PRE-emphasis level select pin
PRE = (RPRE > 12kΩ); Imax = [(1.2/R) x 20 x 2], Rmin = 12kΩ.
PRE = H or floating; pre-emphasis is disabled.
R_FB
VSEL
BISTEN
RSVD
Rising/Falling Bar Clock Edge Select
R_FB = H; Rising Edge,
R_FB = L; Falling Edge
VOD (Differential Output Voltage) Llevel Select
VSEL = L; Low Swing,
VSEL = H; High Swing
BIST Enable
BISTEN = L; BIST OFF, (default), normal operating mode.
BISTEN = H; BIST Enabled (ACTIVE HIGH)
Reserved — MUST BE TIED LOW
LVDS SERIAL INTERFACE PINS
22, 24, TxOUT[3:0]+ O, LVDS
28, 30
Serializer LVDS Non-Inverted Outputs(+)
Serializer LVDS Inverted Outputs(-)
21, 23, TxOUT[3:0]- O, LVDS
27, 29
POWER / GROUND PINS
7, 18,
32, 42
VDD
VDD
Digital Voltage supply, 3.3V
Digital ground
6, 17,
VSS
GND
31, 43
53, 56
54, 55
26
VDDPLL
VSSPLL
VDDA
VDD
GND
VDD
GND
VDD
Analog Voltage supply, PLL POWER, 3.3V
Analog ground, PLL GROUND
Analog Voltage supply
25
VSSA
Analog ground
49
IOVDD
Digital IO Voltage supply
Connect to 1.8V typ for 1.8V LVCMOS interface
Connect to 3.3V typ for 3.3V LVCMOS interface
50
IOVSS
GND
Digital IO ground
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DS92LV3242 Pin Diagram
30103631
FIGURE 4. DS92LV3242 Pin Diagram — Top View
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DS92LV3242 Deserializer Pin Descriptions
Pin #
LVCMOS PARALLEL INTERFACE PINS
5–7, RxOUT[31:29], O, LVCMOS Deserializer Parallel Interface Data Output Pins.
Pin Name
I/O, Type
Description
10–14, RxOUT[28:24],
19–25, RxOUT[23:17],
28–32, RxOUT[16:12],
33–39, RxOUT[11:5],
42–46 RxOUT[4:0]
4
RxCLKOUT
O, LVCMOS Deserializer Recovered Clock Output. Parallel data rate clock recovered from the embedded
clock.
3
LOCK
O, LVCMOS LOCK indicates the status of the receiver PLL LOCK = L; deserializer CDR/PLL is not locked,
RxOUT[31:0] and RCLK are TRI-STATED®
LOCK = H; deserializer CDR/PLL is locked
CONTROL AND CONFIGURATION PINS
48
50
49
R_FB
REN
PDB
I, LVCMOS
I, LVCMOS
I, LVCMOS
Rising/Falling Bar Clock Edge Select
R_FB = H; RxOUT clocked on rising edge
R_FB = L; RxOUT clocked on falling edge
Deserializer Enable, DES Output Enable Control Input (ACTIVE HIGH)
REN = L; disabled, RxOUT[31:0] and RxCLKOUT TRI-STATED, PLL still operational
REN = H; Enabled (ACTIVE HIGH)
Power Down Bar, Control Input Signal (ACTIVE LOW)
PDB = L; disabled, RxOUT[31:0], RCLK, and LOCK are TRI-STATED in stand-by mode,
PLL is shutdown
PDB = H; Enabled
47
RSVD
I, LVCMOS
Reserved — MUST BE TIED LOW
LVDS SERIAL INTERFACE PINS
51, 53, RxIN[0:3]+
57, 59
I, LVDS
Deserializer LVDS Non-Inverted Inputs(+)
Deserializer LVDS Inverted Inputs(-)
52, 54, RxIN[0:3]-
58, 60
I, LVDS
POWER / GROUND PINS
9, 16,
17, 26,
61
VDD
VDD
GND
Digital Voltage supply, 3.3V
Digital Ground
8, 15,
18, 27,
62
VSS
55
56
VDDA
VSSA
VDD
GND
VDD
GND
Analog LVDS Voltage supply, POWER, 3.3V
Analog LVDS GROUND
1, 40, 64 VDDPLL
2, 41, 63 VSSPLL
Analog Voltage supply PLL VCO POWER, 3.3V
Analog ground, PLL VCO GROUND
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Min
Nom
Max
Units
Supply Voltage (VDD
)
3.135
3.3
3.465
V
Supply Voltage (VDD
)
−0.3V to +4V
−0.3V to (VDD +0.3V)
−0.3V to (VDD +0.3V)
Supply Voltage(IOVDD
(SER ONLY)
3.3V I/O Interface
1.8V I/O Interface
Operating Free Air
Temperature (TA)
)
LVCMOS Input
Voltage
LVCMOS Output
Voltage
LVDS Deserializer Input
Voltage
3.135
1.71
3.3
1.8
3.465
1.89
V
V
−40
+25
+85
°C
−0.3V to +3.9V
LVDS Driver Output
Voltage
Junction Temperature
Storage Temperature
Input Clock Rate
Dual Mode
Quad Mode
−0.3V to +3.9V
+125°C
−65°C to +150°C
20
40
50
85
100
MHz
MHz
mVP-P
Tolerable Supply Noise
Lead Temperature
(Soldering, 4 seconds)
+260°C
Maximum Package Power Dissipation Capacity
Package Derating:
1/θJA °C/W above +25°C
ꢀꢀθJA
35.7 °C/W*
ꢀꢀθJC
12.6 °C/W
*4 Layer JEDEC
>4 kV
ESD Rating (HBM)
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
Low Level Input Voltage
Tx: IOVDD = 1.71V to 1.89V
0.65 x
IOVDD
IOVDD
0.3
+
V
Tx: IOVDD = 3.135V to 3.465V
Rx
VDD
2.0
VIL
Tx: IOVDD = 1.71V to 1.89V
0.35 x
IOVDD
GND
GND
V
Tx: IOVDD = 3.135V to 3.465V
0.8
−1.5
+10
+10
VDD
Rx
VCL
IIN
Input Clamp Voltage
Input Current
ICL = −18 mA
−0.8
V
Tx: VIN = 0V or 3.465V(1.89V)
IOVDD = 3.465V(1.89V)
−10
−10
2.4
µA
Rx: VIN = 0V or 3.465V
IOH = −2mA (Dual)
IOH = −2mA (Quad)
IOH = −2mA (Dual)
IOH = −2mA (Quad)
VOUT = 0V (Dual)
VOH
VOL
IOS
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
TRI-STATE® Output Current
3.0
V
V
GND
0.33
0.5
−22
−33
−40
−70
mA
mA
VOUT = 0V (Quad)
IOZ
PDB = 0V,
VOUT = 0V or VDD
−10
+10
μA
9
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
SERIALIZER LVDS DC SPECIFICATIONS
VOD
Output Differential Voltage
No pre-emphasis, VSEL = L
(VSEL = H)
350
(629)
440
(850)
525
(1000)
mVP-P
mVP-P
V
Output Differential Voltage Unbalance VSEL = L,
No pre-emphasis
VSEL = L,
ΔVOD
1
1.25
4
50
1.50
50
VOS
Offset Voltage
1.00
No pre-emphasis
Offset Voltage Unbalance
Output Short Circuit Current
VSEL = L,
No pre-emphasis
ΔVOS
mV
IOS
TxOUT[3:0] = 0V,
PDB = VDD
VSEL = L,
No pre-emphasis
TxOUT[3:0] = 0V,
PDB = VDD
VSEL = H,
,
−2
−6
−5
mA
,
−10
No pre-emphasis
IOZ
TRI-STATE® Output Current
Output Termination
PDB = 0V,
TxOUT[3:0] = 0V OR VDD
−15
−15
90
±1
±1
+15
+15
130
µA
µA
Ω
PDB = VDD
,
TxOUT[3:0] = 0V OR VDD
RT
Internal differential output termination
between differential pairs
100
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
SERIALIZER SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS
IDDTQ
IDDTD
IDDTZ
Serializer (Tx) Total Supply Current
Quad Mode
(includes load current)
f = 85 MHz,
CHECKER BOARD pattern
MODE = H,
VSEL = H,
PRE = OFF
150
150
140
140
120
120
115
200
f = 85 MHz,
CHECKER BOARD pattern
MODE = H,
200
195
195
145
145
135
VSEL = H,
RPRE = 12 kΩ
mA
f = 85 MHz,
RANDOM pattern
MODE = H,
VSEL = H,
PRE = OFF
f = 85 MHz,
RANDOM pattern
MODE = H,
VSEL = H,
RPRE = 12 kΩ
f= 50 MHz,
CHECKER BOARD pattern
MODE = L,
VSEL = H,
Serializer (Tx) Total Supply Current
Dual Mode
(includes load current)
PRE = OFF
f= 50 MHz,
CHECKER BOARD pattern
MODE = H,
VSEL = H,
RPRE = 12 kΩ
f= 50 MHz,
RANDOM pattern
MODE = L,
VSEL = H,
mA
PRE = OFF
f= 50 MHz,
RANDOM pattern
MODE = L,
115
2
135
50
VSEL = H,
RPRE = 12 kΩ
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
Serializer Supply Current
Power-down
µA
11
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
DESERIALIZER LVDS DC SPECIFICATIONS
VTH
VTL
RT
Differential Threshold High Voltage
Differential Threshold Low Voltage
Input Termination
VCM = +1.8V
+50
mV
mV
−50
90
Internal differential output termination
between differential pairs
100
130
Ω
IIN
Input Current
VIN = +2.4V, VDD = 3.6V
VIN = 0V, VDD = 3.6V
±100
±100
±250
±250
µA
µA
DESERIALIZER SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS
IDDR
Deserializer Total Supply Current
(includes load current)
f = 85 MHz,
CL = 8 pF,
240
190
145
122
265
210
185
CHECKER BOARD pattern,
Quad Mode
mA
f = 85 MHz,
CL = 8 pF,
RANDOM pattern,
Quad Mode
f = 50 MHz,
CL = 8 pF,
CHECKER BOARD pattern,
Dual Mode
mA
µA
f = 50 MHz,
CL = 8 pF,
140
100
RANDOM pattern,
Dual Mode
IDDRZ
Deserializer Supply Current Power-
down
PDB = 0V
(All other LVCMOS Inputs = 0V,
RxIN[3:0](P/N) = 0V)
Serializer Input Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tCIP
Parameter
TxCLKIN Period
Conditions
Min
Typ
Max
Units
MODE = L (Dual Mode)
tCIP
20
50
ns
MODE = H (Quad Mode)
20 MHz – 50 MHz
tCIP
11.76
25
tCIH
TxCLKIN High Time
TxCLKIN Low Time
0.45 x
tCIP
0.55 x
tCIP
0.5 x tCIP
0.5 x tCIP
0.5 x tCIP
0.5 x tCIP
ns
ns
40 MHz – 85 MHz
0.45 x
tCIP
0.55 x
tCIP
tTCIL
20 MHz – 50 MHz
Figure 7
0.45 x
tCIP
0.55 x
tCIP
40 MHz – 85 MHz
0.45 x
tCIP
0.55 x
tCIP
tCIT
TxCLKIN Transition Time
TxCLKIN Jitter
20 MHz – 50 MHz
Figure 6
0.5
0.5
1.2
ns
40 MHz – 85 MHz
1.2
tJIT
psP-P
±100
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Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tLLHT
tLHLT
tSTC
Parameter
Conditions
Min
Typ
350
350
Max
Units
ps
LVDS Low-to-High Transition Time No pre-emphasis
Figure 5
LVDS High-to-Low Transition Time
ps
TxIN[31:0] Setup to TxCLKIN
TxIN[31:0] Hold from TxCLKIN
Serializer PLL Lock Time
IOVDD = 1.71V to 1.89V
0
0
Figure 7
ns
ns
IOVDD = 3.135V to 3.465V
tHTC
IOVDD = 1.71V to 1.89V
IOVDD = 3.135V to 3.465V
Figure 9
2.5
2.25
tPLD
tLZD
tHZD
tSD
4400 x
tCIP
5000 x
tCIP
ns
ns
ns
Data Output LOW to TRI-STATE®
Delay
(Note 4)
5
5
10
10
Data Output TRI-STATE® to HIGH (Note 4)
Delay
Serializer Propagation Delay -
Latency
f = 50 MHz,
R_FB = H,
PRE = OFF,
MODE = L
Figure 8
4.5 tCIP
6.77
+
f = 50 MHz,
R_FB = L,
PRE = OFF,
MODE = L
4.5 tCIP + 4.5 tCIP + 4.5 tCIP
5.63 7.09 9.29
+
+
f = 20 MHz,
R_FB = H,
PRE = OFF,
MODE = L
4.5 tCIP + 4.5 tCIP + 4.5 tCIP
6.57
8.74
10.74
ns
f = 85MHz,
R_FB = H,
PRE = OFF,
MODE = H
9.0 tCIP
6.99
+
f = 85MHz,
R_FB = L,
PRE = OFF,
MODE = H
9.0 tCIP + 9.0 tCIP + 9.0 tCIP
5.97 7.38 9.64
+
+
f = 40 MHz,
R_FB = HL,
PRE = OFF,
MODE = H
9.0 tCIP + 9.0 tCIP + 9.0 tCIP
6.30
8.26
10.49
tLVSKD
LVDS Output Skew
LVDS differential output channel-to-
channel skew
30
500
ps
13
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Symbol
ΛSTXBW
Parameter
Conditions
Min
Typ
Max
Units
Jitter Transfer Function -3 dB
Bandwidth
Dual Mode
f = 50 MHz
Figure 15
2.8
MHz
Quad Mode
f = 85 MHz
2
Serializer Jitter Transfer Function
Peaking
Dual Mode
f = 50 MHz
δSTX
0.3
0.9
dB
Quad Mode
f = 85 MHz
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tROCP
Parameter
Conditions
Min
Typ
Max
Units
Receiver Output Clock Period
tROCP = tCIP
(Dual Mode)
Figure 11
tROCP
20
50
ns
tROCP = tCIP
tROCP
11.76
45
25
55
(Quad Mode)
tRODC
tROTR
RxCLKOUT Duty Cycle
50
%
LVCMOS Low-to-High Transition
Time
CL = 8pF
3.2
ns
(lumped load)
(Dual Mode)
Figure 10
tROTF
tROTR
tROTF
tROSC
tROHC
tROSC
tROHC
tHZR
LVCMOS High-to-Low Transition
Time
3.5
2.4
1.9
ns
ns
LVCMOS Low-to-High Transition
Time
CL = 8pF
(lumped load)
(Quad Mode)
LVCMOS High-to-Low Transition
Time
ns
RxOUT[31:0] Setup to RxCLKOUT f = 50 MHz
(Dual Mode)
0.5 x
tROCP
5.6
7.4
3.4
3.4
ns
ns
ns
ns
ns
ns
ns
ns
RxOUT[31:0] Hold to RxCLKOUT
0.5 x
tROCP
RxOUT[31:0] Setup to RxCLKOUT f = 85 MHz
(Quad Mode)
0.5 x
tROCP
RxOUT[31:0] Hold to RxCLKOUT
0.5 x
tROCP
Data Output High to TRI-STATE®
Delay
Figure 13
5
5
5
5
10
10
10
10
tLZR
Data Output Low to TRI-STATE®
Delay
tZHR
Data Output TRI-STATE® to High
Delay
tZLR
Data Output TRI-STATE® to Low
Delay
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Symbol
tRD
Parameter
Conditions
Min
Typ
Max
Units
Deserializer Porpagation Delay –
Latency
5.5 x
tROCP
3.35
ns
f = 20 MHz
(Dual Mode)
Figure 12
+
5.5 x
ns
ns
ns
f = 50 MHz
(Dual Mode)
tROCP
6.00
+
12.0 x
f = 40 MHz
(Quad Mode)
tROCP
7.4
+
12.0 x
f = 85 MHz
tROCP
5.7
+
(Quad Mode)
tRPLLS
Deserializer PLL Lock Time
20 MHz – 50 MHz
(Dual Mode)
Figure 13
128k x
tROCP
ns
ns
(Note 5)
40 MHz – 85 MHz
(Quad Mode)
Figure 13
256k x
tROCP
(Note 5)
TOLJIT
tLVSKR
Deserializer Input Jitter Tolerance
0.25
UI
ns
LVDS Differential Input Skew
Tolerance
20 MHz – 85 MHz
Figure 17
0.4 x
tROCP
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: Typical values represent most likely parametric norms at VDD = 3.3V, TA = +25°C, and at the Recommended Operating Conditions at the time of product
characterization and are not guaranteed.
Note 3: Current into a the device is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD
ΔVOD, VTH, VTL which are differential voltages.
,
Note 4: When the Serializer output is at TRI-STATE® the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 5: tRPLLS is the time required by the Deserializer to obtain lock when exiting power-down mode.
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AC Timing Diagrams and Test Circuits
30103632
FIGURE 5. Serializer LVDS Transition Times
30103645
FIGURE 6. Serializer Input Clock Transition Time
30103649
FIGURE 7. Serializer Setup/Hold and High/Low Times
30103647
FIGURE 8. Serializer Propagation Delay
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30103633
FIGURE 9. Serializer PLL Lock Time
30103648
FIGURE 10. Deserializer LVCMOS Output Transition Time
30103634
FIGURE 11. Deserializer Setup and Hold times
30103646
FIGURE 12. Deserializer Propagation Delay
17
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30103635
FIGURE 13. Deserializer PLL Lock Time and PDB TRI-STATE® Delay
30103636
FIGURE 14. Deserializer TRI_STATE Test Circuit and Timing
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30103651
FIGURE 15. Serializer Jitter Transfer
30103637
FIGURE 16. Serializer VOD Test Circuit Diagram
19
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30103638
FIGURE 17. LVDS Deserializer Input Skew
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TxCLKIN used to strobe the data is selectable via the R_FB
(SER) pin. R_FB (SER) high selects the rising edge for clock-
ing data and low selects the falling edge. The SER outputs
(TxOUT[3:0]+/-) are intended to drive a AC Coupled point-to-
point connections.
Functional Description
The DS92LV3241 Serializer (SER) and DS92LV3242 Dese-
rializer (DES) chipset is a flexible SER/DES chipset that
translates a 32-bit parallel LVCMOS data bus into a quad (4
pairs) or dual (2 pairs) LVDS serial links with embedded clock.
The DS92LV3241 serializes the 32-bit wide parallel LVCMOS
word into four or two high-speed LVDS serial data streams
with embedded clock, scrambles and DC Balances the data
to support AC coupling and enhance signal quality. The
DS92LV3242 receives the dual/quad LVDS serial data
streams and converts it back into a 32-bit wide parallel data
with a recovered clock. The dual/quad LVDS serial data
stream reduces cable size, the number of connectors, and
eases skew concerns.
The SER latches 32-bit parallel data bus and performs sev-
eral operations to it. The 32-bit parallel data is internally
encoded and sequentially transmitted over the two high-
speed serial LVDS channels. For each serial channel, the
SER transmits 20 bits of information per payload to the DES.
In the dual mode, the 32-bit parallel data is scaled and bit-
mapped across two 20-bit data payloads per channel, result-
ing in a per channel throughput of 400 Mbps to 1.0 Gbps (20
bits x clock rate). Under quad mode, the internal PLL operates
at ½ the input clock frequency rate. The 32 bits are bit-
mapped and sequenced per every 2 cycles at ½ the TxCLKIN
frequency across four channels, resutling in a per channel
throughput of 400 Mbps to 850 Mbps (20 bits x clock rate/2).
The chipset supports frequency ranges of 20 MHz to 85 MHz.
Parallel clocks between 20 MHz to 85 MHz are supported by
the dual or quad operating modes. The modes are user se-
lectable through a control pin on Serializer. In dual mode, the
transmit clock frequency supports 20 MHz to 50 MHz and in
quad mode the transmit clock frequency supports 40 MHz to
85 MHz. In the dual mode configuration, the embedded clock
LVDS serial streams have an effective data payload of 640
Mbps (20MHz x 32-bit) to 1.6 Gbps (50MHz x 32- bit). In the
quad mode configuration, the embedded clock LVDS serial
streams have an effective data payload of 1.28 Gbps (40MHz
x 32-bit) to 2.72 Gbps (85MHz x 32-bit). The SER/DES
chipset is designed to transmit data over long distances
through standard twisted pair (TWP) cables. The differential
inputs and outputs are internally terminated with 100 ohm re-
sistors to provide source and load termination, minimize stub
length, to reduce component count and further minimize
board space.
When all of the DES channels obtain lock , the LOCK pin is
driven high and synchronously delivers valid data and recov-
ered clock on the output. The DES locks to the clock, uses it
to generate multiple internal data strobes, and then drives the
recovered clock to the RxCLKOUT pin. The recovered clock
(RxCLKOUT) is synchronous to the data on the RxOUT[31:0]
pins. While LOCK is high, data on RxOUT[31:0] is valid. Oth-
erwise, RxOUT[31:0] is invalid. The polarity of the RxCLK-
OUT edge is controlled by its R_FB (DES) input. RxOUT
[31:0], LOCK and RxCLKOUT outputs will each drive a max-
imum of 8 pF load. REN controls TRI-STATE® for RxOUT0–
RxOUT31 and the RxCLKOUT pin on the DES.
RESYNCHRONIZATION
The DES can attain lock to a data stream without the use of
a separate reference clock source; greatly simplifying system
complexity and reducing overall cost. The DES synchronizes
to the SER regardless of data pattern, delivering true auto-
matic “plug-and-lock” performance. It will lock to the incoming
serial stream without the need of special training patterns or
special sync characters. The DES recovers the clock and data
by extracting the embedded clock information, deskews the
serial data channels and then deserializes the data. The DES
also monitors the incoming clock information, determines lock
status, and asserts the LOCK output high when lock occurs.
In addition the DES also supports an optional AT-SPEED
BIST (Built In Self Test) mode, BIST error flag, and LOCK
status reporting pin. The SER and the DES have a power
down control signal to enable efficient operation in various
applications.
In the absence of data transitions on one of the channels into
the DES (e.g. a loss of the link), it will automatically try to
resynchronize and re-establish lock using the standard lock
sequence on the master channel (Channel 0). For example,
if the embedded clock is not detected one time in succession
on any of the serial links, the LOCK pin is driven low. The DES
then monitors the master channel for lock, once that is ob-
tained, the second channel is locked and aligned. The logic
state of the LOCK signal indicates whether the data on Rx-
OUT is valid; when it is high, the data is valid. The system
may monitor the LOCK pin to determine whether data on the
RxOUT is valid.
POWERDOWN
The Powerdown state is a low power sleep mode that the SER
and DES may use to reduce power when no data is being
transferred. The respective PDB pins are used to set each
device into power down mode, which reduces supply current
into the µA range. The SER enters Powerdown when the SER
PDB pin is driven low. In Powerdown, the PLL stops and the
outputs go into TRI-STATE®, disabling load current and re-
ducing current supply. To exit Powerdown, SER PDB must
be driven high. When the SER exits Powerdown, its PLL must
lock to TxCLKIN before it is ready for sending data to the DES.
The system must then allow time for the DES to lock before
data can be recovered.
DESKEW AND CHANNEL ALIGNMENT
The DES automatically detects dual or quad serial channel
mode and provides a clock alignment and deskew function
without the need for any special training patterns. During the
locking phase, the embedded clock information is recovered
on all channels and the serial links are internally synchro-
nized, de-skewed, and auto aligned. The internal CDR cir-
cuitry will dynamically compensate for up to 0.4 times the
parallel clock period of per channel phase skew (channel-to-
channel) between the recovered clocks of the serial links. This
provides skew phase tolerance from mismatches in intercon-
nect wires such as PCB trace routing, cable pair-to-pair length
differences, and connector imbalances.
The DES enters Powerdown mode when DES PDB is driven
low. In Powerdown mode, the PLL’s stop and the outputs en-
ter TRI-STATE®. To bring the DES block out of the Power-
down state, the system drives DES PDB high. Both the SER
and DES must relock before data can be transferred from
Host and received by the Target. The DES will startup and
assert LOCK high when it is locked to the embedded clocks.
See also Figure 13.
DATA TRANSFER
After SER lock is established (SER PLL to TxCLKIN), the in-
puts TxIN0–TxIN31 are latched into the encoder block. Data
is clocked into the SER by the TxCLKIN input. The edge of
21
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TRI-STATE®
VOD SELECT
For the SER, TRI-STATE® is entered when the SER PDB pin
is driven low. This will TRI-STATE® the driver output pins on
TxOUT[3:0]+/-. In addition, when MODE=0 (dual mode), the
TxOUT[3:2]+/- outputs pins are in TRI-STATE®.
The SER Line Driver Differential Output Voltage (VOD) mag-
nitude is selectable. Two levels are provided and are selected
by the VSEL pin. When this pin is LOW, normal output levels
are obtained. For most application set the VSEL pin LOW.
When this pin is HIGH, the output current is increased to dou-
ble the VOD level. Use this setting only for extra long cables
or high-loss interconnects.
When you drive the REN or DES PDB pin low, the DES output
pins (RxOUT[31:0]) and RxCLKOUT will enter TRI-STATE®.
The LOCK output remains active, reflecting the state of the
PLL. The DES input pins are high impedance during receiver
Powerdown (DES PDB low) and power-off (VDD = 0V). See
also Figure 13.
VOD Control
VSEL Pin Setting
LOW
Effect
Small VOD, typ 440 mVP-P
Large VOD, typ 850 mVP-P
TRANSMIT PARALLEL DATA AND CONTROL INPUTS
HIGH
The DS92LV3241 operates on a core supply voltage of 3.3V
with an optional digital supply voltage for 1.8V, low-swing, in-
put support. The SER single-ended (32-bit parallel data and
control inputs) pins are 1.8V and 3.3V LVCMOS logic level
compatible and is configured through the IOVDD input supply
rail. If 1.8V is required, the IOVDD pin must be connected to
a 1.8V supply rail. Also when power is applied to the trans-
mitter, IOVDD pin must be applied before or simultaneously
with other power supply pins (3.3V). If 1.8V input swing is not
required, this pin should be tied to the common 3.3V rail. Dur-
ing normal operation, the voltage level on the IOVDD pins
must not change.
SERIAL INTERFACE
The serial links between the DS92LV3241 and the
DS92LV3242 are intended for a balanced 100 Ohm intercon-
nects. The links must be configured as an AC coupled inter-
face.
The SER and DES support AC-coupled interconnects
through an integrated DC balanced encoding/decoding
scheme. An external AC coupling capacitors must be placed,
in series, in the LVDS signal path. The DES input stage is
designed for AC-coupling by providing a built-in AC bias net-
work which sets the internal common mode voltage (VCM) to
+1.8V.
PRE-EMPHASIS
The SER LVDS Line Driver features a Pre-Emphasis function
used to compensate for extra long or lossy transmission me-
dia. The same amount of Pre-Emphasis is applied on all of
the enabled differential output channels. Cable drive is en-
hanced with a user selectable Pre-Emphasis feature that
provides additional output current during transitions to coun-
teract cable loading effects. The transmission distance will be
limited by the loss characteristics and quality of the media.
For the high-speed LVDS transmission, small footprint pack-
ages should be used for the AC coupling capacitors. This will
help minimize degradation of signal quality due to package
parasitics. NPO class 1 or X7R class 2 type capacitors are
recommended. 50 WVDC should be the minimum used for
best system-level ESD performance. The most common used
capacitor value for the interface is 100 nF (0.1 uF) capacitor.
One set of capacitors may be used for isolation. Two sets
(both ends) may also be used for maximum isolation of both
the SER and DES from cable faults.
To enable the Pre-Emphasis function, the “PRE” pin requires
one external resistor (Rpre) to VSS (GND) in order to set the
pre-emphasized current level. Options include:
The DS92LV3241 and the DS92LV3242 differential I/O’s are
internally terminated with 100 Ohm resistance between the
inverting and non-inverting pins and do not require external
termination. The internal resistance value will be between 90
ohm and 130 ohm. The integrated terminations improve sig-
nal integrity, reduce stub lengths, and decrease the external
component count resulting in space savings.
1. Normal Output (no Pre-emphasis) – Leave the PRE pin
open, include an R pad, do not populate.
2. Enhanced Output (Pre-emphasis enabled) – connect a
resistor on the PRE pin to Vss.
Values of the Rpre Resistor should be between 12K Ohm and
100K Ohm. Values less than 6K Ohm should not be used. The
amount of Pre-Emphasis for a given media will depend on the
transmission distance and Fmax of the application. In gener-
al, too much Pre-Emphasis can cause over or undershoot at
the receiver input pins. This can result in excessive noise,
crosstalk, reduced Fmax, and increased power dissipation.
For shorter cables or distances, Pre-Emphasis is typically not
be required. Signal quality measurements should be made at
the end of the application cable to confirm the proper amount
of Pre-Emphasis for the specific application.
AT-SPEED BIST FEATURE
The DS92LV3241/ DS92LV3242 serial link is equipped with
built-in self-test (BIST) capability to support both system man-
ufacturing and field diagnostics. BIST mode is intended to
check the entire high-speed serial interface at full link-speed
without the use of specialized and expensive test equipment.
This feature provides a simple method for a system host to
perform diagnostic testing of both SER and DES. The BIST
function is easily configured through the SER BISTEN pin.
When the BIST mode is activated, the SER generates a
PRBS (pseudo-random bit sequence) pattern (2^7-1). This
pattern traverses each lane to the DES input. The
DS92LV3242 includes an on-chip PRBS pattern verification
circuit that checks the data pattern for bit errors and reports
any errors on the data output pins of the DES.
The Pre-Emphasis circuit increases the drive current to I =
48 / (RPRE). For example if RPRE = 15 kOhms, then the current
is increased by an additional 3.2 mA. To calculate the ex-
pected increase in VOD, multiply the increase in current by 50
ohms. So for the case of RPRE = 15 kOhms, the boost to
VOD would be 3.2 mA x 50 Ohms = 160 mV. The duration of
the current is controlled to one bit by time. If more than one
bit value is repeated in the next cycle(s), the Pre-Emphasis
current is turned off (back to the normal output current level)
for the next bit(s). To boost high frequency data and pre-
equalize teh data patternreduce ISI (Inter-Symbol Interfer-
ence) improving the resulting eye pattern.
The AT-Speed BIST feature is enabled by setting the BISTEN
to High on SER. The BISTEN input must be High or Low for
4 or more TxCLKIN clock cycles in order to activate or deac-
tivate the BIST mode. An input clock signal for the Serializer
TxCLKIN must also be applied during the entire BIST opera-
tion. Once BIST is enabled, all the Serializer data inputs (TxIN
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22
[31:0]) are ignored and the DES outputs (RxOUT[31:0]) are
not available. Next, the internal test pattern generator for each
channel starts transmission of the BIST pattern from SER to
DES. The DES BIST mode will be automatically activated by
this sequence. A maximum of 128 consecutives clock sym-
bols on DS92LV3242 DES is needed to detect BIST enable
function. The BIST is implemented with independent transmit
and receive paths for the four serial links. Each channel on
the DES will be individually compared against the expected
bit sequence of the BIST pattern.
30103641
FIGURE 18. BIST Test Enabled/Disabled
Under the BIST mode, the DES parallel outputs on RxOUT
[31:0] are multiplexed to represent BIST status indicators.
The pass/fail status of the BIST is represented by a Pass flag
along with an Error counter. The Pass flag output is desig-
nated on DES RxOUT0 for Channel 0, and RxOUT8 for
Channel 1. The DES's PLL must first be locked to ensure the
Pass status is valid. The output Pass status pin will stay LOW
and then transition to High once 44*10^6 symbols are
achieved across each of the respective transmission links.
The total time duration of the test is defined by the following:
44*10^6 x tCIP . After the Pass output flags reach a HIGH
state, it will not drop to LOW even if subsequent bit errors
occurred after the BIST duration period. Errors will be report-
ed if the input test pattern comparison does not match. If an
error (miss-compare) occurs, the status bit is latched on Rx-
OUT[7:1] for Channel 0, and RxOUT[15:9] for Channel 1;
reflecting the number of errors detected. Whenever a data bit
contains an error, the Error counter bit output for that corre-
sponding channel goes HIGH. Each counter for the serial link
utilizes a 7-bit counter to store the number of errors detected
(0 to 127 max).
23
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30103642
FIGURE 19. BIST Diagram for Different Bit Error Cases
TYPICAL APPLICATION CONNECTION
•
•
•
•
•
BISTEN – Mode Input - tie LOW if BIST mode is not used,
or connect to host
VSEL – tie LOW for normal VOD magnitude (application
dependant)
MODE – For clock rates between 20 MHz and 50 MHz tie
LOW, for 40 MHz to 85 MHz tie HIGH
PRE – Leave open if not required (have a R pad option on
PCB)
Figure 20 shows a typical application of the DS92LV3241 Se-
rializer (SER). The differential outputs utilize 100nF coupling
capacitors to the serial lines. Bypass capacitors are placed
near the power supply pins. A system GPO (General Purpose
Output) controls the PDB and BISTEN pins. In this application
the R_FB (SER) pin is tied Low to latch data on the falling
edge of the TxCLKIN. In this application the link is short,
therefore the VSEL pin is tied LOW for the standard output
swing level. The Pre-emphasis input utilizes a resistor to
ground to set the amount of pre-emphasis desired by the ap-
plication.
RSVD1 & RSVD2 – tie LOW
There are eight power pins for the device. These may be
bussed together on a common 3.3V plane (3.3V LVCMOS I/
O interface). If 1.8V input swing level for parallel data and
control pins are required, connect the IOVDD pin to 1.8V. At
a minimum, eight 0.1uF capacitors should be used for local
bypassing.
Configuration pins for the typical application are shown for
SER:
•
PDB – Power Down Control Input – Connect to host or tie
HIGH (always ON)
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24
30103643
FIGURE 20. DS92LV3241 Typical Connection Diagram
Figure 21 shows a typical application of the DS92LV3242
Deserializer (DES). The differential inputs utilize 100nF cou-
pling capacitors in the serial lines. Bypass capacitors are
placed near the power supply pins. A system GPO (General
Purpose Output) controls the PDB pin. In this application the
R_FB (DES) pin is tied Low to strobe the data on the falling
25
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edge of the RxCLKOUT. The REN signal is not used and is
tied High also.
•
•
REN – tie HIGH if not used (used to MUX two DES to one
target device)
RSVD – tie LOW
Configuration pins for the typical application are shown for
DES:
•
PDB – Power Down Control Input – Connect to host or tie
HIGH
30103644
FIGURE 21. DS92LV3242 Typical Connection Diagram
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26
to achieve low impedance between the supply rails over the
frequency of interest. At high frequency, it is also a common
practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Applications Information
TRANSMISSION MEDIA
The SER and DES are used in AC-coupled point-to-point
configurations, through a PCB trace, or through twisted pair
cables. Interconnect for LVDS typically has a differential
impedance of 100 Ohms. Use cables and connectors that
have matched differential impedance to minimize impedance
discontinuities. In most applications that involve cables, the
transmission distance will be determined on data rates in-
volved, acceptable bit error rate and transmission medium.
Some devices provide separate power and ground pins for
different portions of the circuit. This is done to isolate switch-
ing noise effects between different sections of the circuit.
Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some cas-
es, an external filter many be used to provide clean power to
sensitive circuits such as PLLs.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Use at least a four layer board with a power and ground plane.
Locate LVCMOS signals away from the LVDS lines to prevent
coupling from the LVCMOS lines to the LVDS lines. Closely-
coupled differential lines of 100 Ohms are typically recom-
mended for LVDS interconnect. The closely coupled lines
help to ensure that coupled noise will appear as common
mode and thus is rejected by the receivers. The tightly cou-
pled lines will also radiate less.
Circuit board layout and stack-up for the LVDS SER/DES de-
vices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high fre-
quency or high-level inputs and outputs to minimize unwanted
stray noise pickup, feedback and interference. Power system
performance may be greatly improved by using thin di-
electrics (2 to 4 mils) for power / ground sandwiches. This
arrangement provides plane capacitance for the PCB power
system with low-inductance parasitics, which has proven es-
pecially effective at high frequencies, and makes the value
and placement of external bypass capacitors less critical. Ex-
ternal bypass capacitors should include both RF ceramic and
tantalum electrolytic types. RF capacitors may use values in
the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be
in the 2.2 uF to 10 uF range. Voltage rating of the tantalum
capacitors should be at least 5X the power supply voltage
being used.
PLUG AND GO
The Serializer and Deserializer devices support hot plugging
of the serial interconnect. The automatic receiver lock to ran-
dom data “plug & go” capability allows the DS92LV3242 to
obtain lock to the active data stream during a live insertion
event.
LVDS INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
•
•
Use 100 Ohm coupled differential pairs
Surface mount capacitors are recommended due to their
smaller parasitics. When using multiple capacitors per supply
pin, locate the smaller value closer to the pin. A large bulk
capacitor is recommended at the point of power entry. This is
typically in the 50uF to 100uF range and will smooth low fre-
quency switching noise. It is recommended to connect power
and ground pins directly to the power and ground planes with
bypass capacitors connected to the plane with vias on both
ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the
path.
Use the S/2S/3S rule in spacings
—S = space between the pair
—2S = space between pairs
—3S = space to LVCMOS signal
Minimize the number of vias
Use differential connectors when operating above 500
Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Terminate as close to the TX outputs and RX inputs as
possible
•
•
•
•
•
A small body size X7R chip capacitor, such as 0603, is rec-
ommended for external bypass. Its small body size reduces
the parasitic inductance of the capacitor. The user must pay
attention to the resonance frequency of these external bypass
capacitors, usually in the range of 20-30 MHz range. To pro-
vide effective bypassing, multiple capacitors are often used
Additional general guidance can be found in the LVDS
Owner’s Manual - available in PDF format from the National
web site at: www.national.com/lvds
27
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Typical Performance Characteristics
The waveforms below illustrate the typical performance of the DS92LV3241. The SER was given a PCLK and configured as
described below each picture. In all of the pictures the SER was configured with BISTEN pin set to logic HIGH. Each waveform
was taken by using a high impedance low capacitance differential probe to probe across a 100 ohm differential termination resistor
within one inch of TxOUT0+/-.
30103652
30103653
Serial Output Quad Mode, 85 MHz, VSEL = H, No Pre-
Emphasis
Serial Output Quad Mode, 85 MHz, VSEL = L, No Pre-
Emphasis
30103654
30103655
Serial Output Dual Mode, 50 MHz, VSEL = H, No Pre-
Emphasis
Serial Output Dual Mode, 50 MHz, VSEL = L, No Pre-
Emphasis
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28
Physical Dimensions inches (millimeters) unless otherwise noted
Dimensions show in millimeters only
NS Package Number VEC64A
Ordering Information
NSID
Package Type
Package ID
VEC64A
VEC64A
VEC64A
VEC64A
DS92LV3241TVS
DS92LV3241TVSX
DS92LV3242TVS
DS92LV3242TVSX
64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch
64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch
64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch
64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch, 1000 std reel
29
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