LM12438CIWM [NSC]
Sign Data Acquisition System with Serial I/O and Self-Calibration; 注册数据采集系统的串行I / O和自校准
| 型号： | LM12438CIWM |
| 厂家： | 
National Semiconductor |
| 描述： | Sign Data Acquisition System with Serial I/O and Self-Calibration |
| 文件： | 总80页 (文件大小：1551K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1995
À Ó
LM12434/LM12 L 438 12-Bit
a
Sign Data Acquisition
System with Serial I/O and Self-Calibration
General Description
The LM12434 and LM12 L 438 are highly integrated Data
Acquisition Systems. Operating on 3V to 5V, they combine a
fully-differential self-calibrating (correcting linearity and zero
Key Specifications
f
e
Resolution
À
8 MHz L, f
e
CLK
Ó
6 MHz
12-bit
À
Ó
CLK
Y
Y
Y
Y
a
a
Ó
Ó
sign or 8-bit
À
sign
13-bit conversion time
9-bit conversion time
13-bit Through-put rate
5.5 ms 7.3 ms (max)
2.6 ms 3.5 ms (max)
À
a
errors) 13-bit (12-bit
sign) analog-to-digital converter
(ADC) and sample-and-hold (S/H) with extensive analog
and digital functionality. Up to 32 consecutive conversions,
using two’s complement format, can be stored in an internal
32-word (16-bit wide) FIFO data buffer. An internal 8-word
instruction RAM can store the conversion sequence for up
to eight acquisitions through the LM12 L 438’s eight-input
multiplexer. The LM12434 has a four-channel multiplexer, a
differential multiplexer output, and a differential S/H input.
À
Ó
140k samples/s 105k sample/s (min)
Comparison time (‘‘watchdog’’ mode)
1.4 ms 1.8 ms (max)
Y
À
Ó
Y
Y
Y
Y
Y
À Ó
Serial Clock
Integral Linearity Error
10 MHz 6 MHz (max)
g
1 LSB (max)
a
À
Ó
V
IN
range
GND to V
A
À Ó
45 mW 20 mW (max)
Power dissipation
Stand-by mode
À
Ó
The LM12434 and LM12 L 438 can also operate with 8-bit
sign resolution and in a supervisory ‘‘watchdog’’ mode
À Ó
25 mW 16.5 mW (typ)
power dissipation
Supply voltage LM12L438
LM12434/8
a
Y
g
3.3V 10%
that compares an input signal against two programmable
limits.
g
5V 10%
Features
Three operating modes: 12-bit
Acquisition times and conversion rates are programmable
through the use of internal clock-driven timers. The differen-
tial reference voltage inputs can be externally driven for ab-
solute or ratiometric operation.
Y
a
a
sign,
sign, 8-bit
and ‘‘watchdog’’ comparison mode
Single-ended or differential inputs
Built-in Sample-and-Hold
Y
Y
Y
Y
All registers, RAM, and FIFO are directly accessible through
the high speed and flexible serial I/O interface bus. The
serial interface bus is user selectable to interface with the
following protocols with zero glue logic: MICROWIRE/
PLUSTM, Motorola’s SPI/QSPI, Hitachi’s SCI, 8051 Family’s
2
Serial Port (Mode 0), I C and the TMS320 Family’s Serial
Port.
Instruction RAM and event sequencer
Ó
À
8-channel (LM12 L 438) or 4-channel (LM12434)
multiplexer
32-word conversion FIFO
Y
Y
Y
Y
Y
Programmable acquisition times and conversion rates
Self-calibration and diagnostic mode
Power down output for system power management
Read while convert capability for maximum through-put
rate
An evaluation kit for demonstrating the LM12434 and
À
Ó
LM12 L 438 is available.
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUSTM is a trademark of National Semiconductor Corporation.
WindowsÉ is a registered trademark of Microsoft Corporation.
Applications
Data Logging
Y
Y
Portable Instrumentation
Process Control
Y
Y
Energy Management
Robotics
Y
Connection Diagrams
28-Pin PLCC Package
28-Pin Wide Body SO Package
TL/H/11879–1
TL/H/11879–2
Order Number LM12434CIWM, LM12438CIWM, or
LM12L438CIWM
See NS Package Number M28B
*Pin names in ( ) apply to the LM12434
Order Number LM12434CIV, LM12438CIV, or
LM12L438CIV
See NS Package Number V28A
C
1995 National Semiconductor Corporation
TL/H/11879
RRD-B30M85/Printed in U. S. A.
Table of Contents
1.0 FUNCTIONAL DIAGRAMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3
7.0 DIGITAL INTERFACE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ43
7.1 Standard Interface Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ43
2.0 ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ5
7.1.1 Examples of Interfacing to the HPC 46XXX’s
MICROWIRE/PLUSTM and 68HC11’s SPI ÀÀÀ50
2.1 Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ5
2.1.1 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ5
2.1.2 Operating Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ5
7.2 8051 Interface ModeÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ59
7.2.1 Example of Interfacing to the 8051ÀÀÀÀÀÀÀÀÀÀ62
7.3 TMS320 Interface ModeÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ66
7.3.1 Example of Interfacing to the TMS320C3x ÀÀÀ69
2.2 Performance Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ5
2.2.1 Converter Static Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀ5
2.2.2 Converter Dynamic Characteristics ÀÀÀÀÀÀÀÀÀÀ6
2.2.3 DC CharacteristicsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ8
2.2.4 Digital DC CharacteristicsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ9
2
7.4 I C Bus Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ74
2
7.4.1 Example of Interfacing to an I C ControllerÀÀÀ76
2.3 Digital Switching CharacteristicsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ10
8.0 ANALOG CONSIDERATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ77
8.1 Reference Voltage ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ77
8.2 Input Range ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ77
8.3 Input Current ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ77
8.4 Input Source Resistance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ77
8.5 Input Bypass Capacitance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ77
8.6 Input Noise ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ77
8.7 Power Supply Consideration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ77
8.8 PC Board Layout and Grounding ConsiderationÀÀÀÀ78
2.3.1 Standard Interface Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ10
2.3.2 8051 Interface ModeÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ11
2.3.3 TMS320 Interface ModeÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ12
2
2.3.4 I C Bus Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ13
2.4 Notes on Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ14
3.0 ELECTRICAL CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15
4.0 TYPICAL PERFORMANCE CHARACTERISTICS ÀÀÀ19
5.0 PIN DESCRIPTIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ23
6.0 OPERATIONAL INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ27
6.1 Functional Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ27
6.2 Internal User-Accessible Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ31
6.2.1 Instruction RAM ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ31
6.2.2 Configuration Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38
6.2.3 InterruptsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38
6.2.4 Interrupt Enable Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ39
6.2.5 Interrupt Status Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ39
6.2.6 Limit Status RegisterÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ40
6.2.7 Timer ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ40
6.2.8 FIFOÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ40
6.3 Instruction SequencerÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ41
2
1.0 Functional Diagrams
LM12434
TL/H/11879–3
INTERFACE
Standard
8051
MODESEL1
MODESEL2
P1
R/F
1*
P2
CS
P3
DI
P4
DO
P5
0
0
1
1
1
0
0
1
SCLK
TXD
1*
CS
RXD
SDA
DR
2
I C
SAD0
FSR
SAD1
FSX
SAD2
DX
SCL
TMS320
SCLK
*Internal pull-up
Ordering Information (LM12434)
Part Number
LM12434CIV
Package Type
28-Pin PLCC
28-Pin Wide Body SO
NSC Package Number
Temperature Range
b
b
a
40 C to 85 C
V28A
M28B
§
§
a
40 C to 85 C
LM12434CIWM
§
§
3
1.0 Functional Diagrams (Continued)
À
Ó
LM12 L 438
TL/H/11879–4
INTERFACE
Standard
8051
MODESEL1
MODESEL2
P1
R/F
1*
P2
CS
P3
DI
P4
DO
P5
0
0
1
1
1
0
0
1
SCLK
TXD
1*
CS
RXD
SDA
DR
2
I C
SAD0
FSR
SAD1
FSX
SAD2
DX
SCL
TMS320
SCLK
*Internal pull-up
À Ó
Ordering Information (LM12 L 438)
Part Number
Package Type
NSC Package Number
Temperature Range
b
a
40 C to 85 C
LM12438CIV
LM12L438CIV
28-Pin PLCC
V28A
§
§
b
a
40 C to 85 C
LM12438CIWM
LM12L438CIWM
28-Pin Wide Body SO
M28B
§
§
LM12438 Eval
Evaluation Board and Windows based software
É
4
2.0 Electrical Specifications
2.1 RATINGS
2.1.2 Operating Ratings (Notes 1 & 2)
s
s
T
Temperature Range
LM12434CIV/LM12 L 438CIV
(T
min
T
T
T
)
max
A
2.1.1 Absolute Maximum Ratings (Notes 1 & 2)
s
s
s
s
À
LM12434CIWM, LM12 L 438CIWM 40 C
Ó
b
b
40 C
85 C
85 C
§
§
§
§
A
A
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
À
Ó
Supply Voltage
a, V
a
V
3.0V to 5.5V
A
D
a
a
)
Supply Voltage (V
and V
6.0V
A
D
a
a
s
b
V
V
100 mV
l
l
A
D
l
AGDND DGND
Voltage at Input and Output Pins
except IN0–IN3 (LM12434)
s
b
100 mV
a
l
b
a
0.3V to V
0.3V
a
s
s
s
À
Ó
and IN0–IN7 (LM12 L 438)
Analog Inputs Range
GND
V
V
V
a
a
IN
A
a
s
V
REF
V
REF
V
REF
V
REF
Input Voltage
Input Voltage
1V
V
REF
Voltage at Analog Inputs IN0–IN3 (LM12434)
a
b
a
A
a
a
5V
À
Ó
and IN0–IN7 (LM12 L 438)
b
GND 5V to V
s
s
b
0V
V
V
1V
a
b
a
REF
REF
a
a
b
V
V
300 mV
300 mV
s
s
b
l
l
A
D
l
AGND DGND
V
REF
1V
V
V
b
REF
A
b
l
Common Mode
a
a
A
s
s
0.6 V
Range (Note 16)
0.1 V
V
g
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
5 mA
A
REFCM
g
20 mA
e
Power Dissipation (T
V Package
WM Package
25 C) (Note 4)
§
A
b
a
65 C to 150 C
Storage Temperature
§
§
Soldering Information, Lead Temperature (Note 19)
V Package, Vapor Phase (60 seconds)
Infrared (15 seconds)
WM Package, Vapor Phase (60 seconds)
Infrared (15 seconds)
ESD Susceptibility (Note 5)
1.5 kV
2.2 PERFORMANCE CHARACTERISTICS All specifications apply to the LM12434, LM12438, and LM12L438 unless otherwise
À Ó
noted. Specifications in braces
apply only to the LM12L438.
a
À
Ó
e
e
2.2.1 Converter Static Characteristics The following specifications apply to the LM12434 and LM12 L 438 for V
A
a
e
8.0 MHz 6 MHz , R
À
Ó
Ó
e
e
e
À
Ó
e
s
a
V
5V 3.3V , AGND
À
DGND
e
25X, source impedance for V
S
0V, V
4.096V 2.5V , V
0V, 12-bit sign conversion mode, f
a
b
D
REF
REF
CLK
and V
b
REF
25X, fully-differential input with fixed 2.048V
a
REF
1.25V common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for T
À
Ó
e
A
e
e
e
T
J
T
T
to T
; all other limits T
MAX
25 C. (Notes 6, 7, 8 and 9)
§
J
MIN
A
Typical
Limits
Units
Symbol
Parameter
Conditions
(Note 10)
(Note 11)
(Limit)
ILE
Positive and Negative Integral
Linearity Error
After Auto-Cal (Notes 12, 17)
g
g
1
0.35
LSB (max)
g
TUE
DNL
Total Unadjusted Error
After Auto-Cal (Note 12)
After Auto-Cal (Note 12)
After Auto-Cal
1
LSB
Resolution with No Missing Codes
Differential Non-Linearity
Zero Error
13
Bits
g
g
g
g
g
0.2
0.2
0.2
0.2
1
1
2
2
LSB (max)
LSB (max)
LSB (max)
LSB (max)
LSB (max)
g
g
g
After Auto-Cal (Notes 13, 17)
After Auto-Cal (Notes 12, 17)
After Auto-Cal (Notes 12, 17)
(Note 14)
Positive Full-Scale Error
Negative Full-Scale Error
DC Common Mode Error
g
g
3.5
2
À
Ó
g
4.0
a
ILE
8-Bit
Sign and ‘‘Watchdog’’
(Note 12)
g
g
g
Mode Positive and Negative
Integral Linearity Error
0.15
1/2
LSB (max)
a
Total Unadjusted Error
TUE
8-Bit
Sign and ‘‘Watchdog’’ Mode
After Auto-Zero
g
1/2
1/2
9
LSB (max)
Bits (max)
a
Resolution with No Missing Codes
8-Bit
Sign and ‘‘Watchdog’’ Mode
5
2.0 Electrical Specifications (Continued)
a
À
Ó
e
e
2.2.1 Converter Static Characteristics The following specifications apply to the LM12434 and LM12 L 438 for V
A
a
e
8.0 MHz 6 MHz , R
À
Ó
Ó
e
e
e
À
Ó
e
s
a
V
5V 3.3V , AGND
À
DGND
e
25X, source impedance for V
S
0V, V
4.096V 2.5V , V
0V, 12-bit sign conversion mode, f
a
b
D
REF
REF
CLK
and V
b
REF
25X, fully-differential input with fixed 2.048V
a
REF
1.25V common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for T
À
Ó
e
A
e
e
e
T
J
T
J
T
to T
; all other limits T
MAX
25 C. (Notes 6, 7, 8 and 9) (Continued)
§
MIN
A
Typical
Limits
Units
Symbol
DNL
Parameter
Conditions
(Note 10) (Note 11)
(Limit)
a
Differential Non-Linearity
8-Bit
Sign and ‘‘Watchdog’’ Mode
g
g
g
g
g
0.15
0.05
1/2
1/2
1/2
LSB (max)
LSB (max)
LSB (max)
LSB
a
Zero Error
8-Bit
Sign and ‘‘Watchdog’’ Mode
After Auto-Zero
a
and Negative Full-Scale Error
8-Bit
Sign and ‘‘Watchdog’’ Positive
g
0.1
1/8
0.05
a
DC Common Mode Error
8-Bit
Sign and ‘‘Watchdog’’ Mode
g
Multiplexer Channel-to-Channel
Matching
g
LSB
V
IN
V
IN
V
IN
V
IN
Non-Inverting
Input Range
GND
a
V (min)
V (max)
a
b
a
a
V
A
Inverting
Input Range
GND
a
V (min)
V (max)
V
A
a
b
b
V
A
V
V
Differential Input Voltage Range
V (min)
V (max)
b
b
IN
a
V
A
b
Common Mode Input Voltage Range
GND
a
V (min)
V (max)
IN
V
2
A
a
a
e
e
a
g
g
g
g
g
PSS
Power Supply
Sensitivity
(Note 15)
Zero Error
V
V
V
5V 10%,
0.05
0.25
1.0
1.5
LSB (max)
LSB (max)
LSB
A
D
e
e
GND
Full-Scale Error
Linearity Error
4.096V, V
REF
b
REF
g
0.2
C
V
/V
REF
Input Capacitance
b
85
pF
pF
a
REF
REF
C
IN
Selected Multiplexer Channel Input
Capacitance
75
a
e
2.2.2 Converter Dynamic Characteristics The following specifications apply only to the LM12434 and LM12438 for V
A
a
e
throughput rate
e
133.3 kHz, R
e
e
e
a
e
8.0 MHz,
CLK
V
5V, AGND
DGND
0V, V
REF
e
4.096V, V
REF
0V, 12-bit
and V
2.048V 1.25V common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply
sign conversion mode, f
a
b
D
s
e
25X, source impedance for V
25X, fully-differential input with fixed
a
b
S
REF
REF
À
Ó
e
e
e
e
T
J
for T
T
T
MIN
to T
; all other limits T
MAX
25 C. (Notes 6, 7, 8 and 9)
§
A
J
A
Typical
Limits
Units
Symbol
Parameter
Conditions
(Note 10)
(Note 11)
(Limit)
CLK Duty Cycle
Conversion Time
50
%
40
60
% (min)
% (max)
t
t
13-Bit Resolution,
C
A
a
a
44 (t
21 (t
)
)
44 (t
21 (t
)
50 ns
50 ns
(max)
(max)
CLK
CLK
Sequencer State S5(Figure 10)
9-Bit Resolution,
)
CLK
CLK
Sequencer State S5(Figure 10)
e
CLK Period
Acquisition Time
(Programmable)
Sequencer State S7(Figure 10)
Minimum for 13-Bits
t
CLK
a
a
9 (t
)
9 (t
)
50 ns
(max)
(max)
CLK
39 (t
CLK
e
a
Maximum for 13-Bits (D
15)
)
39 (t
)
50 ns
CLK
CLK
Minimum for 9-Bits(Figure 10)
e
2 (t
2 (t
)
)
2 (t
)
50 ns
(max)
(max)
CLK
CLK
a
50 ns
Maximum for 9-Bits (D
15)
32 (t
)
CLK
CLK
6
2.0 Electrical Specifications (Continued)
a
e
2.2.2 Converter Dynamic Characteristics The following specifications apply only to the LM12434 and LM12438 for V
A
a
e
throughput rate
e
133.3 kHz, R
e
e
e
a
e
8.0 MHz,
CLK
V
D
5V, AGND
DGND
0V, V
REF
e
4.096V, V
REF
0V, 12-bit
and V
2.048V common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for T
sign conversion mode, f
a
b
s
e
25X, source impedance for V
25X, fully-differential input with fixed
a
b
S
REF
REF
e
A
e
e
e
T
J
T
T
to T
; all other limits T
MAX
25 C. (Notes 6, 7, 8 and 9) (Continued)
§
J
MIN
A
Typical
Conditions
(Note 10)
Limits
Units
Symbol
Parameter
(Note 11)
(Limit)
a
t
t
Auto-Zero Time
Sequencer State S2(Figure 10)
76 (t
)
76 (t
)
50 ns
(max)
Z
CLK
CLK
a
Full Calibration Time
Throughput Rate
Sequencer State S2(Figure 10) 4944 (t
)
4944 (t
)
50 ns (max)
CAL
CLK
CLK
(Note 18)
kHz
142
140
(min)
t
‘‘Watchdog’’ Mode Comparison Time Sequencer States S6, S4,
and S5(Figure 10)
WD
a
11 (t
)
11 (t
)
50 ns
(max)
CLK
CLK
e
g
4.096V (Note 20)
SNR
Signal-to-Noise Ratio,
Differential Input
V
IN
e
f
IN
f
IN
f
IN
1 kHz
79
79
70
dB
dB
dB
e
e
10 kHz
62 kHz
e
SNR
Signal-to-Noise Ratio,
Single-Ended Input
V
4.096 V
IN
p-p
e
e
e
f
IN
f
IN
f
IN
1 kHz
71
71
67
dB
dB
dB
10 kHz
62 kHz
a
e
g
SINAD
SINAD
THD
Signal-to-Noise
Distortion Ratio,
V
4.096V (Note 20)
IN
e
e
e
Differential Input
f
IN
f
IN
f
IN
1 kHz
79
78
67
dB
dB
dB
10 kHz
62 kHz
a
Single-Ended Input
e
Signal-to-Noise
Distortion Ratio,
V
IN
4.096 V
p-p
e
e
e
f
IN
f
IN
f
IN
1 kHz
71
70
64
dB
dB
dB
10 kHz
62 kHz
e
g
1 kHz
Total Harmonic Distortion,
Differential Input
V
IN
4.096V (Note 20)
e
e
e
b
b
b
f
IN
f
IN
f
IN
90
85
71
dBc
dBc
dBc
10 kHz
62 kHz
e
THD
Total Harmonic Distortion,
V
IN
4.096 V
p-p
e
e
e
b
b
b
Distortion, Single-Ended Input
f
IN
f
IN
f
IN
1 kHz
88
82
67
dBc
dBc
dBc
10 kHz
62 kHz
e
g
1 kHz
ENOB
ENOB
SFDR
SFDR
Effective Number of Bits,
Differential Input
V
4.096V (Note 20)
IN
e
e
e
f
IN
f
IN
f
IN
12.6
12.2
12.1
Bits
Bits
Bits
10 kHz
62 kHz
e
Effective Number of Bits,
Single-Ended Input
V
IN
4.096 V
p-p
e
e
e
f
IN
f
IN
f
IN
1 kHz
11.3
11.2
10.8
Bits
Bits
Bits
10 kHz
62 kHz
e
g
1 kHz
Spurious Free Dynamic Range,
Differential Input
V
IN
4.096V (Note 20)
e
e
e
f
IN
f
IN
f
IN
90
86
76
dBc
dBc
dBc
10 kHz
62 kHz
e
Spurious Free Dynamic Range,
Single-Ended Input
V
IN
4.096V V
p-p
e
e
e
f
IN
f
IN
f
IN
1 kHz
90
85
72
dBc
dBc
dBc
10 kHz
62 kHz
7
2.0 Electrical Specifications (Continued)
a
e
2.2.2 Converter Dynamic Characteristics The following specifications apply only to the LM12434 and LM12438 for V
A
a
e
throughput rate
e
133.3 kHz, R
e
e
e
a
e
8.0 MHz,
CLK
V
D
5V, AGND
DGND
0V, V
REF
e
4.096V, V
REF
0V, 12-bit
and V
2.048V common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for T
sign conversion mode, f
a
b
s
e
25X, source impedance for V
25X, fully-differential input with fixed
a
b
S
REF
REF
e
A
e
e
e
T
J
T
J
T
to T
; all other limits T
MAX
25 C. (Notes 6, 7, 8 and 9) (Continued)
§
MIN
A
Typical
Limits
Units
Symbol
Parameter
Conditions
(Note 10)
(Note 11)
(Limit)
e
g
4.096V (Note 20)
IMD
Two Tone Intermodulation Distortion
Differential Input
V
IN
e
b
b
f
1
f
2
19.190 kHz
19.482 kHz
82
80
dBc
dBc
e
e
IMD
Two Tone Intermodulation Distortion
Single Ended Input
V
4.096 V
pp
IN
e
e
f
f
19.190 kHz
19.482 kHz
1
2
e
Multiplexer Channel-to-Channel Crosstalk
V
IN
4.096 V
PP
e
f
f
5 kHz
IN
e
b
40 kHz
90
dBc
CROSSTALK
LM12434 MUXOUT Only
and LM12438 MUX
plus Converter (Note 21)
t
t
Power-Up Time
Wake-Up Time
10
ms
ms
PU
(Note 22)
2
WU
a
a
À
Ó
e
e À
]
5V 3.3V ,
2.2.3 DC Characteristics The following specifications apply to the LM12434 and LM12 L 438 for V
V
D
A
e
e
e
À
Ó
4.096V 2.5V , V
otherwise specified. Boldface limits apply for T
e
e À Ó
AGND
DGND
0V, V
REF
0V, f
CLK
8.0 MHz 6 MHz and minimum acquisition time unless
a
b
e
REF
e
e
e
T 25 C. (Notes 6, 7
J
T
T
MIN
to T
; all other limits T
§
A
J
MAX
A
and 8)
Typical
Limits
(Note 11)
Units
Symbol
Parameter
Supply Current
Conditions
(Note 10)
(Limit)
a
a
a
e
À Ó
8 MHz 6 MHz
I
V
V
f
CLK
D
D
e
e
À
Ó
Ó
f
f
Stopped
À
10 MHz 8 MHz
2.0 1.4
mA (max)
mA (max)
SCLK
SCLK
Ó
Ó
À
4.0 2.0
À
5.0 2.5
Ó
Ó
a
e
À
8 MHz 6 MHz
Ó
À
2.8 2.2
Ó
À
4.0 3.5
I
I
Supply Current
f
mA (max)
A
A
CLK
a
a
)
a
I
A
Stand-By Supply Current (I
Stand-By Mode Selected
ST
D
e
f
f
f
Stopped
SCLK
e
e
À Ó
5 5
Stopped
À
8 MHz 6 MHz
mA (max)
mA (max)
CLK
CLK
Ó
À
120 50
Ó
e
À
10 MHz 8 MHz
f
f
f
SCLK
e
e
À
Ó
Ó
Stopped
À
8 MHz 6 MHz
1.4 0.8
mA (max)
mA (max)
CLK
CLK
a
Ó
À
1.4 0.8
e
Multiplexer ON-Channel Leakage Current
V
5.5V
A
e
ON-Channel
5.5V
e
À
1.0 3.0
Ó
OFF-Channel
0V
0.1
0.1
mA (max)
mA (max)
e
ON-Channel
OFF-Channel
0V
e
À
1.0 3.0
Ó
5.5V
a
e
ON-Channel
À
e
Ó
5.5V 3.3V
Multiplexer OFF-Channel Leakage Current
V
5.5V 3.3V
A
À
Ó
e
À
1.0 3.0
Ó
Ó
OFF-Channel
0V
mA (max)
mA (max)
e
ON-Channel
OFF-Channel
0V
e
À
5.5V 3.3V
Ó
À
1.0 3.0
8
2.0 Electrical Specifications (Continued)
a
a
e
8.0 MHz 6 MHz and minimum acquisition time unless
À
Ó
Ó
e
À
]
2.2.3 DC Characteristics The following specifications apply to the LM12434 and LM12 L 438 for V
V
D
5V 3.3V ,
A
e
e
e
À
Ó
4.096V 2.5V , V
otherwise specified. Boldface limits apply for T
e
e
À
AGND
DGND
0V, V
REF
0V, f
CLK
a
b
e
REF
e
e
e
T 25 C. (Notes 6, 7
J
T
T
to T
; all other limits T
§
A
J
MIN
MAX
A
and 8) (Continued)
Typical
Limits
Units
Symbol
Parameter
Conditions
LM12434
(Note 10)
(Note 11)
(Limit)
R
ON
Multiplexer ON-Resistance
e
e
e
V
IN
V
IN
V
IN
5V
650
700
630
1000
1000
1000
X(max)
X(max)
X(max)
2.5V
0V
Multiplexer Channel-to-Channel
LM12434
e
e
e
g
g
g
g
g
g
R
ON
matching
V
V
V
5V
1.0%
1.0%
1.0%
3.0%
3.0%
3.0%
(max)
(max)
(max)
IN
IN
IN
2.5V
0V
a
a
e
; all other
À
Ó
e
2.2.4 Digital DC Characteristics The following specifications apply to the LM12434 and LM12 L 438 for V
V
5V
A
to T
D
À
limits T
Ó
e
e
e
25 C. (Notes 6, 7 and 8)
e
e
T T
J
3.3V , AGND
e
DGND
0V, unless otherwise specified. Boldface limits apply for T
A
MIN
MAX
T
J
§
A
Typical
Limits
Units
Symbol
Parameter
Conditions
(Note 10)
(Note 11)
(Limit)
a
a
a
e
e
e
e
À
5.5V 3.6V
Ó
Ó
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
All Digital Inputs
V
V
V
V
V
V
2.0
V (min)
V (max)
mA (max)
mA (max)
pF
IN(1)
IN(0)
IN(1)
IN(0)
A
D
a
À
4.5V 3.0V
0.8
A
D
e
e
À
Ó
I
I
5V 3.3V
0V
0.005
1.0
IN
IN
b
b
1.0
0.005
6
C
IN
a
a
e
e b
e b
e À
4.5V 3.0V
Ó
Ó
V
Logical ‘‘1’’ Output Voltage
V
V
D
OUT(1)
A
I
I
360 mA
10 mA
2.4
À
4.25 2.9
V (min)
V (min)
OUT
OUT
a
Ó
a
e
e
e À
4.5V 3.0V
V
I
Logical ‘‘0’’ Output Voltage
V
A
V
D
OUT(0)
0.4
V (max)
I
1.6 mA
OUT
e
OUT
b
b
TRI-STATE Output Leakage Current
É
V
0V
À
5V 3.3V
0.05
3.0
mA (max)
mA (max)
OUT
e
Ó
V
0.05
3.0
OUT
9
2.0 Electrical Specifications (Continued)
À
Ó
a
2.3 DIGITAL SWITCHING CHARACTERISTICS The following specifications apply to the LM12434 and LM12 L 438 for V
A
e
a e
À
Ó
5V 3.3V , AGND
Boldface limits apply for T
e
e
e
e
V
D
DGND
T
0V, C (load capacitance) on output lines
L
to T
80 pF unless otherwise specified.
25 C. (Notes 6, 7, and 9)
e
e
e
T
A
T
, all other limits for T
MAX
§
A
J
MIN
J
2.3.1 Standard Mode Interface (MICROWIRE/PLUSTM, SCI and SPI/QSPI)
Symbol
Typical
Limits
Units
Parameter
Conditions
(SeeFigure Below)
(Note 10)
(Note 11)
(Limit)
À
100 125
Ó
t
t
SCLK (Serial Clock) Period
ns (min)
ns (min)
1
2
CS Set-Up Time to First
Clock Transition
À
25 30
Ó
t
t
t
t
DI Valid Set-Up Time to Data
Capture Transition of SCLK
3
4
5
6
0
ns (min)
ns (min)
ns (max)
DI Valid Hold Time to Data
Capture Transition of SCLK
40
DO Hold Time from Data Shift
Transition of SCLK
À
70 120
Ó
CS Hold Time from Last SCLK
Transition in a Read or Write Cycle
(Excluding Burst Read Cycle)
25
3
ns (min)
t
t
CS Inactive to CS Active Again
CLK Cycle
7
8
(min)*
SCLK Idle Time between the
End of the Command Byte
Transfer and the Start of the
Data Transfer in Read Cycles
CLK Cycle
3
(min)*
*CLK is the main clock input to the device, pin number 24 in PLCC package or pin number 2 in SO package.
TL/H/11879–18
10
2.0 Electrical Specifications (Continued)
À
Ó
a
2.3 DIGITAL SWITCHING CHARACTERISTICS The following specifications apply to the LM12434 and LM12 L 438 for V
A
e
a e
À
Ó
5V 3.3V , AGND
Boldface limits apply for T
e
e
e
V
D
DGND
T
0V, C (load capacitance) on output lines
80 pF unless otherwise specified.
e
T 25 C. (Notes 6, 7, and 9) (Continued)
J
L
to T
e
e
e
T
, all other limits for T
§
A
J
MIN
MAX
A
2.3.2 8051 Interface Mode
Symbol
Typical
Limits
Units
Parameter
Conditions
(SeeFigure Below)
(Note 10)
(Note 11)
(Limit)
À
125 250
Ó
t
t
TXD (Serial Clock Period)
ns (min)
ns (min)
9
CS Set-Up Time to First
Clock Transition
10
À
25 40
Ó
t
11
t
12
t
13
t
14
Data in Valid Set-Up Time to
TXD Clock High
40
ns (min)
ns (min)
ns (max)
Data in Valid Hold Time
from TXD Clock High
À
40 90
Ó
Data Out Hold Time
from TXD Clock High
À
70 120
Ó
CS Hold Time from Last TXD
High in a Read or Write Cycle
(Excluding Burst Read Cycle)
À
25 50
Ó
ns (min)
t
t
CS Inactive to CS Active Again
CLK Cycle
15
3
3
(min)*
SCLK Idle Time between the
End of the Command Byte
Transfer and the Start of the
Data Transfer in Read Cycles
16
CLK Cycle
(min)*
*CLK is the main clock input to the device, pin number 24 in PLCC package or pin number 2 in SO package.
TL/H/11879–21
11
2.0 Electrical Specifications (Continued)
À
Ó
a
2.3 DIGITAL SWITCHING CHARACTERISTICS The following specifications apply to the LM12434 and LM12 L 438 for V
A
e
a e
À
Ó
5V 3.3V , AGND
Boldface limits apply for T
e
e
e
V
D
DGND
T
0V, C (load capacitance) on output lines
80 pF unless otherwise specified.
e
T 25 C. (Notes 6, 7, and 9) (Continued)
J
L
to T
e
e
e
T
, all other limits for T
§
A
J
MIN
MAX
A
2.3.3 TMS320 Interface Mode
Symbol
Typical
(Note 10)
Limits
Units
Parameter
SCLK (Serial Clock) Period
Conditions
(SeeFigure Below)
(Note 11)
(Limit)
À
125 167
Ó
t
t
t
t
ns (min)
ns (min)
ns (min)
22
23
24
25
À
30 50
Ó
FSX Set-Up Time to SCLK High
FSX Hold Time from SCLK High
10
0
Data in (DX) Set-Up
Time to SCLK Low
ns (min)
ns (min)
t
26
Data in DX Hold Time from
SCLK Low
À
30 120
Ó
À
80 100
Ó
t
27
t
28
t
29
FSR High from SCLK High
FSR Low from SCLK Low
ns (max)
ns (max)
120
90
SCLK High to Data
Out (DR) Change
ns (max)
TL/H/11879–23
12
2.0 Electrical Specifications (Continued)
À
Ó
a
2.3 DIGITAL SWITCHING CHARACTERISTICS The following specifications apply to the LM12434 and LM12 L 438 for V
A
e
a e
À
Ó
5V 3.3V , AGND
Boldface limits apply for T
e
e
e
V
D
DGND
T
0V, C (load capacitance) on output lines
80 pF unless otherwise specified.
e
T 25 C. (Notes 6, 7, and 9) (Continued)
J
L
to T
e
e
e
T
, all other limits for T
§
A
J
MIN
MAX
A
2
2.3.4 I C Bus Interface
2
The switching characteristics of the LM12434/8 for I C bus interface fully meets or exceeds the published specifications of the
2
I C bus. The following parameters given here are the timing relationships between SCL and SDA signals related to the
2
LM12434/8. They are not the I C bus specifications.
Symbol
Typical
Limits
Units
Parameter
SCL (Clock) Period
Conditions
(SeeFigure Below)
(Note 10)
(Note 11)
(Limit)
À
2500 10000
Ó
t
t
t
t
ns (min)
ns (min)
ns (max)
17
18
19
20
Data in Set-Up Time to SCL High
Data Out Stable after SCL Low
30
À
900 1400
Ó
SDA Low Set-Up Time to SCL
Low (Start Condition)
40
40
ns (min)
ns (min)
t
21
SDA High Hold Time after SCL
High (Stop Condition)
TL/H/11879–22
13
2.0 Electrical Specifications (Continued)
2.4 NOTES ON SPECIFICATIONS
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
a
Note 2: All voltages are measured with respect to GND, unless otherwise specified. GND specifies either AGND and/or DGND and Va specifies either V
and/
A
a
or V
.
D
a
or V a)), the current at that pin should be limited to
D
k
l
(V
Note 3: When the input voltage (V ) at any pin exceeds the power supply rails (V
IN
GND or V
IN
IN
A
5 mA. The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current of 5 mA, to simultaneously exceed the power
supply voltages.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
Jmax
junction to ambient thermal resistance), and T (ambient temperature). The maximum allowable power dissipation at any temperature is PD
(maximum junction temperature), H (package
JA
e
b
T
(T
)/
A
A
max
Jmax
e
H
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
Jmax
package, when board mounted, is 70 C/W and in the WM package, when board mounted, is 60 C/W.
150 C, and the typical thermal resistance (H ) of the V
§
JA
JA
§
§
Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.
a
Note 6: Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above V
or 5V below
a
A
GND will not damage the part. However, errors in the A/D conversion can occur if these diodes are forward biased by more than 100 mV. As an example, if V
is
A
s
4.5 V , the full-scale input voltage must be 4.6 V
DC
to ensure accurate conversions.
DC
TL/H/11879–5
must be connected together to the same power supply voltage and bypassed with separate capacitors at each Va pin to assure
conversion/comparison accuracy. Refer to Section 8.0 for a detailed discussion on grounding the DAS.
a
a
and V
D
Note 7: V
A
À
Ó
e
À
Ó
.
Note 8: Accuracy is guaranteed when operating the LM12434/LM12
L
438 at f
8 MHz 6 MHz
) given as 4.096V, the 12-bit LSB is 1 mV and the 8-bit/‘‘Watchdog’’ LSB is 19 mV.
b
CLK
b
V
REF
a
Note 9: With the test condition for V
REF
(V
a
REF
e
Note 10: Typicals are at T
25 C and represent most likely parametric norm.
§
Note 11: Limits are guaranteed to National’s AOQL (Average Output Quality Level).
A
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-
scale and zero. For negative integral linearity error the straight line passes through negative full-scale and zero. (See Figures 5b and 5c).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions
b
a
between 1 to 0 and 0 to 1 (see Figure 6).
À
Ó
Note 14: The DC common-mode error is measured with both the inverted and non-inverted inputs shorted together and driven from 0V to 5V 3.3V . The
À
Ó
measured value is referred to the resulting output value when the inputs are driven with a 2.5V 1.65V signal.
a
a
at the specified extremes.
Note 15: Power Supply Sensitivity is measured after Auto-Zero and/or Auto-Calibration cycle has been completed with V
and V
A
D
a
Note 16: V
REFCM
(Reference Voltage Common Mode Range) is defined as (V
V
REF
)/2. See Figures 3 and 4.
b
a
REF
Note 17: The device self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in a
g
repeatability uncertainty of 0.10 LSB.
e
Note 18: The Throughput Rate is for a single instruction repeated continuously while reading data during conversions with a serial clock frequency f
Ó
10 MHz
SCLK
À
8 MHz . Sequencer states 0 (1 clock cycle), 1 (1 clock cycle), 7 (9 clock cycles) and 5 (44 clock cycles) are used (see Figure 10) for a total of 56 clock cycles per
conversion. The Throughput Rate is f (MHz)/N, where N is the number of clock cycles/conversion.
CLK
Note 19: See AN-450 ‘‘Surface Mounting Methods and their Effect on Product Reliability’’ for other methods of soldering surface mount devices.
g
Note 20: Each input referenced to the other input sees a 4.096V (8.192 V ) sine wave. However the voltage at each input stays within the supply rails. This is
done by applying two sine waves with 180 phase shift and 4.096 V
p-p
(between GND and V a) to the inputs.
A
§
p-p
e
40 kHz on the remaining channels. 8192 conversions are performed on the channel with the 5 kHz signal. A special response is
Note 21: Multiplexer channel-to-channel crosstalk is measured by placing a sinewave with a frequency of f
e
5 kHz on one channel and another sinewave with a
IN
frequency of f
CROSSTALK
generated by doing a FFT on these samples. The crosstalk is then calculated by subtracting the amplitude of the frequency component at 40 kHz from the
amplitude of the fundamental frequency at 5 kHz.
Note 22: Interrupt 7 is set to return an out-of-standby flag 10 ms (typ) after the device is requested to come out of standby mode. However, characterization has
shown the devices will perform to their rated specifications in 2 ms.
14
3.0 Electrical Characteristics
TL/H/11879–6
FIGURE 1. Output Digital Code vs the Operating Input Voltage Range (General Case)
TL/H/11879–7
e
FIGURE 2. Output Digital Code vs the Operating Input Voltage Range for V
4.096V
REF
15
3.0 Electrical Characteristics (Continued)
TL/H/11879–8
FIGURE 3. V
REF
Operating Range (General Case)
TL/H/11879–9
a
e
5V
FIGURE 4. V
REF
Operating Range for V
A
16
3.0 Electrical Characteristics (Continued)
TL/H/11879–10
FIGURE 5a. Transfer Characteristic
TL/H/11879–11
FIGURE 5b. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles
17
3.0 Electrical Characteristics (Continued)
TL/H/11879–12
FIGURE 5c. Simplified Error Curve vs Output Code after Auto-Calibration Cycle
TL/H/11879–13
FIGURE 6. Offset or Zero Error Voltage
18
4.0 Typical Performance Characteristics
a
a
sign mode after auto-calibration unless otherwise specified. The performance for 8-bit
The following curves apply for 12-bit
sign and ‘‘watchdog’’ modes is equal to or better than shown. (Note 9)
Linearity Error Change
vs CLK Frequency
Linearity Error Change
vs Temperature
Linearity Error Change
vs Reference Voltage
TL/H/11879–14
19
4.0 Typical Performance Characteristics (Continued)
a
a
sign mode after auto-calibration unless otherwise specified. The performance for 8-bit
The following curves apply for 12-bit
sign and ‘‘watchdog’’ modes is equal to or better than shown. (Note 9)
Analog Supply Current
vs Temperature
*Digital Supply Current
vs Clock Frequency
*Digital Supply Current
vs Temperature
TL/H/11879–15
*Free-running conversion and SPI mode data
read at 200 ns SCLK period.
a
e
50X,
The following curves apply to the LM12L438 in 12-bit
a
T
25 C, V
§
V
D
3.3V, V
2.5V, f
6 MHz, f
2.5V
sign mode after auto-calibration unless othxerwise specified. R
0 dB, Sampling Rate
S
a
e
100 kHz.
e
e
e
e
e
e
8 MHz, V
IN
e
A
A
REF
CLK
SCLK
Unipolar Spectral Response with
10 kHz Sine Wave at 0 dB
Unipolar Spectral Response with
20 kHz Sine Wave at 0 dB
TL/H/11879–84
a
e
0 dB, Sampling Rate
e
25 C,
A
100 kHz.
The following curves apply for 12-bit
a
50X, T
V
V
D
5V, V
4.096V, f
8 MHz, f
4.096V
sign mode after auto-calibration unless otherwxise specified. R
§
S
a
e
e
e
e
e
e
10 MHz, V
IN
e
A
REF
CLK
SCLK
Unipolar Special Response
with 41.2 kHz Sine Wave
at 0 dB Reading Data
Unipolar Special Response
with 41.2 kHz Sine Wave
at 0 dB Reading Data
e
during Conversion f
10 MHz
between Conversions
SCLK
TL/H/11879–55
20
4.0 Typical Performance Characteristics (Continued)
a
a
The following curves apply for 12-bit
a
sign mode after auto-calibration unless otherwise specified.
e
Sampling Rate
e
e
e
e
e
e
e
10 MHz, V
IN
R
50X, T
25 C, V
V
D
5V, V
REF
4.096V, f
CLK
8 MHz, f
SCLK
4.096V
x
0 dB,
§
133.3 kHz.
S
A
A
e
Unipolar Signal-to-Noise
a
Unipolar Total
Harmonic Distortion
vs Input Frequency
Unipolar Signal-to-Noise Ratio
vs Input Frequency
Distortion
vs Input Frequency
nse
nse
Unipolar Two Tone Spectral
e
19.482 kHz Sine Wave
Response with f1
e
19.190 kHz and
f2
TL/H/11879
TL/H/11879–24
21
4.0 Typical Performance Characteristics (Continued)
a
a
The following curves apply for 12-bit
a
sign mode after auto-calibration unless otherwise specified.
e
e
Sampling Rate
e
e
e
e
e
e
g
IN
R
50X, T
25 C, V
§
133.3 kHz.
V
D
5V, V
4.096V, f
8 MHz, f
10 MHz, V
4.096V
x
0 dB,
S
A
A
REF
CLK
SCLK
e
Bipolar Signal-to-Noise
a
Bipolar Signal-to-Noise Ratio
vs Input Frequency
Distortion vs
Input Frequency
Bipolar Total Harmonic
Distortion vs Input Frequency
se
se
Bipolar Two Tone Spectral
e
19.482 kHz Sine Waves
Response with f1
e
19.190 kHz and
f2
TL/H/11879
TL/H/11879–26
22
5.0 Pin Descriptions
À
Ó
TABLE I. LM12 L 438 Pin Description
Pin Number
Pin Name
Description
PLCC
Pkg.
SO
Pkg.
1
7
DGND
Digital ground. This is the device’s digital supply ground connection. It should be connected
through a low resistance and low inductance ground return to the system power supply.
2
3
4
5
6
7
8
9
8
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
These are the eight analog inputs to the multiplexer. For each conversion to be performed, the
active channels are selected according to the instruction RAM programming. Any individual
channel can be selected for a single-ended conversion referenced to AGND, or any pair of
channels, whether adjacent or non adjacent, can be selected as a fully differential input pairs.
9
10
11
12
13
14
15
a
a
a
V (See
A
s
s
10
16
V
REF
Positive reference input. The operating voltage range for this input is 1V
V
REF
Figures 3 and4 ). In order to achieve 12-bit performance this pin should be by passed to AGND
at least with a parallel combination of a 10 mF and a 0.1 mF (ceramic) capacitor. The capacitors
should be placed as close to the part as possible.
b
b
a
s
V
REF
s
11
17
V
REF
Negative reference input. The operating voltage range for this input is 0 V
b
V
REF
1V (SeeFigures 3 and4 ). In order to achieve 12-bit performance, this pin should be bypassed
to AGND at least with a parallel combination of a 10 mF and a 0.1 mF (ceramic) capacitor. The
capacitors should be placed as close to the part as possible.
12
13
18
19
AGND
Analog ground. This is the device’s analog supply ground connection. It should be connected
through a low resistance and low inductance ground return to the system power supply.
a
V
A
Analog supply. This is the supply connection for the analog circuitry. The device operating supply
a
a
a
a
voltage range is 3.0V to 5.5V. Accuracy is guaranteed only if the V
and V
are
A
D
connected to the same potential. In order to achieve 12-bit performance, this pin should be
bypassed to AGND at least with a parallel combination of a 10 mF and a 0.1 mF (ceramic)
capacitor. The capacitors should be placed as close to the part as possible.
14
20
DGND
Digital ground. See above definition.
a
15
16
21
22
V
D
Digital supply. This is the supply connection for the analog circuitry. The device operating supply
a
a
and V
D
a
a
voltage range is 3.0V to 5.5V. The device accuracy is guaranteed only if the V
A
are connected to the same potential. In order to achieve 12-bit performance this pin should be
by passed to DGND at least with a parallel combination of a 10 mF and a 0.1 mF (ceramic)
capacitor. The capacitors should be placed as close to the part as possible.
17
23
P5
P1–P5 are the multi-function serial interface input or output pins that have different assignments
depending on the selected mode.
Serial interface input:
Standard:
8051:
2
I C:
SCLK
TXD
SCL
DR
TMS320:
18
19
24
25
P4
P3
Serial interface input/output: Standard:
8051:
DO
RXD
SDA
DR
2
I C:
TMS320:
Serial interface input:
Standard:
8051:
DI
CS
2
I C:
SAD2
DX
TMS320:
23
5.0 Pin Descriptions (Continued)
À
Ó
TABLE I. LM12 L 438 Pin Description (Continued)
Pin Number
Pin Name
Description
PLCC
Pkg.
SO
Pkg.
20
21
26
P2
P1
Serial interface input:
Serial interface input:
Standard:
8051:
2
I C:
CS
1
SAD1
FSX
TMS320:
27
Standard:
8051:
R/F (Clock rise/fall)
1
2
I C:
SAD0
FSR
TMS320:
22
23
28
1
MODESEL2
MODESEL1
Serial mode selection inputs. The logic states of these inputs determine the operation of
the serial mode as shown below. The standard mode covers the National’s MICROWIRE,
Motorola’s SPI and Hitachi’s SCl protocols.
MODESEL1, MODESEL2:
01
00
10
11
Standard mode
8051
2
I C
TMS320
24
25
2
3
CLK
INT
The device main clock input. The operating range of clock frequency is 0.05 MHz to
10.0 MHz. The device accuracy is guaranteed only for the clock frequencies indicated in
the specification tables.
Interrupt output. This is an active low output. An interrupt is generated any time a non-
masked interrupt condition takes place. There are seven different conditions that can
generate an interrupt. (Refer to Section 6.2.4). The interrupt is set high (inactive) by reading
the interrupt status register. This output can drive up to 100 pF of capacitive loads. An
external buffer should be used for driving higher capacitive loads.
26
4
SYNC
Synchronization input/output. SYNC is an input if the Configuration Register’s SYNC I/O bit
is ‘‘0’’ and output when the bit is ‘‘1’’. When sync is an input, a rising edge on this pin
causes the internal S/H to hold the input signal and a conversion cycle or a comparison
cycle (depending on the programmed instruction) to be started. (The conversion or
comparison actually begins on the rising edge of the CLK immediately following the rising
edge of sync.) When output, it goes high at the start of a conversion or a comparison cycle
and returns low when the cycle is completed. At power up the SYNC pin is set as an input.
When used as an output it can drive up to 100 pF of capacitive loads. An external buffer
should be used for driving higher capacitive loads.
27
5
STANDBYOUT
Stand-by output. This is an active low output. STANDBYOUT will be activated when the
À
Ó
LM12 L 438 is put into stand-by mode through the Configuration Register’s stand-by bit. It
is used to force any other devices in the system (signal conditioning circuitry, for example)
to go into power-down mode. This is done by connecting the ‘‘shutdown’’, ‘‘powerdown’’,
‘‘standby’’, etc. pins of the other ICs to STANDBYOUT. In those cases where the peripheral
ICs do not have the power-down inputs, STANDBYOUT can be used to turn off their power
through an electronic switch. Note that the logic polarity of the STANDBYOUT is the
opposite to that of the stand-by bit in the Configuration Register.
a
28
6
V
D
Digital supply. See above definition.
À
Ó
LM12434 Pin Description. (Same as LM12 L 438 with the exceptions of the following pins.)
À
Ó
LM12434 Pin Description (Same As LM12 L 438 with the exception of the following pins.)
b
a
6
7
12
13
MUXOUT
MUXOUT
Multiplexer outputs. These are the LM12434’s externally available analog MUX output pins.
Analog inputs are directed to these outputs based on the Instruction RAM programming.
b
a
8
9
14
15
S/H IN
S/H IN
Sample-and-hold inputs. These are the inverting and non-inverting inputs of the sample-
and-hold. LM12434 allows external analog signal conditioning circuits to be placed
between MUX outputs and S/H inputs.
24
6.0 Operational Information
6.1 FUNCTIONAL DESCRIPTION
aged, and a correction coefficient is created. After comple-
tion of either calibration mode, the offset correction coeffi-
cient is stored in an internal offset correction register.
À
Ó
The LM12434 and LM12 L 438 are multi-functional Data
Acquisition Systems that include a fully differential 12-bit-
plus-sign self-calibrating analog-to-digital converter (ADC)
À
Ó
The LM12434 and LM12 L 438’s overall linearity correction
is achieved by correcting the internal DAC’s capacitor mis-
match. Each capacitor is compared eight times against all
remaining smaller value capacitors and any errors are aver-
aged. A correction coefficient is then created and stored in
one of the thirteen linearity correction registers. A state ma-
chine, using patterns stored in 16-bit x 8-bit ROM, executes
each calibration algorithm.
with
a two’s-complement output format, an 8-channel
À
Ó
(LM12 L 438) or a 4-channel (LM12434) analog multiplex-
er, a first-in-first-out (FIFO) register that can store 32 con-
version results, and an Instruction RAM that can store as
many as eight instructions to be sequentially executed. The
LM12434 also has a differential multiplexer output and a
differential S/H input. All of this circuitry operates on only a
Once the converter has been calibrated, an arithmetic logic
unit (ALU) uses the offset correction coefficient and the 13
linearity correction coefficients to reduce the conversion’s
offset error and linearity error, in the background, during the
a
single 5V power supply. For simplicity, the DAS (Data Ac-
quisition System) abbreviation is used as a generic name for
À
Ó
the members of the LM12434 and LM12 L 438 family
thoughout this discussion.
a
a
sign conversions and
12-bit
‘‘watchdog’’ comparisons use only the offset coefficient. An
sign conversion. 8-bit
Figure 7 illustrates the functional block diagram or user pro-
gramming model of the DAS. Note that this diagram is not
meant to reflect the actual implementation of the internal
building blocks. The model consists of the following blocks:
a
needed for a 12-bit
8-bit
sign conversion requires less than half the time
a
sign conversion.
Diagnostic Mode
Ð A flexible analog multiplexer with differential output at
the front end of the device.
A diagnostic mode is available that allows verification of the
À
Ó
LM12 L 438’s operation. The diagnostic mode is disabled
in the LM12434. This mode internally connects the voltages
a
Ð A fully-differential, self-calibrating 12-bit
converter with sample and hold.
sign ADC
a
b
pins to the internal V
a
IN
S/H inputs. This mode is activated by setting the
present at the V
and V
REF
REF
Ð A 32-word FIFO register as the output data buffer.
b
and V
IN
Ð An 8-word instruction RAM that can be programmed to
repeatedly perform a series of conversions and compari-
sons on selected input channels.
Diagnostic bit (Bit 11) in the Configuration register to a ‘‘1’’.
More information concerning this mode of operation can be
found in Section 6.2.2.
Ð A series of registers for overall control and configuration
of DAS operation and indication of internal operational
status.
Watchdog Mode
In the watchdog mode no conversion is performed, but the
DAS samples an input and compares it with the values of
the two limits stored in the Instruction RAM. If the input
voltage is above or below the limits (as defined by the user)
an interrupt can be generated to indicate a fault condition.
The LM12434 and LM L 438’s ‘‘watchdog’’ mode is used
to monitor a single-ended or differential signal’s amplitude
and generate an output if the signal’s amplitude falls out-
sidde of a programmable ’‘window’’. Each watchdog instruc-
tion includes two limits. An interrupt can be generated if the
input signal is above or below either of the two limits. This
allows interrupt to be generated when analog voltage inputs
are ‘‘outside the window’’. After a ‘‘watchdog’’ mode inter-
rupt, the processor can then request a conversion on the
input signal and read the signal’s magnitude.
Ð Interrupt generation logic to request service from the
processor under specified conditions.
Ð Serial interface logic for input/output operations be-
tween the DAS and the processor. All the registers
shown in the diagram can be read and most of them can
also be written to by the user through the input/output
block.
À
Ó
Ð A controller unit that manages the interactions of the
different blocks inside the DAS and controls the conver-
sion, comparison and calibration sequences.
The DAS has 3 different modes of operation:
a
Ð 12-bit
sign conversion
a
Ð 8-bit
Ð 8-bit
sign conversion
Analog Input Multiplexer
a
sign comparison (also called ‘‘watchdog’’ mode)
The analog input multiplexer can be configured for any com-
bination of single-ended or fully differential operation. Each
input is referenced to AGND when a multiplexer channel
operates in the single-ended mode. Fully differential analog
input channels are formed by pairing any two channels to-
gether.
The fully differential 12-bit-plus-sign ADC uses a charge re-
distribution topology that includes calibration capabilities.
Charge re-distribution ADCs use a capacitor ladder in place
of a resistor ladder to form an internal DAC. The DAC is
used by a successive approximation register to generate
intermediate voltages between the voltages applied to
a. These intermediate voltages are com-
b
The LM12434’s multiplexer outputs and S/H inputs
V
REF
and V
REF
a
b
a
b
(MUXOUT , MUXOUT and S/H IN , S/H IN ) provide
the option for additional analog signal processing after the
multiplexer. Fixed-gain amplifiers, programmable-gain am-
plifiers, filters, and other processing circuits can operate on
the multiplexer output signals before they are applied to the
ADC’s S/H inputs. If external processing is not used, con-
pared against the sampled analog input voltage as each bit
is charged.
Conversion accuracy is ensured by an internal auto-calibra-
tion system. Two different calibration modes are available;
one compensates for offset voltage, or zero error, while the
other corrects the ADC’s linearity and offset errors.
a
a
b
nect MUXOUT to S/H IN and MUXOUT to S/H IN .
b
When correcting offset only, the offset error is measured
once and a correction coefficient is created. During the full
calibration, the offset error is measured eight times, aver-
25
6.0 Operational Information (Continued)
TL/H/11879–27
À
Ó
(a) The LM12 L 438
TL/H/11879–28
(b) The LM12434
FIGURE 7. The LM12 L 438 and LM12434 Functional Block Diagram (Programming Model)
À
Ó
26
6.0 Operational Information (Continued)
Acquisition Time
Microprocessor overhead is reduced through the use of the
internal conversion FIFO. Thirty-two consecutive conver-
sions can be completed and stored in the FIFO without any
microprocessor intervention. The microprocessor can, at
any time, interrogate the FIFO and retrieve its contents. It
À
Ó
The LM12434 and LM12 L 438’s internal S/H is designed
Ó
[
to operate at its minimum acquisition time (1.125 1.5 ms
a
for a 12-bit
sign conversion) when the source imped-
s
À
Ó
À Ó
8 6
ance, R , is less than or equal to 60 80 X (f
S
MHz). When 60 80
CLK
À
Ó
can also wait for the LM12434 and LM12 L 438 to issue an
interrupt when the FIFO is full or after any number ( 32) of
k
s
nal S/H’s acquisition time can be increased to a maximum
À
Ó
À
Ó
X
R
S
4.17 5.56 kX, the inter-
s
conversions have been stored.
À
Ó
a
e
À Ó
8 6 MHz) to
of 4.88 6.5 ms (12
sign bits, f
CLK
provide sufficient time for the sampling capacitor to charge.
See Section 6.2.1 (Instruction RAM ‘‘00’’) Bits 12–15 for
more information.
Configuration Register
The CONFIGURATION Register is the main ‘‘control panel’’
of the DAS. Writing 1s and 0s to the different bits of the
Configuration Register commands the DAS start or stop the
sequencer, reset the pointers and flags, go into ‘‘standby’’
mode for low power consumption, calibrate offset and lin-
earity, and select sections of the RAM.
Instruction Register
The INSTRUCTION RAM is divided into 8 separate words,
each with 48 (3 x 16) bit length. Each word is separated into
three 16-bit sections. Each word has a unique address and
different sections of the instruction word are selected by the
2-bit RAM pointer (RP) in the configuration register. As
shown in Figure 7, the Instruction RAM sections are labeled
Other Registers
The INTERRUPT ENABLE Register lets the user activate up
to 7 sources for interrupt generation (refer to Section 6.2.3).
It also holds two user-programmable values. One is the
number of conversions to be stored in the FIFO register
before the generation of the Data Ready interrupt. The other
value is the instruction number that generates an interrupt
when the sequencer reaches that instruction.
Ý
Instructions, Limits 1 and Limits 2. The Instruction sec-
tion holds operational (12-bit
Ý
a
a
sign or watch-
sign, 8-bit
dog) information such as the input channels to be selected,
the mode of operation to be performed for each instruction,
and the duration of the acquisition period. The other two
sections are used in the watchdog mode and the user-
defined limits are stored in them. Each watchdog instruction
has 2 limits associated with it (usually a low limit and a high
limit, but two low limits or two high limits may be pro-
grammed instead). The DAS starts executing from instruc-
tion 0 and moves through the next instructions up to any
user-specified instruction and then ‘‘loop back’’ to instruc-
tion 0. It is not necessary to execute all 8 instructions in the
instruction loop. The cycle may be repeatedly executed until
stopped by the user. The processor should access the In-
struction RAM only when the instruction sequencer is
stopped.
The INTERRUPT STATUS and LIMIT STATUS Registers
are ‘‘Read only’’ registers. They are used as vectors to indi-
cate which conditions have generated the interrupt and
what watchdog limit boundaries have been passed. Note
that the bits are set in the status registers upon occurrence
of their corresponding interrupt conditions, regardless of
whether the condition is enabled for external interrupt gen-
eration.
The TIMER Register can be programmed to insert a delay
before execution of each instruction. A bit in the instruction
register enables or disables the insertion of the delay before
the execution of an instruction.
FIFO Register
Serial I/O
The FIFO Register stores the conversion results. This regis-
ter is ‘‘Read only’’ and all the locations are accessed
through a single address. Each time a conversion is per-
formed the result is stored in the FIFO and the FIFO’s inter-
nal write pointer points to the next location. The pointer rolls
back to location 1 after a Write to location 32. The same
flow occurs when reading from the FIFO. The internal FIFO
Writes and the external FIFO Reads do not affect each oth-
er’s pointer locations.
A very flexible serial synchronous interface is provided to
facilitate reading from and writing to the LM12434 and
À
Ó
LM12 L 438’s registers. The communication between the
À
Ó
LM12434 and LM12 L 438 and microcontrollers, micro-
processors and other circuitry is accomplished through this
serial interface. The serial interface is designed to directly
communicate with the synchronous serial interfaces of the
most popular microprocessors with no extra hardware re-
quirement. The interface has been also designed to simplify
software development.
27
6.0 Operational Information (Continued)
Instruction RAM
e
(Read/Write)
e
e
00
RP
Limits
10
RP
Limits
01
RP
Ý
Ý
1
2
Instructions
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
0000
0001
0010
0011
0100
0101
0110
0111
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
0000
0001
0010
0011
0100
0101
0110
0111
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
0000
0001
0010
0011
0100
0101
0110
0111
(Read/Write)
1000
e
e
RP
ADD
RAM Pointer
A3, A2, A1, A0
e
e
e
e
e
CONFIGURATION REGISTER
INTERRUPT ENABLE REGISTER
INTERRUPT STATUS REGISTER
TIMER REGISTER
ADD
ADD
ADD
ADD
ADD
(Read/Write)
1001
(Read Only)
1010
(Read/Write)
1011
(Read Only)
CONVERSION FIFO
1100
(32 Locations, 1 address)
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
(Read Only)
e
1101
LIMIT STATUS REGISTER
ADD
À
Ó
FIGURE 8. LM12434 and LM12 L 438 User Accessible Registers
28
6.0 Operational Information (Continued)
6.2 INTERNAL USER-ACCESSIBLE REGISTERS
each of the remaining instructions. With the PAUSE bit set
to ‘‘1’’ in instruction 0, no PAUSE Interrupt (INT 5) is gener-
ated the first time the Sequencer executes Instruction 0.
When the Sequencer encounters a LOOP bit or completes
all eight instructions, Instruction 0 is retrieved and decoded.
A set PAUSE bit in Instruction 0 now halts the Sequencer
À
Ó
Figure 8 shows the LM12434 and LM12 L 438 internal user
accessible registers. Figure 9 shows the bit assignment for
each register. All the registers are accessible through the
serial interface bus. Following are the descriptions of the
registers and their bit assignments.
e
before the instruction is executed. If Pause
tion loop continues to execute.
0, the instruc-
6.2.1 Instruction RAM
The instruction RAM holds up to eight sequentially execut-
able instructions. Each 48-bit long instruction is divided into
three 16-bit sections. READ and WRITE operations can be
issued to each 16-bit section using the instruction’s address
and the 2-bit ‘‘RAM pointer’’ in the Configuration register.
The eight instructions are located at addresses 0000
through 0111. They can be accessed and programmed in
random order.
Bits 2–4 select which of the eight input channels (IN0–IN7)
À
Ó
will be the non-inverting inputs to the LM12 L 438’s ADC.
(See Table III.) They select which of the four input channels
(for IN0–IN3) will be the non-inverting inputs to the
LM12434’s ADC. (See Table IV.)
Bits 5–7 select which of the seven input channels (IN1 to
À
Ó
IN7) will be the inverting inputs to the LM12 L 438 ADC.
(See Table III.) They select which of the three input chan-
nels (IN1–IN4) will be the inverting inputs to the LM12434’s
ADC. (See Table IV.) Fully differential operation is created
by selecting two multiplexer channels, one non-inverting
and the other inverting. A code of ‘‘000’’ selects ground as
the inverting input for single ended operation.
Read/Write Operations
Any Instruction RAM READ or WRITE can affect the se-
quencer’s operation.
Therefore, the Sequencer should be stopped by setting the
RESET bit to a ‘‘1’’ or by resetting the START bit in the
Configuration Register and waiting for the current instruction
to finish execution before any Instruction RAM READ or
WRITE is initiated.
Bit 8 is the SYNC bit. Setting Bit 8 to ‘‘1’’ causes the Se-
quencer to hold operation at the internal S/H’s acquisition
cycle and to wait until a rising edge appears at the SYNC
pin. When a rising edge appears, the S/H goes into the
‘‘Hold’’ mode and the ADC begins to perform a conversion
on the next rising edge of CLK. To make the SYNC pin
serve as an input, the Configuration register’s ‘‘SYNC I/O’’
bit (Bit 7) must be set to a ‘‘0’’. With SYNC configured as an
input, it is possible to synchronize the start of a conversion
to external events. When SYNC pin is defined as an output
A soft RESET should be issued by writing a ‘‘1’’ to the Con-
figuration Register’s RESET bit after any READ or WRITE to
the Instruction RAM.
The three sections in the Instruction RAM are selected by
the Configuration Register’s 2-bit ‘‘RAM Pointer’’, bits D8
and D9. The first 16-bit Instruction RAM section is selected
with the RAM Pointer equal to ‘‘00’’. This section can be
programmed for multiplexer channel selection, conversion
resolution, watchdog mode operation, timer or external
SYNC use, pause in instruction and loop bit as described
e
must not be set to 1.
(SYNC I/O bit
1) the SYNC bit in the instruction registers
À
Ó
When the LM12434 and LM12 L 438 are used in the
‘‘watchdog’’ mode with external synchronization, two rising
edges on the SYNC input are required to initiate the two
comparisons that are performed during a watchdog instruc-
tion. The first rising edge initiates the comparison of the
Ý
later. The second 16-bit section holds ‘‘watchdog’’ limit 1,
its sign, and a bit that determines whether an interrupt can
be generated when the input is greater than or less than
Ý
Ý
limit 1. The third 16-bit section holds ‘‘watchdog’’ limit 2,
Ý
selected analog input signal with Limit 1 (found in Instruc-
tion RAM ‘‘01’’) and the second rising edge initiates the
its sign, and the ‘‘greater than/less than’’ selection bit.
e
Ý
2
comparison of the same analog input signal with Limit
(found in Instruction RAM ‘‘10’’).
Instruction RAM, Bank 1, RP
00
Bit 0 is the LOOP bit. After an instruction with Bit 0 set to a
‘’1’’ is executed, the sequencer will loop back to instruction
0. The next instruction to be executed will be instruction 0.
Bit 9 is the TIMER bit. When Bit 9 is set to ‘‘1’’, the Se-
quencer will halt until the internal 16-bit Timer counts down
to zero. During this time interval, no ‘‘watchdog’’ compari-
sons or analog-to-digital conversions will be performed.
Bit 1 is the PAUSE bit. When the PAUSE bit is set (‘‘1’’), the
Sequencer will stop after reading the current instruction.
The instruction will not execute at this point, and the START
bit in the Configuration register will reset to ‘‘0’’. Setting the
PAUSE also causes an interrupt to be issued. The Sequenc-
er is restarted by placing a ‘‘1’’ in the Configuration regis-
ter’s Bit 0 (Start bit).
Bit 10 selects the ADC conversion resolution. Setting Bit 10
a
to ‘‘1’’ selects 8-bit
a
sign and resetting to ‘‘0’’ selects 12-
bit
sign.
Bit 11 is the ‘‘watchdog’’ comparison mode enable bit.
When operating in the ‘‘watchdog’’ comparison mode, the
selected analog input signal is compared with the program-
mable values stored in Limit 1 and Limit 2 (see Instruc-
tion RAM ‘‘01’’ and Instruction RAM ‘‘10’’). Setting Bit 11 to
‘‘1’’ causes two comparisons of the selected analog input
signal, one with each of the two stored limits. When Bit 11 is
a
sign (depending on
the state of Bit 10 of Instruction RAM ‘‘00’’) conversion of
the input signal can take place.
After the Instruction RAM has been programmed and the
RESET bit is set to ‘‘1’’, the Sequencer retrieves Instruction
0, decodes it, and waits for a ‘‘1’’ to be placed in the Config-
uration register’s START bit. The START bit value of ‘‘1’’
‘‘overrides’’ the action of Instruction 0’s PAUSE bit when
the Sequencer is started. Once started, the Sequencer exe-
cutes Instruction 0 and retrieves, decodes, and executes
Ý
Ý
a
reset to ‘‘0’’, an 8-bit
sign or 12-bit
29
6.0 Operational Information (Continued)
A4 A3 A2 A1
Purpose
Type D15 D14 D13 D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
to
1
0
R/W
b
a
Instruction RAM
Acquisition
Watch-
dog
S/H IN
S/H IN
8/12 Timer Sync
Pause Loop
e
b
a
(MUXIN )*
(RAM Pointer
00)
Time
(MUXIN )*
0
0
1
0
1
0
0
to
1
R/W
Instruction RAM
l
l
k
k
Ý
Ý
Don’t Care
/
/
Sign
Sign
Limit
Limit
1
2
e
(RAM Pointer
01)
0
0
1
0
1
0
0
to
1
R/W
Instruction RAM
Don’t Care
e
(RAM Pointer
10)
0
1
1
0
1
0
Configuration
Register
R/W
Test
RAM
Pointer
SYNC A/Z Each
Stand- Full
by CAL
Auto-
Zero
²
0
Don’t Care
DIAG
I/S
Reset Start
e
0
I/O
Cycle
R/W
Instruction
Number to
Generate
INT7
X
INT5 INT4 INT3 INT2 INT1 INT0
Number of Conversion
Results in FIFO to
Interrupt Enable
Register
1
1
0
0
0
1
0
Generate Interrupt (INT2)
Interrupt (INT1)
R
Instruction
Number
being
INST7
X
INST5 INST4 INST3 INST2 INST1 INST0
Number of Unread
Conversion Results
in FIFO
Interrupt Status
Register
1
Executed
Timer
R/W
1
1
0
1
1
0
1
0
Timer Preset High Byte
Timer Preset Low Byte
Conversion Data: LSBs
Register
Instruction
Number or
Extended
Sign
Conversion
FIFO
Conversion
Data: MSBs
R
R
Sign
Limit Status
Register
Ý
Limit 2: Status
Ý
Limit 1: Status
1
1
0
1
*LM12434 (Refer to Table IV).
²
À
X No interrupt is associated with this bit. When programming the interrupt Enable Register, bit-6 is a don’t care condition.
Ó
438 only. Must be set to ‘‘0’’ for the LM12434.
LM12
L
À
Ó
FIGURE 9. Bit Assignments for LM12434 and LM12 L 438 Internal Registers
30
6.0 Operational Information (Continued)
CONFIGURATION REGISTER (Read/Write):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
Diag.
Test
RAM
Sync
I/O
A/Z Each
Cycle
I/S
Stand-
by
Full
Cal
Auto
Zero
Reset
Start
Pointer
D0:
D1:
Start: 0 stops the instruction execution. 1 starts the instruction execution.
Reset: When set to 1, resets Start bit; also resets all the bits in status registers and resets the instruction pointer to
zero. D1 will then automatically reset itself to zero after 2 clock pulses.
D2:
D3:
D4:
Auto-Zero: When set to 1 a long (8-cycle) auto-zero calibration cycle is performed.
Full Calibration: When set to 1 a full calibration cycle (linearity and auto-zero) is performed.
Standby: When set to 1 the chip goes to low-power standby mode. Resetting the bit will return the chip to active
mode after a short delay.
e
Ý
D5:
I/S: Instruction or extended sign. 0
Bits 13–15 of the conversion result hold the instruction number to which the
Bits 13–15 of the result hold the extended sign bit.
A/Z each Cycle: When set to 1 a short auto-zero cycle is performed before each conversion.
e
result belongs; 1
D6:
D7:
e
e
Sync pin is output.
Sync I/O: 0
Sync pin is input: 1
e
e
e
Limits 1, 10 Limits 2.
Ý
Ý
D9–D8: RAM Pointer: Selects the sections of the instruction RAM, 00
Instruction, 01
This bit is used for production testing and must be kept zero for normal operation.
D10:
D11:
À
Ó
Diagnostic: When set to 1, the LM12 L 438 will perform a diagnostic conversion along with a properly selected
instruction. This mode is not available on the LM12434.
D15–D12: Don’t Care.
INSTRUCTION RAM (Read/Write):
Instruction:
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
b
a
Acquisition Time
Watchdog
8/12
Timer
Sync
MUXIN
MUXIN
Pause
Loop
e
e
Ý
D0:
D1:
Loop: 0
Go to next instruction; 1
Loop back to in instruction 0.
e
Pause; don’t do the instruction. The start bit in the Configuration register resets to 0 when
e
Pause: 0
No pause; 1
a pause encountered; a 1 written to the Start bit restarts the instruction execution.
a
À Ó
D4–D2: MUXIN : For the LM12 L 438, these bits select which input channel is connected to the ADC’s non-inverting input.
a
For the LM12434, they select which input channel is connected to MUXOUT
.
b
À Ó
D7–D5: MUXIN : For the LM12 L 438, these bits select which input channel is connected to the ADC’s inverting input. For
b
the LM12434, they select which input channel is connected to MUXOUT
.
e
(comparison) timing are controlled by an external signal applied to SYNC pin.
e
SYNC is an input; S/H and conversion
D8:
D9:
Sync: 0
Normal operation, internal timing, SYNC is an output. 1
e
e
Instruction execution does not begin until timer counts down to
Timer: 0
zero.
Timer is not used for this instruction; 1
e
a
e
a
sign resolution.
D10:
D11:
8/12: 0
12-bit
sign resolution. 1
8-bit
e
e
Instruction performs watchdog compari-
Watchdog: 0
sons.
Conventional conversion (no watchdog comparison); 1
D15–D12: Acquisition Time: Determines S/H acquisition time
a
e
a
a
e
a
sign: (9 2D) clock cycles. For 8-bit
Contents of D15–D12.
a
a
sign: (2 2D) clock cycles.
For 12-bit
Where D
For 12-bit
For 8-bit
t
t
c
c
[
]
]
[ ]
f MHz .
CLK
sign: Choose D for D
sign: Choose D for D
Input source resistance.
0.45 x R kX
S
[
[ ]
f MHz .
CLK
0.36 x R kX
S
Where R
S
À
Ó
FIGURE 9. Bit Assignments for LM12434 and LM12 L 438 Internal Registers (Continued)
31
6.0 Operational Information (Continued)
INSTRUCTION RAM (Read/Write): (Continued)
Ý
Limits 1 & 2
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
l
k
Don’t Care
/
Sign
Limit
D7–D0: Limit: 8-bit limit value.
e
e
Negative.
D8:
D9:
Sign: Sign of limit value, 0
Positive; 1
l
/
interrupt.
k
: High Limit/Low limit. 0
e
e
Inputs higher than limit generate
Inputs lower than limit generate interrupt, 1
D15–D10: Don’t Care.
INTERRUPT ENABLE REGISTER (Read/Write):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Number of Conversion
Results in FIFO to
Instruction Number
to Generate
INT7
X
INT5
INT4
INT3
INT2
INT1
INT0
Generate Interrupt (INT2)
Interrupt (INT1)
Ý
Bits
D0:
D1:
0 to 7 enable interrupt generation for the following conditions when the bit is set to 1.
INT0: Generates an interrupt when a limit is passed in watchdog mode.
INT1: Generates an interrupt when the sequencer has loaded the instruction number contained in bits D10, D9, and
D8 of the Interrupt Enable register.
D2:
INT2: Generates an interrupt when the number of conversion results in the FIFO is equal to the programmed value
(D15–D11).
D3:
D4:
D5:
D6:
D7:
INT3: Generates an interrupt when an auto-zero cycle is completed.
INT4: Generates an interrupt when a full calibration cycle is completed.
INT5: Generates an interrupt when a pause condition is encountered.
This bit is a don’t care condition. No interrupt is associated with this bit.
INT7: Generates an interrupt when the chip is returned from standby and is ready for operation.
D10–D8: Programmable instruction number used to generate an interrupt when that instruction has been reached.
D15–D11: Programmable number of conversion results in the FIFO to generate an interrupt.
TIMER REGISTER (Read/Write):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
e
N
Timer Preset Value
The Timer delays the execution of an instruction if the Timer bit is set in that instruction.
The time delay is:
e
c
a
N) 2
[ ]
Clock Cycles
Delay
(32
À
Ó
FIGURE 9. Bit Assignments for LM12434 and LM12 L 438 Internal Registers (Continued)
32
6.0 Operational Information (Continued)
FIFO REGISTER (Read only):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Instruction Number
or Extended Sign
Sign
Conversion Result
D11–D0: Conversion Result:
a
a
For 12-bit
For 8-bit
sign: 12-bit result value
e
e
1110
sign: D11–D4
result value, D3–D0
e
e
Negative
D12:
Sign: Conversion result sign bit, 0
Positive, 1
D15–D13: Instruction number associated with the conversion result or the extended sign bit for 2’s complement arithmetic,
selected by bit D5 (Channel Mask) of the Configuration register.
INTERRUPT STATUS REGISTER (Read only):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Number of Unread Results
in FIFO
Instruction Number
Being Executed
INST7
X
INST5
INST4
INST3
INST2
INST1
INST0
Ý
Bits 0 to 7 are interrupt flags (vectors) that will be set to 1 when the following conditions occur. The bits are set to 1 whether
the interrupt is enabled or disabled in the Interrupt Enable register. The bits are reset to 0 when the register is read, or by a
device reset through the Configuration register.
D0:
D1:
INST0: Is set to 1 when a limit is passed in watchdog mode.
INST1: Is set to 1 when the sequencer has loaded the instruction number contained in bits D10, D9, and D8 of the
Interrupt Enable register.
D2:
INST2: Is set to 1 when number of conversion results in FIFO is equal to the programmed value (D15–D11) in the
Interrupt Enable Register.
D3:
D4:
D5:
D6:
D7:
INST3: Is set to 1 when an auto-zero cycle is completed.
INST4: Is set to 1 when a full calibraton cycle is completed.
INST5: Is set to 1 when a pause condition is encountered.
Don’t care.
INST7: Is set to 1 when the chip is returned from standby and is ready.
D10–D8: Holds the instruction number presently being executed or will be executed following a Pause or Timer delay.
D15–D11: Holds the number of conversion results that have been put in the FIFO but that have not yet been read by the user.
LIMIT STATUS REGISTER (Read only):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ý
Limit 2: Status
Ý
Limit 1: Status
The bits in this register are limit flags (vectors) that will be set to 1 when a limit is passed. The bits are associated to individual
instruction limits as indicated below.
Ý
Ý
D0: Limit 1 of Instruction 0 is passed.
Ý
Ý
D1: Limit 1 of Instruction 1 is passed.
Ý
Ý
D2: Limit 1 of Instruction 2 is passed.
Ý
Ý
D3: Limit 1 of Instruction 3 is passed.
Ý
Ý
D4: Limit 1 of Instruction 4 is passed.
Ý
Ý
D5: Limit 1 of Instruction 5 is passed.
Ý
Ý
D6: Limit 1 of Instruction 6 is passed.
Ý
Ý
D7: Limit 1 of Instruction 7 is passed.
Ý
Ý
D8: Limit 2 of Instruction 0 is passed.
Ý
Ý
D9: Limit 2 of Instruction 1 is passed.
Ý
Ý
D10: Limit 2 of Instruction 2 is passed.
Ý
Ý
D11: Limit 2 of Instruction 3 is passed.
Ý
Ý
D12: Limit 2 of Instruction 4 is passed.
Ý
Ý
D13: Limit 2 of Instruction 5 is passed.
Ý
Ý
D14: Limit 2 of Instruction 6 is passed.
Ý
Ý
D15: Limit 2 of Instruction 7 is passed.
À
Ó
FIGURE 9. Bit Assignments for LM12434 and LM12 L 438 Internal Registers (Continued)
33
6.0 Operational Information (Continued)
Bits 12–15 store the user-programmable acquisition time.
The Sequencer keeps the internal S/H in the acquisition
mode for a fixed number of clock cycles (nine clock cycles,
e
01
Instruction RAM, Bank 2 RP
The second Instruction RAM section is selected by placing
‘‘01’’ in Bits 8 and 9 of the Configuration register.
a
sign conversions or ‘‘watchdog’’ comparisons) plus a
for 12-bit
a
sign conversions and two clock cycles for 8-bit
Ý
Bits 0–7 hold ‘‘watchdog’’ limit 1. When Bit 11 of Instruc-
tion RAM ‘‘00’’ is set to ‘‘1’’, the LM12434 and
LM12 L 438 performs a ‘‘watchdog’’ comparison of the
a
variable number of clock cycles equal to twice the value
stored in Bits 12–15. Thus, the S/H’s acquisition time is (9
À
Ó
Ý
sampled analog input signal with the limit 1 value first,
followed by a comparison of the same sampled analog input
Ý
signal with the value found in limit 2 (Instruction RAM
‘‘10’’).
a
2D) clock cycles for 12-bit
a
2D) clock cycles for 8-bit
a
a
sign conversions and (2
sign conversions or ‘‘watch-
dog’’ comparisons, where D is the value stored in Bits 12–
15. The minimum acquisition time compensates for the typi-
cal internal multiplexer series resistance of 2 kX, and any
additional delay created by Bits 12–15 compensates for
Ý
Bit 8 holds limit 1’s sign.
Bit 9’s state determines the limit condition that generates a
‘‘watchdog’’ interrupt. A ‘‘1’’ causes a voltage greater than
Ý
limit 1 to generate an interrupt, while a ‘‘0’’ causes a volt-
age less than limit 1 to generate an interrupt.
À
Ó
source resistances greater than 60X 80X . The necessary
acquisition time is determined by the source impedance at
k
and the clock frequency is 8 MHz, the value stored in bits
Ý
the multiplexer input. If the source resistance R
60X
S
Bits 10–15 are not used.
l
tions determine the value that should be stored in
12–15 (D) can be 0000. If R
60X, the following equa-
S
e
Instruction RAM, Bank 3, RP
10
The third Instruction RAM section is selected by placing
‘‘10’’ in Bits 8 and 9 of the Configuration register.
bits 12–15.
e
D
D
0.45 x R x f
S
CLK
a
for 12-bits
sign
Ý
Bits 0–7 hold ‘‘watchdog’’ limit 2. When Bit 11 of Instruc-
tion RAM ‘‘00’’ is set to ‘‘1’’, the LM12434 and
LM12 L 438 performs a ‘‘watchdog’’ comparison of the
e
0.36 x R x f
S
CLK
a
a
for 8-bits
sign and ‘‘watchdog’’
À
Ó
Ý
sampled analog input signal with the limit 1 value first (In-
struction RAM ‘‘01’’), followed by a comparison of the same
Ý
sampled analog input signal with the value found in limit 2.
R
is in kX and f
is in MHz. Round the result to the next
S
CLK
higher integer value. If the value of 0 obtained from the
expressions above is greater than 15, it is advisable to lower
the source impedance by using an analog buffer between
the signal source and the LM12 L 438’s multiplexer inputs.
The value of D can also be used to compensate for the
settling or response time of external processing circuits con-
nected between the LM12434’s MUXOUT and S/H IN pins.
Ý
Bit 8 holds limit 2’s sign.
À
Ó
Bit 9’s state determines the limit condition that generates a
‘‘watchdog’’ interrupt. A ‘‘1’’ causes a voltage greater than
Ý
limit 2 to generate an interrupt, while a ‘‘0’’ causes a volt-
age less than limit 2 to generate an interrupt.
Ý
Bits 10–15 are not used.
À
Ó
TABLE III. LM12 L 438 Operating Mode Input Channel Selection through Input Multiplexer
Normal Operating Mode
Non-Inverting Input
Channel Selection Bits
in Instruction Register
D4, D3, D2
Input Channel to Be
Connected to A/D
Non-Inverting Input
Inverting Input
Channel Selection Bits
in Instruction Register
D7, D6, D5
Input Channel to Be
Connected to A/D
Inverting Input
a
b
)
(IN
)
(IN
000
001
010
011
100
101
110
111
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
000
001
010
011
100
101
110
111
GND
IN1
IN2
IN3
IN4
IN5
IN6
IN7
34
6.0 Operational Information (Continued)
TABLE IV. LM12434 Input Channel Selection through Input Multiplexer
Normal Operating Mode
Non-Inverting Input
Channel Selection Bits
in Instruction Register
D4, D3, D2
Input Channel to Be
Inverting Input
Channel Selection Bits
in Instruction Register
D7, D6, D5
Input Channel to Be
Connected to MUX
Inverting Output
Connected to MUX
Non-Inverting Output
a
b
)
(MUXOUT
)
(MUXOUT
GND
IN1
000
001
010
011
1XX
IN0
000
001
010
011
1XX
IN1
IN2
IN2
IN3
IN3
None
None
À
Ó
TABLE V. LM12 L 438 Diagnostic Mode Input Channel Selection through Input Multiplexer
Diagnostic Mode
Non-Inverting Input
Channel Selection Bits
in Instruction Register
D4, D3, D2
Input Channel to Be
Connected to A/D
Non-Inverting Input
Inverting Input
Channel Selection Bits
in Instruction Register
D7, D6, D5
Input Channel to Be
Connected to A/D
Inverting Input
a
b
(IN
)
(IN
)
000
001
010
011
100
101
110
111
None
000
001
010
011
100
101
110
111
None
a
b
V
REF
V
REF
IN2
IN2
IN3
IN4
IN5
IN6
IN7
IN3
IN4
IN5
IN6
IN7
35
6.0 Operational Information (Continued)
6.2.2 Configuration Register
analog circuitry power supply current, and preserves all in-
ternal RAM contents. After writing a ‘‘0’’ to the Standby bit,
the DAS returns to an operating state identical to that
caused by exercising the RESET bit. A Standby completion
interrupt is issued after a power-up delay to allow the analog
circuitry to settle. The Sequencer should be restarted only
after the Standby completion interrupt is issued (see Note
22). The Instruction RAM can still be accessed through read
The Configuration register is a 16-bit control register with
read/write capability. It acts as the LM12434’s and
À
Ó
LM12 L 438’s ‘‘control panel’’ holding global information
as well as start/stop, reset, self-calibration, and stand-by
commands.
Bit 0 is the START/STOP bit. Reading Bit 0 returns an indi-
cation of the Sequencer’s status. A ‘‘0’’ indicates that the
Sequencer is stopped and waiting to execute the next in-
struction. A ‘‘1’’ shows that the Sequencer is running. Writ-
ing a ‘‘0’’ halts the Sequencer when the current instruction
has finished execution. The next instruction to be executed
is pointed to by the instruction pointer found in the status
register. Writing a ‘‘1’’ to Bit 0 restarts the Sequencer with
the instruction currently pointed to by the instruction pointer.
(See Bits 8–10 in the Interrupt Status register.)
À
Ó
and write operations while the LM12434 and LM12 L 438
are in Standby Mode.
Bit 5 is the Channel Address Mask. If Bit 5 is set to a ‘‘1’’,
Bits 13–15 in the conversion FIFO will be equal to the sign
bit (Bit 12) of the conversion data. Resetting Bit 5 to a ‘‘0’’
causes conversion data Bits 13 through 15 to hold the in-
struction pointer value of the instruction to which the con-
version data belongs.
Bit 6 selects a ‘‘short’’ auto-zero correction for every con-
version. The Sequencer automatically inserts an auto-zero
before every conversion or ‘‘watchdog’’ comparison if Bit 6
is set to ‘‘1’’. No automatic correction will be performed if Bit
6 is reset to ‘‘0’’.
Bit 1 is the DAS’ system RESET bit. Writing a ‘‘1’’ to Bit 1
stops the Sequencer (resetting the Configuration register’s
START/STOP bit), resets the Instruction pointer to ‘‘000’’
(found in the Interrupt Status register), clears the Conver-
sion FIFO, and resets all interrupt flags. The RESET bit will
return to ‘‘0’’ after two clock cycles unless it is forced high
by writing a ‘‘1’’ into the Configuration register’s Standby bit.
A reset signal is internally generated when power is first
applied to the part. No operation should be started until the
RESET bit is ‘‘0’’.
The DAS’ offset voltage, after calibration, has a typical drift
a
b
of 0.1 LSB over a temperature range of 40 C to 85 C.
§
§
This small drift is less than the variability of the change in
offset that can occur when using the auto-zero correction
with each conversion. This variability is the result of using
only one sample of the offset voltage to create a correction
value. This variability decreases when using the full calibra-
tion mode because eight samples of the offset voltage are
taken, averaged, and used to create a correction value.
Therefore, it is recommended that this mode not be used.
Bit 2 is the auto-zero bit. Writing a ‘‘1’’ to this bit initiates an
auto-zero offset voltage calibration. Unlike the eight-sample
auto-zero calibration performed during the full calibration
procedure, Bit 2 initiates a ‘‘short’’ auto-zero by sampling
the offset once and creating a correction coefficient (full
calibration averages eight samples of the converter offset
voltage when creating a correction coefficient). If the Se-
quencer is running when Bit 2 is set to ‘‘1’’, an auto-zero
starts immediately after the conclusion of the currently run-
ning instruction. Bit 2 is reset automatically to a ‘‘0’’ and an
interrupt flag (Bit 3, in the Interrupt Status register) is set at
the end of the auto-zero (76 clock cycles). After completion
of an auto-zero calibration, the Sequencer fetches the next
instruction as pointed to by the Instruction RAM’s pointer
and resumes execution. If the Sequencer is stopped, an
auto-zero is performed immediately at the time requested.
Bit 7 programs the SYNC pin (29) to operate as either an
input or an output. The SYNC pin becomes an output when
Bit 7 is a ‘‘1’’ and an input when Bit 7 is a ‘‘0’’. With SYNC
programmed as an input, the rising edge of any logic signal
applied to pin 29 will start a conversion or ‘‘watchdog’’ com-
parison. Programmed as an output, the logic level at pin 29
will go high at the start of a conversion or ‘‘watchdog’’ com-
parison and remain high until either have finished. See In-
struction RAM ‘‘00’’, Bit 8.
Bits 8 and 9 form the RAM Pointer that is used to select
each of a 48-bit instruction’s three 16-bit sections during
read or write actions. A ‘‘00’’ selects Instruction RAM sec-
tion one, ‘‘01’’ selects section two, and ‘‘10’’ selects section
three.
Bit 3 is the calibration bit. Writing a ‘‘1’’ to this bit initiates a
complete calibration process that includes a ‘‘long’’ auto-
zero offset voltage correction (this calibration averages
eight samples of the comparator offset voltage when creat-
ing a correction coefficient) followed by an ADC linearity
calibration. This complete calibration is started after the cur-
rently running instruction is completed if the Sequencer is
running when Bit 3 is set to ‘‘1’’. Bit 3 is reset automatically
to a ‘‘0’’ and an interrupt flag (Bit 4, in the Interrupt Status
register) will be generated at the end of the calibration pro-
cedure (4944 clock cycles). After completion of a full auto-
zero and linearity calibration, the Sequencer fetches the
next instruction as pointed to by the Instruction RAM’s
pointer and resumes execution. If the Sequencer is stopped,
a full calibration is performed immediately at the time re-
quested.
Bit 10 activates the Test mode that is used only during pro-
duction testing. Always write ‘‘0’’ in this bit when program-
ming the Instruction Register.
Bit 11 is the Diagnostic bit and is available only in the
Ó
À
LM12 L 438. It can be activated by setting it to a ‘‘1’’. The
Diagnostic mode, along with a properly chosen instruction,
À
Ó
allows verification that the LM12 L 438’s ADC is perform-
ing correctly. When activated, the inverting and non-invert-
ing inputs are connected as shown in Table V. As an exam-
a
b
ple, an instruction with ‘‘001’’ for both IN and IN while
using the Diagnostic mode typically results in a full-scale
output.
6.2.3 Interrupts
Bit 4 is the Standby bit. Writing a ‘‘1’’ to Bit 4 immediately
places the DAS in Standby mode. Normal operation returns
when Bit 4 is reset to a ‘‘0’’. The Standby command (‘‘1’’)
disconnects the external clock from the internal circuitry,
À
Ó
The LM12434 and LM12 L 438 have seven possible inter-
rupts, all with the same priority. Any of these interrupts will
cause a hardware interrupt to appear on the INT pin (31) if
À
Ó
decreases the LM12434 and LM12 L 438’s internal
36
6.0 Operational Information (Continued)
they are not masked (by the Interrupt Enable register). The
Interrupt Status register is then read to determine which of
the seven interrupts has been issued.
Bit 3 enables an external interrupt when the single-sampled
auto-zero calibration has been completed.
Bit 4 enables an external interrupt when a full auto-zero and
linearity self-calibration has been completed.
The Interrupt Status register must be cleared by reading it
after writing to the Interrupt Enable register. This removes
any spurious interrupts on the INT pin generated during an
Interrupt Enable register access.
Bit 5 enables an external interrupt when an internal Pause
interrupt has been generated.
Bit 6 don’t care condition.
Interrupt 0 is generated whenever the analog input voltage
on a selected multiplexer channel crosses a limit while the
Bit 7 enables an external interrupt when the LM12434 and
Ó
À
LM12 L 438 returns from standby to active mode (see
Note 22).
À
Ó
LM12434 and LM12 L 438 are operating in the ‘‘watch-
dog’’ comparison mode. Two sequential comparisons are
Bits 8–10 form the storage location of the user-programma-
ble value against which the Sequencer’s address is com-
pared. When the Sequencer reaches an address that is
equal to the value stored in Bits 8–10, an internal interrupt
is generated and appears in Bit 1 of the Interrupt Status
register. If Bit 1 of the Interrupt Enable register is set to ‘‘1’’,
an external interrupt will appear at pin 31 (INT).
À
Ó
made when the LM12434 and LM12 L 438 are executing a
‘‘watchdog’’ instruction. Depending on the logic state of Bit
9 in the Instruction RAM’s second and third sections, an
interrupt will be generated either when the input signal’s
magnitude is greater than or less than the programmable
limits. (See the Instruction RAM, Bit 9 description.) The Limit
Ý
Status register will indicate which preprogrammed limit (
Ý
1
The value stored in bits 8–10 ranges from 000 to 111, rep-
resenting 1 to 8 instructions stored in the Instruction RAM.
After the Instruction RAM has been programmed and the
RESET bit is set to ‘‘1’’, the Sequencer is started by placing
a ‘‘1’’ in the Configuration register’s START bit. Setting the
INT 1 trigger value to 000 does not generate an INT 1 the
first time the Sequencer retrieves and decodes Instruction
000. The Sequencer generates INT 1 (by placing a ‘‘1’’ in
the Interrupt Status register’s Bit 1) the second time and
every subsequent time that the Sequencer encounters In-
struction 000. It is important to remember that the Sequenc-
er continues to operate even if an Instruction interrupt (INT
1) is internally or externally generated. The only mecha-
nisms that stop the Sequencer are an instruction with the
PAUSE bit set to ‘‘1’’ (halts before instruction execution),
placing a ‘‘0’’ in the Configuration register’s START bit, or
placing a ‘‘1’’ in the Configuration register’s RESET bit.
or 2) was crossed, and which instruction was executing
when the limit was crossed.
Interrupt 1 is generated when the Sequencer reaches the
instruction counter value specified in the Interrupt Enable
register’s bits 8–10. This flag appears before the instruc-
tion’s execution. Instructions continue to execute as pro-
grammed.
Interrupt 2 is activated when the Conversion FIFO holds a
number of conversions equal to the programmable value
stored in the Interrupt Enable register’s Bits 11–15. This
value ranges from 00000 to 11111, with 00001 to 11111
representing 1 to 31 conversions stored in the FIFO, and
00000 generating an interrupt after 32 conversions. See
Section 6.2.8 for more FIFO information.
The completion of the short, single-sampled auto-zero cali-
bration generates Interrupt 3.
The completion of a full auto-zero and linearity self-calibra-
tion generates Interrupt 4.
Bits 11–15 hold the number of conversions that must be
stored in the Conversion FIFO in order to generate an inter-
nal interrupt. This internal interrupt appears in Bit 2 of the
Interrupt Status register. If Bit 2 of the Interrupt Enable reg-
ister is set to ‘‘1’’, an external interrupt will appear at pin 31
(INT).
Interrupt 5 is generated when the Sequencer encounters
an instruction that has its Pause bit (Bit 1 in Instruction RAM
‘‘00’’) set to ‘‘1’’.
Interrupt 7 is issued after a short delay (10 ms typ) while
the DAS returns from Standby mode to active operation us-
ing the Configuration register’s Bit 4. This short delay allows
the internal analog circuitry to settle sufficiently, ensuring
accurate conversion results (see Note 22).
6.2.5 Interrupt Status Register
This read-only register is located at address 1010. The cor-
responding flag in the Interrupt Status register goes high
(‘‘1’’) any time that an interrupt condition takes place,
whether an interrupt is enabled or disabled in the Interrupt
Enable register. Any of the active (‘‘1’’) Interrupt Status reg-
ister flags are reset to ‘‘0’’ whenever this register is read or
a device reset is issued (see Bit 1 in the Configuration Reg-
ister).
6.2.4 Interrupt Enable Register
The Interrupt Enable register at address location 1001
has READ/WRITE capability. An individual interrupt’s ability
to produce an external interrupt at pin 31 (INT) is accom-
plished by placing a ‘‘1’’ in the appropriate bit location. Any
of the internal interrupt-producing operations will set their
corresponding bits to ‘‘1’’ in the Interrupt Status register re-
gardless of the state of the associated bit in the Interrupt
Enable register. See Section 2.3 for more information about
each of the eight internal interrupts.
Bit 0 is set to ‘‘1’’ when a ‘‘watchdog’’ comparison limit
interrupt has taken place.
Bit 1 is set to ‘‘1’’ when the Sequencer has reached the
address stored in Bits 8–10 of the Interrupt Enable register.
Bit 2 is set to ‘‘1’’ when the Conversion FIFO’s limit, stored
in Bits 11–15 of the Interrupt Enable register, has been
reached.
Bit 0 enables an external interrupt when an internal ‘‘watch-
dog’’ comparison limit interrupt has taken place.
Bit 1 enables an external interrupt when the Sequencer has
reached the address stored in Bits 8–10 of the Interrupt
Enable register.
Bit 3 is set to ‘‘1’’ when the single-sampled auto-zero has
been completed.
Bit 4 is set to ‘‘1’’ when an auto-zero and full linearity self-
calibration has been completed.
Bit 2 enables an external interrupt when the Conversion
FIFO’s limit, stored in Bits 11–15 of the Interrupt Enable
register, has been reached.
Bit 5 is set to ‘‘1’’ when a Pause interrupt has been generat-
ed.
37
6.0 Operational Information (Continued)
Bit 6 no interrupt is associated with this bit. Don’t care con-
dition.
activated by the Sequencer only if the current instruction’s
Bit 9 is set (‘‘1’’). If the equivalent decimal value ‘‘N’’
16
s
s
2
b
1) is written inside the 16-bit Timer register
(0
N
Bit 7 is set to ‘‘1’’ when the DAS returns from standby to
active mode (see Note 22).
and the Timer is enabled by setting an instruction’s bit 9 to a
‘‘1’’, the Sequencer will delay that instruction’s execution by
Bits 8–10 hold the Sequencer’s current instruction number
while it is running.
c
a
N
halting at state 3 (S3), as shown in Figure 11, for 32
2 clock cycles.
Bits 11–15 hold the current number of conversion results
stored in FIFO but have not been read by the user. After
each conversion, the result will be stored in the FIFO and
the contents of these bits incremented by one. Each single
read from FIFO decrements the contents of these bits by
one. If more than 32 conversion results being stored in FIFO
the numbers on these bits roll over from ‘‘11111’’ to
‘‘00000’’ and continue incrementing. If reads are performed
from FIFO more than the number of conversions stored in it,
the contents of these bits roll back from ‘‘00000’’ to
‘‘11111’’ and continue decrementing.
6.2.8 FIFO
The result of each conversion is stored in an internal read-
only FIFO (First-In, First-Out) register. It is located at ad-
dress 1100. This register has 32 16-bit wide locations. Each
location holds 13 bits of conversion data. Bits 0–3 hold the
a
four LSBs in the 12 bits
sign mode or ‘‘1110’’ in the 8 bits
a
sign mode. Bits 4–11 hold the eight MSBs and Bit 12
holds the sign bit. Bits 13–15 can hold either the sign bit,
extending the register’s two’s complement data format to a
full sixteen bits or the instruction address that generated the
conversion and the resulting data. These modes are select-
ed according to the logic state of the Configuration regis-
ter’s Bit 5.
6.2.6 Limit Status Register
This read-only register is located at address 1101. This reg-
Ý
Ý
ister is used in tandem with the Limit 1 and Limit 2 regis-
ters in the Instruction RAM. Whenever a given instruction’s
input voltage exceeds the limit set in its corresponding Limit
The FIFO status should be read in the Interrupt Status regis-
ter (Bits 11–15) to determine the number of conversion re-
sults that are held in the FIFO before retrieving them. This
will help prevent conversion data corruption that may take
place if the number of reads are greater than the number of
conversion results contained in the FIFO. Trying to read the
FIFO when it is empty may corrupt new data being written
into the FIFO. Writing more than 32 conversion results into
the FIFO by the ADC results in loss of the first conversion
results. Therefore, to prevent data loss, it is recommended
Ý
Ý
register ( 1 or 2) a bit corresponding to the instruction
number is set in the Limit Status register. Any of the active
(‘‘1’’) Limit Status flags are reset to ‘‘0’’ whenever this regis-
ter is read or a device reset is issued (see Bit 1 in the Con-
figuration register). This register holds the status of limits
Ý
Ý
1 and 2 for each of the eight instructions.
Ý
Bits 0–7 show the Limit 1 status. Each bit will be set high
(‘‘1’’) when the corresponding instruction’s input voltage ex-
À
Ó
that the LM12434 and LM12 L 438’s interrupt capability be
used to inform the system controller that the FIFO is full.
Ý
ceeds the threshold stored in the instruction’s Limit 1 reg-
ister. When, for example, instruction 3 is a ‘‘watchdog’’ op-
eration (Bit 11 is set high) and the input for instruction 3
meets the magnitude and/or polarity data stored in instruc-
Ý
tion 3’s Limit 1 register, Bit 3 in the Limit Status register
will be set to a ‘‘1’’.
a
be 1110 when using 8-bit plus sign resolution.
Bits 0–12 hold 12-bit
sign conversion data. Bits 0–3 will
Bits 13–15 hold either the instruction responsible for the
associated conversion data or the sign bit. Either mode is
selected with Bit 5 in the Configuration register.
Ý
Bits 8–15 show the Limit 2 status. Each bit will be set
Using the FIFO’s full depth is achieved as follows. Set the
value of the Interrupt Enable registers’s Bits 11–15 to
00000 and the Interrupt Enable register’s Bit 2 to a ‘‘1’’. This
generates an external interrupt when the 31st conversion is
stored in the FIFO. This gives the host processor a chance
high (‘‘1’’) when the corresponding instruction’s input volt-
age exceeds the threshold stored in the instruction’s Limit
Ý
2 register. When, for example, the input to instruction 6
Ý
meets the value stored in instruction 6’s Limit 2 register,
Bit 14 in the Limit Status register will be set to a ‘‘1’’.
À
Ó
to send a ‘‘0’’ to the LM12434 and LM12 L 438’s Start bit
(Configuration register) and halt the ADC before it com-
pletes the 32nd conversion. The Sequencer halts after the
current (32) conversion is completed. The conversion data
is then transferred to the FIFO and occupies the 32nd loca-
tion. FIFO overflow is avoided if the Sequencer is halted
before the start of the 32nd conversion by placing a ‘‘0’’ in
the Start bit (Configuration register). It is important to re-
member that the Sequencer continues to operate even if
a FIFO interrupt (INT 2) is internally or externally gener-
ated. The only mechanisms that stop the Sequencer are an
instruction with the PAUSE bit set to ‘‘1’’ (halts before in-
struction execution), placing a ‘‘0’’ in the Configuration reg-
ister’s START bit, or placing a ‘‘1’’ in the Configuration reg-
ister’s RESET bit.
6.2.7 Timer
À
Ó
The LM12434 and LM12 L 438 have an on-board 16-bit
timer that includes a 5-bit pre-scaler. It uses the clock signal
applied to pin 23 as its input. It can generate time intervals
21
5
of 0 through 2 clock cycles in steps of 2 . This time inter-
val can be used to delay the execution of instructions. It can
also be used to slow the conversion rate when converting
slowly changing signals. This can reduce the amount of re-
dundant data stored in the FIFO and retrieved by the con-
troller.
The user-defined timing value used by the Timer is stored in
the 16-bit READ/WRITE Timer register at location 1011 and
is pre-loaded automatically. Bits 0–7 hold the preset value’s
low byte and Bits 8–15 hold the high byte. The Timer is
38
6.0 Operational Information (Continued)
6.3 INSTRUCTION SEQUENCER
State 2: Perform calibration. If bit 2 or bit 6 of the Configu-
ration register is set to a ‘‘1’’, state 2 is 76 clock cycles long.
If the Configuration register’s bit 3 is set to a ‘‘1’’, state 2 is
4944 clock cycles long.
The Sequencer uses a 3-bit counter (Instruction Pointer, or
IP) to retrieve the programmable conversion instructions
stored in the Instruction RAM. The counter is reset to 000
during chip reset or if the current executed instruction has
its Loop bit (Bit 1 in any Instruction RAM ‘‘00’’) set high
(‘‘1’’). It increments at the end of the currently executed
instruction and points to the next instruction. It will continue
to increment up to 111 unless an instruction’s Loop bit is
set. If this bit is set, the counter resets to ‘‘000’’ and execu-
tion begins again with the first instruction. If all instructions
have their Loop bit reset to ‘‘0’’, the Sequencer will execute
all eight instructions continuously. Therefore, it is important
to realize that if less than eight instructions are pro-
grammed, the Loop bit on the last instruction must be set.
Leaving this bit reset to ‘‘0’’ allows the Sequencer to exe-
cute ‘‘unprogrammed’’ instructions, the results of which may
be unpredictable.
State 3: Run the internal 16-bit Timer. The number of
clock cycles for this state varies according to the value
stored in the Timer register. The number of clock cycles is
found by using the expression below
a
32T
2
16
s
s
2
b
1.
where 0
T
Ý
State 7: Sample the input signal and read Limit 1’s val-
ue if needed. The number of clock cycles for acquiring the
a
input signal in the 12-bit
sign mode varies according to
a
9
2D
where D is the user-programmable 4-bit value stored in bits
s
s
12–15 of Instruction RAM ‘‘00’’ and is limited to 0
15.
D
The Sequencer’s Instruction Pointer value is readable at
any time and is found in the Status register at Bits 8–10.
Figure 10 illustrates the instruction execution flow as per-
formed by the sequencer. The Sequencer can go through
eight states during instruction execution:
The number of clock cycles for acquiring the input signal in
a
the 8-bit
sign or ‘‘watchdog’’ mode varies according to
a
2
2D
State 6: Perform first watchdog comparison. This state is
5 clock cycles long.
State 0: The current instruction’s first 16 bits are read
from the Instruction RAM ‘‘00’’. This state is one clock cycle
long.
Ý
State 4: Read Limit 2. This state is 1 clock cycle long.
State 5: Perform a conversion or second watchdog com-
a
sign conver-
parison. This state takes 44 clock cycles for a 12-bit
a
sign
State 1: Checks the state of the Calibration and Start bits.
This is the ‘‘rest’’ state whenever the Sequencer is stopped
using the reset, a Pause command, or the Start bit is reset
low (‘‘0’’). When the Start bit is set to a ‘‘1’’, this state is one
clock cycle long.
conversions or 21 clock cycles for a 8-bit
sions. The ‘‘watchdog’’ comparison mode takes 5 clock cy-
cles.
39
6.0 Operational Information (Continued)
TL/H/11879–19
e
FIGURE 10. Sequencer Logic Flow Chart (IP
40
Instruction Pointer)
7.0 Digital Interface
In order to read from or write to the registers of the
2
2
The ‘‘I C’’ mode supports the Philips’ I C bus specification
for both the standard (100 kHz maximum data rate) and the
fast (400 kHz maximum data rate) modes of operation. The
À
Ó
LM12434 and LM12 L 438 a very flexible serial synchro-
nous interface is provided. Communication between the
2
DAS behaves as a slave device on the I C bus and receives
À
Ó
LM12434 and LM12 L 438 and microcontrollers, micro-
processors and other circuitry is accomplished through this
serial interface. The serial interface is designed to directly
communicate with synchronous serial interface of the most
and transmits the information under the control of a bus
master. Section 7.4.1 shows a general block diagram of
2
how the serial DAS, configured in the I C Interface mode,
2
popular microprocessors and I C serial protocol with no ad-
2
2
can be connected to an I C bus using an I C controller
(PCD8584).
ditional hardware required. The interface has been also de-
signed to accommodate easy and straightforward software
programming.
All the serial interface modes allow for three basic types of
data transfer; these are single write, single read and burst
read. In a single write or read, 16 bits (2 bytes) of data is
written to or read from one of the registers inside the DAS.
In a burst read, multiple reads are performed from one regis-
ter without having to repeatedly send the control and regis-
ter address information for each read. The burst read can
be performed on any LM12434 and LM12 L 438’s register,
however it is primarily provided for multiple reads from the
FlFO register (one address, 32 locations), where a se-
quence of conversion results is stored.
À
Ó
The LM12434 and LM12 L 438 supports four selectable
protocols as shown in Table VI. The MODESEL1 and
MODESEL2 inputs select the desired protocol. These pins
are normally hardwired for a selected protocol, but they can
also be controlled by the system in case a protocol change
within the system is required. P1–P5 are multi-function seri-
al interface input or output pins that have different assign-
ments depending on the selected interface mode.
À
Ó
The ‘‘Standard’’ interface mode uses a simple shift register
type of serial data transfer. It supports several microcontrol-
lers’ serial synchronous protocols, including: National Semi-
conductor’s MICROWIRE/PLUS, Motorola’s SPl, QSPl, and
Hitachi’s synchronous SCl. Section 7.1.1 shows general
block diagrams of how the serial DAS, configured in the
Standard Interface Mode, can be connected to the HPC and
68HC11. Also, detailed assembly routines are included for
single writes, single reads and burst read operations.
7.1 STANDARD INTERFACE MODE
The standard interface mode is a simple shift register type
of serial data transfer. The serial clock synchronizes the
À
Ó
transfer of data to and from the LM12434 and LM12 L 438.
The interface uses 4 lines: 2 data lines (DI and DO), a serial
clock line (SCLK) and a chip-select (CS) line. More than one
device can share the data and serial clock lines provided
that each device has its own chip-select line.
The ‘‘8051’’ mode supports the synchronous serial interface
of the 8051 family of microcontrollers (8051 serial interface
Mode 0). It is also compatible with the serial interface in the
MCS-96 family of 16-bit microcontrollers. Section 7.2.1
shows a general block diagram of how the serial DAS, con-
figured in the 8051 Interface Modes can be connected to
the 8051 family of mCs. Also, detailed assembly routines for
a single write, single read and burst read operations are
included.
À
Ó
The LM12434 and LM12 L 438 standard mode is selected
when the MODESEL1 and MODESEL2 pins have the logic
state of ‘‘01’’. Figure 12 shows a typical connection diagram
À
Ó
for the LM12434 and LM12 L 438 standard mode serial
interface. The CS, DI, DO, and SCLK lines are respectively
assigned to interface pins P2 through P5. The P1 pin is
assigned to a signal called R/F (Rise/Fall). The logic level
on this pin specifies the polarity of the serial clock:
e
and captured at the rising edge of the SCLK.
Ð If R/F
1, data is shifted after falling edge and is stable
The ‘‘TMS320’’ mode is designed to directly interact with
the serial interface of the TMS320C3x and TMS320C5x
families of digital signal processors. This interface is also
compatible with the similar serial interfaces on the
DSP56000 and the ADSP2100 families of DSP processors.
Section 7.3.1 shows a general block diagram of how the
serial DAS, configured in the TMS320 interface mode, can
be connected to the TMS320C3x family of DSP processors.
Also, detailed assembly routines for a single write, single
read and burst read operations are included.
e
and captured at the falling edge of the SCLK.
Ð If R/F
0, data is shifted after rising edge and is stable
À
Ó
TABLE VI. LM12434 and LM12 L 438 Interface Modes and Pin Assignments
Interface
Mode
M0DESEL1
MODESEL2
P1
P2
P3
P4
P5
Standard
8051
0
0
1
1
1
0
1
0
R/F
1*
CS
1*
DI
CS
DO
RXD
DR
SCLK
TXD
CLK
SCL
TMS320
FSR
FSX
DX
2
I C
Slave AD0
Slave AD1
Slave AD2
SDA
*Internally pulled-up
41
7.0 Digital Interface (Continued)
In both cases the data transfer is insensitive to idle state of
the SCLK. SCLK can stay at either logic level high or low
when not clocking (see Figure 11)
This data is written to the register addressed in the com-
mand byte (A3, A2, A1, A0). The data is interpreted as MSB
or LSB first based on the logic level of the 7th bit (MSB/
LSB) in the command byte. There is no activity on the DO
line during write cycles and the DAS leaves the DO line in
the high impedance state. CS will go high after the transfer
of the last bit, thus completing the write cycle.
Data transfer in this mode is basically byte-oriented. This is
compatible with the serial interface of the target microcon-
trolIers and microprocessors. As mentioned, the LM12434
À
Ó
and LM12 L 438 have three different communication cy-
cles: write cycle, read cycle and burst read cycle. At the
start of each data transfer cycle, ‘‘command byte’’ is written
to the serial DAS, followed by write or read data. The com-
Read cycle: A read cycle starts the same way as a write
cycle, except that the command byte’s R/W bits equal to
one. Following the command byte, the DAS outputs the
data on the DO line synchronized with the microcontroller’s
SCLK. The data is read from the register addressed in the
command byte. Data is shifted out MSB or LSB first, de-
pending on the logic level of the MSB/LSB bit. The logic
state of the Dl line is ‘‘don’t care’’ after the command byte.
CS will go high after the transfer of the last data bit, then
completing the read cycle.
À
Ó
mand byte informs the LM12434 and LM12 L 438 about
the communication cycle. The command byte carries the
following information:
Ð what type of data transfer (communication cycle) is start-
ed
Ð which device register to be accessed
The command byte has the following format:
Burst read cycle: A burst read cycle starts the same way
as a single read cycle, but the B bit in the command byte is
set to one, indicating a burst read cycle. Following the com-
mand byte the data is output on the DO line as long as the
DAS receives SCLK from the system. To tell the DAS when
a burst read cycle is completed pull CS high after the 8th
and before the 15th SCLK cycle during the last data byte
transfer (see Figure 11i ). After CS high is detected and the
last data bit is transferred, the DAS is ready for a new com-
munication cycle to begin.
TL/H/11879–52
The timing diagrams in Figure 11 show the transfer of data
in packets of 8 bits (bytes). This represents the way the
serial ports of most microcontrollers and microprocessors
produce serial clock and data. The DAS does not require a
gap between the first and second byte of the data; 16 con-
tinuous clock cycles will transfer the data word. However,
there should be a gap equal to 3 CLK (the DAS main clock
input, not the SCLK) cycles between the end of the com-
mand byte and the start of the data during a read cycle. This
is not a concern in most systems for two reasons. First, the
processor generally has some inherent gap between byte
transfers. Second, the SCLK frequency is usually signifi-
Note that the first bit may be either the MSB or the LSB of
the byte depending on the processor type, but it must be the
À
Ó
first bit transmitted to the LM12434 and LM12 L 438.
Figure 11 shows the timing diagrams for different communi-
cation cycles. Figures 11a, b, c, d show write cycles for
various combinations of R/F pin logic level and SCLK idle
state. Figures 11e, f, g, h show read cycles for similar sets
of conditions. Figure 11i shows a burst read cycle for the
e
case of R/F
0 and low SCLK idle state. Note that these
timing diagrams depict general relationships between the
SCLK edges, the data bits and CS. These diagrams are not
meant to show guaranteed timing. (See specification tables
for parametric switching characteristics.)
cantly slower than the CLK frequency. For example,
a
68HC11 processor with an 8 MHz crystal generates a maxi-
mum SCLK frequency of 1 MHz. If the DAS is running with a
6 MHz CLK, there are 6 cycles of CLK within each cycle of
SCLK and the requirement is satisfied even if SCLK oper-
ates continuously during and after the command byte.
Write cycle: A write cycle begins with the falling edge of
CS. Then a command byte is written to the DAS on the DI
line synchronized by SCLK. The command byte has the
R/W and B bits equal to zero. Following the command byte,
16 bits of data (2 bytes) is shifted in on the same DI line.
42
7.0 Digital Interface (Continued)
TL/H/11879–30
e
0, Data Stable at Rising Edge and Shifted at Falling Edge of the SCLK
(a) Write Cycle, R/F Input (P1)
1
e
Idle State of SCLK
TL/H/11879–31
e
1, Data Stable at Rising Edge and Shifted at Falling Edge of the SCLK
(b) Write Cycle, R/F Input (P1)
1
e
Idle State of SCLK
À
Ó
FIGURE 11. Timing Diagrams for LM12434 and LM12 L 438 Standard Serial Interface
43
7.0 Digital Interface (Continued)
TL/H/11879–32
e
0, Data Stable at Falling Edge and Shifted at Rising Edge of the SCLK
(c) Write Cycle, R/F Input (P1)
0
e
Idle State of SCLK
TL/H/11879–33
e
1, Data Stable at Falling Edge and Shifted at Rising Edge of the SCLK
(d) Write Cycle, R/F Input (P1)
0
e
Idle State of SCLK
À
Ó
FIGURE 11. Timing Diagrams for LM12434 and LM12 L 438 Standard Serial Interface (Continued)
44
7.0 Digital Interface (Continued)
TL/H/11879–34
e
0, Data Stable at Rising Edge and Shifted at Falling Edge of the SCLK
(e) Read Cycle, R/F Input (P1)
1
e
Idle State of SCLK
TL/H/11879–35
e
1, Data Stable at Rising Edge and Shifted at Falling Edge of the SCLK
(f) Read Cycle, R/F Input (P1)
1
e
Idle State of SCLK
À
Ó
FIGURE 11. Timing Diagrams for LM12434 and LM12 L 438 Standard Serial Interface (Continued)
45
7.0 Digital Interface (Continued)
TL/H/11879–36
e
0, Data Stable at Falling Edge and Shifted at Rising Edge of the SCLK
(g) Read Cycle, R/F Input (P1)
0
e
Idle State of SCLK
TL/H/11879–37
e
1, Data Stable at Falling Edge and Shifted at Rising Edge of the SCLK
(h) Read Cycle, R/F Input (P1)
0
e
Idle State of SCLK
À
Ó
FIGURE 11. Timing Diagrams for LM12434 and LM12 L 438 Standard Serial Interface (Continued)
46
7.0 Digital Interface (Continued)
47
7.0 Digital Interface (Continued)
7.1.1 Examples of Interfacing to the HPC’s MICROWIRE/PLUS and 68HC11’s SPI
TL/H/11879–65
Note: Other device pins are not shown.
TM
À
Ó
FIGURE 12a. LM12434 and LM12 L 438 Standard Mode Interface to the HPC’s MICROWIRE/PLUS
TL/H/11879–66
Note: Other device pins are not shown.
À
Ó
FIGURE 12b. LM12434 and LM12 L 438 Standard Mode Interface to the 68HC11’s SPI
48
7.0 Digital Interface (Continued)
HPC Assembly Code Example
TL/H/11879–56
49
7.0 Digital Interface (Continued)
HPC Assembly Code Example (Continued)
TL/H/11879–57
50
7.0 Digital Interface (Continued)
HPC Assembly Code Example (Continued)
TL/H/11879–58
51
7.0 Digital Interface (Continued)
HPC Assembly Code Example (Continued)
TL/H/11879–59
68HC11 Assembly Code Example
TL/H/11879–85
52
7.0 Digital Interface (Continued)
68HC11 Assembly Code Example (Continued)
TL/H/11879–86
53
7.0 Digital Interface (Continued)
68HC11 Assembly Code Example (Continued)
TL/H/11879–87
54
7.0 Digital Interface (Continued)
The command byte has the following format:
7.2 8051 INTERFACE MODE
The 8051 interface mode is designed to work directly with
the 8051 family of microcontrollers’ mode 0 serial interface.
This interface mode is a simple shift register type of serial
data transfer. The serial clock synchronizes the transfer of
À
Ó
data to and from the LM12434 and LM12 L 438. The inter-
face uses 3 lines: a bidirectional data line (RXD), a serial
clock line (TXD) and a chip-select (CS) line. More than one
device can share the data and serial clock lines provided
that each device has its own chip-select line.
The 8051 mode is selected when the MODESEL1 and
MODESEL2 pins have the logic state of ‘‘00’’. Figure 14
shows a typical connection diagram for the 8051 mode seri-
al interface. The CS, RXD and TXD lines are respectively
assigned to interface pins P3 through P5. The P1 and P2
pins are not used in this mode and should be left open or
connected to logic ‘‘1’’. In this interface the idle state of the
serial clock TXD is logic ‘‘1’’. The data is stable at both
edges of the TXD clock and is shifted after its rising edge.
TL/H/11879–53
The first bit is the LSB of the byte based on the 8051 mode
0 serial interface protocol.
Figure 13 shows the timing diagrams for different communi-
cation cycles. Figure 13a shows a write cycle. Figure 13b
shows a read cycle. Figure 13c shows a burst read cycle.
Note that these timing diagrams depict general relationships
between the SCLK edges, the data bits and CS. These dia-
grams are not meant to show guaranteed timing perform-
ance. (See specification tables for parametric switching
characteristics.)
The interface has
a bidirectional RXD data line. The
Ó
À
LM12434 and LM12 L 438 leaves the RXD line in a high
impedance state whenever it is not outputting any data.
Data transfer in this mode is byte oriented. As mentioned,
Write cycle: A write cycle begins with the falling edge of the
CS. Then a command byte is written to the DAS on the RXD
line synchronized by TXD clock. The command byte has the
R/W and B bits equal to zero. Following the command byte,
16 bits of data (2 bytes) is shifted in on the RXD line. The
data is written to the register addressed in the command
byte (A3, A2, A1, A0). The data is always LSB first in this
interface. CS will go high after the transfer of the last bit,
thus completing the write cycle.
À
Ó
the LM12434 and LM12 L 438 has three different commu-
nication cycles: write cycle, read cycle and burst read cycle.
At the start of each data transfer cycle, ‘‘command byte’’ is
À
Ó
written to the LM12434 and LM12 L 438, followed by write
or read data. The command byte informs the LM12434 and
À
Ó
LM12 L 438 about the communication cycle and carries
the following information:
Ð what type of data transfer (communication cycle) is start-
ed
Read cycle: A read cycle starts the same way as a write
cycle, except that the command bytes R/W bit is equal to
one. Following the command byte, the DAS outputs the
data on the RXD line synchronized with the microcontrol-
ler’s TXD clock. The data is read from the register ad-
dressed in the command byte. Data is shifted in LSB first.
Again, CS will go high after the transfer of the last data bit,
thus completing the read cycle.
Ð which device register is to be accessed
55
7.0 Digital Interface (Continued)
Burst read cycle: A burst read cycle starts the same way
as a single read cycle, but the B bit in the command byte is
set to one, indicating a burst read cycle. Following the com-
mand byte the data is output on the RXD line as long as the
DAS receives TXD clock from the system. To tell the DAS
when a burst read cycle is completed, CS should be set high
after the 8th and before the 15th SCLK cycle during the last
data byte transfer (see Figure 13c). After CS high is detect-
ed and the last data bit is transferred, the DAS is ready for a
new communication cycle to begin.
16 continuous clock cycles will transfer the data word. How-
ever, there should be a gap equal to 3 CLK (the DAS main
clock input, not the TXD clock) cycles between the end of
the command byte and the start of the data during a read
cycle. This is not concerned in most systems for two rea-
sons. First, the processor generally has some inherent gap
between byte transfers. Second, the TXD frequency is usu-
ally significantly slower than the CLK frequency. For exam-
ple, an 8051 processor with 12 MHz crystal generates a
TXD of 1 MHz. If the DAS is running with 6 MHz CLK, there
are 6 cycles of CLK within each cycle of TXD and the re-
quirement is satisfied even if TXD comes continuously after
command byte. The user should pay attention to this re-
quirement if running the TXD with a speed near or higher
than CLK.
The timing diagrams in Figure 13 show the transfer of data
in packets of 8 bits (bytes). This represents the way the
serial ports of the 8051 family of microcontrollers produce
the serial clock and data. The DAS does not require a gap
between the first and second bytes of the data;
TL/H/11879–40
(a) Write Cycle
1, Data Shifted at the Rising Edge of the SCLK
e
Idle State of SCLK
TL/H/11879–41
(b) Read Cycle
1, Data Shifted at the Rising Edge of the SCLK
e
Idle State of SCLK
À
Ó
FIGURE 13. Timing Diagrams for LM12434 and LM12 L 438 8051 Serial Interface Mode
56
7.0 Digital Interface (Continued)
57
7.0 Digital Interface (Continued)
7.2.1 Example of Interfacing to the 8051
TL/H/11879–67
À
Ó
FIGURE 14. LM12434 and LM12 L 438 in the 8051 Interface Mode
8051 Assembly Code Example
TL/H/11879–89
58
7.0 Digital Interface (Continued)
8051 Assembly Code Example (Continued)
TL/H/11879–90
59
7.0 Digital Interface (Continued)
8051 Assembly Code Example (Continued)
TL/H/11879–91
60
7.0 Digital Interface (Continued)
8051 Assembly Code Example (Continued)
TL/H/11879–96
61
7.0 Digital Interface (Continued)
The command packet has the following format:
7.3 TMS320 INTERFACE MODE
The TMS320 interface mode is designed to work directly
with the serial interface port of the TMS320C3x and
TMS320C5x families of digital signal processors. This inter-
face uses five lines: two data lines (DX, DR), two frame
synchronization signal lines (FSX, FSR), and a serial clock
line (SCLK). Note that the TMS320C3x/5x serial interface
has two separate serial clock lines for transmit and receive
À
Ó
called CLKX and CLKR, but the LM12434 and LM12 L 438
only uses one clock input for both receive and transmit.
Typically, CLKX is specified as an output and drives SCLK
as well as CLKR (defined as an input). The serial clock for
this interface mode is a free running clock, with the data
stream synchronized by SCLK. The start of each data trans-
fer (the beginning of a data packet) is synchronized by FSX
(Transmit Frame Sync) or FSR (Receive Frame Sync). This
interface can communicate with one device; no device se-
lect signal is used. The following discussion assumes that
the reader has a basic knowledge of the architecture and
operation of the TMS320C3x/5x serial interface port.
TL/H/11879–54
The first bit of the command packet is always the MSB of
the data packet to to be transferred.
Figure 15 shows the timing diagrams for the three communi-
cation cycles. Figure 15a shows a write cycle. Figure 15b
shows a read cycle, and Figure 15c shows a burst read
cycle. Note that these timing diagrams depict general rela-
tionships between the SCLK edges, the data bits and the
frame synchronization signals (FSX, FSR). These diagrams
are not meant to show guaranteed timing performance.
(See specification tables for parametric switching character-
istics.)
The TMS320 interface mode is selected when the
MODESEL1 and MODESEL2 pins have the logic state of
‘‘11’’. Figure 16 shows a typical connection diagram for the
Write cycle: A write cycle begins with an FSX pulse from
the processor. The first data bit is received by the DAS on
the DX line during the next SCLK falling edge after the fall-
ing edge of FSX. A 32-bit data packet is written to the DAS.
The TMS320C3x does this with a 32-bit transfer, using its
serial port 32-bit register. With the TMS320C5x family two
successive 16-bit transfers are initiated without any gap in
between. The first 9 bits (MSBs) of the data are the com-
mand packet with the R/W bit and B bit equal to zero. Fol-
lowing the command packet, a 16-bit data stream starts on
the falling edge of the 10th SCLK cycle and continues
through the 25th cycle. The last 7 bits in the 32-bit data
packet are ‘‘don’t care’’ and are ignored by the DAS. The
data is written to the register addressed in the command
packet (A3, A2, A1, A0). There is no activity on the FSR and
DR lines during a write cycle. The write cycle is completed
after the last data bit is transferred.
À
Ó
LM12434 and LM12 L 438 in the TMS320 serial interface
mode. The FSR, FSX, DX, DR, and SCLK lines are assigned
to interface pins P1 through P5.
Data transfer in this mode is programmable by the proces-
sor for 8-, 16-, 24-, or 32-bit data packets for the
TMS320C3x and 8-, or 16-bit data packets for TMS320C5x.
À
Ó
The LM12434 and LM12 L 438 uses 16-bit and 32-bit data
packets. For the TMS320C5x the 32-bit packet is composed
of two successive 16-bit packets with no gaps between
them. The data bits in each packet are transferred MSB
first, and are shifted in on the rising edge of SCLK and are
stable and captured at the falling edge of the SCLK. As with
the ‘‘Standard’’ and ‘‘8051’’ interface modes, the LM12434
À
Ó
and LM12 L 438 has three different communication cycles:
write cycle, read cycle and burst read cycle. At the start of
each data transfer cycle, a stream of 9 data bits (the ‘‘com-
Read cycle: A read cycle also begins with an FSX pulse
from the processor. The read cycle uses 16-bit data trans-
fer. Following the FSX pulse, 16 bits of data are written to
the DAS on the DX line. The first 9 bits (MSBs) of data are
the command packet with the R/W bit equal to one and the
B bit equal to zero. The last 7 bits (LSBs) are ‘‘don’t care’’
and are ignored by the DAS. About 3 to 4 CLK (the DAS
main clock input, not the SCLK) cycles after the R/W bit is
received, the DAS generates an FSR pulse to initiate the
data transfer. Following the FSR pulse, the DAS will send
16 bits of data to the processor on the DR line. The first bit
(MSB) of the data appears on the DR line on the next SCLK
cycle following the FSR pulse. The data is read from the
register addressed in the command packet. The read cycle
is completed after the last data bit is transferred.
À
Ó
mand packet’’) is written to the LM12434 and LM12 L 438
and informs it about the communication cycle. The place-
ment of these 9 bits in the data packet is different in the
read and write cycles and is discussed for each case sepa-
rately. The command packet carries the following informa-
tion:
Ð what type of data transfer (communication cycle) is start-
ed
Ð which device register is to be accessed
62
7.0 Digital Interface (Continued)
Burst read cycle: A burst read cycle starts the same way
as a single read cycle, but the B bit in the command packet
is set to one, indicating a burst read cycle. After the first 16
bits of data carrying the command packet is written to the
DAS, the DAS begins to send out the data words from the
addressed register on the DR line repeatedly. Each data
word is preceded by an FSR pulse for synchronization. To
terminate a burst read cycle, the processor does a dummy
read from the configuration register during the last
data word. This dummy read should be started so that its
FSR pulse occurs during the 15th to 17th SCLK cycle of the
last data word as shown in Figure 15c. The dummy read
terminates the burst read cycle and shifts out the contents
of the configuration register on the DR line. This data can be
discarded. After transfer of the last data bit from the config-
uration register, the DAS is ready for a new communication
cycle to begin.
TL/H/11879–47
(a) Write Cycle
TL/H/11879–48
(b) Read Cycle
À
Ó
FIGURE 15. Timing Diagram for LM12434 and LM12 L 438 TMS320 Serial Interface Mode
63
7.0 Digital Interface (Continued)
64
7.0 Digital Interface (Continued)
7.3.1 Example of Interfacing to the TMS320C3x
TL/H/11879–75
Note: Other device pins are not shown.
À
Ó
FIGURE 16. LM12434 and LM12 L 438 in the TMS320 Interface Mode
TMS320C3x Assembly Code Example
TL/H/11879–92
65
7.0 Digital Interface (Continued)
TMS320C3x Assembly Code Example (Continued)
TL/H/11879–93
66
7.0 Digital Interface (Continued)
TMS320C3x Assembly Code Example (Continued)
TL/H/11879–94
67
7.0 Digital Interface (Continued)
TMS320C3x Assembly Code Example (Continued)
TL/H/11879–95
68
7.0 Digital Interface (Continued)
TMS320C3x Assembly Code Example (Continued)
TL/H/11879–97
69
7.0 Digital Interface (Continued)
This timing diagram depicts the general relationship be-
tween the serial clock edges and the data bits. It is not
meant to show guaranteed timing performance. (See speci-
fication tables for parametric switching characteristics.) The
2
7.4 I C BUS INTERFACE
2
The I C bus is a serial synchronous bus structure. It is a
multi-master bus, which means that more than one device
capable of controlling the bus can be connected to it. The
bus uses 2 wires, serial data (SDA) and serial clock (SCL),
to carry information between the devices connected to the
bus. Both data and clock lines are bidirectional and are con-
nected to the positive power supply via a pull-up resistor.
Each device is identified by a unique address, whether it is a
microprocessor/controller or a peripheral such as memory,
keyboard, data-converter or display. Each device can oper-
ate as either transmitter or receiver, depending on the func-
tion of the device. In addition to transmitters and receivers,
devices can also be considered as masters and slaves
when performing data transfer. A master is the device that
initiates a data transfer on the bus and generates the clock
signals to permit that transfer. At that time, any device ad-
dressed is considered slave. It should be apparent that the
2
DAS’s I C interface timing parameters fully meet or exceed
2
2
the I C bus specification. Data transfer on the I C bus is
byte oriented and the 16-bit data to be written to or read
from each register is transferred in two bytes.
Write cycle: A write cycle is illustrated in Figure 17a. Com-
munication is initiated with a start condition generated by a
2
master (I C bus specification), followed by a byte of the
DAS’s slave address with the read/write bit (8th bit) being
‘‘0’’, indicating a write cycle will follow. At the 9th SCL clock
pulse of the first data packet, the DAS pulls the SDA line
low (‘‘0’’) to acknowledge that it has been addressed. The
next byte is the address of the DAS register to be accessed.
The format of this byte is three ‘‘0’s’’ (MSBs) followed by
four bits of register address (MSB first as shown) and a ‘‘0’’
as the last bit (LSB). After the DAS acknowledges the ad-
dress byte, the 16-bit data proceeds in two bytes, beginning
with the high order byte (MSB first). The direction of the
data in a write cycle is from master to DAS with acknowl-
edgement given by the DAS at the end of each byte. The
cycle is completed by a stop condition generated by the
master.
2
I C bus is not merely an interconnecting wire, it embodies
comprehensive formats and procedures for addressing,
transfer cycles start and stop, clock generation/synchroni-
zation and bus arbitration. The following discussion as-
sumes that the reader is familiar with the specification and
2
architecture of the I C bus.
2
À
Ó
The LM12434 and LM12 L 438’s I C bus interface is se-
lected when the MODESEL1 and MODESEL2 pins have the
Read/burst read cycle: The read and burst read cycles for
2
the I C interface are combined in a single format. A read
logic state of ‘‘10’’. Figure 18 shows a typical connection
2
cycle is shown in Figure 17b. A read cycle starts the same
as a write with a slave address byte for write followed by a
register address byte. After the register address byte is writ-
ten to the DAS, the bus should be released without any stop
condition. The master then applies a repeat start condition
followed by the DAS’s slave address, but with the read/
write bit being ‘‘1’’, indicating a read request from the mas-
ter. The DAS (slave) acknowledges its address and begin-
ning with the next byte, the direction of the data will be from
DAS to master. The DAS starts to transmit the contents of
its register (addressed previously at second byte of the cy-
cle) synchronized with the clocks applied by the master. An
even number of data bytes should be read from the DAS
(two bytes per register). At the end of each byte received
from the DAS the bus master generates an acknowledge.
The DAS continues to repeat transmitting its register con-
tents as long as the master is transmitting clocks and ac-
knowledges at the end of each byte. The DAS recognizes
the end of the transfer whenever the master does not ac-
knowledge at the end of an even numbered byte. At this
point, the master should generate a stop condition as re-
À
Ó
diagram for the LM12434 and LM12 L 438 to the I C bus.
As was mentioned, communication on the I C bus is per-
2
formed on 2 lines, SCL (serial clock) and SDA (serial data);
pins P5 and P4 are assigned to these lines. The DAS oper-
2
ates as a slave on the I C bus. As a result, the SCL line is
an input (no clock is generated by the LM12434 and
À
Ó
LM12 L 438) and the SDA line is a bi-directional serial data
path. According to I C bus specifications, the DAS has a
2
7-bit slave address. The four most significant bits of the
slave address are hard wired inside the LM12434 and
À
Ó
LM12 L 438 and are ‘‘0101’’. The three least significant
bits of the address are assigned to pins P3–P1. Therefore,
2
À
Ó
the LM12434 and LM12 L 438 I C slave address is:
0
1
0
1
P3
P2
P1
MSB
LSB
Tying the P3–P1 pins to different logic levels allows up to
Ó
eight LM12434 and LM12 L 438’s to be addressed on a
2
single I C bus.
À
Figure 17 shows the timing diagram for the read and write
2
2
quired by the I C bus specification. Notice that the master
À
Ó
cycles for the LM12434 and LM12 L 438’s I C interface.
may read only one word (single read) or as many words (two
bytes each) as it needs using the read procedure.
70
7.0 Digital Interface (Continued)
71
7.0 Digital Interface (Continued)
2
7.4.1 Example of Interfacing to an I C Bus Controller (No Assembly Code)
TL/H/11879–82
Note: Other device pins are not shown.
2
FIGURE 18. Interfacing the DAS to an I C Bus Controller
72
8.0 Analog Considerations
8.1 REFERENCE VOLTAGE
8.3 INPUT CURRENT
The difference between the voltages applied to the V
and V
REF
A charging current flows into or out of (depending on the
input voltage polarity) the analog input pins, IN0–IN7 at the
a
is the analog input voltage span (the difference
REF
b
between the voltages applied across two multiplexer inputs
or the voltage applied to one of the multiplexer inputs and
analog ground, over which 4095 positive and 4096 negative
start of the analog input acquisition time (t ). This cur-
ACQ
rent’s peak value will depend on the actual input voltage
applied.
codes exist). The voltage sources driving V
REF
must have very low output impedance and noise. The circuit
in Figure 19 is an example of a very stable reference appro-
or V
REF
a
b
8.4 INPUT SOURCE RESISTANCE
k
For low impedance voltage sources ( 60X for 8 MHz oper-
ation), the input charging current will decay, before the end
of the S/H’s acquisition time, to a value that will not intro-
duce any conversion errors. For higher source impedances,
the S/H’s acquisition time can be increased. As an exam-
ple, operating with a 8 MHz clock frequency and maximum
acquisition time, the LM12434 and LM12438’s analog inputs
can handle source impedances as high as 4.17 kX. Refer to
Section 6.2.1, Instruction RAM ‘‘00’’, Bits 12–15 for further
information.
À
Ó
priate for use with the LM12434 and LM12 L 438.
The ADC can be used in either ratiometric or absolute refer-
ence applications. In ratiometric systems, the analog input
voltage is proportional to the voltage used for the ADC’s
reference voltage. When this voltage is the system power
a
supply, the V
REF
pin is connected to V
and V
REF
is
b
a
A
connected to GND. This technique relaxes the system refer-
ence stability requirements because the analog input volt-
age and the ADC reference voltage move together. This
maintains the same output code for given input conditions.
8.5 INPUT BYPASS CAPACITANCE
For absolute accuracy, where the analog input voltage var-
ies between very specific voltage limits, a time and tempera-
ture stable voltage source can be connected to the refer-
ence inputs. Typically, the reference voltage’s magnitude
will require an initial adjustment to null reference voltage
induced full-scale errors.
External capacitors (0.01 mF–0.1 mF) can be connected be-
tween the analog input pins, IN0–IN7, and analog ground to
filter any noise caused by inductive pickup associated with
long input leads. These capacitors will not degrade the con-
version accuracy.
8.6 INPUT NOISE
8.2 INPUT RANGE
The leads to each of the analog multiplexer input pins
should be kept as short as possible. This will minimize input
noise and clock frequency coupling that can cause conver-
sion errors. Input filtering can be used to reduce the effects
of the noise sources.
À
Ó
The LM12434 and LM12 L 438’s fully differential ADC and
reference voltage inputs generate a two’s-complement out-
put that is found by using the equation below.
b
b
V
V
V
a
a
b
IN
IN
e
b
(4096) (/2
output code
(12-bit)
V
b
b
8.7 POWER SUPPLY CONSIDERATIONS
REF
REF
Decoupling and bypassing the power supply on a high reso-
lution ADC is an important design task. Noise spikes on the
b
b
V
IN
V
V
a
a
b
IN
e
b
(256) (/2
output code
(8-bit)
V
REF
REF
a
a
(digital supply) can cause
V
(analog supply) or V
A
D
b
Round up to the next integer value between 4096 to 4095
for 12-bit resolution and between 256 to 255 for 8-bit res-
conversion errors. The analog comparator used in the ADC
will respond to power supply noise and will make erroneous
conversion decisions. The DAS is especially sensitive to
power supply spikes that occur during the auto-zero or lin-
earity calibration cycles.
b
olution if the result of the above equation is not a whole
e
e
number. As an example, V
2.5V, V
1V,
sign output
code is positive full-scale, or 0,1111,1111,1111. If V
a
b
REF
REF
e
e
a
V
1.5V and V
GND. The 12-bit
a
b
IN
IN
a
REF
e
GND, the
b
e
5V, V
a
12-bit
e
e
3V, and V
IN
1V, V
b
a
REF
IN
sign output code is 0,1100,0000,0000.
*Tantalum
**Ceramic
TL/H/11879–20
FIGURE 19. Low Drift Extremely Stable Reference Circuit
73
8.0 Analog Considerations (Continued)
a
The LM12434/8 is designed to operate from a single 5V
power supply. The LM12 L 438 is designed to operate from
data and clock traces is very important. This reduces the
overshoot/undershoot and high frequency ringing on these
lines that can be capacitively coupled to analog circuitry
sections through stray capacitances.
À
Ó
a
a single
3.3V supply. The separate supply and ground
pins for the analog and digital portions of the circuit allow
separate external bypassing. To minimize power supply
noise and ripple adequate bypass capacitors should be
placed directly between power supply pins and their associ-
ated grounds. Both supply pins are generally connected to
the same supply source. In systems with separate analog
and digital supplies, the DAS should be powered from the
analog supply. At least a 10 mF tantalum electrolytic capaci-
tor in parallel with a 0.1 mF monolithic ceramic capacitor is
recommended for bypassing each power supply. The key
consideration for these capacitors is to have the low series
resistance and inductance. The capacitors should be placed
as close as physically possible to the supply and ground
pins with the smaller capacitor closer to the device. The
capacitors also should have the shortest possible leads in
order to minimize series lead inductance. Surface mount
chip capacitors are optimal in this respect and should be
used when possible.
À
Ó
The AGND and DGND in the LM12434 and LM12 L 438
are not internally connected together. They should be con-
nected together on the PC board right at the chip. This will
provide the shortest return path for the signals being ex-
changed between the internal analog and digital sections of
the DAS.
It is also a good design practice to have power plane layers
in the PC board. This will improve the supply bypassing (an
effective distributed capacitance between power and
ground plane layers) and voltage drops on the supply lines.
However, power planes are not essential as ground planes
are for the performance of the DAS. If power planes are
used, they should be separated into two planes and the
area and connections should follow the same guidelines as
mentioned for the ground planes. Each power plane should
be laid out over its associated ground planes, avoiding any
overlap between power and ground planes of different
types. When the power planes are not used, it is recom-
When the power supply regulator is not local on the board,
adequate bypassing (a high value electrolytic capacitor)
should be placed at the power entry point. The value of the
capacitor depends on the total supply current of the circuits
on the PC board. All supply currents should be supplied by
the capacitor instead of being drawn from the external sup-
ply lines, while the external supply charges the capacitor at
a steady rate.
a
pins from a low impedance supply point (the regulator
mended to use separate supply traces for the V
a
and
A
V
D
output or the power entry point to the PC board). This will
help ensure that the noisy digital supply does not corrupt
the analog supply.
When measuring AC input signals with the DAS, any cross-
talk between analog input/output lines and the reference
a
The DAS has two V
and DGND pins on two sides of its
D
g
g
g
) should be
REF
lines (IN0–IN7, MUXOUT , S/H IN , V
package. It is recommended to use a 0.1 mF plus a 10 mF
minimized. Cross talk is minimized by reducing any stray
capacitance between the lines. This can be done by in-
creasing the clearance between traces, keeping the traces
as short as possible, shielding traces from each other by
placing them on different sides of the AGND plane, or run-
ning AGND traces between them.
a
capacitor between pins 15 and 16 (V
) and 14 (DGND)
D
a
(DGND) for the PLCC package. The respective pins for the
and a 0.1 mF capacitor between pins 28 (V
) and 1
D
a
a
)
SO package are 21 and 22 (V
) and 20 (DGND), 6 (V
D
D
and 7 (DGND). The layout diagrams in Section 8.8 show the
recommended placement for the supply bypass capacitors.
Figure 20 also shows the reference input bypass capacitors.
Here the reference inputs are considered to be differential.
The performance of the DAS improves by having a 0.1 mF
8.8 PC BOARD LAYOUT AND GROUNDING
CONSIDERATIONS
a
b
, and by bypass-
capacitor between the V
REF
and V
REF
To get the best possible performance from the LM12434
ing in a manner similar to that described in Section 8.7 for
the supply pins. When a single ended reference is used,
À
Ó
and LM12 L 438, the printed circuit boards should have
separate analog and digital ground planes. The reason for
using two ground planes is to prevent digital and analog
ground currents from sharing the same path until they reach
a very low impedance power supply point. This will prevent
noisy digital switching currents from being injected into the
analog ground.
b
V
is connected to AGND and only two capacitors are
REF
used between V
recommended to directly connect the AGND side of these
a
b
a
10 mF). It is
and V
(0.1 mF
REF
REF
b
b
and
capacitors to the V
REF
instead of connecting V
REF
the ground sides of the capacitors separately to the ground
planes. This provides a significantly lower-impedance con-
nection when using surface mount technology.
Figure 20 illustrates a favorable layout for ground planes,
power supply and reference input bypass capacitors. Figure
20a shows a layout using a 28-pin PLCC socket and
through-hole assembly. Figure 20b shows a surface mount
layout for the same 28-pin PLCC package. A similar ap-
proach should be used for the SO package.
Figure 21 is intended to give a general idea of how the DAS
should be wired and interfaced to a mC that operates in the
Standard Interface mode. All necessary analog and digital
power supply and voltage reference bypass capacitors are
shown. A voltage reference of 4.096V generated by the
The analog ground plane should encompass the area under
the analog pins and any other analog components such as
the reference circuit, input amplifiers, signal conditioning cir-
cuits, and analog signal traces.
LM4040-4.1 is connected to the V
REF
of the DAS and the
is connected to analog ground. The serial interface
a
V
REF
b
pins P1 through P5 of the DAS are connected to the mC’s
serial control lines and the interrupt pin of the DAS is wired
directly to the interrupt of the mC. In this diagram the DAS
runs on a separate clock than the mC, however, in some
applications the DAS analog clock (CLK) may be a deriva-
tive of the mC’s clock.
The digital ground plane should encompass the area under
the digital circuits and the digital input/output pins of the
DAS. Having a continuous digital ground plane under the
74
8.0 Analog Considerations (Continued)
TL/H/11879–50
(a) Through Hole Technology with 28-Pin PLCC Socket
À
Ó
FIGURE 20. Printed Circuit Board Layout for LM12434 and LM12 L 438
75
8.0 Analog Considerations (Continued)
TL/H/11879–51
(b) Surface Mount Technology for 28-Pin PLCC Package
À
Ó
FIGURE 20. Printed Circuit Board Layout for LM12434 and LM12 L 438 (Continued)
76
8.0 Analog Considerations (Continued)
Microcontroller (Standard Interface Mode)
TL/H/11879–83
FIGURE 21. General Schematic of the DAS Operating in Standard Interface Mode
77
78
Physical Dimensions inches (millimeters)
Order Number LM12434CIWM, LM12438CIWM or LM12L438CIWM
NS Package Number M28B
79
Physical Dimensions inches (millimeters) (Continued)
Order Number LM12434CIV, LM12438CIV or LM12L438CIV
NS Package Number V28A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
Tel: 1(800) 272-9959
TWX: (910) 339-9240
National Semiconductor
GmbH
Livry-Gargan-Str. 10
D-82256 Furstenfeldbruck
Germany
Tel: (81-41) 35-0
Telex: 527649
Fax: (81-41) 35-1
National Semiconductor National Semiconductor
National Semiconductores
Do Brazil Ltda.
Rue Deputado Lacorda Franco
120-3A
Sao Paulo-SP
Brazil 05418-000
Tel: (55-11) 212-5066
Telex: 391-1131931 NSBR BR
Fax: (55-11) 212-1181
National Semiconductor
(Australia) Pty, Ltd.
Building 16
Business Park Drive
Monash Business Park
Nottinghill, Melbourne
Victoria 3168 Australia
Tel: (3) 558-9999
Japan Ltd.
Hong Kong Ltd.
Sumitomo Chemical
Engineering Center
Bldg. 7F
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
1-7-1, Nakase, Mihama-Ku Hong Kong
Chiba-City,
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Ciba Prefecture 261
Tel: (043) 299-2300
Fax: (043) 299-2500
Fax: (3) 558-9998
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
©2020 ICPDF网 联系我们和版权申明