LM2506GRX [NSC]
IC LINE TRANSCEIVER, BGA49, 4 X 4 MM, 1 MM HEIGHT, 0.50 MM PITCH, BGA-49, Line Driver or Receiver;
| 型号： | LM2506GRX |
| 厂家： | 
National Semiconductor |
| 描述： | IC LINE TRANSCEIVER, BGA49, 4 X 4 MM, 1 MM HEIGHT, 0.50 MM PITCH, BGA-49, Line Driver or Receiver |
| 文件： | 总19页 (文件大小：852K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 2006
LM2506
Low Power Mobile Pixel Link (MPL) Level 0, 18-bit RGB
Display Interface Serializer and Deserializer
General Description
Features
n RGB Display Interface support up to
The LM2506 device adapts RGB style display interfaces to
the Mobile Pixel Link (MPL) Level zero serial link. The
LM2506 supports one RGB display at up to 18-bit color
depth and 800 X 300 pixels (over 216 Mbps and 13.2 MHz
PCLK) is supported. A mode pin configures the device as a
Serializer (SER) or Deserializer (DES) so the same chip can
be used on both sides of the interface.
1
800 x 300 ⁄
2
SVGA formats
n MPL-Level 0 Physical Layer using two data and one
clock signal
n Low Power Consumption
n Pinout mirroring enables straight through layout with
minimal vias
The interconnect is reduced from 22 signals to only 3 active
signals with the LM2506 chipset easing flex interconnect
design, size constraints and cost.
n Level translation between host and display
n Auto Power Down on STOP PCLK
n Link power down mode reduces quiescent power
The LM2506 in SER mode resides beside an application,
graphics or baseband processor and translates a parallel
bus from LVCMOS levels to serial Mobile Pixel Link levels for
transmission over a flex cable (or coax) and PCB traces to
the DES located near the display module.
<
under 10 µA
n 1.74V to 2.0V core / analog supply voltage range
n 1.74V to 3.0V I/O supply voltage range
n −30C to 85C Operating temperature range
When the Power_Down (PD*) input is asserted on the SER,
the MDn and MC line drivers are powered down to save
current. The DES can be controlled by a separate Power-
_Down input or via a signal from the SER (PDOUT*).
System Benefits
n Small Interface
n Low Power
n Low EMI
n Intrinsic Level Translation
The LM2506 implements the physical layer of the MPL Level
0 Standard (MPL-0) and a 150 µA IB current (Class 0).
Typical Application Diagram - Bridge Chips
20125522
© 2006 National Semiconductor Corporation
DS201255
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Typical Application Diagram - RGB Mode to Display Driver
20125533
Ordering Information
NSID
Package Type
Package ID
GRA49A
LM2506GR
LM2506SQ
49L MicroArray, 4.0 X 4.0 X 1.0 mm, 0.5 mm pitch
40L LLP, 5.0 X 5.0 X 0.8 mm, 0.4 mm pitch
SQF40A
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2
Pin Descriptions - RGB Mode
Description
No.
Pin Name
I/O, Type
of Pins
MPL SERIAL BUS PINS
RGB Serializer
RGB Deserializer
MD[1:0]
MC
2
1
IO, MPL
IO, MPL
Ground
MPL Data Line Driver
MPL Data Receiver
MPL Clock Line Driver
MPL Clock Receiver
VSSA
MPL Ground - see Power/Ground Pins
CONFIGURATION/PARALLEL BUS PINS
RGB*
M/S*
TM
1
1
1
1
1
I,
RGB Mode Input
LVCMOS
Tie Low
I,
LVCMOS
I,
Tie High for Serializer (Master)
Tie Low for Deserializer (Slave)
Test Mode control input
Tie Low (normal mode)
RGB Mode control input zero
Tie Low
LVCMOS
I,
RM0
RM1
LVCMOS
I,
RGB Mode control input one
Tie Low
LVCMOS
CLOCK / POWER DOWN SIGNALS
PCLK
1
IO,
PCLK input
PCLK output
NA
LVCMOS
O,
PDOUT*
1
Power Down Output,
L = device in Power Down
H = Device active.
LVCMOS
PD*
1
I,
Power Down input,
LVCMOS
L = Powered down (sleep mode)
H = active mode
PARALLEL INTERFACE SIGNALS
D[17:0]
18
IO,
LVCMOS
IO,
RGB Data Bus inputs
Vertical Sync. Input
Horizontal Sync. Input
Data Enable Input
NA
RGB Data Bus outputs
Vertical Sync. Output
Horizontal Sync. Output
Data Enable Output
Parity Error Output
VS
1
LVCMOS
IO,
HS
1
LVCMOS
IO,
DE
1
LVCMOS
O,
PE
1
LVCMOS
POWER/GROUND PINS
VDDA
VSSA
1
1
1
1
2
2
9
1
Power
Ground
Power
Power Supply Pin for the SER PLL and MPL Interface. 1.74V to 2.0V
Ground Pin for the MPL Interface, and analog circuitry.
Power Supply Pin for the digital core. 1.74V to 2.0V
Ground Pin for the digital core.
VDDcore
VSScore
VDDIO
VSSIO
Vbulk
Ground
Power
Power Supply Pin for the parallel interface I/Os. 1.74V to 3.0V
Ground Pin for the parallel interface I/Os.
Ground
Connect to Ground - uArray Package
DAP
Connect to Ground - LLP Package
Note:
I = Input, O = Output, IO = Input/Output. Do not float input pins.
3
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Maximum Package Power Dissipation Capacity at 25˚C
GRA Package
1.8W
15mW/˚C
1.8W
Derate GRA Package above 25˚C
SQF Package
Supply Voltage (VDDA
Supply Voltage (VDD
Supply Voltage (VDDIO
)
−0.3V to +2.2V
−0.3V to +2.2V
−0.3V to +3.6V
−0.3V to (VDDIO
+0.3V)
Derate SQF Package above 25˚C
15mW/˚C
)
)
Recommended Operating
Conditions
LVCMOS Input/Output Voltage
Min Typ Max Units
MPL Input/Output Voltage
Junction Temperature
Storage Temperature
Lead Temperature Soldering,
40 Seconds
−0.3V to VDDA
+150˚C
Supply Voltage
VDDA to VSSA and
VDDcore to VSScore
VDDIO to VSSIO
−65˚C to +150˚C
1.74 1.8 2.0
V
V
1.74
3.0
+260˚C
PCLK Frequency
Ambient Temperature
2
13.3 MHz
ESD Ratings:
−30 25
85
˚C
HBM, 1.5 kΩ, 100 pF
EIAJ, 0Ω, 200 pF
≥ 2 kV
≥ 200V
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)
Symbol
MPL
Parameter
Conditions
Min
Typ
Max
Units
IOLL
Logic Low Current (5X IB)
Mid Scale Current
(Notes 4, 9)
3.67 IB
2.1IB
5.0 IB
3.0 IB
6.33 IB
3.9IB
µA
µA
IOMS
IOLH
IB
Logic High Current (1X IB)
Current Bias
0.7 IB
1.0 IB
150
1.4 IB
µA
µA
µA
IOFF
MPL Leakage Current
VMPL = 0.8V
−2
+2
LVCMOS (1.74V to 3.0V Operation)
VIH
VIL
Input Voltage High Level
Input Voltage Low Level
Input Hysteresis
0.7 VDDIO
GND
VDDIO
V
0.3 VDDIO
V
VHY
VDDIO = 1.74V
VDDIO = 3.0V
Includes IOZ
150
200
0
mV
mV
µA
µA
IIH
Input Current High Level
Input Current Low Level
Vin = VDDIO
Vin = GND
−1
−1
+1
+1
IIL
0
VOH
Output Voltage High Level IOH = −2 mA
0.75
VDDIO
VSSIO
VDDIO
V
V
VOL
Output Voltage Low Level
IOL = 2 mA
SER
0.2 VDDIO
SUPPLY CURRENT
IDD Total Supply
VDDIO
DD/VDDA
VDDIO
20
5
66
12
10
11
µA
mA
mA
Current—Enabled
Conditions: MC = 80 MHz,
MD = 160 Mbps
(Note 5)
V
DES
4
VDD/VDDA
6
mA
µA
Supply Current—Enabled
1.8V
SER
DES
VDDIO
10
V
DD/VDDA
4.7
2.3
6.2
mA
mA
mA
(Note 6)
VDDIO
V
DD/VDDA
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4
Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)
Symbol
MPL
Parameter
Conditions
Min
Typ
Max
Units
<
<
<
<
<
<
IDDZ
Supply Current—Disable
TA = 25˚C
SER
VDDIO
1
1
1
1
1
1
2
2.2
2
µA
µA
PD* = L
V
DD/VDDA
Power Down Modes
SER
VDDIO
µA
Stop Clock
V
DD/VDDA
2.2
2
µA
DES
VDDIO
µA
PD* = L
V
DD/VDDA
2.2
µA
PD
Power Dissipation
RGB
SER
DES
8.5
mW
mW
(Note 6)
15.3
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
PARALLEL BUS TIMING See
tSET
Set Up Time
Hold Time
Rise Time
RGB Mode Inputs
5
5
ns
ns
ns
ns
ns
ns
Figure 11
tHOLD
tRISE
PCLK Output
CL = 15 pF,
Figure 2
VDDIO = 1.74V
VDDIO = 3.0V
VDDIO = 1.74V
VDDIO = 3.0V
7
3
7
2
12
7
tFALL
Fall Time
11
6
SERIAL BUS TIMING
tDVBC Serial Data Valid before
DES Input
MC = 80MHz
(Note 9)
Clock
Figure 1
1.5
1.5
ns
ns
(Set Time)
Serial Data Valid after
Clock
tDVAC
(Hold Time)
POWER UP TIMING
t0
SER PLL Lock Counter
PCLK
cycles
MC
4,096
180
180
180
7
t1
MC Pulse Width Low
MC Pulse Width High
MC H-L to Active State
cycles
MC
t2
cycles
MC
t3
cycles
PCLK
cycles
tPZXclk
Enable Time - Clock Start
RGB Mode
CLK to PDout*
(Note 8)
Figure 4
MPL POWER OFF TIMING
tPAZ
Disable Time to Power
2
ms
Down
tPXZclk
Disable Time - Clock Stop
PCLK to PDOUT*
PCLK
cycles
7
Figure 3
5
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Recommended Input Timing Requirements
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SER PIXEL CLOCK (PCLK)
f
Pixel Clock Frequency
2
75.2
30
13.3
500
70
MHz
ns
tCP
Pixel Clock Period
Pixel Clock Duty Cycle
Transition Time
PCLKDC
tT
50
%
(Note 7)
2
ns
tSTOPpclk
PClock Stop Gap
300
ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
= 1.8V and V
= V
= 1.8V and T = 25˚C.
DDA A
DDIO
DD
Note 3: Current into a device pin is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to Ground unless otherwise
specified.
Note 4: MPL Current Threshold is set to be 3XI by the MPL start up Sequence - this is a functional specification only.
B
Note 5: Total Supply Current Conditions: RGB Mode, worse case data pattern, 13.3MHz PCLK, DES C = 15pF, TYP V
= V
= V
= 1.8V, MAX VDDIO
DDcore
L
DDIO
DDA
= 3.0V, MAX VDDA = VDDcore = 2.0V.
Note 6: Supply Current Conditions: RGB Mode, PRBS case data pattern, 13.3MHz PCLK, DES C = 15pF, TYP V
= V
= V
= 1.8V.
DDcore
L
DDIO
DDA
Note 7: Maximum transition time is a function of clock rate and should be less than 30% of the clock period to preserve signal quality.
Note 8: Guaranteed functionally by the I parameter. See also Figure 8.
DDZ
Note 9: This is a functional parameter and is guaranteed by design or characterization.
Timing Diagrams
20125516
FIGURE 1. Serial Data Valid—DES Input Set and Hold Time
20125518
FIGURE 2. DES Output Rise and Fall Time (PCLK)
20125529
FIGURE 3. Stop Clock Power Down (SER)
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6
Timing Diagrams (Continued)
20125530
FIGURE 4. Stop Clock Power Up (SER)
SERIAL BUS TIMING
Functional Description
Data valid is relative to both edges for a RGB transaction as
shown in Figure 6. Data valid is specified as: Data Valid
before Clock, Data Valid after Clock, and Skew between
data lines should be less than 500ps.
BUS OVERVIEW
The LM2506 is a dual link SER/DES configurable part that
supports an 18-bit RGB Display interface. The MPL physical
layer is purpose-built for an extremely low power and low
EMI data transmission while requiring the fewest number of
signal lines. No external line components are required, as
termination is provided internal to the MPL receiver. A maxi-
mum raw throughput of 320 Mbps (raw) is possible with this
chipset. When the protocol overhead is taken into account, a
maximum data throughput of 240 Mbps is possible. The MPL
interface is designed for use with common 50Ω to 100Ω lines
using standard materials and connectors. Lines may be
microstrip or stripline construction. Total length of the inter-
connect is expected to be less than 20cm.
20125503
FIGURE 6. Dual Link Timing (WRITE)
SERIAL BUS PHASES
There are three bus phases on the MPL serial bus. These
are determined by the state of the MC and MD lines. The
MPL bus phases are shown in Table 1.
The LM2506 supports MPL Level 0 Enhanced Protocol with
a Class 0 PHY.
20125502
FIGURE 5. MPL Point-to-Point Bus
TABLE 1. Link Phases
MDn State Phase Description
Name
MC State
Pre-Phase
A, I or LU
LU, A, or I
O
Post-Phase
LU
OFF (O)
0
A
H
0
X
-
Link is Off
ACTIVE (A)
Data Out
A, I, or O
A, I, or O
LINK-UP (LU)
SER initiated Link-Up
Notes on MC/MD Line State:
0 = no current (off)
L = Logic Low — The higher level of current on the MC and MD lines
H = Logic High — The lower level of current on the MC and MD lines
X = Low or High
A = Active Clock
SERIAL BUS START UP TIMING
are de-asserted (driven High) the SER enables its PLL and
waits for enough time to pass for its PLL to lock. After the
SER’s PLL is locked (t0 = 4,096 PCLK Cycles), the SER will
perform an MPL start up sequence. The DES will power up
and await the start up sequence from the SER once its PD*
input is driven High.
In the Serial Bus OFF phase, SER transmitters for MD0,
MD1 and MC are turned off such that zero current flows over
the MPL lines. In addition, both the SER and the DES are
internally held in a low power state. When the PD* input pins
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Next the SER drives the MC line logically HIGH for 180 MC
cycles (t2). The optimized current configuration is held as
long as the MPL remains active. Next, the SER drives both
the MC and the MD lines to a logical Low for another 180 MC
cycles (t3), after which it begins to toggle the MC line at 6X
the PCLK rate. The SER will continue to toggle the MC line
as long as its PD* pin remains de-asserted (High). At this
point, video data is streaming to the DES.
Functional Description (Continued)
The MPL start up sequence gives the DES an opportunity to
optimize the current sources in its receivers to maximize
noise margins. The SER begins the sequence by driving the
MC line logically Low for 180 MC cycles (t1). At this point, the
DES’s receiver samples the MC current flow and adjusts
itself to interpret that amount of current as a logical Low.
20125561
FIGURE 7. Bus Power Up Timing
Once power is applied and stable, the PCLK should be
applied to the SER. Next the PD* inputs are driven High to
enable the SER and DES. The DES PD* input may be driven
High first, at the same time, or slightly later than the SER’s
PD* input. The SER’s PLL locks to the PCLK and the SER
drives the MC line to the 5I (Logic Low) state at point "A" for
t1. Next the SER drives the MC line to the 1I (Logic High)
state for t2. On the T1 to t2 transition - point "B", the DES
calibrates its current to that of the SER to maximize noise
margins. Next the SER drives the MC and MD lines to the 5I
(logic Low) state for t3. At point "C", video data is now
sampled and streamed to the DES.
OFF PHASE
20125506
In the OFF phase, both SER and DES MPL transmitters are
turned off with zero current flowing on the MC and MDn
lines. Figure 8 shows the transition of the MPL bus into the
OFF phase. If an MPL line is driven to a logical Low (high
current) when the OFF phase is entered it may temporarily
pass through as a logical High (low current) before reaching
the zero line current state.
FIGURE 8. Bus Power Down Timing
RGB VIDEO INTERFACE
The LM2506 is transparent to data format and control signal
timing. Each PCLK, data inputs, HS, VS and DE are
sampled. A PCLK by PCLK representation of these signals is
duplicated on the opposite device after being transferred
across the MPL Level-0 interface.
The LM2506 uses a multiple range PLL and an on-chip
multiplier to accommodate a wide range of display formats.
QVGA to 1⁄
SVGA can be supported within the 2 MHz to 13.3
2
MHz PCLK input range.
Pixel Bandwidth = H. X V. X Color Depth X Frames
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8
PCLK Rate = Net Bandwidth / 24
Functional Description (Continued)
Pixel bandwidth is equal to display resolution times color
depth times frame rate.
The PCLK rate is equal to the net bandwidth divided by the
total number of bits.
Net Bandwidth = (Pixel BW)(24/18)(1.0 + % Blanking)
Net bandwidth is equal to the pixel bandwidth times the
overhead times the blanking overhead.
Format
Hor.
Ver.
Color
Frames
fps
Pixel
BW
Percent
Net
BW
PCLK
rate
MHz
13.2
11
Pixels
Pixels
Depth
Blanking
Mbps
216
180
152
76
Mbps
316
265
223
122
1
⁄
2SVGA
800
640
320
320
300
320
480
240
18
16
18
18
50
55
55
55
10
10
10
20
3
⁄
⁄
4
VGA
VGA
1
2
9.3
QVGA
5.1
Other RGB Color Depths
the RGB are not used and data is offset toward the upper
(MSB) end of the bit fields. Unused inputs should be tied off.
When transporting color depth below 18-bit, the 18-bit pro-
tocol can be used by offsetting the color data. The LSBs of
201255024
FIGURE 9. 18-bit RGB Display Mode Transaction
Parity Error Output
for each frame containing an error. The PCLK output can be
used to sample the PE bit. SET time is nominally 2 MC
cycles and a HOLD time of 1 MC cycle. The serial PE bit is
Odd Parity and is based on the RGB, and Control (VS, HS,
DE) bits only. See Figure 10.
Parity Status is output as a pulse on the Parity Error (PE)
output pin (DES) whenever there is a parity error. These
pulses could be counted or used by various diagnostic
equipment. PE is a high going pulse that is 3 MC cycles long
20125550
FIGURE 10. PE Output Timing
SYNCHRONIZATION DETECT AND RECOVERY
method chosen is a data transparent method, and has very
little overhead because it does not use a data expansion
coding method. For the 18-bit color transaction (or frame), it
If a data error or clock slip error occurs over the MPL link, the
LM2506 can detect this condition and recover from it. The
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If however, a clock slip or error occurs, the next N frames will
be bad and the F[1:0] field will not be detected properly for
each frame after the clock error. In this case, the hysteresis
counter will decrement to zero quickly (again where N=4 or 8
pixels). This action shuts down the output data (output PCLK
held Low), and initiates a search function for the increment-
ing sequence.
Functional Description (Continued)
uses two bits that are already required in the 6-MC cycle
transaction. Since double-edge clocking is used with two
data signals, adding one clock cycle to the transaction actu-
ally adds four bits. One of these bits is absolutely required -
data enable - thus the others are allocated to Parity and the
frame sequence (F[1:0]). Therefore total overhead for each
pixel is 3/24 or 12.5% in 18-bit RGB mode.
Detecting the Incrementing Sequence
Acquiring synchronization from a random position requires
looking only at the MD1 line, as this line contains the incre-
menting sequence F[1:0]. This is done by examining six
two-bit pairs and comparing each pair to an incrementing
sequence. A snapshot of the data is first taken and loaded
into six two-bit adders. The adders increment by one and
then compare the same bit positions in the next 12-bits. If a
match is found a flag is set for that bit pair. This same
procedure is followed until there is only one flag set. After
only one flag is set, the synchronization is tested for the full
count of the hysteresis counter (4 or 8 pixels) and then a
valid synchronization is declared and pixel data and strobes
are again output to the display.
HOST SIDE FUNCTION
The LM2506 in serializer mode simply increments the two bit
field F[1:0] on every pixel or frame transmitted. Therefore
every four frames, the pattern will repeat. It is very unlikely
that this pattern would be found within the payload data, and
if it were found, the probability that it would repeat for many
frames becomes infinitely small.
DISPLAY SIDE FUNCTION
The LM2506 in deserializer mode, upon a normal power up
sequence, starts in the proper synchronization. It looks for
the incrementing pattern for N (N = 4 or 8) pixels (frames)
and finding it, starts to output the pixel gray scale data and
timing signals.
In the best case, this parallel method of detecting sync is
very fast. If only one flag exists on the first frame tested, then
resynchronization can occur in as little as 6 pixel times
(assuming NNE = no new errors). If however, random data
emulates an incrementing sequence for several pixels of
time, the process can take longer. It is data dependant.
If a random bit error occurs in the F[1:0] field, the hysteresis
counter decrements by one, but the chip continues to output
data normally. The next frame will likely recover, increment-
ing the hysteresis counter back to the maximum and things
will continue normally. Likewise if a random bit error occurs
in the gray scale data, it only effects that bit and transmission
will continue normally on the next frame (pixel). The worst
case data bit error would cause a one pixel wide glitch in the
HS, VS or DE signals. This would likely cause a visible jump
in the display, but it would recover in a maximum of one
display frame time. (typically under 20mS)
It is important to note that a pathological case exists, as it
does for most pattern detection methods, where the data can
forever emulate this incrementing sequence, when in fact
the true F[1:0] is not detected. This F’[1:0] (F prime) may
occur for several pixels, but becomes linearly less probable
as more and more data passes through the system.
20125526
FIGURE 11. Serializer Mode Input Timing for RGB Interface
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Functional Description (Continued)
TABLE 2. Serializer Input Timing Parameters for RGB Interface
Sym.
tSET
Parameter
Min
5
Typ
Max
Units
ns
Data (RGB, DE, VS or HS) to PCLK - Set Time
PCLK to Data (RGB, DE, VS or HS) - Hold Time
tHOLD
5
ns
Note 10: Signal rise and fall times are equal to or less than 20ns
Note 11: Measurement of signal timing is made using 0.3 x VDDIO for the low sate and 0.7 x VDDIO for the high state.
20125527
FIGURE 12. Deserializer Mode Output Timing for RGB Interface
TABLE 3. Deserializer Output Timing Parameters for RGB Interface
Sym.
Parameter
Min
230
30
Typ
Max
Units
ns
tDVBC
Data Valid before PCLK (rise) PCLK = 2 MHz
(Note 9)
PCLK = 13.3 MHz
PCLK = 2 MHz
ns
tDVAC
Data Valid after PCLK (rise)
(Note 9)
230
30
ns
PCLK = 13.3 MHz
ns
tPCLK
Pixel Clock Period
Pixel Clock Low
Pixel Clock High
75.2
500
ns
PCLKLOW
PCLKHIGH
50
50
%
%
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POWER DOWN/OFF CONFIGURATION / OPTIONS AND
CLOCK STOP
LM2506 Features and Operation
Power Up Operation - Upon the application of power to the
LM2506, devices configured as a DES activate all outputs.
Outputs are held in deasserted states, with all zeros on the
data busses until valid data is received from the SER. If PD*
is asserted (Low) prior to the application of power, then the
part remains in its power down state.
POWER SUPPLIES
The VDDcore and VDDA (MPL and PLL) must be connected to
the same potential between 1.74V and 2.0V. VDDIO powers
the logic interface and may be powered between 1.74 and
3.0V to be compatible with a wide range of host and target
devices. On this device, VDDIO should be powered up
On both the SER and the DES, the PD* pin resets the logic.
The PD* pins should be held low until the power supply
has ramped up and is stable and within specifications.
before VDDcore/VDDA or at the same time as VDDcore
VDDAfor proper device configuration.
/
BYPASS RECOMMENDATIONS
Power Down and the use of the PD* Input - When the PD*
signal is asserted low, the entire chip regardless of mode,
powers down. A Low on the PD* input pin will power down
the entire device and turn off the line current to MD0, MD1,
and MC. In this state the following outputs are driven to:
Bypass capacitors should be placed near the power supply
pins of the device. Use high frequency ceramic (surface
mount recommended) 0.1 µF capacitors. A 2.2 to 4.7 µF
Tantalum capacitor is recommended near the SER VDDA pin
for PLL bypass. Connect bypass capacitors with wide traces
and use dual or larger via to reduce resistance and induc-
tance of the feeds. Utilizing a thin spacing between power
and ground planes will provide good high frequency bypass
above the frequency range where most typical surface
mount capacitors are less effective. To gain the maximum
benefit from this, low inductance feed points are important.
Also, adjacent signal layers can be filled to create additional
capacitance. Minimize loops in the ground returns also for
improved signal fidelity and lowest emissions.
SER:
PDOUT = Low
DES:
DATAn = PCLK = Low,
VS = HS = DE = PE = Low
Multiple configurations for PowerDown are possible with the
chipset. These depend on the operating mode and configu-
ration chosen. Two possible applications are shown in Figure
14. RGB Modes are shown in (A) and (B). "A" provides PD*
input pins on both devices, this may be common or seperate.
In (B), the SER is controlled by the PCLK STOP feature and
a PDOUT* pin is provided to control the DES. When using
the SER PDOUT* mode, the VDDIO rails of the devices should
be the same to meet the PD* input thresholds of the DES.
UNUSED/OPEN PINS
Unused inputs must be tied to the proper input level—do not
float them. Unused outputs should be left open to minimize
power dissipation.
The LM2506 provides a PCLK STOP feature on the SER
device. Gating of the pixel clock signal can be used to
generate a control signal for the SER to Power down or start
up. When a loss of pixel clock is detected (PLL out of lock),
the SER PDOUT* pin is driven Low and the SER powers
down. When a PCLK is reapplied, the SER powers up, and
the PLL locks to the incoming clock signal. After 4,096 cycles
(t0), the SER MPL outputs are enabled and the DES is
calibrated. Once this is complete (t1 + t2 + t3), data trans-
mission can occur. See Figures 3, 4. The stopping of the
pixel clock should be done cleanly. Floating of the PCLK
input pin is not recommended.
PHASE-LOCKED LOOP
When the LM2506 is configured as a RGB Serializer, a PLL
is enabled to generate the serial link clock. The Phase-
locked loop system generates the serial data clock at 6X of
the input clock. The MC rate must be between 12 and 80
MHz (PCLKs from 2 to 13.3 MHz).
MASTER(SER)/SLAVE(DES) SELECTION
The M/S* pin is used to configure the device as either a SER
or DES device. When the M/S* pin is a Logic High, the
Serializer (SER) configuration is selected. The Driver block
is enabled for the MC line, and the MD lines. When the M/S*
pin is a Logic Low, the Deserializer (DES) configuration is
selected. The Receiver block is enabled for the MC line, and
the MD lines.
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12
LM2506 Features and Operation (Continued)
20125532
FIGURE 13. Power Down Control Options
MPL SWAP FEATURE
Application Information
The LM2506 provides a swap function of MPL MD lines
depending upon the state of the M/S* pin. This facilitates a
straight through MPL interface design eliminating the needs
for via and crossovers as shown on Figure 14. The parallel
bus pins are also swapped to facilitate a flow though orien-
tation of parallel bus signals.
SYSTEM CONSIDERATIONS
When employing the MPL SER/DES chipset in place of a
parallel bus, a few system considerations must be taken into
account. VDDIO levels of the Host and SER must be com-
patible. VDDIO levels of the DES and the Display must be
compatible. The LM2506 only supports rising edge clocking,
both the Host and Display must be compatible with this.
201255029
FIGURE 14. MPL Interface Layout
13
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Application Information (Continued)
Power and Ground - Bumped Package
PCB for the microArray package. See also, National’s Appli-
cation Note AN-1126, Ball Grid Array, for information on land
pattern recommendations and escape routing guidelines.
Power and ground bump assignments are shown in Figure
15. The nine center balls must be connected ground on the
20125521
FIGURE 15. LM2506 PWR (VDD) and GND (VSS) Bumps (TOP VIEW)
FLEX CIRCUIT RECOMMENDATIONS
common ground plane. The separate ground pins help to
isolate switching currents from different sections of the inte-
grated circuit (IC). Also required is a nearby signal return
(ground) for the MPL signals. These should be provided next
to the MPL signals, as that will create the smallest current
loop area. The grounds are also useful for noise isolation
and impedance control.
The three MPL lines should generally run together to mini-
mize any trace length differences (skew). For impedance
control and also noise isolation (crosstalk), guard ground
traces are recommended in between the signals. Commonly
a Ground-Signal-Ground (GSGSGSG) layout is used. Lo-
cate fast edge rate and large swing signals further away to
also minimize any coupling (unwanted crosstalk). In a
stacked flex interconnect, crosstalk also needs to be taken
into account in the above and below layers (vertical direc-
tion). To minimize any coupling locate MPL traces next to a
ground layer. Power rails also tend to generate less noise
than LVCMOS so they are also good candidates for use as
isolation and separation.
PCB RECOMMENDATIONS
General guidelines for the PCB design:
•
•
•
Floor plan – locate MPL SER near the connector to limit
chance of cross talk to high speed serial signals.
Route serial traces together, minimize the number of
layer changes to reduce loading.
Use ground lines are guards to minimize any noise cou-
pling (guarantees distance).
The interconnect from the SER to the DES typically acts like
a transmission line. Thus impedance control and ground
returns are an important part of system design. Impedance
should be in the 50 to 100 Ohm nominal range for the
LM2506. Testing has been done with cables ranging from 40
to 110 Ohms without error (BER Testing). To obtain the
impedance, adjacent grounds are typically required ( 1 layer
flex), or a ground shield / layer. Total interconnect length is
intended to be in the 20cm range, however 30cm is possible
at lower data rates. Skew should be less than 500ps to
maximize timing margins.
•
•
Avoid parallel runs with fast edge, large LVCMOS swings.
Also use a GSGSG pinout in connectors (Board to Board
or ZIF).
•
•
DES device - follow similar guidelines.
Bypass the device with MLC surface mount devices and
thinly separated power and ground planes with low induc-
tance feeds.
•
High current returns should have a separate path with a
width proportional to the amount of current carried to
minimize any resulting IR effects.
GROUNDING
While the LM2506 employs three separate types of ground
pins, these are intended to be connected together to a
www.national.com
14
Application Information (Continued)
20125562
FIGURE 16. MPL Interface Layout
15
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Connection Diagram microArray Package
20125519
TOP VIEW
(not to scale)
RGB SER Pinout
SER
1
2
RGB*
PDOUT*
R0
3
4
5
6
RM1
PD*
VS
7
M/S*
HS
A
TM
MD0
RM0
Vbulk
Vbulk
Vbulk
G2
MC
MD1
VDDA
Vbulk
Vbulk
Vbulk
G5
B
PCLK
R1
VSSA
Vbulk
C
DE
D
VDDIO
R2
VSSIO
R3
Vbulk
VSSIO
B4
VDDIO
B5
E
Vbulk
F
R4
R5
VSScore
VDDcore
B1
B3
G
G0
G1
G3
G4
B0
B2
RGB DES Pinout
DES
1
TM
VS
2
RGB*
HS
3
4
5
6
7
M/S*
PE
A
MD1
RM0
Vbulk
Vbulk
Vbulk
G4
MC
MD0
VDDA
Vbulk
Vbulk
Vbulk
G1
RM1
PD*
PCLK
VSSIO
R2
B
VSSA
Vbulk
C
B5
DE
R0
D
VDDIO
B4
VSSIO
B3
Vbulk
VDDIO
R1
E
Vbulk
F
B2
B1
VSScore
VDDcore
R5
R3
G
B0
G5
G3
G2
G0
R4
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16
Connection Diagram - LLP Package
20125553
TOP VIEW — (not to scale)
TABLE 4. RGB Mode Pad Assignment
Pin #
1
SER
DES
Pin #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DAP
SER
G0
DES
M/S*
RM1
VDDA
B0
G5
G4
2
G1
3
G2
4
MD1
MD0
MD0
MD1
HS
G3
5
VSSA
MC
VSScore
VDDcore
6
7
G4
G5
B0
B1
B2
B3
B4
B5
G2
G1
G0
R5
R4
R3
R2
R1
8
RM0
9
RGB*
10
11
12
13
14
15
16
17
18
19
20
DAP
PDOUT*
TM
PCLK
R0
VS
DE
B5
R1
VSSIO
VDDIO
VSSIO
VDDIO
R2
R3
R4
R5
B4
B3
B2
B1
DE
VS
HS
R0
PCLK
PE
PD*
GND
GND
Note: Pins are different between SER and DES configurations.
17
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
49L MicroArray, 0.5mm pitch
Order Number LM2506GR
NS Package Number GRA49A
40L LLP, 0.4mm pitch
Order Number LM2506SQ
NS Package Number SQF40A
www.national.com
18
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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