LM25115AMTX [NSC]

Secondary Side Post Regulator/DC-DC Converter with Power-Up/Power-Down Tracking; 次级侧后稳压器/ DC -DC转换器上电/断电跟踪


型号：	LM25115AMTX
厂家：	National Semiconductor
描述：	Secondary Side Post Regulator/DC-DC Converter with Power-Up/Power-Down Tracking 次级侧后稳压器/ DC -DC转换器上电/断电跟踪转换器稳压器
文件：	总20页 (文件大小：403K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

February 2007

LM25115A

Secondary Side Post Regulator/DC-DC Converter with

Power-Up/Power-Down Tracking

General Description

Features

The LM25115A controller contains all of the features neces-

sary to produce multiple tracking outputs using the Secondary

Side Post Regulation (SSPR) technique. The SSPR tech-

nique develops a highly efficient and well regulated auxiliary

output from the secondary side switching waveform of an iso-

lated power converter. LM25115A can be also used as a

standalone DC/DC synchronous buck controller (Refer to

Synchronous Buck section). Regulation of the auxiliary

output voltage is achieved by leading edge pulse width mod-

ulation (PWM) of the main channel duty cycle. Leading edge

modulation is compatible with either current mode or voltage

mode control of the main output. The LM25115A drives ex-

ternal high-side and low-side NMOS power switches config-

ured as a synchronous buck regulator. A current sense

amplifier provides overload protection and operates over a

wide common mode input range. Additional features include

a low dropout (LDO) bias regulator, error amplifier, precision

reference, adaptive dead time control of the gate signals and

thermal shutdown.

Power-up/Power-down Tracking

■

Self-synchronization to main channel output

Leading edge pulse width modulation

Valley current Mode control

Standalone DC/DC synchronous buck mode

Operates from AC or DC input up to 42V

Wide 4.5V to 30V bias supply range

Wide 0.75V to 13.5V output range.

Top and bottom gate drivers sink 2.5A peak

Adaptive gate driver dead-time control

Wide bandwidth error amplifier (4MHz)

Programmable soft-start

Thermal shutdown protection

■

TSSOP-16 package

■

Typical Application Circuit

30008301

FIGURE 1. Simplified Multiple Output Power Converter Utilizing SSPR Technique

300083

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Connection Diagram

16-Lead TSSO³P^0008302

See NS Package Numbers MTC16

Ordering Information

Ordering Number

LM25115AMT

Package Type

Nsc Package Drawing

MTC16

Supplied As

TSSOP-16

92 Units Per Anti-Static Tube

2500 units shipped as Tape & Reel

LM25115AMTX

MTC16

Pin Descriptions

Name

Description

Application Information

Current Sense amplifier positive input

A low inductance current sense resistor is connected between CS

and VOUT. Current limiting occurs when the differential voltage

between CS and VOUT exceeds 45mV (typical).

VOUT

Current sense amplifier negative input

Connected directly to the output voltage. The current sense

amplifier operates over a voltage range from 0V to 13.5V at the

VOUT pin.

AGND

Analog ground

Connect directly to the power ground pin (PGND).

Current limit output

For normal current limit operation, connect the CO pin to the

COMP pin through a diode. CO pin is connected to ground through

a resistor in series with a capacitor to provide adequate control

loop compensation for the current limit gm amplifier. Leave this

pin open to disable the current limit function.

COMP

Compensation. Error amplifier output

Feedback. Error amplifier inverting input

COMP pin pull-up is provided by an internal 300uA current source.

Connected to the regulated output through the feedback resistor

divider and compensation components. The non-inverting input of

the error amplifier is internally connected to the SS pin.

TRK/SS

RAMP

Tracking/Soft-start control

PWM Ramp signal

Non-inverting input to error amp with 15 µA pull-up current source.

Can be used with capacitor for soft-start or tied to external divider

of a master output for tracking. TRK/SS is the reference input to

the amplifier when the voltage applied to the pin is < 0.75V. For

higher inputs, the internal reference controls the amplifier.

An external capacitor connected to this pin sets the ramp slope

for the voltage mode PWM. The RAMP capacitor is charged with

a current that is proportional to current into the SYNC pin. The

capacitor is discharged at the end of every cycle by an internal

MOSFET.

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Name

Description

Synchronization input

Application Information

SYNC

A low impedance current input pin. The current into this pin sets

the RAMP capacitor charge current and the frequency of an

internal oscillator that provides a clock for the free-run (DC input)

mode .

PGND

Power Ground

Connect directly to the analog ground pin (AGND).

Low-side gate driver output

Connect to the gate of the low-side synchronous MOSFET

through a short low inductance path.

VCC

Output of bias regulator

Nominal 7V output from the internal LDO bias regulator. Locally

decouple to PGND using a low ESR/ESL capacitor located as

close to controller as possible.

High-side MOSFET source connection

High-side gate driver output

Connect to negative terminal of the bootstrap capacitor and the

source terminal of the high-side MOSFET.

Connect to the gate of high-side MOSFET through a short low

inductance path.

High-side gate driver bootstrap rail

Connect to the cathode of the bootstrap diode and the positive

terminal of the bootstrap capacitor. The bootstrap capacitor

supplies current to charge the high-side MOSFET gate and should

be placed as close to controller as possible.

VBIAS

Supply Bias Input

Input to the LDO bias regulator and current sense amplifier that

powers internal blocks. Input range of VBIAS is 4.5V to 30V.

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Junction Temperature

ESD Rating

HBM (Note 2)

+150°C

2 kV

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Operating Ratings

VBIAS supply voltage

VCC supply voltage

HS voltage

VBIAS to GND

VCC to GND

–0.3V to 32V

–0.3V to 9V

5V to 30V

5V to 7.5V

0V to 42V

HS to GND

–1V to 45V

VOUT, CS to GND

All other inputs to GND

Storage Temperature Range

– 0.3V to 15V

−0.3V to 7.0V

–55°C to +150°C

HB voltage

Operating Junction Temperature

VCC + HS

–40°C to +125°C

Typical Operating Conditions

Min

Parameter

Typ

Max

Units

Supply Voltage, VBIAS

4.5

Supply Voltage, VCC

Supply voltage bypass, CVBIAS

Reference bypass capacitor, CVCC

HB-HS bootstrap capacitor

0.1

µF

µA

0.1

0.047

SYNC Current Range (VCC = 4.5V)

RAMP Saw Tooth Amplitude

150

1.75

13.5

VOUT regulation voltage (VBIAS min = 3V + VOUT)

0.75

Electrical Characteristics (Note 3) Unless otherwise specified, T_J= –40°C to +125°C, VBIAS = 12V, No Load

on LO or HO.

Symbol

Parameter

Conditions

F_SYNC= 200kHz

Min

Typ

Max

Units

VBIAS SUPPLY

Ibias

VBIAS Supply Current

VCC LOW DROPOUT BIAS REGULATOR

VccReg

VCC Regulation

VCC open circuit. Outputs not switching

(Note 4)

6.65

7.15

VCC Current Limit

VCC Under-voltage Lockout Voltage Positive going VCC

VCC Under-voltage Hysteresis

4.5

0.3

0.2

0.25

TRACK / SOFT-START

SS Pull-up Source

µA

SS Discharge Impedance

140

Ω

ERROR AMPLIFIER and FEEDBACK REFERENCE

VREF

FB Reference Voltage

FB Input Bias Current

COMP Source Current

Open Loop Voltage Gain

Gain Bandwidth Product

Input Offset Voltage

COMP Offset

Measured at FB pin

FB = 2V

.737

.750

0.2

300

.763

0.5

µA

MHz

GBW

Vio

Threshold for V_HO= high RAMP = CS =

VOUT = 0V

RAMP Offset

Threshold for V_HO= high COMP = 1.5V,

CS = VOUT = 0V

1.0

CURRENT SENSE AMPLIFIER

Current Sense Amplifier Headroom Headroom = V_bias– Vout

V_bias= 4.5 V and Vout= 1.5 V

Current Sense Amplifier Gain

V/V

Output DC Offset

1.27

500

Amplifier Bandwidth

kHz

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

CURRENT LIMIT

Slow ILIMIT Amp Transconductance

Overall Transconductance

Slow ILimit Threshold

mA / V

V_CL= V_CS- V_VOUT

VOUT = 6V and CO/COMP = 1.5V

V_CL= V_CS- V_VOUT

Slow ILimit Foldback

VOUT = 0V and CO/COMP = 1.5V

Vds = 2V

Fast ILimit Pull-Down Current

Fast ILimit Threshold

V_CLNEG

Negative Current Limit

VOUT = 6V

-17

V_CL= V_CS- V_VOUTto cause LO to shutoff

CO Clamp Voltage

ICO Pull-Up Current

5.5

6.5

µA

RAMP GENERATOR

SYNC Input Impedance

2.5

kΩ

µA

SYNC Threshold

End of cycle detection threshold

Free Run Mode Peak Threshold

RAMP peak voltage with dc current

applied to SYNC.

2.35

3.3

Current Mirror Gain

Ratio of RAMP charge current to SYNC

input current.

2.7

A/A

Discharge Impedance

100

Ω

LOW-SIDE GATE DRIVER

V_OLL

V_OHL

LO Low-state Output Voltage

LO High-state Output Voltage

LO Rise Time

I_LO= 100mA

0.15

0.35

0.5

0.8

I_LO= -100mA, V_OHL= V_CC-V_LO

C_LOAD= 1000pF

V_LO= 0V

LO Fall Time

I_OHL

I_OLL

Peak LO Source Current

Peak LO Sink Current

V_LO= 12V

2.5

HIGH-SIDE GATE DRIVER

V_OLH

V_OHH

HO Low-state Output Voltage

I_HO= 100mA

0.15

0.35

0.5

0.8

HO High-state Output Voltage

HO Rise Time

I_HO= -100mA, V_OHH= V_HB–V_HO

C_LOAD= 1000pF

V_HO= 0V

HO High-side Fall Time

Peak HO Source Current

Peak HO Sink Current

I_OHH

I_OLH

V_HO= 12V

2.5

SWITCHING CHARACTERISITCS

LO Fall to HO Rise Delay

C_LOAD= 0

HO Fall to LO Rise Delay

SYNC Fall to HO Fall Delay

SYNC Rise to LO Fall Delay

120

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Symbol

Parameter

Conditions

Min

150

Typ

Max

Units

THERMAL SHUTDOWN

T_SD

Thermal Shutdown Temp.

165

°C

Thermal Shutdown Hysteresis

THERMAL RESISTANCE

Junction to Ambient

MTC Package

SDA Package

125

°C/W

θ_JA

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation

of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,

see the Electrical Characteristics tables.

Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.

Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical

Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

Note 4: Device thermal limitations may limit usable range.

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Typical Performance Characteristics

Efficiency vs. Load Current and Vphase

(V_OUT= 2.5V)

V_CCRegulator Start-up Characteristics, V_CCvs. V_BIAS

30008322

30008304

Current Value (CV) vs. Current Limit (V_CL

)

Current Sense Amplifier Gain and Phase vs. Frequency

30008307

30008306

Current Error Amplifier Transconductance

Overall Current Amplifier Transconductance

30008309

30008308

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Common Mode Output Voltage vs. Positive Current Limit Common Mode Output Voltage vs. Negative Current Limit

(Room Temp)

30008310

30008311

V_CCLoad Regulation to Current Limit

30008305

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Block Diagram

30008303

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Detailed Operating Description

Synchronization (SYNC) and Feed-

Forward (RAMP)

The LM25115A controller contains all of the features neces-

sary to implement multiple output power converters utilizing

the Secondary Side Post Regulation (SSPR) technique. The

SSPR technique develops a highly efficient and well regulat-

ed auxiliary output from the secondary side switching wave-

form of an isolated power converter. Regulation of the

auxiliary output voltage is achieved by leading edge pulse

width modulation (PWM) of the main channel duty cycle.

Leading edge modulation is compatible with either current

mode or voltage mode control of the main output. The

LM25115A drives external high-side and low-side NMOS

power switches configured as a synchronous buck regulator.

A current sense amplifier provides overload protection and

operates over a wide common mode input range from 0V to

13.5V. Additional features include a low dropout (LDO) bias

regulator, error amplifier, precision reference, adaptive dead

time control of the gate driver signals and thermal shutdown.

The pulsing “phase signal” from the main converter synchro-

nizes the PWM ramp and gate drive outputs of the LM25115A.

The phase signal is the square wave output from the trans-

former secondary winding before rectification (Figure 1). A

resistor connected from the phase signal to the low

impedance SYNC pin produces a square wave current

(I_SYNC) as shown in Figure 2. A current comparator at the

SYNC input monitors I_SYNCrelative to an internal 15µA refer-

ence. When I_SYNCexceeds 15µA, the internal clock signal

(CLK) is reset and the capacitor connected to the RAMP be-

gins to charge. The current source that charges the RAMP

capacitor is equal to 3 times the I_SYNCcurrent. The falling edge

of the phase signal sets the CLK signal and discharges the

RAMP capacitor until the next rising edge of the phase signal.

The RAMP capacitor is discharged to ground by a low

impedance (100Ω) n-channel MOSFET. The input

impedance at SYNC pin is 2.5kΩ which is normally much

smaller than the external SYNC pin resistance.

Low Drop-Out Bias Regulator (VCC)

The LM25115A contains an internal LDO regulator that op-

erates over an input supply range from 4.5V to 30V. The

output of the regulator at the VCC pin is nominally regulated

at 7V and is internally current limited to 40mA. VCC is the

main supply to the internal logic, PWM controller, and gate

driver circuits. When power is applied to the VBIAS pin, the

regulator is enabled and sources current into an external ca-

pacitor connected to the VCC pin. The recommended output

capacitor range for the VCC regulator is 0.1uF to 100uF.

When the voltage at the VCC pin reaches the VCC under-

voltage lockout threshold of 4.25V, the controller is enabled.

The controller is disabled if VCC falls below 4.0V (250mV

hysteresis). In applications where an appropriate regulated dc

bias supply is available, the LM25115A controller can be

powered directly through the VCC pin instead of the VBIAS

pin. In this configuration, it is recommended that the VCC and

the VBIAS pins be connected together such that the external

bias voltage is applied to both pins. The allowable VCC range

when biased from an external supply is 4.5V to 7V.

The RAMP and SYNC functions illustrated in Figure 2 provide

line voltage feed-forward to improve the regulation of the aux-

iliary output when the input voltage of the main converter

changes. Varying the input voltage to the main converter pro-

duces proportional variations in amplitude of the phase signal.

The main channel PWM controller adjusts the pulse width of

the phase signal to maintain constant volt*seconds and a

regulated main output as shown in Figure 3. The variation of

the phase signal amplitude and duration are reflected in the

slope and duty cycle of the RAMP signal of the LM25115A

(I_SYNCα phase signal amplitude). As a result, the duty cycle

of the LM25115A is automatically adjusted to regulate the

auxiliary output voltage with virtually no change in the PWM

threshold voltage. Transient line regulation is improved be-

cause the PWM duty cycle of the auxiliary converter is imme-

diately corrected, independent of the delays of the voltage

regulation loop.

30008312

FIGURE 2. Line Feed-Forward Diagram

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30008313

FIGURE 3. Line Feed-Forward Waveforms

The recommended SYNC input current range is 50µA to

VOUT(final) = regulator output set point

150µA. The SYNC pin resistor (R_SYNC) should be selected to

set the SYNC current (I_SYNC) to 150µA with the maximum

phase signal amplitude, V_PHASE(max). This will guarantee that

I_SYNCstays within the recommended range over a 3:1 change

in phase signal amplitude. The SYNC pin resistor is therefore:

Pull-up current for the error amplifier output is provided by an

internal 300µA current source. The PWM threshold signal at

the COMP pin can be controlled by either the open drain error

amplifier or the open drain current amplifier connected

through the CO pin to COMP. Since the internal error amplifier

is configured as an open drain output it can be disabled by

connecting FB to ground. The current sense amplifier and

current limiting function will be described in a later section.

R_SYNC= (V_PHASE(max)/ 150µA) - 2.5kΩ

Once I_SYNChas been established by selecting R_SYNC, the

RAMP signal slope/amplitude may be programmed by se-

lecting the proper RAMP pin capacitor value. The RAMP

signal slope should be selected to provide adequate slope

compensation for the Valley current mode control scheme

(Please refer to the Valley current mode section). The rec-

ommended peak amplitude of the ramp waveform is 1.75V.

Power-Up/Power-Down Tracking

The LM25115A can track the output of a master power supply

during soft start by connecting a resistor divider to the TRACK

pin (Figure 4). Therefore, the output voltage slew rate of the

LM25115A will be controlled by the master supply for loads

that require precise sequencing. In order to track properly the

output voltage of the LM25115A must be lower than the output

voltage of the master supply.

Error Amplifier and Soft-Start (FB,

CO, COMP & TRK/SS)

One way to use the tracking feature is to design the tracking

resistor divider so that the master supply output voltage

(VOUT1) and the LM25115A output voltage (VOUT2) both

rise together and reach their target values at the same time.

For this case, the equation governing the values of the track-

ing divider resistors RT1 and RT2 is:

An internal wide bandwidth error amplifier is provided within

the LM25115A for voltage feedback to the PWM controller.

The amplifier’s inverting input is connected to the FB pin. The

output of the auxiliary converter is regulated by connecting a

voltage setting resistor divider between the output and the FB

pin. Loop compensation networks are connected between the

FB pin and the error amplifier output (COMP). The amplifier

has two non-inverting inputs. The first non-inverting input

connects to a 0.75V bandgap reference while the second non-

inverting input connects to the TRK/SS pin and it has 15 µA

pull-up current source. The TRK/SS pin can be tied to an ex-

ternal resistor divider from the master output for tracking, or

it can be tied to a capacitor for soft-start . TRK/SS is the ref-

erence input to the amplifier when the voltage applied to the

pin is < 0.75V. For higher inputs, the internal reference con-

trols the amplifier. When the VCC voltage is below the UVLO

threshold, the TRK/SS pin is discharged to ground. When

VCC rises and exceeds the positive going UVLO threshold

(4.25V), the TRK/SS pin is released and allowed to rise. If an

external capacitor is connected to the TRK/SS pin, it will be

charged by the internal 15uA pull-up current source to grad-

ually increase the non-inverting input of the error amplifier to

0.75V. During start-up, the output of the LM25115A converter

will follow the following equation:

A value of 10kΩ (1%) is recommended for RT2 as a good

compromise between high precision and low quiescent cur-

rent through the divider. If the master supply voltage was 3.3V

and the LM25115A output voltage was 2.5 V, then the value

of RT1 needed to give the two supplies identical soft start

times would be 2.94 kΩ (1%). The timing diagram and wave-

forms for the equal soft start time configuration are shown in

Figure 5 and Figure 6.

VOUT(t) = VOUT(final) x15 µA x t /(.75 Vx Css )

Where

Css = external Soft-Start capacitor

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Alternatively, the tracking feature can be used to create equal

slew rates between the output voltages of the master supply

and the LM25115A. This method ensures that the output volt-

age of the LM25115A always reaches regulation before the

output voltage of the master supply. In this case, the tracking

resistors can be determined based on the following equation:

Again, a value of 10kΩ 1% is recommended for RT2. For the

case of VOUT1 = 3.3V and VOUT2 = 2.5V, RT1 should be

4.32 kΩ 1%. The timing diagram and the waveforms for equal

slew rates configuration are shown in Figure 7 and Figure 8.

30008329

FIGURE 4.

30008330

FIGURE 7.

30008331

FIGURE 5.

30008328

Vphase = 10V

CH1 = Master output, 1V/Div

CH2 = COMP, 5/Div

CH3 = Iout, 1A/Div

CH4 = SSPR Output (Slave), 1V/Div

Horizontal Resolution= 200 µs/Div

30008327

Vphase = 10V

CH1 = Master output, 1V/Div

CH2 = COMP, 5/Div

CH3 = Iout, 1A/Div

FIGURE 8. Tracking with Equal Slew Rate

CH4 = SSPR Output (Slave), 1V/Div

Horizontal Resolution= 200 µs/Div

FIGURE 6. Tracking with Equal Soft Start Time

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Leading edge modulation of the auxiliary PWM controller is

required if the main converter uses peak current mode con-

trol. If trailing edge modulation were used, the additional load

on the transformer secondary from the auxiliary channel

would be drawn only during the first portion of the phase signal

pulse. Referring to Figure 10, the turn-off of the high- side

MOSFET of the auxiliary regulator would create a non-mono-

tonic negative step in the transformer current. This negative

current step would produce instability in a peak current mode

controller. With leading edge modulation, the additional load

presented by the auxiliary regulator on the transformer sec-

ondary will be present during the latter portion of the phase

signal. This positive step in the phase signal current can be

accommodated by a peak current mode controller without in-

stability.

Leading Edge Pulse Width

Modulation

Unlike conventional voltage mode controllers, the LM25115A

implements leading edge pulse width modulation. A current

source equal to 3 times the I_SYNCcurrent is used to charge

the capacitor connected to the RAMP pin as shown in Figure

9. The ramp signal and the output of the error amplifier

(COMP) are combined through a resistor network to produce

a voltage ramp with variable dc offset (CRMIX in Figure 9).

The high-side MOSFET which drives the HS pin is held in the

off state at the beginning of the phase signal. When the volt-

age of CRMIX exceeds the internal threshold voltage CV, the

PWM comparator turns on the high-side MOSFET. The HS

pin rises and the MOSFET delivers current from the main

converter phase signal to the output of the auxiliary regulator.

The PWM cycle ends when the phase signal falls and power

is no longer supplied to the drain of the high-side MOSFET.

30008314

FIGURE 9. Synchronization and Leading Edge Modulation

30008320

FIGURE 10. Leading versus Trailing Edge Modulation

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old (CV), the PWM comparator turns on the high-side MOS-

FET. Insure that the Vbias voltage is at least 3V above the

regulated output voltage (VOUT) to provide enough head-

room for the current sense amplifier.

Valley Current Mode Control

The LM25115A controller uniquely utilizes the elements and

benefits of valley current mode control in conjunction with

leading edge modulation to correct changes in output voltage

due to line and load transients. Contrary to peak current mode

control, valley current mode control turns on the high-side

MOSFET when the inductor valley current reaches a pro-

grammable threshold. This programmable threshold (CRMIX)

is the sum of the output of voltage error amplifier and the

RAMP signal generated at the RAMP pin. Valley current

mode control experiences sub-harmonic oscillation when the

duty ratio, D, is less than or equal to 50%. Therefore, ade-

quate slope compensation is needed for the proper operation

across the full range of the duty ratio. The RAMP signal is

proportional to the input voltage and it provides the required

slope compensation for the valley current mode scheme. The

desired RAMP pin capacitance can be calculated from the

following equation:

Valley current mode control improves the control loop stability

and bandwidth. It also eliminates the R-C lead network in the

feedback path that is normally required with voltage mode

control (Figure 12). Eliminating the lead network not only sim-

plifies the compensation, but also reduces sensitivity to output

noise that could pass through the lead network to the error

amplifier.

The design of the voltage feedback path through the error

amp begins with the selection of R1 and R2 in Figure 12 to

set the regulated output voltage. The steady state output volt-

age after soft-start is determined by the following equation:

VOUT(final) = 0.75V x (1+R1/R2)

The parallel impedance of the R1, R2 resistor divider should

be approximately 2kΩ (between 0.5kΩ and 5kΩ). Lower re-

sistance values may not be properly driven by the error am-

plifier output and higher feedback resistances can introduce

noise sensitivity. The next step in the design process is se-

lection of R3, which sets the ac gain of the error amplifier.

C_RAMP= (0.05 x L) /(R_SYNCx R_SENSE

)

Where L is the power inductor, R_SYNCis the SYNC pin resistor

and R_SENSEis the current sense resistor.

The current sense amplifier shown in Figure 11 monitors the

inductor current as it flows through a sense resistor connected

between CS and VOUT. The voltage gain of the sense am-

plifier is nominally equal to 16. The current sense output

signal is shifted by 1.27V to produce the internal CV reference

signal. The CV signal is applied to the negative input of the

PWM comparator and compared to CRMIX as illustrated in

Figure 11. Therefore when CRMIX exceeds the PWM thresh-

The capacitor C1 is connected in series with R3 to increase

the dc gain of the voltage regulation loop and improve output

voltage accuracy. The corner frequency set by R3 x C1 should

be less than 1/10th of the cross-over frequency of the overall

converter such that capacitor C1 does not add phase lag at

the crossover frequency.

30008315

FIGURE 11. Current Sensing and Limiting

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30008316

FIGURE 12. Voltage Sensing and Feedback

comparator will inhibit output pulses. Once the fault condition

is removed, the fast current limit amplifier will release COMP.

Therefore, the CRMIX signal will increase to a normal oper-

ating threshold and the switching will resume (Figure 14). A

current limit fold-back feature is provided by the LM25115A

to reduce the peak output current delivered to a shorted load.

When the common mode input voltage to the current sense

amplifier (CS and VOUT pins) falls below 2V, the current limit

threshold is reduced from the normal level. At common mode

voltages > 2V, the current limit threshold is nominally 45mV.

When VOUT is reduced to 0 V the current limit threshold drops

to 39mV to reduce stress on the inductor and power MOS-

FETs.

Current Limiting (CS, CO and VOUT)

Current limiting is implemented through the current sense

amplifier as illustrated in Figure 11. The current sense ampli-

fier monitors the inductor current that flows through a sense

resistor connected between CS and VOUT. The voltage gain

of the current sense amplifier is nominally equal to 16. The

output of current sense signal is shifted by 1.27V to produce

the internal CV reference signal. The CV signal drives two

current limit amplifiers. Both of the current limit amplifiers

have open drain (sink only) output stages which are connect-

ed to the CO pin. The CO pin is typically connected to the

COMP pin through a diode (the cathode is connected to the

CO pin and the anode is connected to the COMP pin). The

slow current limit amplifier has a nominal transconductance

of 5 mA/V and provides constant current mode operation at

the desired current limit set point. The fast current limit am-

plifier has nominal current pull-down capability of 100mA and

provides protection against fast over-current conditions. Dur-

ing normal operation, the voltage error amplifier controls the

COMP pin voltage which adjusts the PWM duty cycle by vary-

ing the internal CRMIX level. However when the current

sense input voltage, V_CL, exceeds 45mV, the slow current

limit amplifier gradually pulls down on COMP through the CO

pin. Pulling COMP low reduces the CRMIX signal and thereby

reducing the operating duty cycle. By controlling the operating

duty cycle, the slow current limit amplifier will force a constant

current mode of operation at the desired current limit set point

(Figure 13). A resistor in series with a capacitor are connected

from the CO Pin to ground to provide adequate control loop

compensation for the slow current limit (Figure 11). The de-

sired current limit set point, ILimit, can be programmed by

selecting the proper current sense resistor, R_SENSE,using the

following equation:

30008325

Vphase=10V

CH1 = CO, 5V/Div

CH2 = COMP, 5/Div

CH3 = Iout, 5A/Div

CH4 = SSPR Switch Signal, 5V/Div

Horizontal Resolution= 2 µs/Div

R_SENSE= 0.045 V/ ILimit

In the event that the current sense input voltage, V_CL, exceeds

60mV, the fast current limit amplifier will pull down hard on

COMP through the CO pin. This will reduce the CRMIX signal

to a voltage below the CV signal level. Therefore, the PWM

FIGURE 13. SSPR Steady State Current Limit (Output

Shorted)

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dead-time control to avoid shoot through currents. The adap-

tive dead-time control circuit monitors the state of each driver

to ensure that one MOSFET is turned off before the other is

turned on. The HB and VCC capacitors should be placed

close to the pins of the LM25115A to minimize voltage tran-

sients due to parasitic inductances and the high peak output

currents of the drivers. The recommended range of the HB

capacitor is 0.047µF to 0.22µF.

Both drivers are controlled by the PWM logic signal from the

PWM latch. When the phase signal is low, the outputs are

held in the reset state with the low-side MOSFET on and the

high-side MOSFET off. When the phase signal switches to

the high state, the PWM latch reset signal is de-asserted. The

high-side MOSFET remains off until the PWM latch is set by

the PWM comparator (CRMIX > CV as shown in Figure 9).

When the PWM latch is set, the LO driver turns off the low-

side MOSFET and the HO driver turns on the high-side MOS-

FET. The high-side pulse is terminated when the phase signal

falls and SYNC input comparator resets the PWM latch.

30008326

Vphase=10V

CH1 = CO, 5V/Div

CH2 = COMP, 5/Div

CH3 = Iout, 10A/Div

CH4 = SSPR Switch Signal, 4V/Div

Horizontal Resolution= 20 µs/Div

Thermal Protection

Internal thermal shutdown circuitry is provided to protect the

integrated circuit in the event the maximum junction temper-

ature limit is exceeded. When activated, typically at 165 de-

grees Celsius, the controller is forced into a low power

standby state with the output drivers and the bias regulator

disabled. The device will restart when the junction tempera-

ture falls below the thermal shutdown hysteresis, which is

typically 25 degrees. The thermal protection feature is pro-

vided to prevent catastrophic failures from accidental device

overheating.

FIGURE 14. SSPR Short Circuit Transient (No-Load to

Short-Circuit)

Negative Current Limit

Under certain conditions synchronous buck regulators are

capable of sinking current from the output capacitors. This

energy is stored in the inductor and returned to the input

source. The LM25115A detects this current reversal by de-

tecting a negative voltage being developed across the current

sense resistor. The intent of this negative current comparator

is to protect the low-side MOSFET from excessive currents.

Excessive negative current can also lead to a large positive

voltage spike on the HS pin at the turn-off of the low-side

MOSFET. This voltage spike may damage the chip if its mag-

nitude exceeds the maximum voltage rating of the part. The

negative current comparator threshold is sufficiently negative

to allow inductor current to reverse at no load or light load

conditions. It is not intended to support discontinuous con-

duction mode with diode emulation by the low-side MOSFET.

The negative current comparator shown in Figure 11 monitors

the CV signal and compares this signal to a fixed 1V thresh-

old. This corresponds to a negative V_CLvoltage between CS

and VOUT of -17mV. The negative current limit comparator

turns off the low-side MOSFET for the remainder of the cycle

when the V_CLinput falls below this threshold.

Standalone DC/DC Synchronous

Buck Mode

The LM25115A can be configured as a standalone DC/DC

synchronous buck controller. In this mode the LM25115A us-

es leading edge modulation in conjunction with valley current

mode control to control the synchronous buck power stage.

The internal oscillator within the LM25115A sets the clock

frequency for the high and low-side drivers of the external

synchronous buck power MOSFETs . The clock frequency in

the synchronous buck mode is programmed by the SYNC pin

resistor and RAMP pin capacitor. Connecting a resistor be-

tween a dc bias supply and the SYNC pin produces a current,

I_SYNC, which sets the charging current of the RAMP pin ca-

pacitor. The RAMP capacitor is charged until its voltage

reaches the peak ramp threshold of 2.25V. The RAMP ca-

pacitor is then discharged for 300ns before beginning a new

PWM cycle. The 300ns reset time of the RAMP pin sets the

minimum off-time of the PWM controller in this mode. The in-

ternal clock frequency in the synchronous buck mode is set

by I_SYNC, the ramp capacitor, the peak ramp threshold, and

the 300ns deadtime.

Gate Driver Outputs (HO & LO)

The LM25115A provides two gate driver outputs, the floating

high-side gate driver HO and the synchronous rectifier low-

side driver LO. The low-side driver is powered directly by the

VCC regulator. The high-side gate driver is powered from a

bootstrap capacitor connected between HB and HS. An ex-

ternal diode connected between VCC and HB charges the

bootstrap capacitor when the HS is low. When the high-side

MOSFET is turned on, HB rises with HS to a peak voltage

equal to VCC + V_HS- V_Dwhere V_Dis the forward drop of the

external bootstrap diode. Both output drivers have adaptive

F_CLK≊ 1 / ((C_RAMPx 2.25V) / (I_SYNCx 3) + 300ns)

See the LM5115 dc evaluation board application note

(AN-1367) for more details on the synchronous buck mode.

Please note that LM25115A is similar to LM5115 except for

the tracking feature.

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Application Circuit

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Physical Dimensions inches (millimeters) unless otherwise noted

TSSOP-16 Outline Drawing

NS Package Number MTC16

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Notes

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Notes

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