LM25115MT [NSC]
Secondary Side Post Regulator Controller; 次级侧后稳压器控制器
| 型号： | LM25115MT |
| 厂家： | 
National Semiconductor |
| 描述： | Secondary Side Post Regulator Controller |
| 文件： | 总17页 (文件大小：725K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2005
LM25115
Secondary Side Post Regulator Controller
General Description
Features
n Self-synchronization to main channel output
n Free-run mode for buck regulation of DC input
n Leading edge pulse width modulation
n Voltage-mode control with current injection and input line
feed-forward
The LM25115 controller contains all of the features neces-
sary to implement multiple output power converters utilizing
the Secondary Side Post Regulation (SSPR) technique. The
SSPR technique develops a highly efficient and well regu-
lated auxiliary output from the secondary side switching
waveform of an isolated power converter. Regulation of the
auxiliary output voltage is achieved by leading edge pulse
width modulation (PWM) of the main channel duty cycle.
Leading edge modulation is compatible with either current
mode or voltage mode control of the main output. The
LM25115 drives external high side and low side NMOS
power switches configured as a synchronous buck regulator.
A current sense amplifier provides overload protection and
operates over a wide common mode input range. Additional
features include a low dropout (LDO) bias regulator, error
amplifier, precision reference, adaptive dead time control of
the gate signals and thermal shutdown.
n Operates from AC or DC input up to 42V
n Wide 4.5V to 30V bias supply range
n Wide 0.75V to 13.5V output range.
n Top and bottom gate drivers sink 2.5A peak
n Adaptive gate driver dead-time control
n Wide bandwidth error amplifier (4MHz)
n Programmable soft-start
n Thermal shutdown protection
n TSSOP-16 or thermally enhanced LLP-16 packages
Typical Application Circuit
20172601
FIGURE 1. Simplified Multiple Output Power Converter Utilizing SSPR Technique
© 2005 National Semiconductor Corporation
DS201726
www.national.com
Connection Diagram
20172602
16-Lead TSSOP, LLP
See NS Package Numbers MTC16 and SDA16A
Ordering Information
Ordering Number
Package Type
NSC Package Drawing
Supplied As
92 Units Per Anti-Static Tube
2500 shipped as Tape & Reel
Available Soon
LM25115MT
TSSOP-16
MTC16
MTC16
LM25115MTX
LM25115SD
LM25115SDX
TSSOP-16
LLP-16
SDA16A
SDA16A
LLP-16
Available Soon
Pin Descriptions
Pin
Name
Description
Application Information
1
CS
Current Sense amplifier positive input
A low inductance current sense resistor is connected between
CS and VOUT. Current limiting occurs when the differential
voltage between CS and VOUT exceeds 45mV (typical).
Connected directly to the output voltage. The current sense
amplifier operates over a voltage range from 0V to 13.5V at the
VOUT pin.
2
VOUT
Current sense amplifier negative input
3
4
AGND
CO
Analog ground
Connect directly to the power ground pin (PGND).
For normal current limit operation, connect the CO pin to the
COMP pin. Leave this pin open to disable the current limit
function.
Current limit output
5
6
COMP
FB
Compensation. Error amplifier output
COMP pin pull-up is provided by an internal 300uA current
source.
Feedback. Error amplifier inverting input Connected to the regulated output through the feedback resistor
divider and compensation components. The non-inverting input
of the error amplifier is internally connected to the SS pin.
7
8
SS
Soft-start control
An external capacitor and the equivalent impedance of an
internal resistor divider connected to the bandgap voltage
reference set the soft-start time. The steady state operating
voltage of the SS pin equal to 0.75V (typical).
RAMP
PWM Ramp signal
An external capacitor connected to this pin sets the ramp slope
for the voltage mode PWM. The RAMP capacitor is charged
with a current that is proportional to current into the SYNC pin.
The capacitor is discharged at the end of every cycle by an
internal MOSFET.
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2
Pin Descriptions (Continued)
Pin
Name
Description
Synchronization input
Application Information
9
SYNC
A low impedance current input pin. The current into this pin sets
the RAMP capacitor charge current and the frequency of an
internal oscillator that provides a clock for the free-run (DC
input) mode .
10
11
PGND
LO
Power Ground
Connect directly to the analog ground pin (AGND).
Connect to the gate of the low side synchronous MOSFET
through a short, low inductance path.
Low side gate driver output
12
VCC
Output of bias regulator
Nominal 7V output from the internal LDO bias regulator. Locally
decouple to PGND using a low ESR/ESL capacitor located as
close to controller as possible.
13
14
15
HS
HO
HB
High side MOSFET source connection
High side gate driver output
Connect to negative terminal of the bootstrap capacitor and the
source terminal of the high side MOSFET.
Connect to the gate of high side MOSFET through a short, low
inductance path.
High side gate driver bootstrap rail
Connect to the cathode of the bootstrap diode and the positive
terminal of the bootstrap capacitor. The bootstrap capacitor
supplies current to charge the high side MOSFET gate and
should be placed as close to controller as possible.
Input to the LDO bias regulator and current sense amplifier that
powers internal blocks. Input range of VBIAS is 4.5V to 30V.
16
-
VBIAS
Supply Bias Input
Exposed Pad Exposed Pad, underside of LLP package Internally bonded to the die substrate. Connect to system
(LLP
Package
Only)
ground for low thermal impedance.
3
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Block Diagram
20172603
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4
Absolute Maximum Ratings (Note 1)
ESD Rating
HBM (Note 2)
2 kV
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings
VBIAS supply voltage
VCC supply voltage
HS voltage
VBIAS to GND
–0.3V to 32V
–0.3V to 9V
–1V to 45V
5V to 30V
5V to 7.5V
VCC to GND
HS to GND
0V to 42V
VOUT, CS to GND
All other inputs to GND
Storage Temperature Range
Junction Temperature
– 0.3V to 15V
−0.3V to 7.0V
–55˚C to +150˚C
+150˚C
HB voltage
VCC + HS
Operating Junction Temperature
–40˚C to +125˚C
Typical Operating Conditions
Min
Parameter
Typ
Max
30
7
Units
V
Supply Voltage, VBIAS
4.5
4.5
Supply Voltage, VCC
V
Supply voltage bypass, CVBIAS
Reference bypass capacitor, CVCC
HB-HS bootstrap capacitor
0.1
1
1
µF
µF
µF
µA
V
0.1
10
0.047
50
SYNC Current Range (VCC = 4.5V)
RAMP Saw Tooth Amplitude
150
1.75
13.5
1
VOUT regulation voltage (VBIAS min = 3V + VOUT)
0.75
V
Electrical Characteristics Unless otherwise specified, TJ = –40˚C to +125˚C, VBIAS = 12V, No Load on
LO or HO.
Symbol
Parameter
Conditions
FSYNC = 200kHz
Min
Typ
Max
4
Units
mA
V
VBIAS SUPPLY
Ibias
VBIAS Supply Current
VCC LOW DROPOUT BIAS REGULATOR
VccReg
VCC Regulation
VCC open circuit. Outputs not
switching
6.65
7
7.15
VCC Current Limit
(Note 4)
40
mA
V
VCC Under-voltage Lockout Voltage Positive going VCC
VCC Under-voltage Hysteresis
4
4.5
0.3
0.2
0.25
V
SOFT-START
SS Source Impedance
43
60
77
kΩ
SS Discharge Impedance
100
Ω
ERROR AMPLIFIER and FEEDBACK REFERENCE
VREF
FB Reference Voltage
FB Input Bias Current
COMP Source Current
Open Loop Voltage Gain
Gain Bandwidth Product
Input Offset Voltage
COMP Offset
Measured at FB pin
FB = 2V
0.737
0.75
0.2
300
60
4
0.763
0.5
V
µA
µA
dB
MHz
mV
V
GBW
Vio
-7
0
7
Threshold for VHO = high RAMP = CS
= VOUT = 0V
2
RAMP Offset
Threshold for VHO = high COMP =
1.5V, CS = VOUT = 0V
1.1
V
CURRENT SENSE AMPLIFIER
Current Sense Amplifier Gain
16
V/V
V
Output DC Offset
1.27
500
Amplifier Bandwidth
kHz
5
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Electrical Characteristics Unless otherwise specified, TJ = –40˚C to +125˚C, VBIAS = 12V, No Load on LO
or HO. (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CURRENT LIMIT
ILIMIT Amp Transconductance
Overall Transconductance
Positive Current Limit
16
237
45
mA / V
mA / V
mV
VCL = VCS - VVOUT
37
31
53
45
VOUT = 6V and CO/COMP = 1.5V
VCL = VCS - VVOUT
Positive Current Limit Foldback
Negative Current Limit
38
mV
mV
VOUT = 0V and CO/COMP = 1.5V
VOUT = 6V
VCLneg
-17
VCL = VCS - VVOUT to cause LO to
shutoff
RAMP GENERATOR
SYNC Input Impedance
2.5
15
kΩ
µA
V
SYNC Threshold
End of cycle detection threshold
RAMP peak voltage with dc current
applied to SYNC.
Free Run Mode Peak Threshold
2.3
3.3
Current Mirror Gain
Ratio of RAMP charge current to
SYNC input current.
2.7
A/A
Discharge Impedance
100
Ω
LOW SIDE GATE DRIVER
VOLL
VOHL
LO Low-state Output Voltage
LO High-state Output Voltage
LO Rise Time
ILO = 100mA
0.2
0.4
15
12
2
0.5
0.8
V
V
ILO = -100mA, VOHL = VCC -VLO
CLOAD = 1000pF
CLOAD = 1000pF
VLO = 0V
ns
ns
A
LO Fall Time
IOHL
IOLL
Peak LO Source Current
Peak LO Sink Current
VLO = 12V
2.5
A
HIGH SIDE GATE DRIVER
VOLH
VOHH
HO Low-state Output Voltage
IHO = 100mA
0.2
0.4
15
12
2
0.5
0.8
V
V
HO High-state Output Voltage
HO Rise Time
IHO = -100mA, VOHH = VHB –VHO
CLOAD = 1000pF
CLOAD = 1000pF
VHO = 0V
ns
ns
A
HO High Side Fall Time
Peak HO Source Current
Peak HO Sink Current
IOHH
IOLH
VHO = 12V
2.5
A
SWITCHING CHARACTERISITCS
LO Fall to HO Rise Delay
HO Fall to LO Rise Delay
SYNC Fall to HO Fall Delay
SYNC Rise to LO Fall Delay
THERMAL SHUTDOWN
CLOAD = 0
CLOAD = 0
CLOAD = 0
CLOAD = 0
70
50
ns
ns
ns
ns
120
50
TSD
Thermal Shutdown Temp.
150
165
25
˚C
˚C
Thermal Shutdown Hysteresis
THERMAL RESISTANCE
θJA
θJA
Junction to Ambient
Junction to Ambient
MTC Package
SDA Package
125
32
˚C/W
˚C/W
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.
Note 3: Min and Max limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 4: Device thermal limitations may limit usable range.
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Typical Performance Characteristics
VCC Regulator Start-Up Characteristics, VCC vs VBIAS
VCC Load Regulation to Current Limit
20172605
20172604
Current Value (CV) vs Current Limit (VCL
)
Current Sense Amplifier Gain and Phase vs Frequency
20172606
20172607
Current Error Amplifier Transconductance
Overall Current Amplifier Transconductance
20172608
20172609
7
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Typical Performance Characteristics (Continued)
Common Mode Output Voltage vs Negative Current
Limit (Room Temp)
Common Mode Output Voltage vs Positive Current Limit
20172610
20172611
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8
former secondary winding before rectification (Figure 1). A
resistor connected from the phase signal to the low imped-
ance SYNC pin produces a square wave current (ISYNC) as
shown in Figure 2. A current comparator at the SYNC input
monitors ISYNC relative to an internal 15µA reference. When
ISYNC exceeds 15µA, the internal clock signal (CLK) is reset
and the capacitor connected to the RAMP begins to charge.
The current source that charges the RAMP capacitor is
equal to 3 times the ISYNC current. The falling edge of the
phase signal sets the CLK signal and discharges the RAMP
capacitor until the next rising edge of the phase signal. The
RAMP capacitor is discharged to ground by a low imped-
ance (100Ω) n-channel MOSFET. The input impedance at
SYNC pin is 2.5kΩ which is normally much less than the
external SYNC pin resistance.
Detailed Operating Description
The LM25115 controller contains all of the features neces-
sary to implement multiple output power converters utilizing
the Secondary Side Post Regulation (SSPR) technique. The
SSPR technique develops a highly efficient and well regu-
lated auxiliary output from the secondary side switching
waveform of an isolated power converter. Regulation of the
auxiliary output voltage is achieved by leading edge pulse
width modulation (PWM) of the main channel duty cycle.
Leading edge modulation is compatible with either current
mode or voltage mode control of the main output. The
LM25115 drives external high side and low side NMOS
power switches configured as a synchronous buck regulator.
A current sense amplifier provides overload protection and
operates over a wide common mode input range from 0V to
13.5V. Additional features include a low dropout (LDO) bias
regulator, error amplifier, precision reference, adaptive dead
time control of the gate driver signals and thermal shutdown.
A programmable oscillator provides a PWM clock signal
when the LM25115 is powered by a dc input (free-run mode)
instead of the phase signal of the main channel converter
(SSPR mode).
Low Drop-out Bias Regulator
(VCC)
The LM25115 contains an internal LDO regulator that oper-
ates over an input supply range from 4.5V to 30V. The output
of the regulator at the VCC pin is nominally regulated at 7V
and is internally current limited to 40mA. VCC is the main
supply to the internal logic, PWM controller, and gate driver
circuits. When power is applied to the VBIAS pin, the regu-
lator is enabled and sources current into an external capaci-
tor connected to the VCC pin. The recommended output
capacitor range for the VCC regulator is 0.1uF to 100uF.
When the voltage at the VCC pin reaches the VCC under-
voltage lockout threshold of 4.25V, the controller is enabled.
The controller is disabled if VCC falls below 4.0V (250mV
hysteresis). In applications where an appropriate regulated
dc bias supply is available, the LM25115 controller can be
powered directly through the VCC pin instead of the VBIAS
pin. In this configuration, it is recommended that the VCC
and the VBIAS pins be connected together such that the
external bias voltage is applied to both pins. The allowable
VCC range when biased from an external supply is 4.5V to
7V.
20172612
FIGURE 2. Line Feed-forward Diagram
The RAMP and SYNC functions illustrated in Figure 2 pro-
vide line voltage feed-forward to improve the regulation of
the auxiliary output when the input voltage of the main
converter changes. Varying the input voltage to the main
converter produces proportional variations in amplitude of
the phase signal. The main channel PWM controller adjusts
the pulse width of the phase signal to maintain constant
volt*seconds and a regulated main output as shown in Fig-
ure 3. The variation of the phase signal amplitude and dura-
tion are reflected in the slope and duty cycle of the RAMP
signal of the LM25115 (ISYNC α phase signal amplitude). As
a result, the duty cycle of the LM25115 is automatically
adjusted to regulate the auxiliary output voltage with virtually
no change in the PWM threshold voltage. Transient line
regulation is improved because the PWM duty cycle of the
auxiliary converter is immediately corrected, independent of
the delays of the voltage regulation loop.
Synchronization (SYNC) and
Feed-forward (RAMP)
The pulsing “phase signal” from the main converter synchro-
nizes the PWM ramp and gate drive outputs of the LM25115.
The phase signal is the square wave output from the trans-
9
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Synchronization (SYNC) and Feed-forward (RAMP) (Continued)
20172613
FIGURE 3. Line Feed-forward Waveforms
The recommended SYNC input current range is 50µA to
Error Amplifier and Soft-Start (FB,
CO, & COMP, SS)
150µA. The SYNC pin resistor (RSYNC) should be selected to
set the SYNC current (ISYNC) to 150µA with the maximum
phase signal amplitude, VPHASE(max). This will guarantee
that ISYNC stays within the recommended range over a 3:1
change in phase signal amplitude. The SYNC pin resistor is
therefore:
An internal wide bandwidth error amplifier is provided within
the LM25115 for voltage feedback to the PWM controller.
The amplifier’s inverting input is connected to the FB pin.
The output of the auxiliary converter is regulated by connect-
ing a voltage setting resistor divider between the output and
the FB pin. Loop compensation networks are connected
between the FB pin and the error amplifier output (COMP).
The amplifier’s non-inverting input is internally connected to
the SS pin. The SS pin is biased at 0.75V by a resistor
divider connected to the internal 1.27V bandgap reference.
When the VCC voltage is below the UVLO threshold, the SS
pin is discharged to ground. When VCC rises and exceeds
the positive going UVLO threshold (4.25V), the SS pin is
released and allowed to rise. If an external capacitor is
connected to the SS pin, it will be charged by the internal
resistor divider to gradually increase the non-inverting input
of the error amplifier to 0.75V. The equivalent impedance of
the SS resistor divider is nominally 60kΩ which determines
the charging time constant of the SS capacitor. During start-
up, the output of the LM25115 converter will follow the
exponential equation:
RSYNC = (VPHASE(max) / 150µA) - 2.5kΩ
Once ISYNC has been established by selecting RSYNC, the
RAMP signal amplitude may be programmed by selecting
the proper RAMP pin capacitor value. The recommended
peak amplitude of the RAMP waveform is 1V to 1.75V. The
CRAMP capacitor is chosen to provide the desired RAMP
amplitude with the nominal phase signal voltage and pulse
width.
CRAMP = (3 x ISYNC x TON ) / VRAMP
Where
CRAMP = RAMP pin capacitance
ISYNC = SYNC pin current current
TON = corresponding phase signal pulse width
VRAMP = desired RAMP amplitude (1V to 1.75V)
For example,
Main channel output = 3.3V. Phase signal maximum ampli-
tude = 12V. Phase signal frequency = 250kHz
VOUT(t) = VOUT(final) x (1 - exp(-t/RSS x CSS))
Where
•
Set ISYNC = 150µA with phase signal at maximum ampli-
tude (12V):
Rss = internal resistance of SS pin (60kΩ)
Css = external Soft-Start capacitor
VOUT(final) = regulator output set point
ISYNC = 150µA = VPHASE(max) / (RSYNC + 2.5 kΩ) = 12V /
(RSYNC + 2.5 kΩ)
RSYNC = 12V/150µA - 2.5kΩ = 77.5kΩ
TON = Main channel duty cycle / Phase frequency =
(3.3V/12V) / 250kHz = 1.1µs
The initial ∆v / ∆t of the output voltage is VOUT(final) / Rss x
Css and VOUT will be within 1% of the final regulation level
after 4.6 time constants or when t = 4.6 x Rss x Css.
•
Pull-up current for the error amplifier output is provided by an
internal 300µA current source. The PWM threshold signal at
the COMP pin can be controlled by either the open drain
error amplifier or the open drain current amplifier connected
through the CO pin to COMP. Since the internal error ampli-
fier is configured as an open drain output it can be disabled
by connecting FB to ground. The current sense amplifier and
current limiting function will be described in a later section.
•
•
Assume desired VRAMP = 1.5V
CRAMP = (3 x ISYNC x TON ) / VRAMP = (3 x 150µA x 1.1µs)
/ 1.5V
•
CRAMP = 330pF
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The high side MOSFET which drives the HS pin is held in the
off state at the beginning of the phase signal. When the
voltage of CRMIX exceeds the internal threshold voltage CV,
the PWM comparator turns on the high side MOSFET. The
HS pin rises and the MOSFET delivers current from the main
converter phase signal to the output of the auxiliary regula-
tor. The PWM cycle ends when the phase signal falls and
power is no longer supplied to the drain of the high side
MOSFET.
Leading Edge Pulse Width
Modulation
Unlike conventional voltage mode controllers, the LM25115
implements leading edge pulse width modulation. A current
source equal to 3 times the ISYNC current is used to charge
the capacitor connected to the RAMP pin as shown in Figure
4. The ramp signal and the output of the error amplifier
(COMP) are combined through a resistor network to produce
a voltage ramp with variable dc offset (CRMIX in Figure 4).
20172614
FIGURE 4. Synchronization and Leading Edge Modulation
Leading edge modulation of the auxiliary PWM controller is
required if the main converter is implemented with peak
current mode control. If trailing edge modulation were used,
the additional load on the transformer secondary from the
auxiliary channel would be drawn only during the first portion
of the phase signal pulse. Referring to Figure 5, the turn off
the high side MOSFET of the auxiliary regulator would cre-
ate a non-monotonic negative step in the transformer cur-
rent. This negative current step would produce instability in a
peak current mode controller. With leading edge modulation,
the additional load presented by the auxiliary regulator on
the transformer secondary will be present during the latter
portion of the phase signal. This positive step in the phase
signal current can be accommodated by a peak current
mode controller without instability.
20172620
FIGURE 5. Leading versus Trailing Edge Modulation
11
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The design of the voltage feedback path through the error
amp begins with the selection of R1 and R2 in Figure 7 to set
the regulated output voltage. The steady state output voltage
after soft-start is determined by the following equation:
Voltage Mode Control with Current
Injection
The LM25115 controller uniquely combines elements and
benefits of current mode control in a voltage mode PWM
controller. The current sense amplifier shown in Figure 6
monitors the inductor current as it flows through a sense
resistor connected between CS and VOUT. The voltage gain
of the sense amplifier is nominally equal to 16. The current
sense output signal is shifted by 1.27V to produce the inter-
nal CV reference signal. The CV signal is applied to the
negative input of the PWM comparator and compared to
CRMIX as illustrated in Figure 4. Thus the PWM threshold of
the voltage mode controller (CV) varies with the instanta-
neous inductor current. Insure that the Vbias voltage is at
least 3V above the regulated output voltage (VOUT).
VOUT(final) = 0.75V x (1+R1/R2)
The parallel impedance of the R1, R2 resistor divider should
be approximately 2kΩ (between 0.5kΩ and 5kΩ). Lower
resistance values may not be properly driven by the error
amplifier output and higher feedback resistances can intro-
duce noise sensitivity. The next step in the design process is
selection of R3, which sets the ac gain of the error amplifier.
The ac gain is given by the following equation and should be
set to a value less than 30.
<
GAIN(ac) = R3/(R1|| R2) 30
The capacitor C1 is connected in series with R3 to increase
the dc gain of the voltage regulation loop and improve output
voltage accuracy. The corner frequency set by R3 x C1
should be less than 1/10th of the cross-over frequency of the
overall converter such that capacitor C1 does not add phase
lag at the crossover frequency. Capacitor C2 is added to
reduce the noise in the voltage control loop. The value of C2
should be less than 500pF and C2 may not be necessary
with very careful PC board layout.
Injecting a signal proportional to the instantaneous inductor
current into a voltage mode controller improves the control
loop stability and bandwidth. This current injection eliminates
the lead R-C lead network in the feedback path that is
normally required with voltage mode control (see Figure 7).
Eliminating the lead network not only simplifies the compen-
sation, but also reduces sensitivity to output noise that could
pass through the lead network to the error amplifier.
20172615
FIGURE 6. Current Sensing and Limiting
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12
Voltage Mode Control with Current Injection (Continued)
20172616
FIGURE 7. Voltage Sensing and Feedback
Current Limiting (CS, CO and
VOUT)
Negative Current Limit
When inductor current flows from the regulator output
through the low side MOSFET, the input to the current sense
comparator becomes negative. The intent of the negative
current comparator is to protect the low-side MOSFET from
excessive currents. Negative current can lead to large nega-
tive voltage spikes on the output at turn off which can dam-
age circuitry powered by the output. The negative current
comparator threshold is sufficiently negative to allow induc-
tor current to reverse at no load or light load conditions. It is
not intended to support discontinuous conduction mode with
diode emulation by the low-side MOSFET. The negative
current comparator illustrated in Figure 6 monitors the CV
signal and compares this signal to a fixed 1V threshold. This
corresponds to a negative VCL voltage between CS and
VOUT of -17mV. The negative current limit comparator turns
off the low-side MOSFET for the remainder of the cycle when
the VCL input falls below this threshold.
Current limiting is implemented through the current sense
amplifier as illustrated in Figure 6. The current sense ampli-
fier monitors the inductor current that flows through a sense
resistor connected between CS and VOUT. The voltage gain
of the current sense amplifier is nominally equal to 16. The
output of current sense amplifier is level shifted by 1.27V to
produce the internal CV reference signal. The CV signal
drives a current limit amplifier with nominal transconduc-
tance of 16mA/V. The current limit amplifier has an open
drain (sink only) output stage and its output pin, CO is
typically connected to the COMP pin. During normal opera-
tion, the voltage error amplifier controls the COMP pin volt-
age which adjusts the PWM duty cycle by varying the inter-
nal CRMIX level (Figure 4). However, when the current
sense input voltage VCL exceeds 45mV, the current limit
amplifier pulls down on COMP through the CO pin. Pulling
COMP low reduces the CRMIX signal below the CV signal
level. When CRMIX does not exceed the CV signal, the
PWM comparator inhibits output pulses until the CRMIX
signal increases to a normal operating level.
Gate Drivers Outputs (HO & LO)
The LM25115 provides two gate driver outputs, the floating
high-side gate driver HO and the synchronous rectifier low-
side driver LO. The low-side driver is powered directly by the
VCC regulator. The high-side gate driver is powered from a
bootstrap capacitor connected between HB and HS. An
external diode connected between VCC and HB charges the
bootstrap capacitor when the HS is low. When the high-side
MOSFET is turned on, HB rises with HS to a peak voltage
equal to VCC + VHS - VD where VD is the forward drop of the
external bootstrap diode. Both output drivers have adaptive
dead-time control to avoid shoot through currents. The adap-
tive dead-time control circuit monitors the state of each
driver to ensure that the opposing MOSFET is turned off
before the other is turned on. The HB and VCC capacitors
should be placed close to the pins of the LM25115 to mini-
A current limit fold-back feature is provided by the LM25115
to reduce the peak output current delivered to a shorted
load. When the common mode input voltage to the current
sense amplifier (CS and VOUT pins) falls below 2V, the
current limit threshold is reduced from the normal level. At
>
common mode voltages
2V, the current limit threshold is
nominally 45mV. When VOUT is reduced to 0V the current
limit threshold drops to 36mV to reduce stress on the induc-
tor and power MOSFETs.
13
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before beginning a new PWM cycle. The 300ns reset time of
the RAMP pin sets the minimum off time of the PWM con-
troller in the free-run mode. The internal clock frequency in
the free-run mode is set by the synchronization current,
ramp capacitor, free-run peak threshold, and 300ns dead-
time.
Gate Drivers Outputs (HO & LO)
(Continued)
mize voltage transients due to parasitic inductances and the
high peak output currents of the drivers. The recommended
range of the HB capacitor is 0.047µF to 0.22µF.
FCLK ) 1 / ((CRAMP x 2.25V) / (ISYNC x 3) + 300ns)
Both drivers are controlled by the PWM logic signal from the
PWM latch. When the phase signal is low, the outputs are
held in the reset state with the low-side MOSFET on and the
high-side MOSFET off. When the phase signal switches to
the high state, the PWM latch reset signal is de-asserted.
The high-side MOSFET remains off until the PWM latch is
Note that the VCC supply can be used as the dc bias to
produce ISYNC. Note that the input voltage feedforward is no
longer functional in this operating mode, so the loop gain will
vary as a function of Vin. The LM25115 controls the buck
power stage with leading edge pulse width modulaton to
hold off the high-side driver until the necessary volt*seconds
is established for regulation. Other features described for the
secondary side post regulator apply in the free run mode
operation. They include voltage mode control with current
injection, positive and negative current limit, programmable
soft-start, adaptive delays for outputs, and thermal protec-
tion.
>
set by the PWM comparator (CRMIX
CV as shown in
Figure 4). When the PWM latch is set, the LO driver turns off
the low-side MOSFET and the HO driver turns on the high-
side MOSFET. The high-side pulse is terminated when the
phase signal falls and the SYNC input comparator resets the
PWM latch.
Free-Run Mode
Thermal Protection
The LM25115 can be operated as a conventional synchro-
nous buck controller with a dc input supply instead of the
square wave phase signal. In the dc or free-run mode, the
LM25115 PWM controller synchronizes to an internal clock
signal instead of the phase signal pulses. The clock fre-
quency in the free-run mode is programmed by the SYNC
pin resistor and RAMP pin capacitor. Connecting a resistor
between a dc bias supply and the SYNC pin produces a
current ISYNC which controls the charging current of the
RAMP pin capacitor . The RAMP capacitor is charged until
its voltage reaches the free-run mode peak threshold of
2.25V. The RAMP capacitor is then discharged for 300ns
Internal thermal shutdown circuitry is provided to protect the
integrated circuit in the event the maximum junction tem-
perature limit is exceeded. When activated, typically at 165
degrees Celsius, the controller is forced into a low power
standby state with the output drivers and the bias regulator
disabled. The device will restart when the junction tempera-
ture falls below the thermal shutdown hysteresis, which is
typically 25 degrees. The thermal protection feature is pro-
vided to prevent catastrophic failures from accidental device
overheating.
www.national.com
14
15
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Physical Dimensions inches (millimeters) unless otherwise noted
TSSOP-16 Outline Drawing
NS Package Number MTC16
LLP-16 Outline Drawing
NS Package Number SDA16A
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16
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain
no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
Leadfree products are RoHS compliant.
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