LM2612BTLX [NSC]

400mA Sub-miniature, Programmable, Step-Down DC-DC Converter for Ultra Low-Voltage Circuits; 400毫安超小型可编程，降压型DC -DC转换器，用于超低电压电路


型号：	LM2612BTLX
厂家：	National Semiconductor
描述：	400mA Sub-miniature, Programmable, Step-Down DC-DC Converter for Ultra Low-Voltage Circuits 400毫安超小型可编程，降压型DC -DC转换器，用于超低电压电路转换器开关
文件：	总19页 (文件大小：2315K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

December 2002

LM2612BL

400mA Sub-miniature, Programmable, Step-Down DC-DC

Converter for Ultra Low-Voltage Circuits

General Description

Key Specifications

n Operates from a single LiION cell (2.8V to 5.5V)

n Internal synchronous rectification for high PWM mode

efficiency

The LM2612 step-down DC-DC converter is optimized for

powering ultra-low voltage circuits from a single Lithium-Ion

cell. It provides up to 400mA (300mA for B grade), over an

input voltage range of 2.8V to 5.5V. Pin programmable out-

put voltages of 1.05V, 1.3V, 1.5V or 1.8V allow adjustment

for MPU voltage options without board redesign or external

feedback resistors.

n Pin programmable output voltage (1.05V, 1.3V, 1.5V and

1.8V)

n 400mA maximum load capability (300mA for B grade)

2% PWM mode DC output voltage precision

The device has three pin-selectable modes for maximizing

battery life in mobile phones and similar portable applica-

tions. Low-noise PWM mode offers 600kHz fixed-frequency

operation to reduce interference in RF and data acquisition

applications during full-power operation. In PWM mode, in-

ternal synchronous rectification provides high efficiency

(91% typ. at 1.8V_OUT). A SYNC input allows synchronizing

the switching frequency in a range of 500kHz to 1MHz to

n 5mV typ PWM mode output voltage ripple

n 160 µA typ PFM mode quiescent current

n 0.02µA typ shutdown mode current

n 600kHz PWM mode switching frequency

n SYNC input for PWM mode frequency synchronization

from 500kHz to 1MHz

avoid noise from intermodulation with system frequencies. Features

Low-current hysteretic PFM mode reduces quiescent current

to 160 µA (typ.) during system standby. Shutdown mode

turns the device off and reduces battery consumption to

0.02µA (typ.). Additional features include soft start and cur-

rent overload protection.

n Sub-miniature 10-pin micro SMD package

n Only three tiny surface-mount external components

required

n Uses small ceramic capacitors

n Internal soft start

n Current overload protection

n No external compensation required

n Thermal shutdown protection

The LM2612 is available in a 10 pin micro SMD packge. This

package uses National’s wafer level chip-scale micro SMD

technology and offers the smallest possible size. Only three

small external surface-mount components, an inductor and

two ceramic capacitors are required.

Applications

n Mobile Phones

n Hand-Held Radios

n Battery Powered Devices

Typical Application Circuit

20041802

DS200418

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Connection Diagrams

micro SMD package

20041804

20041805

TOP VIEW

BOTTOM VIEW

Ordering Information

Order Number

Package Type

NSC Package

Marking(*)

Supplied As

10-Pin micro SMD

LM2612ABL

XYTT IS41A

XYTT IS41B

XYTT IS41A

XYTT IS41B

250 Units, Tape and Reel

3000 Units, Tape and Reel

BLP106WB

10-bump Wafer Level Chip Scale

(micro SMD)

LM2612BBL

LM2612ABLX

LM2612BBLX

(*) XY - denotes the date code marking (2 digit) in production

TT - refers to die run/lot traceability for production

I - pin one indication

S - Product line designator

Note the Package Marking may change over the course of production time without notice

Order Number

Package Type

NSC Package

Marking(*)

Supplied As

10-Pin micro SMD

LM2612ATL

XYTT IS41A

XYTT IS41B

XYTT IS41A

XYTT IS41B

250 Units, Tape and Reel

3000 Units, Tape and Reel

TLP106WA

10-bump Wafer Level Chip Scale

(micro SMD)

LM2612BTL

LM2612ATLX

LM2612BTLX

(*) XY - denotes the date code marking (2 digit) in production

TT - refers to die run/lot traceability for production

I - pin one indication

S - Product line designator

Note the Package Marking may change over the course of production time without notice

Pin Description

Pin Number

Pin Name

Function

Feedback Analog Input. Connect to the output at the output filter capacitor (Figure 1)

Output Voltage Control Inputs. Set the output voltage using these digital inputs (see Table

1). The output defaults to 1.5V if these pins are unconnected.

VID1

VID0

SYNC/MODE Synchronization Input. Use this digital input for frequency synchronization or modulation

control. Set:

SYNC/MODE = high for low-noise 600kHz PWM mode

SYNC/MODE = low for low-current PFM mode

SYNC/MODE = 500kHz - 1MHz external clock for synchronization to an external clock in

PWM mode. See Synchronization and Operating Modes in the Device Information section.

Enable Input. For shutdown, set low to SGND.(See Shutdown Mode in the Device

Information section.)

PGND

Power Ground

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Pin Description (Continued)

Pin Number

Pin Name

Function

Switching Node connection to the internal PFET switch and NFET synchronous rectifier.

Power Supply Input to the internal PFET switch. Connect to the input filter capacitor

(Figure 1).

PVIN

VDD

Analog Supply Input. If board layout is not optimum, an optional 0.1µF ceramic capacitor

is suggested (Figure 1)

SGND

Analog and Control Ground

(*) Note that the pin numbering scheme for the Micro SMD package was revised in April, 2002 to conform to JEDEC standard. Only the pin numbers were revised.

No changes to the physical location of the inputs/outputs were made. For reference purpose, the obselete numbering had FB as pin 1, VID1 as pin 2, VID0 as pin

3, SYNC as pin 4, EN as pin 5, PGND as pin 6, SW as pin 7, PVIN as pin 8, VDD as pin 9 and SGND as pin 10.

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Absolute Maximum Ratings (Note 1)

Lead temperature

(Soldering, 10 sec.)

260˚C

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Junction Temperature (Note 2)

Minimum ESD Rating

Human body model, C = 100pF, R =

1.5 kΩ

−25˚C to 125˚C

PVIN, VDD, to SGND

PGND to SGND

EN, SYNC/MODE, VID0, VID1 to

SGND

−0.2V to +6V

2kV

−0.2V to +0.2V

Thermal Resistance (θ_JA

LM2612ABL/LM2612ATL &

)

−0.2V to +6V

(GND −0.2V) to

(VDD +0.2V)

LM2612BBL/LM2612BTL(Note 3)

140˚C/W

FB, SW

Storage Temperature Range

−45˚C to +150˚C

Electrical Characteristics

Specifications with standard typeface are for T_A= T_J= 25˚C, and those in bold face type apply over the full Operating Tem-

perature Range (T_A= T_J= −25˚C to +85˚C). Unless otherwise specified, PVIN = VDD = EN = SYNC = 3.6V, VID0 = VID1 =

0V.

Symbol

V_IN

Parameter

Input Voltage Range (Note

Conditions

PVIN = VDD = VID1 = V_IN

VID0 = 0V

Min

Typ

Max

Units

2.8

5.5

VID0 = V_IN, VID1 = V_IN

VID0 = V_IN, VID1 = 0V

VID0 = 0V, VID1 = 0V

VID0 = 0V, VID1 = V_IN

1.029

1.274

1.470

1.764

1.05

1.30

1.50

1.8

1.071

1.326

1.530

1.836

Feedback Voltage

(Note 5)

V_FB

V_HYST

PFM Comparator Hysteresis PFM Mode (SYNC = 0V)

Voltage

(Note 6)

µA

I_SHDN

I_Q1

Shutdown Supply Current

DC Bias Current into VDD

EN = 0V

0.02

160

No switching, PFM mode

(SYNC/MODE = 0V)

No switching, PWM mode

195

µA

I_Q2

605

395

325

0.5

725

550

500

(SYNC/MODE = V_IN

)

R_{DSON (P)}

R_{DSON (N)}

R_{DSON , TC}

I_lim

Pin-Pin Resistance for P

FET

mΩ

%/C

Pin-Pin Resistance for N

FET

FET Resistance

Temperature Coefficient

Switch Peak Current Limit

(Note 7)

LM2612ABL/LM2612ATL

LM2612BBL/LM2612BTL

510

400

710

850

980

V_{EN_H}

V_{EN_L}

EN Positive Going

0.95

0.80

0.95

0.84

0.92

0.83

1.8

1.3

3.0

Threshold Voltage

EN Negative Going

Threshold Voltage

0.4

V_{SYNC_H}

V_{SYNC_L}

V_{ID_H}

SYNC/MODE Positive

Going Threshold Voltage

SYNC/MODE Negative

Going Threshold Voltage

V_ID0, V_ID1Positive Going

Threshold Voltage

V_{ID_L}

V_ID0, V_ID1Negative Going

Threshold Voltage

I_VID

VID1, VID0 Pull Down

Current

VID1, VID0 = 3.6V

µA

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Electrical Characteristics (Continued)

Specifications with standard typeface are for T_A= T_J= 25˚C, and those in bold face type apply over the full Operating Tem-

perature Range (T_A= T_J= −25˚C to +85˚C). Unless otherwise specified, PVIN = VDD = EN = SYNC = 3.6V, VID0 = VID1 =

0V.

Symbol

f_sync

Parameter

SYNC/MODE Clock

Frequency Range

(Note 8)

Conditions

Min

500

Typ

Max

Units

1000

kHz

F_OSC

Internal Oscillator

Frequency

LM2612ABL/ATL, PWM Mode

(SYNC = VIN)

468

450

600

200

732

750

kHz

LM2612BBL/BTL, PWM Mode

(SYNC = VIN)

T_min

Minimum ON-Time of P FET

Switch in PWM Mode

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended

to be functional, but parameter specifications may not be guaranteed. For guaranteed specifications and associated test conditions, see the Min and Max limits and

Conditions in the Electrical Characteristics table. Electrical Characteristics table limits are guaranteed by production testing, design or correlation using standard

Statistical Quality Control methods. Typical (Typ) specifications are mean or average values from characterization at 25˚C and are not guaranteed.

Note 2: Thermal shutdown will occur if the junction temperature exceeds the 150˚C maximum junction temperature of the device.

Note 3: Thermal resistance specified with 2 layer PCB(0.5/0.5 oz. cu).

Note 4: The LM2612 is designed for applications where turn-on after system power-up is controlled by the system processor and internal UVLO (Under Voltage

LockOut) circuitry is unnecessary. The LM2612 has no UVLO circuitry and should be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.8V.

Although the LM2612 exhibits safe behavior while enabled at low input voltages, this is not guaranteed.

Note 5: The feedback voltage is trimmed at the 1.5V output setting. The other output voltages result from the pin selection of the internal DAC’s divider ratios. The

precision for the feedback voltages is 2%.

Note 6: : The hysteresis voltage is the minimum voltage swing on FB that causes the internal feedback and control circuitry to turn the internal PFET switch on and

then off during PFM mode.

Note 7: Current limit is built-in, fixed, and not adjustable. If the current limit is reached while the output is pulled below about 0.7V, the internal PFET switch turns

off for 2.5 µs to allow the inductor current to diminish.

Note 8: SYNC driven with an external clock switching between V and GND. When an external clock is present at SYNC, the IC is forced to PWM mode at the

external clock frequency. The LM2612 synchronizes to the rising edge of the external clock.

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Typical Operating Characteristics LM2612ABL/ATL, Circuit of Figure 1, V_IN= 3.6V, T_A= 25˚C, L₁

10 µH, unless otherwise noted.

Quiescent Supply Current vs Temperature

Quiescent Supply Current vs Supply Voltage

20041806

20041807

Shutdown Quiescent Current vs Temperature

Output Voltage vs Temperature (PWM Mode)

20041808

20041809

Output Voltage vs Supply Voltage

(V_OUT= 1.5V, PWM Mode)

Output Voltage vs Temperature (PFM Mode)

20041810

20041813

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Typical Operating Characteristics LM2612ABL/ATL, Circuit of Figure 1, V_IN= 3.6V, T_A= 25˚C, L₁

10 µH, unless otherwise noted. (Continued)

Output Voltage vs Supply Voltage

(V_OUT= 1.5V, PFM Mode)

Output Voltage vs Output Current

(V_OUT= 1.5V, PWM Mode)

20041814

20041821

Output Voltage vs Output Current

(V_OUT= 1.5V, PFM Mode)

Efficiency vs Output Current

(V_OUT= 1.8V, PWM Mode, With Diode)

20041822

20041827

Efficiency vs Output Current

(V_OUT= 1.8V, PFM Mode, With Diode)

(V_OUT= 1.5V, PWM Mode, With Diode)

20041828

20041829

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Typical Operating Characteristics LM2612ABL/ATL, Circuit of Figure 1, V_IN= 3.6V, T_A= 25˚C, L₁

10 µH, unless otherwise noted. (Continued)

Efficiency vs Output Current

(V_OUT= 1.5V, PFM Mode, With Diode)

(V_OUT= 1.3V, PWM Mode, With Diode)

20041830

20041831

Efficiency vs Output Current

(V_OUT= 1.3V, PFM Mode, With Diode)

(V_OUT= 1.05V, PWM Mode, With Diode)

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20041833

Efficiency vs Output Current

(V_OUT= 1.05V, PFM Mode, With Diode)

(V_OUT= 1.8V, PWM Mode,No Diode)

20041835

20041834

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Typical Operating Characteristics LM2612ABL/ATL, Circuit of Figure 1, V_IN= 3.6V, T_A= 25˚C, L₁

10 µH, unless otherwise noted. (Continued)

Efficiency vs Output Current

(V_OUT= 1.8V, PFM Mode, No Diode)

Switching Frequency vs Temperature

(PWM Mode)

20041839

20041836

Load Transient Response (PWM Mode)

Load Transient Response (PFM Mode)

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20041846

A: INDUCTOR CURRENT, 500mA/div

B: SW PIN, 5V/div

C: V , 50mV/div, AC COUPLED

A: INDUCTOR CURRENT, 500mA/div

B: SW PIN, 5V/div

C: V , 50mV/div, AC COUPLED,

OUT

D: LOAD, 20mA to 200mA, 200mA/div

D: LOAD, 10mA to 100mA, 100mA/div

Shutdown Response (PWM Mode)

Shutdown Response (PFM Mode)

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20041845

A: INDUCTOR CURRENT, 500mA/div

B: SW PIN, 2V/div

A: INDUCTOR CURRENT, 500mA/div

B: SW PIN, 2V/div

C: V

, 1V/div, D: EN, 5V/div

C: V

, 1V/div , D: EN, 5V/div

OUT

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Typical Operating Characteristics LM2612ABL/ATL, Circuit of Figure 1, V_IN= 3.6V, T_A= 25˚C, L₁

10 µH, unless otherwise noted. (Continued)

PWM to PFM Response

Line Transient Response (PWM Mode)

20041844

20041849

A: INDUCTOR CURRENT, 500mA/div

B: SW PIN, 2V/div

C: V , 50mV/div, AC COUPLED

A: SUPPLY VOLTAGE, 500mV/div, AC COUPLED

B: SW PIN, 5V/div

C: V , 10mV/div, AC COUPLED

OUT

D: SYNC/MODE, 5V/div

= 22 µH

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operation or shutdown to conserve battery power. During

standby operation, hysteretic PFM mode reduces quiescent

current to 160µA typ to maximize battery life. Shutdown

mode turns the device off and reduces battery consumption

to 0.02µA (typ.).

Device Information

The LM2612 is a simple, step-down DC-DC converter opti-

mized for powering low-voltage CPUs or DSPs in cell

phones and other miniature battery powered devices. It pro-

vides pin-selectable output voltages of 1.05V, 1.3V, 1.5V or

1.8V from a single 2.8V to 5.5V LiION battery cell. It is

designed for a maximum load current of 400mA (300mA for

B grade).

The LM2612 offers good performance and a full set of fea-

tures. It is based on

a current-mode switching buck

architecture. The SYNC/MODE input accepts an external

clock between 500kHz and 1MHz. The output voltage selec-

tion pins eliminate external feedback resistors. Additional

features include soft-start, current overload protection, over-

voltage protection and thermal shutdown protection.

The device has all three of the pin-selectable operating

modes required for cell phones and other complex portable

devices. Such applications typically spend a small portion of

their time operating at full power. During full power operation,

synchronized or fixed-frequency PWM mode offers full out-

put current capability while minimizing interference to sensi-

tive IF and data acquisition circuits. PWM mode uses syn-

chronous rectification for high efficiency: typically 91% for a

100mA load with 1.8V output, 2.8V input. These applications

spend the remainder of their time in low-current standby

The LM2612 is constructed using a chip-scale 10-pin micro

SMD package. The micro SMD package offers the smallest

possible size for space critical applications, such as cell

phones. Required external components are only a small

10uH inductor, and tiny 10uF and 22uF ceramic capacitors

for reduced board area.

20041803

FIGURE 1. Typical Operating Circuit

transferred back into the circuit and depleted, the inductor

current ramps down with a slope of V_OUT/L. If the inductor

current reaches zero before the next cycle, the synchronous

rectifier is turned off to prevent current reversal. The output

filter capacitor stores charge when the inductor current is

high, and releases it when low, smoothing the voltage across

the load.

Circuit Operation

Referring to Figure 1, Figure 2, and Figure 3 the LM2612

operates as follows: During the first part of each switching

cycle, the control block in the LM2612 turns on the internal

PFET switch. This allows current to flow from the input

through the inductor to the output filter capacitor and load.

The inductor limits the current to a ramp with a slope of (V_IN

-V_OUT)/L, by storing energy in a magnetic field. During the

second part of each cycle, the controller turns the PFET

switch off, blocking current flow from the input, and then

turns the NFET synchronous rectifier on. In response, the

inductor’s magnetic field collapses, generating a voltage that

forces current from ground through the synchronous rectifier

to the output filter capacitor and load. As the stored energy is

The output voltage is regulated by modulating the PFET

switch on-time to control the average current sent to the

load. The effect is identical to sending a duty-cycle modu-

lated rectangular wave formed by the switch and synchro-

nous rectifier to a low-pass filter created by the inductor and

output filter capacitor. The output voltage is equal to the

average voltage at the SW pin.

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Circuit Operation (Continued)

20041801

FIGURE 2. Simplified Functional Diagram

the PWM comparator resets the flip-flop and turns off the

PFET switch, ending the first part of the cycle. The NFET

synchronous rectifier turns on until the next clock pulse or

the inductor current ramps to zero. If an increase in load

pulls the output voltage down, the error amplifier output

increases, which allows the inductor current to ramp higher

before the comparator turns off the PFET switch. This in-

creases the average current sent to the output and adjusts

for the increase in the load.

PWM Operation

The LM2612 can be set to current-mode PWM operation by

connecting the SYNC/MODE pin to VDD. While in PWM

(Pulse Width Modulation) mode, the output voltage is regu-

lated by switching at a constant frequency and then modu-

lating the energy per cycle to control power to the load.

Energy per cycle is set by modulating the PFET switch

on-time pulse-width to control the peak inductor current. This

is done by controlling the PFET switch using a flip-flop driven

by an oscillator and a comparator that compares a ramp

from the current-sense amplifier with an error signal from a

voltage-feedback error amplifier. At the beginning of each

cycle, the oscillator sets the flip-flop and turns on the PFET

switch, causing the inductor current to ramp up. When the

current sense signal ramps past the error amplifier signal,

Before going to the PWM comparator, the current sense

signal is summed with a slope compensation ramp from the

oscillator for stability of the current feedback loop. During the

second part of the cycle, a zero crossing detector turns off

the NFET synchronous rectifier if the inductor current ramps

to zero.

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PWM Operation (Continued)

PWM Mode Switching Waveform

PFM Mode Switching Waveform

20041843

20041842

A: INDUCTOR CURRENT, 500mA/div

B: SW PIN, 2V/div

C: V , 50mV/div, AC COUPLED

B: SW PIN, 2V/div

C: V

, 10mV/div, AC COUPLED

OUT

FIGURE 3. Typical Circuit Waveforms in (a) PWM Mode and (b) PFM Mode

50mA for precise regulation and reduced current consump-

tion when the system is in standby. The LM2612 has an

over-voltage protection feature that may activate if the de-

PFM Operation

Connecting the SYNC/MODE pin to SGND sets the LM2612

to hysteretic PFM operation. While in PFM (Pulse Frequency

Modulation) mode, the output voltage is regulated by switch-

ing with a discrete energy per cycle and then modulating the

cycle rate, or frequency, to control power to the load. This is

done by using an error comparator to sense the output

voltage and control the PFET switch. The device waits as the

load discharges the output filter capacitor, until the output

voltage drops below the lower threshold of the PFM error-

comparator. Then the error comparator initiates a cycle by

turning on the PFET switch. This allows current to flow from

the input, through the inductor to the output, charging the

output filter capacitor. The PFET switch is turned off when

the output voltage rises above the regulation threshold of the

PFM error comparator. After the PFET switch turns off, the

output voltage rises a little higher as the inductor transfers

stored energy to the output capacitor by pushing current into

the output capacitor. Thus, the output voltage ripple in PFM

mode is proportional to the hysteresis of the error compara-

tor and the inductor current.

vice is left in PWM mode under low-load conditions ( 50mA)

to prevent the output voltage from rising too high. See Ov-

ervoltage Protection, for more information.

Select modes with the SYNC/MODE pin using a signal with

a slew rate faster than 5V/100µs. Use a comparator Schmitt

trigger or logic gate to drive the SYNC/MODE pin. Do not

leave the pin floating or allow it to linger between logic levels.

These measures will prevent output voltage errors that could

otherwise occur in response to an indeterminate logic state.

Ensure a minimum load to keep the output voltage in regu-

lation when switching modes frequently. The minimum load

requirement varies depending on the mode change fre-

quency. A typical load of 8µA is required when modes are

changed at 100 ms intervals, 85µA for 10 ms and 800µA for

1 ms.

Frequency Synchronization

(SYNC/MODE Pin)

In PFM mode, the device only switches as needed to service

the load. This lowers current consumption by reducing power

consumed during the switching action in the circuit due to

transition losses in the internal MOSFETs, gate drive cur-

rents, eddy current losses in the inductor, etc. It also im-

proves light-load voltage regulation. During the second part

of the cycle, the intrinsic body diode of the NFET synchro-

nous rectifier conducts until the inductor current ramps to

zero. The LM2612 does not turn on the synchronous rectifier

while in PFM mode.

The SYNC/MODE input can also be used for frequency

synchronization. To synchronize the LM2612 to an external

clock, supply a digital signal to the SYNC/MODE pin with a

voltage swing exceeding 0.4V to 1.3V. During synchroniza-

tion, the LM2612 initiates cycles on the rising edge of the

clock. When synchronized to an external clock, it operates in

PWM mode. The device can synchronize to an external

clock over frequencies from 500kHz to 1MHz.

Use the following waveform and duty-cycle guidelines when

applying an external clock to the SYNC/MODE pin. Each

duty cycle between 30% and 70% and the total clock period

should be 2µs or less. Clock under/overshoot should be less

than 100mV below GND or above V_DD. When applying noisy

clock signals, especially sharp edged signals from a long

cable during evaluation, terminate the cable at its character-

istic impedance; add an RC filter to the SYNC pin, if neces-

sary, to soften the slew rate and over/undershoot. Note that

Operating Mode Selection

(SYNC/MODE Pin)

The SYNC/MODE digital input pin is used to select between

PWM or PFM operating modes. Set SYNC/MODE high

(above 1.3V) for 600kHz PWM operation when the system is

active and the load is above 50mA. Set SYNC/MODE low

(below 0.4V) to select PFM mode when the load is less than

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limiting is implemented using an independent internal com-

parator that trips at current limit of the device. In PWM mode,

cycle-by-cycle current limiting is normally used. If an exces-

sive load pulls the output voltage down to approximately

0.7V, then the device switches to a timed current limit mode.

In timed current limit mode the internal P-FET switch is

turned off after the current comparator trips and the begin-

ning of the next cycle is inhibited for 2.5µs to force the

instantaneous inductor current to ramp down to a safe value.

PFM mode also uses timed current limit operation. The

synchronous rectifier is off in timed current limit mode. Timed

current limit prevents the loss of current control seen in some

products when the output voltage is pulled low in serious

overload conditions.

Frequency Synchronization

(SYNC/MODE Pin) ^(Continued)

sharp edged signals from a pulse or function generator can

develop under/overshoot as high as 10V at the end of an

improperly terminated cable.

Overvoltage Protection

The LM2612 has an over-voltage comparator that prevents

the output voltage from rising too high when the device is left

in PWM mode under low-load conditions. Otherwise, the

output voltage could rise out of regulation from the minimum

energy transferred per cycle due to the 200ns minimum

on-time of the PFET switch while in PWM mode. When the

output voltage rises by 50mV over its regulation threshold,

the OVP comparator inhibits PWM operation to skip pulses

until the output voltage returns to the regulation threshold. In

over voltage protection, output voltage and ripple increase

slightly.

Current Limiting and PWM Mode

Transient Response

Considerations

The LM2612 was designed for fast response to moderate

load steps. Harsh transient conditions during loads above

300mA can cause the inductor current to swing up to the

maximum current limit, resulting in PWM mode jitter or insta-

bility from activation of the current limit comparator. To avoid

this jitter or instability, do not power-up or start the LM2612

into a full load (loads near or above 400mA). Do not change

operating modes or output voltages when operating at a full

load. Avoid extremely sharp and wide-ranging load steps to

Shutdown Mode

Setting the EN input low to SGND places the LM2612 in a

0.02uA (typ) shutdown mode. During shutdown, the PFET

switch, NFET synchronous rectifier, reference, control and

bias of the LM2612 are turned off. Setting EN high to VDD

enables normal operation. While turning on, soft start is

activated.

full load, such as from 30mA to 350mA.

EN must be set low to turn off the LM2612 during undervolt-

age conditions when the supply is less than the 2.8V mini-

mum operating voltage. The LM2612 is designed for mobile

phones and similar applications where power sequencing is

determined by the system controller and internal UVLO (Un-

der Voltage LockOut) circuitry is unnecessary. The LM2612

has no UVLO circuitry. Although the LM2612 exhibits safe

behavior while enabled at low input voltages, this is not

guaranteed.

Pin Selectable Output Voltage

The LM2612 features pin-selectable output voltage to elimi-

nate the need for external feedback resistors. The output

can be set to 1.05V, 1.3V, 1.5V or 1.8V by configuring the

VID0 and VID1 pins. See Setting the Output Voltage in the

Application Information section for further details.

Soft-Start

Internal Synchronous Rectification

The LM2612 has soft start to reduce current inrush during

power-up and startup. This reduces stress on the LM2612

and external components. It also reduces startup transients

on the power source.

While in PWM mode, the LM2612 uses an internal NFET as

a synchronous rectifier to improve efficiency by reducing

rectifier forward voltage drop and associated power loss. In

general, synchronous rectification provides a significant im-

provement in efficiency whenever the output voltage is rela-

tively low compared to the voltage drop across an ordinary

rectifier diode.

Soft start is implemented by ramping up the internal refer-

ence in the LM2612 to gradually increase the output voltage.

The reference ramps up in about 400µs. When powering up

in PWM mode, soft start may take an additional 200us to

allow time for the error amplifier compensation network to

charge.

Under moderate and heavy loads, the internal NFET syn-

chronous rectifier is turned on during the inductor current

down-slope in the second part of each cycle. The synchro-

nous rectifier is turned off prior to the next cycle, or when the

inductor current ramps near zero at light loads. The NFET is

designed to conduct through its intrinsic body diode during

transient intervals before it turns on, eliminating the need for

an external diode.

Thermal Shutdown Protection

The LM2612 has thermal shutdown protection that operates

to protect from short-term misuse and overload conditions.

When the junction temperature exceeds about 150˚C, the

device shuts down, re-starting in soft start after the tempera-

ture drops below 130˚C. Prolonged operation in thermal

overload conditions may damage the device and is consid-

ered bad practice.

Synchronous rectification is disabled and the NFET con-

ducts through its body diode during the second part of each

cycle while in PFM mode to reduce quiescent current asso-

ciated with the synchronous rectifier’s control circuitry. To

increase efficiency in PFM or PWM conditions, place an

external Schottky diode from PGND to SW.

Current Limiting

A current limit feature allows the LM2612 to protect itself and

external components during overload conditions. Current

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Application Information

SETTING THE OUTPUT VOLTAGE

The LM2612 features pin-selectable output voltage to elimi-

nate the need for external feedback resistors. Select an

output voltage of 1.05V, 1.3V, 1.5V or 1.8V by configuring the

VID0 and VID1 pins, as directed in Table 1.

TABLE 1. VID0 and VID1 Output Voltage Selection Settings

V_OUT(V)

Logic Level

VID0 VID1

1.8

1.5

1.3

1.05

VID0 and VID1 are digital inputs. They may be set high by

connecting to VDD or low by connecting to SGND. Option-

ally, VID0 and VID1 may be driven by digital gates that

provide over 1.3V for a high state and less than 0.4V for a

low state to ensure valid logic levels. The VID0 and VID1

inputs each have an internal 1.8 µA pull-down that pulls them

low for a default 1.5V output when left unconnected. Leaving

these pins open is acceptable, but setting the pins high or

low is recommended.

INDUCTOR SELECTION

A 10µH inductor with a saturation current rating greater than

the max current limit of the device is recommended for most

applications. The inductor’s resistance should be less than

0.3Ω for good efficiency. Table 2 lists suggested inductors

and suppliers.

TABLE 2. Suggested Inductors and Their Suppliers

Model

DO1608C-103

DO1606T-103

UP1B-100

Vendor

Coilcraft

Phone

FAX

847-639-6400

847-639-1469

Coilcraft

Coiltronics

Panasonic

Pulse Engineering

Sumida

561-241-7876

714-373-7366

561-241-9339

714-373-7323

UP0.4CB-100

ELL6GM100M

ELL6PM100M

P1174.103T

858-674-8100

847-956-0666

858-674-8262

847-956-0702

P0770.103T

CDRH5D18-100

CDRH4D28-100

CDC5D23-100

NP05D B100M

NP04S B100N

SLF6025T-100M1R0

SLF6020T-100MR90

A918CY-100M

A915AY-100M

Sumida

Taiyo Yuden

TDK

847-925-0888

847-803-6100

847-297-0070

847-925-0899

847-803-6296

847-699-7864

TDK

Toko

For low-cost applications, an unshielded bobbin inductor is

suggested. For noise critical applications, a toroidal or

shielded-bobbin inductor should be used. A good practice is

to lay out the board with overlapping footprints of both types

for design flexibility. This allows substitution of a low-noise

toroidal inductor, in the event that noise from low-cost bobbin

models is unacceptable.

the inductor loses its ability to limit current through the PFET

switch to a ramp and allows the switch current to increase

rapidly. This can cause poor efficiency, regulation errors or

stress to DC-DC converters like the LM2612. Saturation

occurs when the magnetic flux density from current through

the windings of the inductor exceeds what the inductor’s

core material can support with energy storage in a corre-

sponding magnetic field.

The saturation current rating is the current level beyond

which an inductor loses its inductance. Beyond this rating,

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Application Information (Continued)

TABLE 3. Suggested Capacitors and Their Suppliers

Model

Size

Vendor

Phone

FAX

22µF, X7R or X5R Ceramic Capacitor for C2 (Output Filter Capacitor)

C3225X5RIA226M

JMK325BJ226MM

ECJ4YB0J226M

1210

TDK

847-803-6100

847-925-0888

714-373-7366

404-436-1300

847-803-6296

847-925-0899

714-373-7323

404-436-3030

Taiyo-Yuden

Panasonic

muRata

GRM42-2X5R226K6.3

10µF, 6.3V, X7R or X5R Ceramic Capacitor for C1 (Input Filter Capacitor)

C2012X5R0J106M

JMK212BJ106MG

ECJ3YB0J106K

0805

1206

0805

TDK

847-803-6100

847-925-0888

714-373-7366

404-436-1400

847-803-6296

847-925-0899

714-373-7323

404-436-3030

Taiyo Yuden

Panasonic

muRata

GRM40X5R106K6.3

CAPACITOR SELECTION

Assembly Considerations. For best results in assembly,

alignment ordinals on the PC board should be used to

facilitate placement of the device. Since micro SMD packag-

ing is a new technology, all layouts and assembly means

must be thoroughly tested prior to production. In particular,

proper placement, solder reflow and resistance to thermal

cycling must be verified.

Use a 10µF, 6.3V, X7R or X5R ceramic input filter capacitor

and a 22uF, X7R or X5R ceramic output filter capacitor.

These provide an optimal balance between small size, cost,

reliability and performance. Do not use Y5V ceramic capaci-

tors. Table 3 lists suggested capacitors and suppliers.

A 10µF ceramic capacitor can be used for the output filter

capacitor for smaller size in applications where the worst-

case transient load step is less than 200mA. Use of a 10µF

output capacitor trades off smaller size for an increase in

output voltage ripple, and undershoot during line and load

transient response.

The 10-Bump package used for the LM2612 has 300micron

solder balls and requires 10.82mil (0.275mm) pads for

mounting on the circuit board. The trace to each pad should

enter the pad with a 90˚ entry angle to prevent debris from

being caught in deep corners. Initially, the trace to each pad

should be 6 mil wide, for a section 6 mil long or longer, as a

thermal relief. Then each trace should neck up to its optimal

width over a span of 11 mils or more, so that the taper

extends beyond the edge of the package. The important

criterion is symmetry. This ensures the solder bumps on the

LM2612 re-flow evenly and that the device solders level to

the board. In particular, special attention must be paid to the

pads for bumps A3, B3, C3, D3 and A2. Because PVIN and

PGND are typically connected to large copper planes, inad-

equate thermal reliefs can result in late or inadequate reflow

of these bumps.

The input filter capacitor supplies current to the PFET switch

of the LM2612 in the first part of each cycle and reduces

voltage ripple imposed on the input power source. The out-

put filter capacitor smoothes out current flow from the induc-

tor to the load, helps maintain a steady output voltage during

transient load changes and reduces output voltage ripple.

These capacitors must be selected with sufficient capaci-

tance and sufficiently low ESR to perform these functions.

The ESR, or equivalent series resistance, of the filter capaci-

tors is a major factor in voltage ripple. The contribution from

ESR to voltage ripple is around 75-95% for most electrolytic

capacitors and considerably less for ceramic capacitors. The

remainder of the ripple is from charge storage due to capaci-

tance.

The pad style used with micro SMD package must be the

NSMD (non-solder mask defined) type. This means that the

solder-mask opening is larger than the pad size or 14.7mils

for the LM2612. This prevents a lip that otherwise forms if

the solder-mask and pad overlap. This lip can hold the

device off the surface of the board and interfere with mount-

ing. See Applications Note AN-1112 for specific instructions.

DIODE SELECTION

An optional Schottky diode (D1 in Figure 1) can be added to

increase efficiency in PFM mode and PWM mode. This may

be desired in applications where increased efficiency for

improving operational battery life takes precedence over

increased system size associated with the Schottky diode.

Typically, use of an external schottky diode increases PFM

mode efficiency from 72.7% to 85.0% (20 mA load, V_OUT

1.8V, V_IN= 3.6V). See the efficiency curves in the Typical

Operating Characteristics.

BOARD LAYOUT CONSIDERATIONS

PC board layout is an important part of DC-DC converter

design. Poor board layout can disrupt the performance of a

DC-DC converter and surrounding circuitry by contributing to

EMI, ground bounce, and resistive voltage loss in the traces.

These can send erroneous signals to the DC-DC converter

IC, resulting in poor regulation or instability. Poor layout can

also result in reflow problems leading to poor solder joints

between the micro SMD package and board pads. Poor

solder joints can result in erratic or degraded performance.

Use a Schottky diode with a current rating higher than maxi-

mum current limit, such as an MBRM120T3 or MBRM140T3.

Use of a device rated for 30V or more reduces diode reverse

leakage in high temperature applications

Good layout for the LM2612 can be implemented by follow-

ing a few simple design rules:

MICRO SMD PACKAGE ASSEMBLY AND USE

Use of the micro SMD package requires specialized board

layout, precision mounting and careful reflow techniques, as

detailed in National Semiconductor Application Note AN-

1112. Refer to the section Surface Mount Technology (SMT)

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ground-plane noise by preventing the switching currents

from circulating through the ground plane. It is recom-

mended to have a dedicate ground plan between the

switch signal and feedback traces. It also reduces

ground bounce at the LM2612 by giving it a low-

impedance ground connection.

Application Information (Continued)

1. Place the LM2612 on 10.82mil pads for micro SMD

package. As a thermal relief, connect to each pad with a

6mil wide trace (micro SMD), 6mils long or longer, then

incrementally increase each trace to its optimal width

over a span so that the taper extends beyond the edge

of the package. The important criterion is symmetry, to

ensure re-flow occurs evenly (see Micro SMD Package

Assembly and Use).

5. Use wide traces between the power components and for

power connections to the DC-DC converter circuit. This

reduces voltage errors caused by resistive losses across

the traces.

2. Place the LM2612, inductor and filter capacitors close

together and make the traces short. The traces between

these components carry relatively high switching cur-

rents and act as antennas. Following this rule reduces

radiated noise. Place the capacitors and inductor within

0.2in (5mm) of the LM2612.

6. Route noise sensitive traces, such as the voltage feed-

back path, away from noisy traces between the power

components. The voltage feedback trace must remain

close to the LM2612 circuit and should be direct but

routed away from noisy components. This reduces EMI

radiated onto the DC-DC converter’s own voltage feed-

back trace.

3. Arrange the components so that the switching current

loops curl in the same direction. During the first part of

each cycle, current flows from the input filter capacitor,

through the LM2612 and inductor to the output filter

capacitor and back through ground, forming a current

loop. In the second part of each cycle, current is pulled

up from ground, through the LM2612 by the inductor, to

the output filter capacitor and then back through ground,

forming a second current loop. Routing these loops so

the current curls in the same direction prevents mag-

netic field reversal between the two part-cycles and

reduces radiated noise.

7. Place noise sensitive circuitry, such as radio IF blocks,

away from the DC-DC converter, CMOS digital blocks

and other noisy circuitry. Interference with noise-

sensitive circuitry in the system can be reduced through

distance.

In mobile phones, for example, a common practice is to

place the DC-DC converter in one corner of the board,

arrange the CMOS digital circuitry around it (since this also

generates noise), and then place sensitive preamplifiers and

IF stages in the diagonally opposing corner. Often, the sen-

sitive circuitry is shielded with a metal pan and power to it is

post-regulated to reduce conducted noise, using low-dropout

linear regulators, such as the LP2966.

4. Connect the ground pins of the LM2612 and filter ca-

pacitors together using generous component-side cop-

per fill as a pseudo-ground plane. Then, connect this to

the ground-plane with several vias. This reduces

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Physical Dimensions inches (millimeters) unless otherwise noted

10-Bump micro SMD Package

NS Package Number BLP106WB (LM2612ABL/BBL package)

The dimensions for X1, X2 and X3 are as given:

X1 = 2.250+/− 0.030mm

X2 = 2.504 +/− 0.030mm

X3 = 0.945 +/− 0.1mm

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

NOTES: UNLESS OTHERWISE SPECIFIED

1. EPOXY COATING

2. 63Sn/37Pb EUTECTIC BUMP

3. RECOMMEND NON-SOLDER MASK DEFINED LANDING PAD.

4. PIN A1 IS ESTABLISHED BY LOWER LEFT CORNER WITH RESPECT TO TEXT ORIENTATION.

5. XXX IN DRAWING NUMBER REPRESENTS PACKAGE SIZE VARIATION WHERE X1 IS PACKAGE WIDTH, X2 IS PACKAGE LENGTH AND X3 IS

PACKAGE HEIGHT.

REFERENCE JEDEC REGISTRATION MO - 211. VARIATION BD.

10-Bump micro SMD Package

NS Package Number TLP106WA (LM2612ATL/BTL package)

The dimensions for X1, X2 and X3 are as given:

X1 = 2.250+/− 0.030mm

X2 = 2.504 +/− 0.030mm

X3 = 0.600 +/− 0.075mm

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

Fax: +49 (0) 180-530 85 86

Email: support@nsc.com

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 8790

Email: ap.support@nsc.com

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

LM2612BTLX [NSC]

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