LM2726M [NSC]
High Speed Synchronous MOSFET Drivers; 高速同步MOSFET驱动器
| 型号： | LM2726M |
| 厂家： | 
National Semiconductor |
| 描述： | High Speed Synchronous MOSFET Drivers |
| 文件： | 总9页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2000
LM2725/LM2726
High Speed Synchronous MOSFET Drivers
needed by the top MOSFET can be obtained through an
external bootstrap structure. Minimum pulse width is as low
as 55ns.
General Description
The LM2725/LM2726 is a family of dual MOSFET drivers
that can drive both the top MOSFET and bottom MOSFET in
a push-pull structure simultaneously. It takes a logic level
PWM input and splits it into two complimentary signals with
Features
n High peak output current
n Adaptive shoot-through protection
n 36V SW pin absolute maximum voltage
n Input Under-Voltage-Lock-Out
n Typical 20ns internal delay
n Plastic 8-pin SO package
a
typical 20ns dead time in between. The built-in
shoot-through protection circuitry prevents the top and bot-
tom FETs from turning on simultaneously. With a bias volt-
age of 5V, the peak sourcing and sinking current for each
driver of the LM2725 is about 1.2A and that of the LM2726 is
about 3A. In an SO-8 package, each driver is able to handle
50mA
average
current.
Input
UVLO
(Under-Voltage-Lock-Out) ensures that all the driver outputs
stay low until the supply rail exceeds the power-on threshold
during system power on, or after the supply rail drops below
power-on threshold by a specified hysteresis during system
power down. The cross-conduction protection circuitry de-
tects both the driver outputs and will not turn on a driver until
the other driver output is low. The top gate bias voltage
Applications
n High Current DC/DC Power Supplies
n High Input Voltage Switching Regulators
n Microprocessors
Typical Application
DS200072-1
Connection Diagram
8-Lead Small Outline Package
DS200072-2
Top View
© 2000 National Semiconductor Corporation
DS200072
www.national.com
Ordering Information
Order Number
Package Type
LM2725M
NSC Package Drawing
Supplied As
95 Units/Rail
LM2725
LM2725MX
LM2726M
2500 Units/Reel
95 Units/Rail
M08A
LM2726
LM2726MX
2500 Units/Reel
Pin Description
Pin
Name
Function
1
SW
Top driver return. Should be connected to the common node of
top and bottom FETs
2
3
HG
Top gate drive output
CBOOT
Bootstrap. Accepts a bootstrap voltage for powering the high-side
driver
4
5
6
7
8
PWM_IN
EN
Accepts a 5V-logic control signal
Chip Enable
VCC
LG
Connect to +5V supply
Bottom gate drive output
Ground
GND
Block Diagram
DS200072-4
www.national.com
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
−65˚ to 150˚C
ESD Susceptibility
Human Body Model (Note 3)
1 kV
Soldering Time, Temperature
10sec., 300˚C
VCC
7.5V
42V
Operating Ratings (Note 1)
CBOOT
CBOOT to SW
SW to PGND
Junction Temperature
8V
VCC
4V to 7V
36V
Junction Temperature Range
0˚ to 125˚C
+150˚C
Power Dissipation
(Note 2)
720mW
Electrical Characteristics
LM2725
VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA
= TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
POWER SUPPLY
Iq_op
Parameter
Condition
Min
Typ
Max
Units
Operating Quiescent
Current
PWM_IN = 0V
µA
180
0.5
250
15
Iq_sd
Shutdown Quiescent
Current
EN = 0V, PWM_IN = 0V
µA
TOP DRIVER
Peak Pull-Up Current
Test Circuit 1, Vbias = 5V,
R = 0.1Ω
1.2
2.4
A
Ω
A
Pull-Up Rds_on
ICBOOT = IHG = 0.7A
Peak Pull-down Current
Test Circuit 2, Vbias = 5V,
R = 0.1Ω
−1.0
Pull-down Rds_on
Rise Time
ISW = IHG = 0.7A
1.4
17
10
23
Ω
t4
t6
t3
t5
Timing Diagram, CLOAD
3.3nF
=
ns
ns
ns
Fall Time
Pull-Up Dead Time
Pull-Down Delay
Timing Diagram
Timing Diagram, from
PWM_IN Falling Edge
21
ns
BOTTOM DRIVER
Peak Pull-Up Current
Test Circuit 3, Vbias = 5V,
R = 0.1Ω
1.2
2.6
−2
A
Ω
A
Pull-up Rds_on
IVCC = ILG = 0.7A
Peak Pull-down Current
Test Circuit 4, Vbias = 5V,
R = 0.1Ω
Pull-down Rds_on
Rise Time
IGND = ILG = 0.7A
0.65
18
6
Ω
t8
t2
t7
t1
Timing Diagram, CLOAD
3.3nF
=
ns
ns
ns
Fall Time
Pull-up Dead Time
Pull-down Delay
Timing Diagram
28
Timing Diagram, from
PWM_IN Rising Edge
15
ns
LOGIC
Vuvlo_up
Power On Threshold
VCC rises from 0V toward
5V
3.0
2.5
0.5
V
V
V
Vuvlo_dn
Under-Voltage-Lock-Out
Threshold
Vuvlo_hys
Under-Voltage-Lock-Out
Hysteresis
3
www.national.com
Electrical Characteristics
LM2725 (Continued)
VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA
= TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
LOGIC
Parameter
Condition
Min
2.4
Typ
Max
Units
VIH_EN
VIL_EN
Ileak_EN
EN Pin High Input
V
V
EN Pin Low Input
0.8
2
EN Pin Leakage Current
EN = VCC = 5V
−2
−2
µA
VCC = 5V, EN = 0V
2
ton_min
Minimum Positive Input
Pulse Width
55
55
(Note 4)
ns
toff_min
Minimum Negative Input
Pulse Width
(Note 5)
VIH_PWM
VIL_PWM
PWM_IN High Level
Input Voltage
When PWM_IN pin goes
high from 0V
2.4
V
PWM_IN Low Level
Input Voltage
When PWM_IN pin goes
low from 5V
0.8
Electrical Characteristics
LM2726
VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA
= TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
POWER SUPPLY
Iq_op
Parameter
Condition
Min
Typ
Max
Units
Operating Quiescent
Current
PWM_IN = 0V
µA
185
0.5
250
15
Iq_sd
Shutdown Quiescent
Current
EN = 0V, PWM_IN = 0V
µA
TOP DRIVER
Peak Pull-Up Current
Test Circuit 1, Vbias = 5V,
R = 0.1Ω
3.0
1.2
A
Ω
A
Pull-Up Rds_on
ICBOOT = IHG = 1.0A
Peak Pull-down Current
Test Circuit 2, Vbias = 5V,
R = 0.1Ω
−3.2
Pull-down Rds_on
Rise Time
ISW = IHG = 1.0A
0.5
17
12
19
Ω
t4
t6
t3
t5
Timing Diagram, CLOAD
3.3nF
=
ns
ns
ns
Fall Time
Pull-Up Dead Time
Pull-Down Delay
Timing Diagram
Timing Diagram, from
PWM_IN from Falling Edge
27
ns
BOTTOM DRIVER
Peak Pull-Up Current
Test Circuit 3, Vbias = 5V,
R = 0.1Ω
3.2
1.1
A
Ω
A
Pull-up Rds_on
IVCC = ILG = 1.0A
Peak Pull-down Current
Test Circuit 4, Vbias = 5V,
R = 0.1Ω
−3.2
Pull-down Rds_on
Rise Time
IGND = ILG = 1.0A
0.6
17
14
12
Ω
t8
t2
t7
Timing Diagram, CLOAD
3.3nF
=
ns
ns
ns
Fall Time
Pull-up Dead Time
Timing Diagram
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4
Electrical Characteristics
LM2726 (Continued)
VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA
= TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
Parameter
Condition
Min
Typ
Max
Units
BOTTOM DRIVER
t1
Pull-down Delay
Timing Diagram, from
PWM_IN Rising Edge
13
ns
LOGIC
Vuvlo_up
Power On Threshold
VCC rises from 0V toward
5V
2.8
2.5
0.3
V
V
V
Vuvlo_dn
Under-Voltage-Lock-Out
Threshold
Vuvlo_hys
Under-Voltage-Lock-Out
Hysteresis
VIH_EN
VIL_EN
Ileak_EN
EN Pin High Input
2.4
V
V
EN Pin Low Input
0.25
2
EN Pin Leakage Current
EN = VCC = 5V
−2
−2
µA
VCC = 5V, EN = 0V
2
ton_min
Minimum Positive Input
Pulse Width
55
55
(Note 4)
ns
toff_min
Minimum Negative Input
Pulse Width
(Note 5)
VIH_PWM
VIL_PWM
PWM_IN High Level
Input Voltage
When PWM_IN pin goes
high from 0V
2.4
V
PWM_IN Low Level
Input Voltage
When PWM_IN pin goes
low from 5V
0.25
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which the device operates
correctly. Operating Ratings do not imply guaranteed performance limits.
Note 2: Maximum allowable power dissipation is a function of the maximum junction temperature, T
, the junction-to-ambient thermal resistance, θ , and the
JA
JMAX
ambient temperature, T . The maximum allowable power dissipation at any ambient temperature is calculated using: P
= (T
-T ) / θ . The junction-to-
JMAX A JA
A
MAX
ambient thermal resistance, θ , for LM2725/LM2726 is 172˚C/W. For a T
of 150˚C and T of 25˚C, the maximum allowable power dissipation is 0.7W.
A
JA
JMAX
Note 3: ESD machine model susceptibility is 100V.
Note 4: If after a rising edge, a falling edge occurs sooner than the specified value, the IC may intermittently fail to turn on the bottom gate when the top gate is off.
As the falling edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output.
Note 5: If after a falling edge, a rising edge occurs sooner than the specified value, the IC may intermittently fail to turn on the top gate when the bottom gate is off.
As the rising edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output.
5
www.national.com
Timing Diagram
DS200072-3
www.national.com
6
Test Circuits
DS200072-5
DS200072-6
Test Circuit 1
Test Circuit 2
DS200072-7
DS200072-8
Test Circuit 3
Test Circuit 4
7
www.national.com
Typical Waveforms
DS200072-13
DS200072-15
FIGURE 1. Switching Waveforms of Test Circuit
FIGURE 3. When Input Goes Low
DS200072-14
DS200072-16
FIGURE 2. When Input Goes High
FIGURE 4. Minimum Positive Pulse
www.national.com
8
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead Small Outline Package
NS Package Number M08A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
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Europe
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www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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