LM27342SD_技术文档

December 16, 2008

LM27341/LM27342

2 MHz 1.5A/2A Wide Input Range Step-Down DC-DC

Regulator with Frequency Synchronization

General Description

Features

The LM27341 and LM27342 regulators are monolithic, high

frequency, PWM step-down DC-DC converters in 10-pin LLP

and 10-pin eMSOP packages. They contain all the active

functions to provide local DC-DC conversion with fast tran-

sient response and accurate regulation in the smallest possi-

ble PCB area.

Space saving 3 X 3 mm LLP-10 & eMSOP-10 package

■

Wide input voltage range

Wide output voltage range

3 to 20 V

1 to 18 V

■

LM27341 delivers 1.5A maximum output current

LM27342 delivers 2A maximum output current

High switching frequency

Frequency synchronization 1.00 MHz < f_SW< 2.35 MHz

150 mΩ NMOS switch with internal bootstrap supply

70 nA shutdown current

Internal voltage reference accuracy of 1%

Peak Current-Mode, PWM operation

Thermal shutdown

2 MHz

With a minimum of external components the LM27341 and

LM27342 are easy to use. The ability to drive 1.5A or 2A loads

respectively, with an internal 150 mΩ NMOS switch results in

the best power density available. The world-class control cir-

cuitry allows for on-times as low as 65 ns, thus supporting

exceptionally high frequency conversion. Switching frequen-

cy is internally set to 2 MHz and synchronizable from 1 to 2.35

MHz, which allows the use of extremely small surface mount

inductors and chip capacitors. Even though the operating fre-

quency is very high, efficiencies up to 90% are easy to

achieve. External shutdown is included featuring an ultra-low

shutdown current of 70 nA. The LM27341and LM27342 utilize

peak current-mode control and internal compensation to pro-

vide high-performance regulation over a wide range of oper-

ating conditions. Additional features include internal soft-start

circuitry to reduce inrush current, pulse-by-pulse current limit,

thermal shutdown, and output over-voltage protection.

Applications

Local 12V to Vcore Step-Down Converters

■

Radio Power Supply

Core Power in HDDs

Set-Top Boxes

Automotive

USB Powered Devices

DSL Modems

Typical Application Circuit

30005674

30005676

Efficiency vs Load Current

V_OUT= 5V, f_sw= 2 MHz

300056

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Connection Diagrams

Top View

30005604

30005605

10 - Lead LLP

10 - Lead eMSOP

Ordering Information

Order Number

Package Type NSC Package Drawing

Package Marking

SSCB

Transport Media

LM27341MY

eMSOP -10

MUC10A

SDA10A

1000 Units on Tape and Reel

3500 Units on Tape and Reel

1000 Units on Tape and Reel

3500 Units on Tape and Reel

1000 Units on Tape and Reel

4500 Units on Tape and Reel

1000 Units on Tape and Reel

4500 Units on Tape and Reel

LM27341MYX eMSOP -10

LM27342MY eMSOP -10

LM27342MYX eMSOP -10

LM27341SD LLP - 10

LM27341SDX LLP - 10

LM27342SD LLP - 10

SSCB

SSCA

L231B

L231A

LM27342SDX LLP - 10

L231A

Pin Descriptions

1,2

3

Name

Function

SW

Output switch. Connects to the inductor, catch diode, and bootstrap capacitor.

BOOST Boost voltage that drives the internal NMOS control switch. A bootstrap capacitor is connected between

the BOOST and SW pins.

4

5

EN

Enable control input. Logic high enables operation. Do not allow this pin to float or be greater than V_IN

+ 0.3V.

SYNC

Frequency synchronization input. Drive this pin with an external clock or pulse train. Ground it to use

the internal clock.

6

7

FB

Feedback pin. Connect FB to the external resistor divider to set output voltage.

GND

Signal and Power Ground pin. Place the bottom resistor of the feedback network as close as possible

to this pin for accurate regulation.

8

AVIN

PVIN

GND

Supply voltage for the control circuitry.

9,10

DAP

Supply voltage for output power stage. Connect a bypass capacitor to this pin.

Signal / Power Ground and thermal connection. Tie this directly to GND (pin 7). See Application

Information regarding optimum thermal layout.

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2

ESD Susceptibility (Note 2)

Soldering Information

Infrared Reflow (5sec)

2kV

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

260°C

Operating Ratings (Note 1)

AVIN, PVIN

-0.5V to 24V

-0.5V to 28V

AVIN, PVIN

3V to 20V

-0.5V to 20V

-0.5V to 24V

SW Voltage

Boost Voltage

Boost to SW Voltage

FB Voltage

SYNC Voltage

SW Voltage

Boost Voltage

Boost to SW Voltage

Junction Temperature Range

Thermal Resistance (θ_JA) LLP10 (Note 3)

-0.5V to 6.0V

-0.5V to 3.0V

-0.5V to 6.0V

-0.5V to (V_IN+ 0.3V)

−65°C to +150°C

150°C

3.0V to 5.5V

−40°C to +125°C

33°C/W

EN Voltage

Thermal Resistance (θ_JA) eMSOP10 (Note 3)

45°C/W

Storage Temperature Range

Junction Temperature

Electrical Characteristics

Specifications with standard typeface are for T_J= 25°C, and those in boldface type apply over the full Operating Temperature

Range (T_J= -40°C to 125°C). V_IN= 12V, and V_BOOST- V_SW= 4.3V unless otherwise specified. Datasheet min/max specification

limits are guaranteed by design, test, or statistical analysis.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

SYSTEM PARAMETERS

T_J= 0°C to 85°C

T_J= -40°C to 125°C

V_IN= 3V to 20V

0.990

1.0

1.010

V_FB

Feedback Voltage

V

0.984

1.014

ΔV_FB/ΔV_IN

Feedback Voltage Line Regulation

Feedback Input Bias Current

0.003

20

% / V

nA

I_FB

100

Over Voltage Protection, V_FBat

which PWM Halts.

OVP

1.13

V

V_INRising until V_SWis Switching

V_INFalling from UVLO

Undervoltage Lockout

UVLO Hysteresis

Soft Start Time

2.60

0.30

0.5

2.75

0.47

1

2.90

0.6

UVLO

SS

V

1.5

ms

mA

Quiescent Current, I_Q= I_{Q_AVIN}

I_{Q_PVIN}

+

V_FB= 1.1 (not switching)

V_EN= 0V (shutdown)

2.4

70

I_Q

Quiescent Current, I_Q= I_{Q_AVIN}

I_{Q_PVIN}

nA

f_SW= 2 MHz

f_SW= 1 MHz

8.2

4.4

10

I_BOOST

Boost Pin Current

mA

6

OSCILLATOR

f_SW

Switching Frequency

SYNC = GND

V_FB= 0V

1.75

2

2.3

MHz

V

FB Pin Voltage where SYNC input

is overridden.

V_{FB_FOLD}

0.53

220

f_{FOLD_MIN}

Frequency Foldback Minimum

250

kHz

LOGIC INPUTS (EN, SYNC)

f_SYNC

V_IL

SYNC Frequency Range

1

2.35

0.4

MHz

V

EN, SYNC Logic low threshold

EN, SYNC Logic high threshold

Logic Falling Edge

Logic Rising Edge

V_IH

1.8

SYNC, Time Required above V_IHto

Ensure a Logical High.

t_{SYNC_HIGH}

100

ns

SYNC, Time Required below V_ILto

Ensure a Logical Low.

t_{SYNC_LOW}

I_SYNC

ns

nA

µA

V_SYNC< 5V

V_EN= 3V

SYNC Pin Current

20

6

15

I_EN

Enable Pin Current

V_IN= V_EN= 20V

50

100

3

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

INTERNAL MOSFET

R_DS(ON)

I_CL

Switch ON Resistance

Switch Current Limit

150

320

4.0

3.7

mΩ

LM27342

LM27341

2.5

2.0

85

A

D_MAX

t_MIN

%

ns

nA

Maximum Duty Cycle

Minimum on time

SYNC = GND

93

65

40

I_SW

Switch Leakage Current

BOOST LDO

V_LDO

Boost LDO Output Voltage

3.9

V

THERMAL

T_SHDN

Thermal Shutdown Temperature

Thermal Shutdown Hysteresis

Junction temperature rising

Junction temperature falling

165

15

°C

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the recommended Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and should not be

operated beyond such conditions.

Note 2: Human body model, 1.5 kΩ in series with 100 pF.

Note 3: Thermal shutdown will occur if the junction temperature exceeds 165°C. The maximum power dissipation is a function of T_J(MAX), θ_JAand T_A. The

maximum allowable power dissipation at any ambient temperature is P_D= (T_J(MAX)– T_A)/θ_JA. All numbers apply for packages soldered directly onto a 3” x 3” PC

board with 2oz. copper on 4 layers in still air.

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Typical Performance Characteristics All curves taken at V_IN= 12V, V_BOOST- V_SW= 4.3V and

T_A= 25°C, unless specified otherwise.

Efficiency vs Load Current

V_OUT= 5V, f_SW= 2 MHz

Refer to Figure 10

Load Transient

V_OUT= 5V, I_OUT= 100 mA - 2A @ slewrate = 2A / µs

Refer to Figure 10

300056100

30005676

30005680

30005684

Efficiency vs Load Current

V_OUT= 3.3V, f_SW= 2 MHz

Refer to Figure 12

Load Transient

V_OUT= 3.3V, I_OUT= 100 mA - 2A @ slewrate = 2A / µs

Refer to Figure 12

300056102

Efficiency vs Load Current

V_OUT= 1.8V, f_SW= 2 MHz

Refer to Figure 15

Load Transient

V_OUT= 1.8V, I_OUT= 100 mA - 2A @ slewrate = 2A / µs

Refer to Figure 15

300056105

5

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Line Transient

V_IN= 10 to 15V, V_OUT= 3.3V, no C_FF

Refer to Figure 13

Line Transient

V_IN= 10 to 15V, V_OUT= 3.3V

Refer to Figure 12

300056108

300056109

Short Circuit

Short Circuit Release

300056110

300056111

Soft Start

Soft Start with EN Tied to V_IN

30005653

30005654

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V_IN= 12V, V_OUT= 5 V, L = 2.2 µH, C_OUT= 44 µF Iout =1A

V_IN= 12V, V_OUT= 3.3V, L = 1.5 µH C_OUT= 44 µF Iout =1A

Refer to Figure 10

Refer to Figure 12

300056112

300056113

V_IN= 5V, V_OUT= 1.8V, L = 1.0 µH C_OUT= 44 µF Iout =1A

V_IN= 5V, V_OUT= 1.2V, L = 0.56 µH C_OUT= 68 µF Iout =1A

Refer to Figure 15

Refer to Figure 17

300056115

300056114

Sync Functionality

Loss of Synchronization

30005656

30005655

7

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Oscillator Frequency vs Temperature

V_SYNC= GND, f_SW= 2 MHz

Oscillator Frequency vs V_FB

30005629

30005628

V_FBvs Temperature

V_FBvs V_IN

30005630

30005631

Current Limit vs Temperature

V_IN= 12V

R_DSONvs Temperature

30005633

30005632

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I_Q(Shutdown) vs Temperature

I_Q= I_AVIN+ I_PVIN

I_ENvs V_EN

30005635

30005634

9

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Block Diagram

30005698

FIGURE 1.

voltage (V_FB) and V_REF. When the output of the PWM com-

parator goes high, the switch turns off until the next switching

cycle begins. During the switch off-time (t_OFF), inductor cur-

rent discharges through the catch diode D1, which forces the

SW pin (V_SW) to swing below ground by the forward voltage

(V_D1) of the catch diode. The regulator loop adjusts the duty

cycle (D) to maintain a constant output voltage.

Application Information

THEORY OF OPERATION

The LM27341/LM27342 is a constant-frequency, peak cur-

rent-mode PWM buck regulator IC that delivers a 1.5 or 2A

load current. The regulator has a preset switching frequency

of 2 MHz. This high frequency allows the LM27341/LM27342

to operate with small surface mount capacitors and inductors,

resulting in a DC-DC converter that requires a minimum

amount of board space. The LM27341/LM27342 is internally

compensated, which reduces design time, and requires few

external components.

The following operating description of the LM27341/LM27342

will refer to the Block Diagram (Figure 1) and to the waveforms

in Figure 2. The LM27341/LM27342 supplies a regulated out-

put voltage by switching the internal NMOS switch at a con-

stant frequency and varying the duty cycle. A switching cycle

begins at the falling edge of the reset pulse generated by the

internal oscillator. When this pulse goes low, the output con-

trol logic turns on the internal NMOS switch. During this on-

time, the SW pin voltage (V_SW) swings up to approximately

V_IN, and the inductor current (i_L) increases with a linear slope.

The current-sense amplifier measures i_L, which generates an

output proportional to the switch current typically called the

sense signal. The sense signal is summed with the regulator’s

corrective ramp and compared to the error amplifier’s output,

which is proportional to the difference between the feedback

30005607

FIGURE 2. LM27341/LM27342 Waveforms of SW Pin

Voltage and Inductor Current

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BOOST FUNCTION

Capacitor C₂in Figure 1, commonly referred to as C_BOOST, is

used to store a voltage V_BOOST. When the LM27341/LM27342

starts up, an internal LDO charges C_BOOST,via an internal

diode, to a voltage sufficient to turn the internal NMOS switch

on. The gate drive voltage supplied to the internal NMOS

switch is V_BOOST- V_SW

.

During a normal switching cycle, when the internal NMOS

control switch is off (t_OFF) (refer to Figure 2), V_BOOSTequals

V_LDOminus the forward voltage of the internal diode (V_D2). At

the same time the inductor current (i_L) forward biases the

catch diode D1 forcing the SW pin to swing below ground by

the forward voltage drop of the catch diode (V_D1). Therefore,

the voltage stored across C_BOOSTis

V_BOOST- V_SW= V_LDO- V_D2+ V_D1

30005636

Thus,

V_BOOST= V_SW+ V_LDO- V_D2+ V_D1

When the NMOS switch turns on (t_ON), the switch pin rises to

V_SW= V_IN– (R_DSONx I_L),

FIGURE 4. Minimum Load Current for L = 1.5 µH

ENABLE PIN / SHUTDOWN MODE

Connect the EN pin to a voltage source greater than 1.8V to

enable operation of the LM27341/LM27342. Apply a voltage

less than 0.4V to put the part into shutdown mode. In shut-

down mode the quiescent current drops to typically 70 nA.

Switch leakage adds another 40 nA from the input supply. For

proper operation, the LM27341/LM27342 EN pin should nev-

reverse biasing D1, and forcing V_BOOSTto rise. The voltage

at V_BOOSTis then

V_BOOST= V_IN– (R_DSONx I_L) + V_LDO– V_D2+ V_D1

which is approximately

V_IN+ V_LDO- 0.4V

er be left floating, and the voltage should never exceed V_IN

0.3V.

+

V_BOOSThas pulled itself up by its "bootstraps", or boosted to

a higher voltage.

The simplest way to enable the operation of the LM27341/

LM27342 is to connect the EN pin to AVIN which allows self

start-up of the LM27341/LM27342 when the input voltage is

applied.

LOW INPUT VOLTAGE CONSIDERATIONS

When the input voltage is below 5V and the duty cycle is

greater than 75 percent, the gate drive voltage developed

across C_BOOSTmight not be sufficient for proper operation of

the NMOS switch. In this case, C_BOOSTshould be charged via

an external Schottky diode attached to a 5V voltage rail, see

Figure 3. This ensures that the gate drive voltage is high

enough for proper operation of the NMOS switch in the triode

region. Maintain V_BOOST- V_SWless than the 6V absolute max-

imum rating.

When the rise time of V_INis longer than the soft-start time of

the LM27341/LM27342 this method may result in an over-

shoot in output voltage. In such applications, the EN pin

voltage can be controlled by a separate logic signal, or tied to

a resistor divider, which reaches 1.8V after V_INis fully estab-

lished (see Figure 5). This will minimize the potential for

output voltage overshoot during a slow V_INramp condition.

Use the lowest value of V_IN, seen in your application when

calculating the resistor network, to ensure that the 1.8V min-

imum EN threshold is reached.

30005626

FIGURE 3. External Diode Charges C_BOOST

30005608

FIGURE 5. Resistor Divider on EN

HIGH OUTPUT VOLTAGE CONSIDERATIONS

When the output voltage is greater than 3.3V, a minimum load

current is needed to charge C_BOOST, see Figure 4. The mini-

mum load current forward biases the catch diode D1 forcing

the SW pin to swing below ground. This allows C_BOOSTto

charge, ensuring that the gate drive voltage is high enough

for proper operation. The minimum load current depends on

many factors including the inductor value.

11

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FREQUENCY SYNCHRONIZATION

The UVLO threshold has approximately 470 mV of hysteresis,

so the part will operate until V_INdrops below 2.28V(typ). Hys-

teresis prevents the part from turning off during power up if

V_INhas finite impedance.

The LM27341/LM27342 switching frequency can be synchro-

nized to an external clock, between 1.00 and 2.35 MHz,

applied at the SYNC pin. At the first rising edge applied to the

SYNC pin, the internal oscillator is overridden and subse-

quent positive edges will initiate switching cycles. If the ex-

ternal SYNC signal is lost during operation, the LM27341/

LM27342 will revert to its internal 2 MHz oscillator within 1.5

µs. To disable Frequency Synchronization and utilize the in-

ternal 2 MHz oscillator, connect the SYNC pin to GND.

THERMAL SHUTDOWN

Thermal shutdown limits total power dissipation by turning off

the internal NMOS switch when the IC junction temperature

exceeds 165°C (typ). After thermal shutdown occurs, hys-

teresis prevents the internal NMOS switch from turning on

until the junction temperature drops to approximately 150°C.

The SYNC pin gives the designer the flexibility to optimize

their design. A lower switching frequency can be chosen for

higher efficiency. A higher switching frequency can be chosen

to keep EMI out of sensitive ranges such as the AM radio

band. Synchronization can also be used to eliminate beat fre-

quencies generated by the interaction of multiple switching

power converters. Synchronizing multiple switching power

converters will result in cleaner power rails.

Design Guide

INDUCTOR SELECTION

Inductor selection is critical to the performance of the

LM27341/LM27342. The selection of the inductor affects sta-

bility, transient response and efficiency. A key factor in induc-

tor selection is determining the ripple current (Δi_L) (see Figure

2).

The selected switching frequency (f_SYNC) and the minimum

on-time (t_MIN) limit the minimum duty cycle (D_MIN) of the de-

vice.

The ripple current (Δi_L) is important in many ways.

First, by allowing more ripple current, lower inductance values

can be used with a corresponding decrease in physical di-

mensions and improved transient response. On the other

hand, allowing less ripple current will increase the maximum

achievable load current and reduce the output voltage ripple

(see Output Capacitor section for more details on calculating

output voltage ripple). Increasing the maximum load current

D_MIN= t_MINx f_SYNC

Operation below D_MINis not reccomended. The LM27341/

LM27342 will skip pulses to keep the output voltage in regu-

lation, and the current limit is not guaranteed. The switching

is in phase but no longer at the same switching frequency as

the SYNC signal.

is achieved by ensuring that the peak inductor current (I_LPK

never exceeds the minimum current limit of 2.0A min

(LM27341) or 2.5A min (LM27342) .

)

CURRENT LIMIT

The LM27341 and LM27342 use cycle-by-cycle current lim-

iting to protect the output switch. During each switching cycle,

a current limit comparator detects if the output switch current

exceeds 2.0A min (LM27341) or 2.5A min (LM27342) , and

turns off the switch until the next switching cycle begins.

I_LPK= I_OUT+ Δi_L/ 2

Secondly, the slope of the ripple current affects the current

control loop. The LM27341/LM27342 has a fixed slope cor-

rective ramp. When the slope of the current ripple becomes

significantly less than the converter’s corrective ramp (see

Figure 1), the inductor pole will move from high frequencies

to lower frequencies. This negates one advantage that peak

current-mode control has over voltage-mode control, which

is, a single low frequency pole in the power stage of the con-

verter. This can reduce the phase margin, crossover frequen-

cy and potentially cause instability in the converter. Contrarily,

when the slope of the ripple current becomes significantly

greater than the converter’s corrective ramp, resonant peak-

ing can occur in the control loop. This can also cause insta-

bility (Sub-Harmonic Oscillation) in the converter. For the

power supply designer this means that for lower switching

frequencies the current ripple must be increased to keep the

inductor pole well above crossover. It also means that for

higher switching frequencies the current ripple must be de-

creased to avoid resonant peaking.

FREQUENCY FOLDBACK

The LM27341/LM27342 employs frequency foldback to pro-

tect the device from current run-away during output short-

circuit. Once the FB pin voltage falls below regulation, the

switch frequency will smoothly reduce with the falling FB volt-

age until the switch frequency reaches 220 kHz (typ). If the

device is synchronized to an external clock, synchronization

is disabled until the FB pin voltage exceeds 0.53V

SOFT-START

The LM27341/LM27342 has a fixed internal soft-start of 1 ms

(typ). During soft-start, the error amplifier’s reference voltage

ramps from 0.0 V to its nominal value of 1.0 V in approximately

1 ms. This forces the regulator output to ramp in a controlled

fashion, which helps reduce inrush current. Upon soft-start

the part will initially be in frequency foldback and the frequen-

cy will rise as FB rises. The regulator will gradually rise to 2

MHz. The LM27341/LM27342 will allow synchronization to an

external clock at FB > 0.53V.

With all these factors, how is the desired ripple current se-

lected? The ripple ratio (r) is defined as the ratio of inductor

ripple current (Δi_L) to output current (I_OUT), evaluated at max-

imum load:

OUTPUT OVERVOLTAGE PROTECTION

The overvoltage comparator turns off the internal power

NFET when the FB pin voltage exceeds the internal reference

voltage by 13% (V_FB> 1.13 * V_REF). With the power NFET

turned off the output voltage will decrease toward the regula-

tion level.

A good compromise between physical size, transient re-

sponse and efficiency is achieved when we set the ripple ratio

between 0.2 and 0.4. The recommended ripple ratio vs. duty

cycle shown below (see Figure 6) is based upon this com-

promise and control loop optimizations. Note that this is just

UNDERVOLTAGE LOCKOUT

Undervoltage lockout (UVLO) prevents the LM27341/

LM27342 from operating until the input voltage exceeds

2.75V(typ).

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a guideline. Please see Application note AN-1197 for further

considerations.

D_MAX

= (V_OUT+ V_D1) / (V_IN+ V_D1- V_DS)

= (3.3V + 0.5V) / (7V + 0.5V - 0.30V)

= 0.528

Using Figure 6 gives us a recommended ripple ratio = 0.4.

Now the minimum duty cycle is calculated.

D_MIN

= (V_OUT+ V_D1) / (V_IN+ V_D1- V_DS)

= (3.3V + 0.5V) / (16V + 0.5V - 0.30V)

= 0.235

The inductance can now be calculated.

= (1 - D_MIN) x (V_OUT+ V_D1) / (I_OUTx r x f_sw

L

)

= (1 - 0.235) x (3.3V + .5V) / (2A x 0.4 x 2 MHz)

= 1.817 µH

This is close to the standard inductance value of 1.8 µH. This

leads to a 1% deviation from the recommended ripple ratio,

which is now 0.4038.

Finally, we check that the peak current does not reach the

minimum current limit of 2.5A.

30005627

FIGURE 6. Recommended Ripple Ratio Vs. Duty Cycle

I_LPK= I_OUTx (1 + r / 2)

= 2A x (1 + .4038 / 2 )

= 2.404A

The Duty Cycle (D) can be approximated quickly using the

ratio of output voltage (V_OUT) to input voltage (V_IN):

The peak current is less than 2.5A, so the DC load specifica-

tion can be met with this ripple ratio. To design for the

LM27341 simply replace I_OUT= 1.5A in the equations for

I_LPKand see that I_LPKdoes not exceed the LM27341's current

limit of 2.0A (min).

The application's lowest input voltage should be used to cal-

culate the ripple ratio. The catch diode forward voltage drop

INDUCTOR MATERIAL SELECTION

(V_D1) and the voltage drop across the internal NFET (V_DS

)

When selecting an inductor, make sure that it is capable of

supporting the peak output current without saturating. Induc-

tor saturation will result in a sudden reduction in inductance

and prevent the regulator from operating correctly. To prevent

the inductor from saturating over the entire -40 °C to 125 °C

range, pick an inductor with a saturation current higher than

the upper limit of I_CLlisted in the Electrical Characteristics ta-

ble.

must be included to calculate a more accurate duty cycle.

Calculate D by using the following formula:

V_DScan be approximated by:

V_DS= I_OUTx R_DS(ON)

Ferrite core inductors are recommended to reduce AC loss

and fringing magnetic flux. The drawback of ferrite core in-

ductors is their quick saturation characteristic. The current

limit circuit has a propagation delay and so is oftentimes not

fast enough to stop a saturated inductor from going above the

current limit. This has the potential to damage the internal

switch. To prevent a ferrite core inductor from getting into sat-

uration, the inductor saturation current rating should be higher

than the switch current limit I_CL. The LM27341/LM27342 is

quite robust in handling short pulses of current that are a few

amps above the current limit. Saturation protection is provid-

ed by a second current limit which is 30% higher than the

cycle by cycle current limit. When the saturation protection is

triggered the part will turn off the output switch and attempt to

soft-start. (When a compromise has to be made, pick an in-

ductor with a saturation current just above the lower limit of

the I_CL.) Be sure to validate the short-circuit protection over

the intended temperature range.

The diode forward drop (V_D1) can range from 0.3V to 0.5V

depending on the quality of the diode. The lower V_D1is, the

higher the operating efficiency of the converter.

Now that the ripple current or ripple ratio is determined, the

required inductance is calculated by:

where D_MINis the duty cycle calculated with the maximum

input voltage, f_swis the switching frequency, and I_OUTis the

maximum output current of 2A. Using I_OUT= 2A will minimize

the inductor's physical size.

INDUCTOR CALCULATION EXAMPLE

An inductor's saturation current is usually lower when hot. So

consult the inductor vendor if the saturation current rating is

only specified at room temperature.

Operating conditions for the LM27342 are:

V_IN= 7 - 16V

f_SW= 2 MHz

V_OUT= 3.3V

V_D1= 0.5V

I_OUT= 2A

Soft saturation inductors such as the iron powder types can

also be used. Such inductors do not saturate suddenly and

First the maximum duty cycle is calculated.

13

www.national.com

therefore are safer when there is a severe overload or even

shorted output. Their physical sizes are usually smaller than

the Ferrite core inductors. The downside is their fringing flux

and higher power dissipation due to relatively high AC loss,

especially at high frequencies.

the initial current of a load transient. Capacitance can be in-

creased significantly with little detriment to the regulator sta-

bility. However, increasing the capacitance provides diminin-

shing improvement over 100 uF in most applications,

because the bandwidth of the control loop decreases as out-

put capacitance increases. If improved transient performance

is required, add a feed forward capacitor. This becomes es-

pecially important for higher output voltages where the band-

width of the LM27341/LM27342 is lower. See Feed Forward

Capacitor and Frequency Synchronization sections.

INPUT CAPACITOR

An input capacitor is necessary to ensure that V_INdoes not

drop excessively during switching transients. The primary

specifications of the input capacitor are capacitance, voltage,

RMS current rating, and Equivalent Series Inductance (ESL).

The recommended input capacitance is 10 µF, although 4.7

µF works well for input voltages below 6V. The input voltage

rating is specifically stated by the capacitor manufacturer.

Make sure to check any recommended deratings and also

verify if there is any significant change in capacitance at the

operating input voltage and the operating temperature. The

Check the RMS current rating of the capacitor. The RMS cur-

rent rating of the capacitor chosen must also meet the follow-

ing condition:

input capacitor maximum RMS input current rating (I_RMS-IN

must be greater than:

)

where I_OUTis the output current, and r is the ripple ratio.

CATCH DIODE

The catch diode (D1) conducts during the switch off-time. A

Schottky diode is recommended for its fast switching times

and low forward voltage drop. The catch diode should be

chosen so that its current rating is greater than:

where r is the ripple ratio defined earlier, I_OUTis the output

current, and D is the duty cycle. It can be shown from the

above equation that maximum RMS capacitor current occurs

when D = 0.5. Always calculate the RMS at the point where

the duty cycle, D, is closest to 0.5. The ESL of an input ca-

pacitor is usually determined by the effective cross sectional

area of the current path. A large leaded capacitor will have

high ESL and a 0805 ceramic chip capacitor will have very

low ESL. At the operating frequencies of the LM27341/

LM27342, certain capacitors may have an ESL so large that

the resulting impedance (2πfL) will be higher than that re-

quired to provide stable operation. As a result, surface mount

capacitors are strongly recommended. Sanyo POSCAP, Tan-

talum or Niobium, Panasonic SP or Cornell Dubilier Low ESR

are all good choices for input capacitors and have acceptable

ESL. Multilayer ceramic capacitors (MLCC) have very low

ESL. For MLCCs it is recommended to use X7R or X5R di-

electrics. Consult the capacitor manufacturer's datasheet to

see how rated capacitance varies over operating conditions.

I_D1= I_OUTx (1-D)

The reverse breakdown rating of the diode must be at least

the maximum input voltage plus appropriate margin. To im-

prove efficiency choose a Schottky diode with a low forward

voltage drop.

BOOST DIODE (OPTIONAL)

For circuits with input voltages V_IN< 5V and duty cycles (D)

>0.75V. a small-signal Schottky diode is recommended. A

good choice is the BAT54 small signal diode. The cathode of

the diode is connected to the BOOST pin and the anode to a

5V voltage rail.

BOOST CAPACITOR

A ceramic 0.1 µF capacitor with a voltage rating of at least

6.3V is sufficient. The X7R and X5R MLCCs provide the best

performance.

OUTPUT VOLTAGE

OUTPUT CAPACITOR

The output voltage is set using the following equation where

R2 is connected between the FB pin and GND, and R1 is

connected between V_OUTand the FB pin. A good starting val-

ue for R2 is 1 kΩ.

The output capacitor is selected based upon the desired out-

put ripple and transient response. The LM27341/2's loop

compensation is designed for ceramic capacitors. A minimum

of 22 µF is required at 2 MHz (33 uF at 1 MHz) while 47 - 100

µF is recommended for improved transient response and

higher phase margin. The output voltage ripple of the con-

verter is:

FEED FORWARD CAPACITOR (OPTIONAL)

A feed forward capacitor C_FFcan improve the transient re-

sponse of the converter. Place C_FFin parallel with R1. The

value of C_FFshould place a zero in the loop response at, or

above, the pole of the output capacitor and R_LOAD. The C_FF

capacitor will increase the crossover frequency of the design,

thus a larger minimum output capacitance is required for de-

signs using C_FF. C_FFshould only be used with an output

capacitance greater than or equal to 44 uF.

When using MLCCs, the ESR is typically so low that the ca-

pacitive ripple may dominate. When this occurs, the output

ripple will be approximately sinusoidal and 90° phase shifted

from the switching action. Another benefit of ceramic capac-

itors is their ability to bypass high frequency noise. A certain

amount of switching edge noise will couple through parasitic

capacitances in the inductor to the output. A ceramic capac-

itor will bypass this noise while a tantalum will not.

The transient response is determined by the speed of the

control loop and the ability of the output capacitor to provide

www.national.com

14

MOSFET SWITCHING LOSSES

Calculating Efficiency, and Junction

Temperature

The complete LM27341/LM27342 DC-DC converter efficien-

cy can be calculated in the following manner.

Switching losses are also associated with the internal NFET.

They occur during the switch on and off transition periods,

where voltages and currents overlap resulting in power loss.

The simplest means to determine this loss is to empirically

measuring the rise and fall times (10% to 90%) of the switch

at the switch node:

P_SWF= 1/2(V_INx I_OUTx f_SWx t_FALL

)

P_SWR= 1/2(V_INx I_OUTx f_SWx t_RISE

)

P_SW= P_SWF+ P_SWR

Or

Typical Rise and Fall Times vs Input Voltage

V_IN

5V

t_RISE

8ns

t_FALL

8ns

10V

15V

9ns

10ns

Calculations for determining the most significant power loss-

es are shown below. Other losses totaling less than 2% are

not discussed.

IC QUIESCENT LOSSES

Another loss is the power required for operation of the internal

circuitry:

Power loss (P_LOSS) is the sum of two basic types of losses in

the converter, switching and conduction. Conduction losses

usually dominate at higher output loads, where as switching

losses remain relatively fixed and dominate at lower output

loads. The first step in determining the losses is to calculate

the duty cycle (D).

P_Q= I_Qx V_IN

I_Qis the quiescent operating current, and is typically around

2.4 mA.

MOSFET DRIVER LOSSES

The other operating power that needs to be calculated is that

required to drive the internal NFET:

P_BOOST= I_BOOSTx V_BOOST

V_DSis the voltage drop across the internal NFET when it is

on, and is equal to:

V_BOOSTis normally between 3VDC and 5VDC. The I_BOOSTrms

current is dependant on switching frequency f_SW. I_BOOSTis

approximately 8.2 mA at 2 MHz and 4.4 mA at 1 MHz.

V_DS= I_OUTx R_DSON

TOTAL POWER LOSSES

V_Dis the forward voltage drop across the Schottky diode. It

can be obtained from the Electrical Characteristics section of

the schottky diode datasheet. If the voltage drop across the

inductor (V_DCR) is accounted for, the equation becomes:

Total power losses are:

P_LOSS= P_COND+ P_SWR+ P_SWF+ P_Q+ P_BOOST+ P_DIODE+ P_IND

Losses internal to the LM27341/LM27342 are:

P_INTERNAL= P_COND+ P_SWR+ P_SWF+ P_Q+ P_BOOST

EFFICIENCY CALCULATION EXAMPLE

Operating conditions are:

V_DCRusually gives only a minor duty cycle change, and has

been omitted in the examples for simplicity.

V_IN= 12V

V_OUT= 3.3V

V_D1= 0.5V

I_OUT= 2A

f_SW= 2 MHz

R_DCR= 20 mΩ

SCHOTTKY DIODE CONDUCTION LOSSES

Internal Power Losses are:

The conduction losses in the free-wheeling Schottky diode

are calculated as follows:

P_COND

= I_OUT²x R_DSONx D

= 2²x 0.15Ω x 0.314

= (V_INx I_OUTx f_SWx t_FALL

P_DIODE= V_D1x I_OUT(1-D)

= 188 mW

Often this is the single most significant power loss in the cir-

cuit. Care should be taken to choose a Schottky diode that

has a low forward voltage drop.

P_SW

)

= (12V x 2A x 2 MHz x 10ns)

= I_Qx V_IN

= 480 mW

= 29 mW

P_Q

INDUCTOR CONDUCTION LOSSES

Another significant external power loss is the conduction loss

in the output inductor. The equation can be simplified to:

= 2.4 mA x 12V

P_BOOST

= I_BOOSTx V_BOOST

= 8.2 mA x 4.5V

P_IND= I_OUT²x R_DCR

= 37 mW

________

= 733 mW

MOSFET CONDUCTION LOSSES

The LM27341/LM27342 conduction loss is mainly associated

with the internal NFET:

P_INTERNAL= P_COND+ P_SW+ P_Q+ P_BOOST

Total Power Losses are:

P_COND= I_OUT²x R_DSONx D

15

www.national.com

With this information we can estimate the junction tempera-

ture of the LM27341/LM27342.

P_DIODE

= V_D1x I_OUT(1 - D)

= 0.5V x 2 x (1 - 0.314)

= I_OUT²x R_DCR

= 686 mW

= 80 mW

CALCULATING THE LM27341/LM27342 JUNCTION

TEMPERATURE

P_IND

= 2²x 20 mΩ

Thermal Definitions:

________

= 1.499 W

T_J= IC junction temperature

P_LOSS

= P_INTERNAL+ P_DIODE+ P_IND

T_A= Ambient temperature

R_θJC= Thermal resistance from IC junction to device case

R_θJA= Thermal resistance from IC junction to ambient air

The efficiency can now be estimated as:

30005666

FIGURE 7. Cross-Sectional View of Integrated Circuit Mounted on a Printed Circuit Board.

Heat in the LM27341/LM27342 due to internal power dissi-

pation is removed through conduction and/or convection.

layers within the PCB. The type and number of thermal vias

can also make a large difference in the thermal impedance.

Thermal vias are necessary in most applications. They con-

duct heat from the surface of the PCB to the ground plane.

Six to nine thermal vias should be placed under the exposed

pad to the ground plane. Placing more than nine thermal vias

results in only a small reduction to R_θJAfor the same copper

area. These vias should have 8 mil holes to avoid wicking

solder away from the DAP. See AN-1187 and AN-1520 for

more information on package thermal performance. If a com-

promise for cost needs to be made, the thermal vias for the

eMSOP package can range from 8-14 mils, this will increase

the possibility of solder wicking.

Conduction: Heat transfer occurs through cross sectional

areas of material. Depending on the material, the transfer of

heat can be considered to have poor to good thermal con-

ductivity properties (insulator vs conductor).

Heat Transfer goes as:

Silicon→Lead Frame→PCB

Convection: Heat transfer is by means of airflow. This could

be from a fan or natural convection. Natural convection occurs

when air currents rise from the hot device to cooler air.

Thermal impedance is defined as:

To predict the silicon junction temperature for a given appli-

cation, three methods can be used. The first is useful before

prototyping and the other two can more accurately predict the

junction temperature within the application.

Method 1:

Thermal impedance from the silicon junction to the ambient

air is defined as:

The first method predicts the junction temperature by extrap-

olating a best guess R_θJAfrom the table or graph. The tables

and graph are for natural convection. The internal dissipation

can be calculated using the efficiency calculations. This al-

lows the user to make a rough prediction of the junction

temperature in their application. Methods two and three can

later be used to determine the junction temperature more ac-

curately.

This impedance can vary depending on the thermal proper-

ties of the PCB. This includes PCB size, weight of copper

used to route traces , the ground plane, and the number of

The two tables below have values of R_θJAfor the LLP and the

eMSOP package.

www.national.com

16

R_θJAvalues for the eMSOP @ 1Watt dissipation:

The second method requires the user to know the thermal

impedance of the silicon junction to case. (R_θJC) is approxi-

mately 9.5°C/W for the eMSOP package or 9.1°C/W for the

LLP. The case temperature should be measured on the bot-

tom of the PCB at a thermal via directly under the DAP of the

LM27341/LM27342. The solder resist should be removed

from this area for temperature testing. The reading will be

more accurate if it is taken midway between pins 2 and 9,

where the NMOS switch is located. Knowing the internal dis-

sipation from the efficiency calculation given previously, and

the case temperature (T_C) we have:

Number

Size of

Size of Top Number R_θJA

of Board Bottom Layer Layer Copper of 10 mil

Layers

Copper

Connected to

DAP

Connected to Thermal

Dap

Vias

2

0.25 in²

0.5625 in²

1 in²

0.05 in²

2.25 in²

8

80.6 °

C/W

8

70.9 °

C/W

8

62.1 °

C/W

1.3225 in²

3.25 in²

8

54.6 °

C/W

Therefore:

T_J= (R_θJCx P_LOSS) + T_C

4 (Eval

Board)

14

35.3 °

C/W

METHOD 2 EXAMPLE

R_θJAvalues for the LLP @ 1Watt dissipation:

The operating conditions are the same as the previous Effi-

ciency Calculation:

Number

Size of

Size of Top Number R_θJA

V_IN= 12V

V_OUT= 3.3V

V_D1= 0.5V

I_OUT= 2A

of Board Bottom Layer Layer Copper of 8 mil

f_SW= 2 MHz

R_DCR= 20 mΩ

Layers

Copper

Connected to

DAP

Connected to Thermal

Dap

Vias

Internal Power Losses are:

P_COND

= I_OUT²x R_DSONx D

= 2²x 0.15Ω x 0.314

= (V_INx I_OUTx f_SWx t_FALL

2

0.25 in²

0.5625 in²

1 in²

0.05 in²

2.25 in²

8

78 °C/

W

= 188 mW

8

65.6 °

C/W

P_SW

)

= (12V x 2A x 2 MHz x 10ns)

= I_Qx V_IN

= 480 mW

= 29 mW

8

58.6 °

C/W

P_Q

= 1.5 mA x 12V

1.3225 in²

3.25 in²

8

50 °C/

W

P_BOOST

= I_BOOSTx V_BOOST

= 7 mA x 4.5V

= 37 mW

________

= 733 mW

4 (Eval

Board)

15

30.7 °

C/W

P_INTERNAL= P_COND+ P_SW+ P_Q+ P_BOOST

The junction temperature can now be estimated as:

T_J= (R_θJCx P_INTERNAL) + T_C

A National Semiconductor eMSOP evaluation board was

used to determine the T_Jof the LM27341/LM27342. The four

layer PCB is constructed using FR4 with 2oz copper traces.

There is a ground plane on the internal layer directly beneath

the device, and a ground plane on the bottom layer. The

ground plane is accessed by fourteen 10 mil vias. The board

measures 2in x 2in (50.8mm x 50.8mm). It was placed in a

container with no airflow. The case temperature measured on

this LM27342MY Demo Board was 48.7°C. Therefore,

T_J= (9.5 °C/W x 733 mW) + 48.7 °C

T_J= 55.66 °C

To keep the Junction temperature below 125 °C for this lay-

out, the ambient temperature must stay below 94.33 °C.

30005690

T_{A_MAX}= T_{J_MAX}- T_J+T_A

T_{A_MAX}= 125 °C - 55.66 °C + 25 °C

T_{A_MAX}= 94.33 °C

FIGURE 8. Estimate of Thermal Resistance vs. Ground

Copper Area

Eight Thermal Vias and Natural Convection

Method 3:

Method 2:

The third method can also give a very accurate estimate of

silicon junction temperature. The first step is to determine

17

www.national.com

R_θJAof the application. The LM27341/LM27342 has over-

temperature protection circuitry. When the silicon tempera-

ture reaches 165 °C, the device stops switching. The

protection circuitry has a hysteresis of 15 °C. Once the silicon

temperature has decreased to approximately 150 °C, the de-

vice will start to switch again. Knowing this, the R_θJAfor any

PCB can be characterized during the early stages of the de-

sign by raising the ambient temperature in the given applica-

tion until the circuit enters thermal shutdown. If the SW-pin is

monitored, it will be obvious when the internal NFET stops

switching indicating a junction temperature of 165 °C. We can

calculate the internal power dissipation from the above meth-

ods. All that is needed for calculation is the estimate of

R_DSONat 165 °C. This can be extracted from the graph of

R_DSONvs. Temperature. The value is approximately 0.267

ohms. With this, the junction temperature, and the ambient

temperature R_θJAcan be determined.

structed using FR4 with 2oz copper traces. There is a ground

plane on the internal layer directly beneath the device, and a

ground plane on the bottom layer. The ground plane is ac-

cessed by fourteen 10 mil vias. The board measures 2in x 2in

(50.8mm x 50.8mm). It was placed in an oven with no forced

airflow.

The ambient temperature was raised to 132 °C, and at that

temperature, the device went into thermal shutdown. R_θJAcan

now be calculated.

To keep the Junction temperature below 125 °C for this lay-

out, the ambient temperature must stay below 92 °C.

T_{A_MAX}= T_{J_MAX}- (R_θJAx P_INTERNAL

)

T_{A_MAX}= 125 °C - (37.46 °C/W x 0.881 W)

T_{A_MAX}= 92 °C

This calculation of the maximum ambient temperature is only

2.3 °C different from the calculation using method 2. The

methods described above to find the junction temperature in

the eMSOP package can also be used to calculate the junc-

tion temperature in the LLP package. The 10 pin LLP package

has a R_θJC= 9.1°C/W, while R_θJAcan vary depending on the

layout. R_θJAcan be calculated in the same manner as de-

scribed in method 3.

Once this is determined, the maximum ambient temperature

allowed for a desired junction temperature can be found.

METHOD 3 EXAMPLE

The operating conditions are the same as the previous Effi-

ciency Calculation:

V_IN= 12V

V_OUT= 3.3V

V_D1= 0.5V

I_OUT= 2A

PCB Layout Considerations

f_SW= 2 MHz

R_DCR= 20 mΩ

COMPACT LAYOUT

Internal Power Losses are:

The performance of any switching converter depends as

much upon the layout of the PCB as the component selection.

The following guidelines will help the user design a circuit with

maximum rejection of outside EMI and minimum generation

of unwanted EMI.

P_COND

= I_OUT²x R_DSONx D

= 2²x 0.267Ω x .314

= (V_INx I_OUTx f_SWx t_FALL

= 335 mW

P_SW

)

= (12V x 2A x 2 MHz x 10nS)

= I_Qx V_IN

= 480 mW

= 29 mW

Parasitic inductance can be reduced by keeping the power

path components close together and keeping the area of the

loops small, on which high currents travel. Short, thick traces

or copper pours (shapes) are best. In particular, the switch

node (where L1, D1, and the SW pin connect) should be just

large enough to connect all three components without exces-

sive heating from the current it carries. The LM27341/

LM27342 operates in two distinct cycles (see Figure 2) whose

high current paths are shown below in Figure 9:

P_Q

= 1.5 mA x 12V

P_BOOST

= I_BOOSTx V_BOOST

= 7 mA x 4.5V

= 37 mW

________

= 881 mW

P_INTERNAL= P_COND+ P_SW+ P_Q+ P_BOOST

Using a National Semiconductor eMSOP evaluation board to

determine the R_θJAof the board. The four layer PCB is con-

30005660

FIGURE 9. Buck Converter Current Loops

www.national.com

18

The dark grey, inner loop represents the high current path

during the MOSFET on-time. The light grey, outer loop rep-

resents the high current path during the off-time.

2. The most important consideration when completing the

layout is the close coupling of the GND connections of

the C_INcapacitor and the catch diode D1. These ground

connections should be immediately adjacent, with

multiple vias in parallel at the pad of the input capacitor

connected to GND. Place C_INand D1 as close to the IC

as possible.

GROUND PLANE AND SHAPE ROUTING

The diagram of Figure 9 is also useful for analyzing the flow

of continuous current vs. the flow of pulsating currents. The

circuit paths with current flow during both the on-time and off-

time are considered to be continuous current, while those that

carry current during the on-time or off-time only are pulsating

currents. Preference in routing should be given to the pulsat-

ing current paths, as these are the portions of the circuit most

likely to emit EMI. The ground plane of a PCB is a conductor

and return path, and it is susceptible to noise injection just like

any other circuit path. The path between the input source and

the input capacitor and the path between the catch diode and

the load are examples of continuous current paths. In con-

trast, the path between the catch diode and the input capacitor

carries a large pulsating current. This path should be routed

with a short, thick shape, preferably on the component side

of the PCB. Multiple vias in parallel should be used right at

the pad of the input capacitor to connect the component side

shapes to the ground plane. A second pulsating current loop

that is often ignored is the gate drive loop formed by the SW

and BOOST pins and boost capacitor C_BOOST. To minimize

this loop and the EMI it generates, keep C_BOOSTclose to the

SW and BOOST pins.

3. Next in importance is the location of the GND connection

of the C_OUTcapacitor, which should be near the GND

connections of C_INand D1.

4. There should be a continuous ground plane on the

copper layer directly beneath the converter. This will

reduce parasitic inductance and EMI.

5. The FB pin is a high impedance node and care should

be taken to make the FB trace short to avoid noise pickup

and inaccurate regulation. The feedback resistors should

be placed as close as possible to the IC, with the GND

of R2 placed as close as possible to the GND of the IC.

The V_OUTtrace to R1 should be routed away from the

inductor and any other traces that are switching.

6. High AC currents flow through the V_IN, SW and V_OUT

traces, so they should be as short and wide as possible.

However, making the traces wide increases radiated

noise, so the layout designer must make this trade-off.

Radiated noise can be decreased by choosing a shielded

inductor.

The remaining components should also be placed as close

as possible to the IC. Please see Application Note AN-1229

for further considerations and the LM27342 demo board as

an example of a four-layer layout.

FB LOOP

The FB pin is a high-impedance input, and the loop created

by R2, the FB pin and ground should be made as small as

possible to maximize noise rejection. R2 should therefore be

placed as close as possible to the FB and GND pins of the IC.

PCB SUMMARY

1. Minimize the parasitic inductance by keeping the power

path components close together and keeping the area of

the high-current loops small.

19

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LM27341/LM27342 Circuit Examples

30005615

FIGURE 10. V_IN= 7 - 16V, V_OUT= 5V, f_SW= 2 MHz, I_OUT= Full Load

300056100

30005677

Transient Response

I_OUT= 100 mA - 2A @ slewrate = 2A / µs

LM27342 Efficiency vs. Load Current

Bill of Materials for Figure 10

Part Number

Part Name

Buck Regulator

C_PVIN

Part ID Part Value

Manufacturer

National Semiconductor

Murata

U1

C1

C2

C3

C4

C5

D1

L1

1.5 or 2A Buck Regulator

LM27341 / LM27342

GRM32DR71E106KA12L

GRM188R71C104KA01D

C3225X7R1C226K

0603ZC184KAT2A

CMS06

10 µF

C_BOOST

0.1 µF

Murata

C_OUT

22 µF

TDK

C_OUT

22 µF

TDK

C_FF

0.18 µF

AVX

Catch Diode

Inductor

Schottky Diode Vf = 0.32V

Toshiba

Sumida

2.2 µH

560Ω

140Ω

CDRHD5D28RHPNP

CRCW0603560RFKEA

CRCW0603140RFKEA

Feedback Resistor

R1

R2

Vishay

www.national.com

20

30005673

FIGURE 11. V_IN= 7 - 16V, V_OUT= 5V, f_SW= 1 MHz, I_OUT= Full Load

300056101

30005679

Transient Response

I_OUT= 100 mA - 2A @ slewrate = 2A / µs

LM27342 Efficiency vs. Load Current

Bill of Materials for Figure 11

Part Number

Part Name

Buck Regulator

C_PVIN

Part ID Part Value

Manufacturer

National Semiconductor

Murata

U1

C1

C2

C3

C4

C5

D1

L1

1.5 or 2A Buck Regulator

LM27341 / LM27342

GRM32DR71E106KA12L

GRM188R71C104KA01D

GRM32ER61A476KE20L

C3225X7R1C226K

10 µF

C_BOOST

0.1 µF

Murata

C_OUT

47 µF

Murata

C_OUT

22 µF

TDK

C_FF

0. 27 µF

C0603C274K4RACTU

CMS06

Kemet

Catch Diode

Inductor

Schottky Diode Vf = 0.32V

Toshiba

3.3 µH

560Ω

140Ω

CDRH6D26HPNP

Sumida

Feedback Resistor

R1

R2

CRCW0603560RFKEA

CRCW0603140RFKEA

Vishay

21

www.national.com

30005615

FIGURE 12. V_IN= 5 - 16V, V_OUT= 3.3V, f_SW= 2 MHz, I_OUT= Full Load

300056102

30005681

Transient Response

I_OUT= 100 mA - 2A @ slewrate = 2A / µs

LM27342 Efficiency vs. Load Current

Bill of Materials for Figure 12

Part Number

Part Name

Buck Regulator

C_PVIN

Part ID Part Value

Manufacturer

National Semiconductor

Murata

U1

C1

C2

C3

C4

C5

D1

L1

1.5 or 2A Buck Regulator

LM27341 / LM27342

GRM32DR71E106KA12L

GRM188R71C104KA01D

C3225X7R1C226K

0603ZC184KAT2A

CMS06

10 µF

C_BOOST

0.1 µF

Murata

C_OUT

22 µF

TDK

C_OUT

22 µF

TDK

C_FF

0.18 µF

AVX

Catch Diode

Inductor

Schottky Diode Vf = 0.32V

Toshiba

Sumida

1.5 µH

430 Ω

187 Ω

CDRH5D18BHPNP

CRCW0603430RFKEA

CRCW0603187RFKEA

Feedback Resistor

R1

R2

Vishay

www.national.com

22

30005614

FIGURE 13. V_IN= 5 - 16V, V_OUT= 3.3V, f_SW= 2 MHz, I_OUT= Full Load

300056103

30005681

Transient Response

I_OUT= 100 mA - 2A @ slewrate = 2A / µs

LM27342 Efficiency vs. Load Current

Bill of Materials for Figure 13

Part Number

Part Name

Buck Regulator

C_PVIN

Part ID Part Value

Manufacturer

National Semiconductor

Murata

U1

C1

C2

C3

C4

D1

L1

1.5 or 2A Buck Regulator

LM27341 / LM27342

GRM32DR71E106KA12L

GRM188R71C104KA01D

C3225X7R1C226K

CMS06

10 µF

C_BOOST

0.1 µF

Murata

C_OUT

22 µF

TDK

C_OUT

22 µF

TDK

Catch Diode

Inductor

Schottky Diode Vf = 0.32V

Toshiba

1.5 µH

430 Ω

187 Ω

CDRH5D18BHPNP

CRCW0603430RFKEA

CRCW0603187RFKEA

Sumida

Feedback Resistor

R1

R2

Vishay

23

www.national.com

30005673

FIGURE 14. V_IN= 5 - 16V, V_OUT= 3.3V, f_SW= 1 MHz, I_OUT= Full Load

300056104

30005683

Transient Response

I_OUT= 100 mA - 2A @ slewrate = 2A / µs

LM27342 Efficiency vs. Load Current

Bill of Materials for Figure 14

Part Number

Part Name

Buck Regulator

C_PVIN

Part ID Part Value

Manufacturer

National Semiconductor

Murata

U1

C1

C2

C3

C4

C5

D1

L1

1.5 or 2A Buck Regulator

LM27341 / LM27342

GRM32DR71E106KA12L

GRM188R71C104KA01D

GRM32ER61A476KE20L

C3225X7R1C226K

10 µF

C_BOOST

0.1 µF

Murata

C_OUT

47 µF

Murata

C_OUT

22 µF

TDK

C_FF

0.27 µF

C0603C274K4RACTU

CMS06

Kemet

Catch Diode

Inductor

Schottky Diode Vf = 0.32V

Toshiba

2.7 µH

430 Ω

187 Ω

CDRH5D18BHPNP

CRCW0603430RFKEA

CRCW0603187RFKEA

Sumida

Feedback Resistor

R1

R2

Vishay

www.national.com

24

30005614

FIGURE 15. V_IN= 3.3 - 16V, V_OUT= 1.8V, f_SW= 2 MHz, I_OUT= Full Load

300056105

30005685

Transient Response

I_OUT= 100 mA - 2A @ slewrate = 2A / µs

LM27342 Efficiency vs. Load Current

Bill of Materials for Figure 15

Part Number

Part Name

Buck Regulator

C_PVIN

Part ID Part Value

Manufacturer

National Semiconductor

Murata

U1

C1

C2

C3

C4

D1

L1

1.5 or 2A Buck Regulator

LM27341 / LM27342

GRM32DR71E106KA12L

GRM188R71C104KA01D

C3225X7R1C226K

CMS06

10 µF

C_BOOST

0.1 µF

Murata

C_OUT

22 µF

TDK

C_OUT

22 µF

TDK

Catch Diode

Inductor

Schottky Diode Vf = 0.32V

Toshiba

1.0 µH

12 kΩ

15 kΩ

CDRH5D18BHPNP

CRCW060312K0FKEA

CRCW060315K0FKEA

Sumida

Feedback Resistor

R1

R2

Vishay

25

www.national.com

30005673

FIGURE 16. V_IN= 3.3 - 16V, V_OUT= 1.8V, f_SW= 1 MHz, I_OUT= Full Load

300056106

30005687

Transient Response

I_OUT= 100 mA - 2A @ slewrate = 2A / µs

LM27342 Efficiency vs. Load Current

Bill of Materials for Figure 16

Part Number

Part Name

Buck Regulator

C_PVIN

Part ID Part Value

Manufacturer

National Semiconductor

Murata

U1

C1

C2

C3

C4

C5

D1

L1

1.5 or 2A Buck Regulator

LM27341 / LM27342

GRM32DR71E106KA12L

GRM188R71C104KA01D

C3225X7R1C226K

GRM188R71H392KA01D

CMS06

10 µF

C_BOOST

0.1 µF

Murata

C_OUT

22 uF

TDK

C_OUT

22 uF

TDK

C_FF

3.9 nF

Murata

Catch Diode

Inductor

Schottky Diode Vf = 0.32V

Toshiba

1.8 µH

12 kΩ

15 kΩ

CDRH5D18BHPNP

CRCW060312K0FKEA

CRCW060315K0FKEA

Sumida

Feedback Resistor

R1

R2

Vishay

www.national.com

26

30005615

FIGURE 17. V_IN= 3.3 - 9V, V_OUT= 1.2V, f_SW= 2 MHz, I_OUT= Full Load

300056107

30005689

Transient Response

I_OUT= 100 mA - 2A @ slewrate = 2A / µs

LM27342 Efficiency vs. Load Current

Bill of Materials for Figure 17

Part Number

Part Name

Buck Regulator

C_PVIN

Part ID Part Value

Manufacturer

National Semiconductor

Murata

U1

C1

C2

C3

C4

C5

D1

L1

1.5 or 2A Buck Regulator

LM27341 / LM27342

10 µF

GRM32DR71E106KA12L

GRM188R71C104KA01D

GRM32ER61A476KE20L

C3225X7R1C226K

C_BOOST

0.1 µF

Murata

C_OUT

47 µF

Murata

C_OUT

22 µF

TDK

C_FF

NOT MOUNTED

Schottky Diode Vf = 0.32V

0.56 µH

Catch Diode

Inductor

CMS06

Toshiba

Sumida

Vishay

CDRH2D18/HPNP

CRCW06031K02FKEA

CRCW06035K10FKEA

Feedback Resistor

R1

R2

1.02 kΩ

5.10 kΩ

27

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

10-Lead LLP Package

NS Package Number SDA10A

10-Lead eMSOP Package

NS Package Number MUC10A

www.national.com

28

Notes

29

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型号：	LM27342SD
厂家：	National Semiconductor
描述：	2 MHz 1.5A/2A Wide Input Range Step-Down DC-DC Regulator with Frequency Synchronization 2 MHz的1.5A / 2A宽输入范围降压型DC- DC调节器，频率同步调节器
文件：	总30页 (文件大小：715K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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