LM3430SDX [NSC]
Boost Controller for LED Backlighting; 升压控制器，用于LED背光
| 型号： | LM3430SDX |
| 厂家： | 
National Semiconductor |
| 描述： | Boost Controller for LED Backlighting |
| 文件： | 总24页 (文件大小：564K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2007
LM3430
Boost Controller for LED Backlighting
General Description
Features
The LM3430 is a high voltage low-side N-channel MOSFET
controller. Ideal for use in a boost regulator, the LM3430 can
power the LED backlight in LCD panels, such as in notebook
PCs. It contains all of the features needed to implement single
ended primary topologies. Output voltage regulation is based
on current-mode control, which eases the design of loop com-
pensation while providing inherent input voltage feed-forward.
The LM3430 includes a start-up regulator that operates over
a wide input range of 6V to 40V. The PWM controller is de-
signed for high speed capability including an oscillator fre-
quency range up to 2 MHz and total propagation delays less
than 100 ns. Additional features include an error amplifier,
precision reference, line under-voltage lockout, cycle-by-cy-
cle current limit, slope compensation, soft-start, external syn-
chronization capability and thermal shutdown. The LM3430 is
available in the LLP-12 package.
Internal 40V Startup Regulator
■
■
■
■
■
■
■
■
1A Peak MOSFET Gate Driver
VIN Range 6V to 40V
Duty Cycle Limit in Excess of 90%
Programmable UVLO with Hysteresis
Cycle-by-Cycle Current Limit
External Synchronizable (AC-coupled)
Single Resistor Oscillator Frequency Set
Slope Compensation
■
■
■
Adjustable Soft-start
LLP-12 (3mm x 3mm)
Applications
LED Backlight Driver (companion to LM3432)
■
■
■
Boost Converter
SEPIC Converter
Typical Application
20209601
© 2007 National Semiconductor Corporation
202096
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Connection Diagram
12-Lead LLP Package20209602
NS Package Number SDF12A
Ordering Information
Part Number
LM3430SD
NS Package Drawing
SDF12A
Supplied As
1000 Units on Tape and Reel
4500 Units on Tape and Reel
LM3430SDX
SDF12A
Pin Descriptions
Pin(s)
Name
VDHC
VIN
Description
Application Information
This pin accepts a control signal from LM3432 to adjust the output
voltage in real time.
1
2
Proprietary control input from LM3432
Source input voltage
Input to the start-up regulator. Operates from 6V to 40V.
Inverting input to the internal voltage error amplifier. The non-
inverting input of the error amplifier connects to a 1.25V
reference.
3
4
FB
Feedback pin
Error amplifier output and PWM
comparator input
The control loop compensation components connect between
this pin and the FB pin.
COMP
Output of the internal, high voltage linear This pin should be bypassed to the GND pin with a ceramic
5
6
VCC
OUT
regulator.
capacitor.
Output of gate driver
Connect this pin to the gate of the external MOSFET. The gate
driver has a 1A peak current capability.
7
8
GND
System ground
Set the start-up and shutdown levels by connecting this pin to the
input voltage through a resistor divider. A 20 µA current source
provides hysteresis.
UVLO
Input Under-Voltage Lock-out
Current Sense input
Input for the switch current sensing used for current mode control
and for current limiting.
9
CS
An external resistor connected from this pin to GND sets the
oscillator frequency. This pin can also accept an ac-coupled input
for synchronization from an external clock.
Oscillator frequency adjust pin and
synchronization input
10
RT/SYNC
An external capacitor placed from this pin to ground will be
charged by a 10 µA current source, creating a ramp voltage to
control the regulator start-up.
11
SS
Soft-start pin
12
NC
EP
No-connect
Leave this pin open-circuit.
DAP
Exposed Pad
Thermal connection pad, connect to GND.
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Storage Temperature
Soldering Information
Vapor Phase (60 sec.)
Infrared (15 sec.)
-65°C to +150°C
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
215°C
220°C
ESD Rating
VIN to GND
VCC to GND
-0.3V to 45V
-0.3V to 16V
-0.3V to 5.5V
-1.5V for < 100 ns
-0.3V to 7V
Human Body Model (Note 2)
2 kV
RT/SYNC to GND
OUT to GND
All other pins to GND
Power Dissipation
Junction Temperature
Operating Ranges (Note 4)
Supply Voltage
External Volatge at VCC
Junction Temperature Range
6V to 40V
7.5V to 14V
Internally Limited
150°C
-40°C to +125°C
Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the
junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
VIN = 18V and RT = 27.4 kΩ unless otherwise indicated. (Note 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SYSTEM PARAMETERS
VFB
FB Pin Voltage
1.225 1.250 1.275
V
-40°C ≤ TJ ≤ 125°C
9V ≤ VIN ≤ 40V, ICC = 1 mA
START-UP REGULATOR
6.6
5
7
7.4
4
VCC Regulation
VCC
V
6V ≤ VIN < 9V, VCC Pin Open
Circuit
VCC Regulation
OUT Pin Capacitance = 0
VCC = 10V
3.5
ICC
Supply Current
mA
mA
ICC-LIM
VCC Current Limit
VCC = 0V, (Note 4, 6)
ICC = 0 mA, fSW < 200 kHz
6V ≤ VIN ≤ 8.5V
VIN increasing
15
35
200
VIN - VCC
Dropout Voltage Across Bypass Switch
mV
VBYP-HI
Bypass Switch Turn-off Threshold
Bypass Switch Threshold Hysteresis
8.7
260
58
V
VBYP-HYS
VIN Decreasing
VIN = 6.0V
mV
VCC Pin Output Impedance
ZVCC
VIN = 8.0V
53
Ω
0 mA ≤ ICC ≤ 5 mA
VIN = 18.0V
1.1
5
VCC-HI
VCC-HYS
IVIN
VCC Pin UVLO Rising Threshold
VCC Pin UVLO Falling Hysteresis
Start-up Regulator Leakage
Shutdown Current
V
300
150
350
mV
µA
µA
VIN = 40V
500
450
IIN-SD
VUVLO = 0V, VCC = Open Circuit
ERROR AMPLIFIER
GBW
ADC
Gain Bandwidth
4
MHz
dB
DC Gain
75
17
VFB = 1.5V
VCOMP = 1V
5
ICOMP
COMP Pin Current Sink Capability
mA
UVLO
VSD
Shutdown Threshold
1.22
16
1.25
20
1.28
24
V
Shutdown
Hysteresis Current Source
ISD-HYS
µA
CURRENT LIMIT
tLIM-DLY
CS steps from 0V to 0.6V
OUT transitions to 90% of VCC
30
Delay from ILIM to Output
ns
VCS
tBLK
RCS
Current Limit Threshold Voltage
Leading Edge Blanking Time
CS Pin Sink Impedance
0.45
0.5
65
40
0.55
75
V
ns
Ω
Blanking active
3
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Symbol
SOFT-START
ISS
Parameter
Conditions
Min
Typ
Max
Units
Soft-start Current Source
Soft-start to COMP Offset
7
10
13
µA
V
VSS-OFF
0.35
0.55
0.75
OSCILLATOR
(Note 5)
(Note 5)
(Note 5)
170
525
865
3.8
200
600
990
230
675
kHz
kHz
kHz
V
RT to GND = 84.5 kΩ
fSW
RT to GND = 27.4 kΩ
1115
RT to GND = 16.2 kΩ
Synchronization Rising Threshold
VSYNC-HI
PWM COMPARATOR
VCOMP = 2V
25
tCOMP-DLY
Delay from COMP to OUT Transition
ns
CS stepped from 0V to 0.4V
VCOMP = 0V
DMIN
DMAX
Minimum Duty Cycle
0
%
%
Maximum Duty Cycle
90
95
0.33
5.2
APWM
COMP to PWM Comparator Gain
COMP Pin Open Circuit Voltage
COMP Pin Short Circuit Current
V/V
V
VCOMP-OC
ICOMP-SC
VFB = 0V
4.3
0.6
6.1
1.5
VCOMP = 0V, VFB = 1.5V
1.1
mA
SLOPE COMPENSATION
VSLOPE
MOSFET DRIVER
VSAT-HI
Slope Compensation Amplitude
80
105
130
mV
V
Output High Saturation Voltage (VCC –
VOUT)
IOUT = 50 mA
0.25
0.75
0.75
VSAT-LO
tRISE
Output Low Saturation Voltage (VOUT)
OUT Pin Rise Time
IOUT = 100 mA
0.25
18
V
OUT Pin load = 1 nF
OUT Pin load = 1 nF
ns
ns
tFALL
OUT Pin Fall Time
15
THERMAL CHARACTERISTICS
TSD
TSD-HYS
θJA
Thermal Shutdown Threshold
165
25
°C
°C
Thermal Shutdown Hysteresis
Junction to Ambient Thermal Resistance
SDF-12A Package
122
°C/W
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. The Recommended Operating Limits define the conditions within
which the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.
Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 4: Device thermal limitations may limit usable range.
Note 5: Specification applies to the oscillator frequency.
Note 6: VCC provides bias for the internal gate drive and control circuits.
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Typical Performance Characteristics
Efficiency, VO = 40V
VFB vs. Temp (VIN = 18V)
20209654
20209603
VFB vs. VIN (TA = 25°C)
VCC vs. VIN (TA = 25°C)
20209604
20209605
Max Duty Cycle vs. fSW (TA = 25°C)
fSW vs. Temperature (RT = 16.2 kΩ)
20209606
20209607
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RT vs. fSW (TA = 25°C)
SS vs. Temperature
20209609
20209608
OUT Pin tR vs. Gate Capacitance
OUT Pin tF vs. Gate Capacitance
20209610
20209611
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Block Diagram
20209612
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Example Circuit: LM3430 and LM3432
20209613
FIGURE 1. LM3430 with LM3432
Application Parameters for Various LED Configurations
Input Voltage
8V to 21V
33V
8V to 21V
50V
8V to 18V
33V
Maximum Output
Voltage
LED Configuration 8 LEDs x 6 Strings, 20 mA per 12 LEDs x 6 Strings, 20 mA per string 8 LEDs x 6 Strings, 20 mA per string
string
Switching Frequency
1 MHz
22 µH
1 MHz
22 µH
2 MHz
4.7 µH
L1
Co
10 µF, 50V
20 µF, 100V
10 µF, 50V
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Cin
10 µF, 50V
100 nF
1 nF
10 µF, 50V
100 nF
1 nF
10 µF, 50V
100 nF
1 nF
Cinx
Css
Rt
16.5 kΩ
4.64 kΩ
118 kΩ
10 kΩ
16.5 kΩ
3.01 kΩ
118 kΩ
10 kΩ
8.25 kΩ
16.5 kΩ
422 kΩ
10 kΩ
Rfb1
Rfb2
Ruv1
Ruv2
49.9 kΩ
49.9 kΩ
49.9 kΩ
Control Loop Compensation
C1
12 pF
75 kΩ
220 nF
12 pF
118 kΩ
47 nF
39 pF
150 kΩ
4.7 nF
R1
C2
VDHC
Rdhc
30 kΩ
9.09 kΩ
60.4 kΩ
Slope Compensation
Rs1
Rs2
4.02 kΩ
4.02 kΩ
4.02 kΩ
301Ω
301Ω
301Ω
Current Sensing
Rsns
0.2Ω (1W)
0.2Ω (1W)
Two 1Ω (1W) in parallel
Csns
1 nF
1 nF
1 nF
UVLO falling threshold (4.7V) during the initial start-up. Dur-
ing a fault condition when the converter auxiliary winding is
inactive, external current draw on the VCC line should be lim-
ited such that the power dissipated in the start-up regulator
does not exceed the maximum power dissipation capability of
the controller.
Applications Information
OVERVIEW
The LM3430 is a low-side N-channel MOSFET controller that
contains all of the features needed to implement single ended
power converter topologies. The LM3430 includes a high-
voltage startup regulator that operates over a wide input
range of 6V to 40V. The PWM controller is designed for high
speed capability including an oscillator frequency range up to
2 MHz and total propagation delays less than 100 ns. Addi-
tional features include an error amplifier, precision reference,
input under-voltage lockout, cycle-by-cycle current limit, slope
compensation, soft-start, oscillator sync capability and ther-
mal shutdown.
An external start-up or other bias rail can be used instead of
the internal start-up regulator by connecting the VCC and the
VIN pins together and feeding the external bias voltage (7.5V
to 14V) to the two pins.
INPUT UNDER-VOLTAGE DETECTOR
The LM3430 contains an input Under Voltage Lock Out (UV-
LO) circuit. UVLO is programmed by connecting the UVLO
pin to the center point of an external voltage divider from VIN
to GND. The resistor divider must be designed such that the
voltage at the UVLO pin is greater than 1.25V when VIN is in
the desired operating range. If the under voltage threshold is
not met, all functions of the controller are disabled and the
controller remains in a low power standby state. UVLO hys-
teresis is accomplished with an internal 20 µA current source
that is switched on or off into the impedance of the set-point
divider. When the UVLO threshold is exceeded, the current
source is activated to instantly raise the voltage at the UVLO
pin. When the UVLO pin voltage falls below the 1.25V thresh-
old the current source is turned off, causing the voltage at the
UVLO pin to fall. The UVLO pin can also be used to implement
a remote enable / disable function. If an external transistor
pulls the UVLO pin below the 1.25V threshold, the converter
will be disabled. This external shutdown method is shown in
Figure 2.
The LM3430 is designed for current-mode control power con-
verters that require a single drive output, such as boost and
SEPIC topologies. The LM3430 provides all of the advan-
tages of current-mode control including input voltage feed-
forward, cycle-by-cycle current limiting and simplified loop
compensation.
HIGH VOLTAGE START-UP REGULATOR
The LM3430 contains an internal high-voltage startup regu-
lator that allows the VIN pin to be connected directly to line
voltages as high as 40V. The regulator output is internally
current limited to 35 mA (typical). When power is applied, the
regulator is enabled and sources current into an external ca-
pacitor, CF, connected to the VCC pin. The recommended
capacitance range for CF is 0.1 µF to 100 µF. When the volt-
age on the VCC pin reaches the rising threshold of 5V, the
controller output is enabled. The controller will remain en-
abled until VCC falls below 4.7V. In applications using a
transformer, an auxiliary winding can be connected through
a diode to the VCC pin. This winding should raise the VCC
pin voltage to above 7.5V to shut off the internal startup reg-
ulator. Powering VCC from an auxiliary winding improves
conversion efficiency while reducing the power dissipated in
the controller. The capacitance of CF must be high enough
that the it maintains the VCC voltage greater than the VCC
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To set the switching frequency, fSW, RT can be calculated
from:
The LM3430 can also be synchronized to an external clock.
The external clock must have a higher frequency than the free
running oscillator frequency set by the RT resistor. The clock
signal should be capacitively coupled into the RT/SYNC pin
with a 100 pF capacitor, shown in Figure 3. A peak voltage
level greater than 3.8V at the RT/SYNC pin is required for
detection of the sync pulse. The sync pulse width should be
set between 15 ns to 150 ns by the external components. The
RT resistor is always required, whether the oscillator is free
running or externally synchronized. The voltage at the RT/
SYNC pin is internally regulated to 2V, and the typical delay
from a logic high at the RT/SYNC pin to the rise of the OUT
pin voltage is 120 ns. RT should be located very close to the
device and connected directly to the pins of the controller (RT/
SYNC and GND).
20209614
FIGURE 2. Enable/Disable Using UVLO
ERROR AMPLIFIER
An internal high gain error amplifier is provided within the
LM3430. The amplifier’s non-inverting input is internally set to
a fixed reference voltage of 1.25V. The inverting input is con-
nected to the FB pin. In non-isolated applications such as the
boost converter the output voltage, VO, is connected to the FB
pin through a resistor divider. The control loop compensation
components are connected between the COMP and FB pins.
For most isolated applications the error amplifier function is
implemented on the secondary side of the converter and the
internal error amplifier is not used. The internal error amplifier
is configured as an open drain output and can be disabled by
connecting the FB pin to ground. An internal 5 kΩ pull-up re-
sistor between a 5V reference and COMP can be used as the
pull-up for an opto-coupler in isolated applications.
CURRENT SENSING AND CURRENT LIMITING
The LM3430 provides a cycle-by-cycle over current protec-
tion function. Current limit is accomplished by an internal
current sense comparator. If the voltage at the current sense
comparator input exceeds 0.5V, the MOSFET gate drive will
be immediately terminated. A small RC filter, located near the
controller, is recommended to filter noise from the current
sense signal. The CS input has an internal MOSFET which
discharges the CS pin capacitance at the conclusion of every
cycle. The discharge device remains on an additional 65 ns
after the beginning of the new cycle to attenuate leading edge
ringing on the current sense signal.
20209653
FIGURE 3. Sync Operation
PWM COMPARATOR AND SLOPE COMPENSATION
The LM3430 current sense and PWM comparators are very
fast, and may respond to short duration noise pulses. Layout
considerations are critical for the current sense filter and
sense resistor. The capacitor associated with the CS filter
must be located very close to the device and connected di-
rectly to the pins of the controller (CS and GND). If a current
sense transformer is used, both leads of the transformer sec-
ondary should be routed to the sense resistor and the current
sense filter network. The current sense resistor can be locat-
ed between the source of the primary power MOSFET and
power ground, but it must be a low inductance type. When
designing with a current sense resistor all of the noise sensi-
tive low-power ground connections should be connected to-
gether locally to the controller and a single connection should
be made to the high current power ground (sense resistor
ground point).
The PWM comparator compares the current ramp signal with
the error voltage derived from the error amplifier output. The
error amplifier output voltage at the COMP pin is offset by
1.4V and then further attenuated by a 3:1 resistor divider. The
PWM comparator polarity is such that 0V on the COMP pin
will result in a zero duty cycle at the controller output. For duty
cycles greater than 50%, current mode control circuits can
experience sub-harmonic oscillation. By adding an additional
fixed-slope voltage ramp signal (slope compensation) this os-
cillation can be avoided. The LM3430 generates the slope
compensation with a 45 µAP-P sawtooth-waveform current
source generated by the clock. (See Figure 4) This current
flows through an internal 2 kΩ resistor to create a minimum
compensation ramp voltage of 100 mV (typical). The ampli-
tude of the compensation ramp increases when external re-
sistance is added for filtering the current sense (RS1) or in the
position RS2. As shown in Figure 4 and the block diagram, the
sensed current slope and the compensation slope add to-
gether to create the signal used for current limiting and for the
control loop itself.
OSCILLATOR, SHUTDOWN AND SYNC
A single external resistor, RT, connected between the RT/
SYNC and GND pins sets the LM3430 oscillator frequency.
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20209616
FIGURE 4. Slope Compensation
In addition to preventing sub-harmonic oscillation, increasing
the amplitude of the compensation ramp voltage decreases
the voltage across RSNS required to trip the current limit com-
parator. This technique can be used to lower the value of
RSNS and reduce power dissipation. Care must be taken not
to add too much slope compensation, however. Reducing
RSNS causes the control loop gain to increase, and too large
of a compensation ramp can overwhelm the sensed current
signal. This imbalance causes the system to act more like a
voltage-mode regulator with a low frequency double pole that
is more difficult to compensate.
(VD is the forward voltage drop of the output diode)
The following is a design procedure for selecting all the com-
ponents for the boost converter portion of the Example Circuit
of Figure 1. This circuit operates in continuous conduction
mode (CCM), where inductor current stays above 0A at all
times, and delivers an output voltage of 33.0V ±2% at an out-
put current of 180 mA. The load is a white LED-based LCD
monitor backlight, formed by six parallel strings of seven white
LEDs each with a multi-channel linear current regulator to sink
30 mA through each string. The forward voltage of each LED
varies from 3.0V to 4.2V over process and temperature and
the current regulator requires approximately 4V of headroom.
The required output voltage is therefore 7 x 4.2V + 4V ≊ 33V.
SOFT-START
The soft-start feature allows the power converter output to
gradually reach the initial steady state output voltage, thereby
reducing start-up stresses and current surges. At power on,
after the VCC and input under-voltage lockout thresholds are
satisfied, an internal 10 µA current source charges an external
capacitor connected to the SS pin. The capacitor voltage will
ramp up slowly and will limit the COMP pin voltage and the
switch current.
The input voltage will come from a three-to-four-cell stack of
lithium ion batteries (VIN = 9.0V to 16.8V) or a poorly regulated
AC-DC adapter that supplies 14.0V to 20.9V. The diode drop
VD will be 0.5V, typical of a Schottky diode.
MOSFET GATE DRIVER
The LM3430 provides an internal gate driver through the OUT
pin that can source and sink a peak current of 1A to control
external, ground-referenced MOSFETs.
SWITCHING FREQUENCY
The selection of switching frequency is based on the tradeoffs
between size, cost, and efficiency. In general, a lower fre-
quency means larger, more expensive inductors and capac-
itors will be needed. A higher switching frequency generally
results in a smaller but less efficient solution, as the power
MOSFET gate capacitances must be charged and dis-
charged more often in a given amount of time. For this appli-
cation, a frequency of 600 kHz was selected as a good
compromise between the size of the inductor and efficiency.
PCB area and component height are restricted in this appli-
cation. Following the equation given for RT in the Applications
Information section, a 27.4 kΩ 1% resistor should be used to
switch at 600 kHz.
DYNAMIC HEADROOM CONTROL
The VDHC pin of the LM3430 can be used in conjunction with
the LM3432 to provide on-the-fly adjustments to the output
voltage for maximum efficiency when driving an array of
LEDs. When this feature is not being used the VDHC pin
should be left open circuit.
THERMAL SHUTDOWN
Internal thermal shutdown circuitry is provided to protect the
LM3430 in the event that the maximum junction temperature
is exceeded. When activated, typically at 165°C, the controller
is forced into a low power standby state, disabling the output
driver and the VCC regulator. After the temperature is re-
duced (typical hysteresis is 25°C) the VCC regulator will be
re-enabled and the LM3430 will perform a soft-start.
MOSFET
Selection of the power MOSFET is governed by tradeoffs be-
tween cost, size, and efficiency. Breaking down the losses in
the MOSFET is one way to determine relative efficiencies be-
tween different devices. For this example, the SO-8 package
provides a balance of a small footprint with good efficiency.
Design Considerations
The most common circuit controlled by the LM3430 is a non-
isolated boost regulator. The boost regulator steps up the
input voltage and has a duty ratio D of:
Losses in the MOSFET can be broken down into conduction
loss, gate charging loss, and switching loss.
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Conduction, or I2R loss, PC, is approximately:
time. This power dissipation can be calculating by checking
the typical diode forward voltage, VD, from the I-V curve on
the diode's datasheet and then multiplying it by ID. Diode
datasheets will also provide a typical junction-to-ambient ther-
mal resistance, θJA, which can be used to estimate the oper-
ating die temperature of the Schottky. Multiplying the power
dissipation (PD = IO x VD) by θJA gives the temperature rise.
The diode case size can then be selected to maintain the
Schottky diode temperature below the operational maximum.
The factor 1.3 accounts for the increase in MOSFET on re-
sistance due to heating. Alternatively, the factor of 1.3 can be
ignored and the on resistance of the MOSFET can be esti-
mated using the RDSON Vs. Temperature curves in the MOS-
FET datasheets.
In this example a Schottky diode rated to 40V and 0.5A will
be suitable, as the maximum diode current will be 180 mA. A
small case such as SOD-123 or SOT-23 can be used if a small
footprint is critical. Larger case sizes generally have lower
Gate charging loss, PG, results from the current required to
charge and discharge the gate capacitance of the power
MOSFET and is approximated as:
θ
JA and lower forward voltage drop, so for better efficiency, a
larger case size such as SMA can be used. In applications
with a high boost ratio, such as 1:4, the reverse recovery time,
tRR, has a large impact on losses and efficiency. The Schottky
diode selected should therefore have a tRR value below 15 ns.
PG = VCC x QG x fSW
BOOST INDUCTOR
QG is the total gate charge of the MOSFET. Gate charge loss
differs from conduction and switching losses because the ac-
tual dissipation occurs in the LM3430 and not in the MOSFET
itself. If no external bias is applied to the VCC pin, additional
loss in the LM3430 IC occurs as the MOSFET driving current
flows through the VCC regulator. This loss, PVCC, is estimated
as:
The first criterion for selecting an inductor is the inductance
itself. In fixed-frequency boost converters this value is based
on the desired peak-to-peak ripple current, ΔiL, which flows in
the inductor along with the average inductor current, IL. For a
boost converter in CCM IL is greater than the average output
current, IO. The two currents are related by the following ex-
pression:
IL = IO / (1 – D)
PVCC = (VIN – VCC) x QG x fSW
As with switching frequency, the inductance used is a tradeoff
between size and cost. Larger inductance means lower input
ripple current, however because the inductor is connected to
the output during the off-time only there is a limit to the re-
duction in output ripple voltage. Lower inductance results in
smaller, less expensive magnetics. An inductance that gives
a ripple current of 30% to 50% of IL is a good starting point for
a CCM boost converter. Minimum inductance should be cal-
culated at the extremes of input voltage to find the operating
condition with the highest requirement:
Switching loss, PSW, occurs during the brief transition period
as the MOSFET turns on and off. During the transition period
both current and voltage are present in the channel of the
MOSFET. The loss can be approximated as:
PSW = 0.5 x VIN x [IO / (1 – D)] x (tR + tF) x fSW
Where tR and tF are the rise and fall times of the MOSFET
For this example, the maximum drain-to-source voltage ap-
plied across the MOSFET is VO plus the ringing due to para-
sitic inductance and capacitance. The maximum drive voltage
at the gate of the high side MOSFET is VCC, or 7V typical.
The MOSFET selected must be able to withstand 33V plus
any ringing from drain to source, and be able to handle at least
7V plus ringing from gate to source. A minimum voltage rating
of 40VD-S and 10VG-S MOSFET will be used. Comparing the
losses in a spreadsheet leads to a 60VD-S rated MOSFET in
SO-8 with a typical RDSON of 22 mΩ, a gate charge of 18 nC,
and rise and falls times of 10 ns and 12 ns, respectively.
By calculating in terms of amperes, volts, and megahertz, the
inductance value will come out in microhenrys.
In order to ensure that the boost regulator operates in CCM
a second equation is needed, and must also be evaluated at
the corners of input voltage to find the minimum inductance
required:
BOOST DIODE
The boost regulator requires a boost diode D1 (see the Typ-
ical Application circuit) to carrying the inductor current during
the MOSFET off-time. The most efficient choice for D1 is a
Schottky diode due to low forward drop and zero reverse re-
covery time. D1 must be rated to handle the maximum output
voltage plus any switching node ringing when the MOSFET
is on. In practice, all switching converters have some ringing
at the switching node due to the diode parasitic capacitance
and the lead inductance. D1 must also be rated to handle the
average output current, IO.
By calculating in terms of volts, amps and megahertz the in-
ductance value will come out in microhenrys.
For this design ΔiL will be set to 40% of the maximum IL. Duty
cycle is evaluated first at VIN(MIN) and at VIN(MAX). Second, the
average inductor current is evaluated at the two input volt-
ages. Third, the inductor ripple current is determined. Finally,
the inductance can be calculated, and a standard inductor
value selected that meets all the criteria.
The overall converter efficiency becomes more dependent on
the selection of D1 at low duty cycles, where the boost diode
carries the load current for an increasing percentage of the
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12
Inductance for Minimum Input Voltage
average current of 0.93A. Finally, the inductor current ripple
is recalculated at the maximum input voltage:
DVIN(MIN) = (33 – 9.0 – 0.5) / (33 – 0.5) = 72%
IL-VIN(MIN) = 0.18 / (1 – 0.72) = 0.64A
ΔiL = 0.4 x 0.64A = 0.26A
ΔiL-VIN(MAX) = (20.9 x 0.36) / (0.6 x 47) = 267 mAP-P
OUTPUT CAPACITOR
The output capacitor in a boost regulator supplies current to
the load during the MOSFET on-time and also filters the AC
portion of the load current during the off-time. This capacitor
determines the steady state output voltage ripple, ΔVO, a crit-
ical parameter for all voltage regulators. Output capacitors are
selected based on their capacitance, CO, their equivalent se-
ries resistance (ESR) and their RMS or AC current rating.
The magnitude of ΔVO is comprised of three parts, and in
steady state the ripple voltage during the on-time is equal to
the ripple voltage during the off-time. For simplicity the anal-
ysis will be performed for the MOSFET turning off (off-time)
only. The first part of the ripple voltage is the surge created
as the output diode D1 turns on. At this point inductor/diode
current is at the peak value, and the ripple voltage increase
can be calculated as:
Inductance for Maximum Input Voltage
DVIN(MAX) = (33 – 20.9) / 33 = 37%
IL-VIN(MIAX) = 0.18 / (1 – 0.37) = 0.29A
ΔiL = 0.4 x 0.29A = 0.12A
ΔVO1 = IPK x ESR
The second portion of the ripple voltage is the increase due
to the charging of CO through the output diode. This portion
can be approximated as:
Maximum average inductor current occurs at VIN(MIN), and the
corresponding inductor ripple current is 0.26AP-P. Selecting
an inductance that exceeds the ripple current requirement at
VIN(MIN) and the requirement to stay in CCM for VIN(MAX) pro-
vides a tradeoff that allows smaller magnetics at the cost of
higher ripple current at maximum input voltage. For this ex-
ample, a 47 µH inductor will satisfy these requirements.
ΔVO2 = (IO / CO) x (D / fSW
)
The final portion of the ripple voltage is a decrease due to the
flow of the diode/inductor current through the output
capacitor’s ESR. This decrease can be calculated as:
The second criterion for selecting an inductor is the peak cur-
rent carrying capability. This is the level above which the
inductor will saturate. In saturation the inductance can drop
off severely, resulting in higher peak current that may over-
heat the inductor or push the converter into current limit. In a
boost converter, peak current, IPK, is equal to the maximum
average inductor current plus one half of the ripple current.
First, the current ripple must be determined under the condi-
tions that give maximum average inductor current:
ΔVO3 = ΔiL x ESR
The total change in output voltage is then:
ΔVO = ΔVO1 + ΔVO2 - ΔVO3
The combination of two positive terms and one negative term
may yield an output voltage ripple with a net rise or a net fall
during the converter off-time. The ESR of the output capacitor
(s) has a strong influence on the slope and direction of ΔVO.
Capacitors with high ESR such as tantalum and aluminum
electrolytic create an output voltage ripple that is dominated
by ΔVO1 and ΔVO3, with a shape shown in Figure 5. Ceramic
capacitors, in contrast, have very low ESR and lower capac-
itance. The shape of the output ripple voltage is dominated by
ΔVO2, with a shape shown in Figure 6.
Maximum average inductor current occurs at VIN(MIN). Using
the selected inductance of 47 µH yields the following:
ΔiL = (9 x 0.72) / (0.6 x 47) = 230 mAP-P
The highest peak inductor current over all operating condi-
tions is therefore:
IPK = IL + 0.5 x ΔiL = 0.64 + 0.115 = 0.76A
Hence an inductor must be selected that has a peak current
rating greater than 0.76A and an average current rating
greater than 0.64A. One possibility is an off-the-shelf 47 µH
±20% inductor that can handle a peak current of 0.9A and an
13
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ΔVO2 = (0.18 / 5 x 10-7) x (0.72 / 600000) = 432 mV
Finally, the worst-case value for ΔVO3 occurs when inductor
ripple current is highest, at maximum input voltage:
ΔVO3 = 0.398 x 0.003 = 1.2 mV (negligible)
The output voltage ripple can be estimated by summing the
three terms:
20209626
ΔVO = 3.8 mV + 432 mV - 1.2 mV = 435 mV
FIGURE 5. ΔVO Using High ESR Capacitors
The RMS current through the output capacitor(s) can be es-
timated using the following, worst-case equation:
The highest RMS current occurs at minimum input voltage.
For this example the maximum output capacitor RMS current
is:
IO-RMS(MAX) = 1.13 x 0.64 x (0.72 x 0.28)0.5 = 0.32ARMS
Ceramic capacitors in 1206 case sizes are generally capable
of sustaining RMS currents in excess of 2A, making them
more than adequate for this application.
20209627
VCC DECOUPLING CAPACITOR
The VCC pin should be decoupled with a ceramic capacitor
placed as close as possible to the VCC and GND pins of the
LM3430. The decoupling capacitor should have a minimum
X5R or X7R type dielectric to ensure that the capacitance re-
mains stable over voltage and temperature, and be rated to
a minimum of 470 nF. One good choice is a 1.0 µF device
with X7R dielectric and 1206 case size rated to 25V.
FIGURE 6. ΔVO Using Low ESR Capacitors
For this example, the load is fairly constant, and the height
restriction favors the low profile of ceramic capacitors. The
output ripple voltage waveform of Figure 6 is assumed, and
the capacitance will be selected first. The desired ΔVO is ±2%
of 33V, or 1.32VP-P. Beginning with the calculation for ΔVO2
the required minimum capacitance is:
,
INPUT CAPACITOR
The input capacitors to a boost regulator control the input
voltage ripple, ΔVIN, hold up the input voltage during load
transients, and prevent impedance mismatch (also called
power supply interaction) between the LM3430 and the in-
ductance of the input leads. Selection of input capacitors is
based on their capacitance, ESR, and RMS current rating.
The minimum value of ESR can be selected based on the
maximum output current transient, ISTEP, using the following
expression:
CO-MIN = (IO / ΔVO) x (DMAX / fSW
)
CO-MIN = (0.18 / 1.32) x (0.72 / 600000) = 164 nF
Ceramic capacitors rated 1.0 µF ±20% are available from
many manufacturers. The minimum quality dielectric that is
suitable for switching power supply output capacitors is X5R,
while X7R (or better) is preferred. Careful attention must be
paid to the DC voltage rating and case size, as ceramic ca-
pacitors can lose 60%+ of their rated capacitance at the
maximum DC voltage. For example, the typical loss in ca-
pacitance for a 1.0 µF, 50V, 1206-size capacitor is 50% at
30V. This is the reason that ceramic capacitors are often de-
rated to 50% of their capacitance at their working voltage.
For this example, no specific load transient is given, hence
ISTEP is set equal to the maximum load current of 180 mA. The
desired ΔVIN is 4%P-P. ΔVIN and duty cycle are taken at min-
imum input voltage to give the worst-case value:
The ESR of the selected capacitor has a typical value of 3
mΩ. The worst-case value for ΔVO1 occurs during the peak
current at minimum input voltage:
ΔVO1 = 1.26 x 0.003 = 3.8 mV
ESRMIN = [(1 – 0.72) x 0.36] / 0.36 = 0.28Ω
The worst-case capacitor charging ripple occurs at maximum
duty cycle, taking into account an output capacitance of 50%
x 1 µF = 500 nF:
The minimum input capacitance can be selected based on
ΔVIN, based on the drop in VIN during a load transient, or
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14
based on prevention of power supply interaction. In general,
the requirement for greatest capacitance comes from the
power supply interaction. The inductance and resistance of
the input source must be estimated, and if this information is
not available, they can be assumed to be 1 µH and 0.1Ω, re-
spectively. Minimum capacitance is then estimated as:
the sensed current exceeds the peak current rating of the in-
ductor.
For this example the inductor peak current rating is 0.9A. The
threshold for current limit, ILIM, is set slightly below to account
for tolerance of the circuit components, at a level of 0.8A. The
required resistor calculation must take into account both the
switch current through RSNS and the compensation ramp cur-
rent flowing through the internal 2 kΩ and external 100Ω
resistors:
As with ESR, the worst-case, highest minimum capacitance
calculation comes at the minimum input voltage. Using the
default estimates for LS and RS, minimum capacitance is:
RSNS = [0.5 - 45µ x (2000 + 100)] / 0.8 = 0.51Ω
Power dissipation in RSNS can be estimated by calculating the
average current. The worst-case average current through
RSNS occurs at minimum input voltage/maximum duty cycle
and can be calculated as:
The closest standard 20% capacitor value is 1.5 µF, but be-
cause the actual input source impedance and resistance are
not known, a 3.3 µF capacitor will be used. In general, dou-
bling the calculated value of input capacitance provides a
good safety margin. The final calculation is for the RMS cur-
rent. For boost converters operating in CCM this can be
estimated as:
PCS = [(0.18 / 0.27)2 x 0.51] x 0.73 = 0.16W
IRMS = 0.29 x ΔiL(MAX)
For this example a 0.51Ω ±1%, thick-film chip resistor in a
1206 case size rated to 0.33W will be used.
From the inductor section, maximum inductor ripple current is
267 mA, hence the input capacitor(s) must be rated to handle
0.29 x 0.267 = 77 mARMS
.
CONTROL LOOP COMPENSATION
The input capacitors can be ceramic, tantalum, aluminum, or
almost any type, however the low capacitance requirement
makes ceramic capacitors particularly attractive. As with the
output capacitors, the minimum quality dielectric used should
X5R, with X7R or better preferred. The voltage rating for input
capacitors need not be as conservative as the output capac-
itors, as the need for capacitance decreases as input voltage
increases. For this example, the capacitor selected will be 3.3
µF ±20%, rated to 25V, in a 1206 case size. The RMS current
rating is over 1A, more than enough for this application.
The LM3430 uses peak current-mode PWM control to correct
changes in output voltage due to line and load transients.
Peak current-mode provides inherent cycle-by-cycle current
limiting, improved line transient response, and easier control
loop compensation.
The control loop is comprised of two parts. The first is the
power stage, which consists of the pulse width modulator,
output filter, and the load. The second part is the error ampli-
fier, which is an op-amp configured as an inverting amplifier.
Figure 7 shows the regulator control loop components.
CURRENT SENSE FILTER
Parasitic circuit capacitance, inductance and gate drive cur-
rent create a spike in the current sense voltage at the point
where Q1 turns on. In order to prevent this spike from termi-
nating the on-time prematurely, every circuit should have a
low-pass filter that consists of CCS and RS1, shown in Figure
1. The time constant of this filter should be long enough to
reduce the parasitic spike without significantly affecting the
shape of the actual current sense voltage. The recommended
range for RS1 is between 10Ω and 500Ω, and the recom-
mended range for CCS is between 100 pF and 2.2 nF. For this
example, the values of RS1 and CCS will be 100Ω and 1 nF,
respectively.
RSNS AND CURRENT LIMIT
The current sensing resistor RSNS is used for steady state
regulation of the inductor current and to sense over-current
conditions. The resistance value selected must be low
enough to keep the power dissipation to a minimum, yet high
enough to provide good signal-to-noise ratio for the current
sensing circuitry. The resistance should be set so that the
current limit comparator, with a threshold of 0.5V, trips before
20209634
FIGURE 7. Power Stage and Error Amp
15
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One popular method for selecting the compensation compo-
nents is to create Bode plots of gain and phase for the power
stage and error amplifier. Combined, they make the overall
bandwidth and phase margin of the regulator easy to deter-
mine. Software tools such as Excel, MathCAD, and Matlab
are useful for observing how changes in compensation or the
power stage affect system gain and phase.
Sn = RSNS x VIN / L
The external ramp slope is:
Se = 45 µA x (2000 + RS1 + RS2)] x fSW
The power stage in a CCM peak current mode boost con-
verter consists of the DC gain, APS, a single low frequency
In the equation for APS, DC gain is highest when input voltage
is at the maximum and output current is at the lower threshold
of CCM operation. (IL = 0.5 x ΔiL) In this the example those
conditions are VIN = 20.9V and IO = 180 mA.
pole, fLFP, the ESR zero, fZESR, a right-half plane zero, fRHP
,
and a double pole resulting from the sampling of the peak
current. The power stage transfer function (also called the
Control-to-Output transfer function) can be written:
Maximum DC gain is 44 dB. The low frequency pole fP
=
2πωP is at 1.9 kHz, the ESR zero fZ = 2πωZ is at 80 MHz, and
the right-half plane zero fRHP = 2πωRHP is at 230 kHz. The
sampling double-pole occurs at one-half of the switching fre-
quency. Gain and phase plots for the power stage are shown
in Figure 8.
Where the DC gain is defined as:
Where:
RO = VO / IO
The system ESR zero is:
The low frequency pole is:
The right-half plane zero is:
The sampling double pole quality factor is:
20209641
The sampling double corner frequency is:
ωn = π x fSW
FIGURE 8. Power Stage Gain and Phase
The single pole causes a roll-off in the gain of -20 dB/decade
at lower frequency, which then flattens out due to the RHP
zero. The sharp drop in gain beginning around 200 kHz is a
result of the sampling double pole. The phase tends towards
-90° at lower frequency but then increases to -180° from the
The natural inductor current slope is:
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16
RHP zero and the sampling double pole. The effect of the
ESR zero is not seen because its frequency is several
decades above the switching frequency. The combination of
increasing gain and decreasing phase makes converters with
RHP zeroes difficult to compensate. Setting the overall con-
trol loop bandwidth to 1/3 to 1/10 of the RHP zero frequency
minimizes these negative effects. If this loop were left un-
compensated, the bandwidth would be 312 kHz and the
phase margin -100°. The converter would oscillate, and there-
fore is compensated using the error amplifier and a few
passive components.
For this example, C1 = 401 pF
10. Plug the closest 1% tolerance values for RFB2 and
R1, then the closest 10% values for C1 and C2 into
GEA and model the error amp: The open-loop gain and
bandwidth of the LM3430’s internal error amplifier are 75
dB and 4 MHz, respectively. Their effect on GEA can be
modeled using the following expression:
The transfer function of the compensation block, GEA, can be
derived by treating the error amplifier as an inverting op-amp
with input impedance ZI and feedback impedance ZF. The
majority of applications will require a Type II, or two-pole one-
zero amplifier, shown in Figure 7. The LaPlace domain trans-
fer function for this Type II network is given by the following:
ADC is a linear gain, the linear equivalent of 75 dB is
approximately 5600V/V. C1 = 390 pF 10%, C2 = 39 nF
10%, R1 = 2 kΩ 1%
11. Plot or evaluate the actual error amplifier transfer
function:
Many techniques exist for selecting the compensation com-
ponent values. The following method is based upon setting
the mid-band gain of the error amplifier transfer function first
and then positioning the compensation zero and pole:
1. Determine the desired control loop bandwidth: The
control loop bandwidth, f0dB, is the point at which the total
control loop gain (H = GPS x GEA) is equal to 0 dB. For
this example, a low bandwidth of 30 kHz, or
approximately 1/8th of the RHP zero frequency, is
chosen because of the wide variation in input voltage.
2. Determine the gain of the power stage at f0dB: This
value, A, can be read graphically from the gain plot of
GPS or calculated by replacing the ‘s’ terms in GPS with
‘2πf0dB’. For this example the gain at 30 kHz is
approximately 20 dB.
3. Calculate the negative of A and convert it to a linear
gain: By setting the mid-band gain of the error amplifier
to the negative of the power stage gain at f0dB, the control
loop gain will equal 0 dB at that frequency. For this
example, -20 dB = 0.1V/V.
4. Select the resistance of the top feedback divider
resistor RFB2: This value is arbitrary, however selecting
a resistance between 10 kΩ and 100 kΩ will lead to
practical values of R1, C1 and C2. For this example,
RFB2 = 20 kΩ 1%.
5. Set R1 = A x RFB2: For this example: R1 = 0.1 x 20000
= 2 kΩ
6. Select a frequency for the compensation zero, fZ1
:
The suggested placement for this zero is at the low
frequency pole of the power stage, fLFP = ωLFP / 2π. For
this example, fZ1 = fLFP = 1.9 kHz
7. Set
For this example, C2 = 41.2 nF
8. Select a frequency for the compensation pole, fP1:
The suggested placement for this pole is at one-half of
the switching frequency. For this example, fP1 = 200 kHz
9. Set
17
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20209648
20209649
FIGURE 9. Error Amplifier Gain and Phase
FIGURE 10. Overall Loop Gain and Phase
12. Plot or evaluate the complete control loop transfer
function: The complete control loop transfer function is ob-
tained by multiplying the power stage and error amplifier
functions together. The bandwidth and phase margin can
then be read graphically or evaluated numerically.
The bandwidth of this example circuit is 34 kHz, with a phase
margin of 60°.
Efficiency Calculations
A reasonable estimation for the efficiency of a boost regulator
controlled by the LM3430 can be obtained by adding together
the loss is each current carrying element and using the equa-
tion:
The following shows an efficiency calculation to complement
the circuit design from the Design Considerations section.
Output power for this circuit is 33V x 0.18A = 5.9W. Input
voltage is assumed to be 12V, and the calculations used as-
sume that the converter runs in CCM. Duty cycle for VIN = 12V
is 63%, and the average inductor current is 0.49A.
CHIP OPERATING LOSS
This term accounts for the current drawn at the VIN pin. This
current, IIN, drives the logic circuitry and the power MOSFETs.
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18
The gate driving loss term from the power MOSFET section
of Design Considerations is included in the chip operating
loss. For the LM3430, IIN is equal to the steady state operating
current, ICC, plus the MOSFET driving current, IGC. Power is
lost as this current passes through the internal linear regulator
of the LM3430.
Layout Considerations
To produce an optimal power solution with the LM3430, good
layout and design of the PCB are as important as the com-
ponent selection. The following are several guidelines to aid
in creating a good layout.
FILTER CAPACITORS
IGC = QG X fSW
The low-value ceramic filter capacitors are most effective
when the inductance of the current loops that they filter is
minimized. Place CINX as close as possible to the VIN and
GND pins of the LM3430. Place COX close to the load. CCS
should be placed right next to RSNS, and CF next to the VCC
and GND pins of the LM3430.
IGC = 18 nC x 600 kHz = 11 mA
ICC is typically 3.5 mA, taken from the Electrical Characteris-
tics table. Chip Operating Loss is then:
PQ = VIN X (IQ + IGC
)
PQ = 12 X (3.5m + 11m) = 0.17W
MOSFET SWITCHING LOSS
PSW = 0.5 x VIN x IL x (tR + tF) x fSW
PSW = 0.5 x 12 x 0.49 x (10 ns + 12 ns) x 6 x105 = 39 mW
MOSFET AND RSNS CONDUCTION LOSS
PC = D x (I2L x (RDSON x 1.3 + RSNS))
PC = 0.63 x (0.492 x (0.029 + 0.51) = 82 mW
INPUT CAPACITOR LOSS
This term represents the loss as input ripple current passes
through the ESR of the input capacitor bank. In this equation
‘n’ is the number of capacitors in parallel. The 3.3 µF input
capacitor selected has an ESR of approximately 3 mΩ, and
ΔiL for a 12V input is 268 mA:
IIN-RMS = 0.29 x ΔiL = 0.29 x 0.268 = 0.08A
PCIN = 0.082 x 0.003 = 0.3 mW (negligible)
OUTPUT CAPACITOR LOSS
This term is calculated using the same method as the input
capacitor loss, substituting the output capacitor RMS current
for VIN = 12V:
IO-RMS = 1.13 x 0.49 x (0.37 x 0.63)0.5 = 0.267A
PCO = 0.267 x 0.003 = 1 mW
BOOST INDUCTOR LOSS
PDCR = IL2 x DCR
PDCR = 0.492 x 0.18 = 43 mW
Core loss in the inductor is assumed to be equal to the DCR
loss, adding an additional 43 mW to the total inductor loss.
TOTAL LOSS
PLOSS = Sum of All Loss Terms = 0.38W
EFFICIENCY
η = 5.9/(5.9 + 0.38) = 94%
19
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SENSE LINES
COMPACT LAYOUT
The top of RSNS should be connected to the CS pin with a
separate trace made as short as possible. Route this trace
away from the inductor and the switch node (where D1, Q1,
and L1 connect). For the voltage loop, keep RFB1/2 close to
the LM3430 and run a trace from as close as possible to the
positive side of COX to RFB2. As with the CS line, the FB line
should be routed away from the inductor and the switch node.
These measures minimize the length of high impedance lines
and reduce noise pickup.
Parasitic inductance can be reduced by keeping the power
path components close together and keeping the area of the
loops that high currents travel small. Short, thick traces or
copper pours (shapes) are best. In particular, the switch node
should be just large enough to connect all the components
together without excessive heating from the current it carries.
The LM3430 (boost converter) operates in two distinct cycles
whose high current paths are shown in Figure 11:
20209652
FIGURE 11. Boost Converter Current Loops
The dark grey, inner loops represents the high current paths
during the MOSFET on-time. The light grey, outer loop rep-
resents the high current path during the off-time.
less risk of injecting noise into other circuits. The path be-
tween the input source, input capacitor and the power switch
and the path between the output capacitor and the load are
examples of continuous current paths. In contrast, the path
between the grounded side of the power switch and the neg-
ative output capacitor terminal carries a large pulsating cur-
rent. This path should be routed with a short, thick shape,
preferably on the component side of the PCB. Multiple vias in
parallel should be used right at the negative pads of the input
and output capacitors to connect the component side shapes
to the ground plane. Vias should not be placed directly at the
grounded side of the power switch (or RSNS) as they tend to
inject noise into the ground plane. A second pulsating current
loop that is often ignored but must be kept small is the gate
drive loop formed by the OUT and VCC pins, Q1, RSNS and
capacitor CF.
GROUND PLANE AND SHAPE ROUTING
The diagram of Figure 11 is also useful for analyzing the flow
of continuous current vs. the flow of pulsating currents. The
circuit paths with current flow during both the on-time and off-
time are considered to be continuous current, while those that
carry current during the on-time or off-time only are pulsating
currents. Preference in routing should be given to the pulsat-
ing current paths, as these are the portions of the circuit most
likely to emit EMI. The ground plane of a PCB is a conductor
and return path, and it is susceptible to noise injection just as
any other circuit path. The continuous current paths on the
ground net can be routed on the system ground plane with
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20
BOM for Example Circuit
ID
U1
Q1
D1
L1
Part Number
LM3430
Type
Low-Side Controller
MOSFET
Size
LLP-12
Parameters
Qty
1
Vendor
NSC
Si4850EY
CMHSH5-4
SO-8
1
Vishay
60V, 31mΩ, 18nC
40V, 0.5A
Schottky Diode
Inductor
SOD-123
7.0 x7.0 x 4.5mm
1
Central Semi
TDK
SLF7045T-470M90-1P
F
1
47µH, 0.9A, 180mΩ
Cin
Co
Cf
C3216X7R1E335M
C3216X7R1H105M
C2012X7R1E105K
VJ0805Y104KXXAT
Capacitor
Capacitor
Capacitor
Capacitor
1206
1206
0805
0805
1
1
1
1
TDK
TDK
3.3µF, 25V, 3mΩ
1µF, 50V, 3mΩ
1µF, 25V
TDK
Cinx
Cox
100nF 10%
Vishay
C1
C2
VJ0805A391KXXAT
VJ0805Y393KXXAT
VJ0805Y103KXXAT
VJ0805Y102KXXAT
CRCW08052001F
CRCW08057870F
CRCW08052002F
CRCW0805101J
Capacitor
Capacitor
Capacitor
Capacitor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
0805
0805
0805
0805
0805
0805
0805
0805
1206
0805
0805
390pF 10%
39nF 10%
10nF 10%
1nF 10%
1
1
1
1
1
1
1
1
1
1
2
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Panasonic
Vishay
Vishay
Css
Ccs
R1
2kΩ 1%
Rfb1
Rfb2
Rs1
787Ω 1%
20kΩ 1%
100Ω 5%
Rsns
Rt
ERJ8BQFR51V
0.51Ω 1%, 0.33W
27.4kΩ 1%
10kΩ 1%
CRCW08052742F
CRCW08051002F
Ruv1 Ruv2
21
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Physical Dimensions inches (millimeters) unless otherwise noted
12-Lead LLP Package
NS Package Number SDF12A
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22
Notes
23
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