LM3677LEX-1.82 [NSC]
3MHz, 600mA Miniature Step-Down DC-DC Converter for Ultra Low Voltage Circuits; 3MHz的， 600毫安微型降压型DC -DC转换器，用于超低电压电路
| 型号： | LM3677LEX-1.82 |
| 厂家： | 
National Semiconductor |
| 描述： | 3MHz, 600mA Miniature Step-Down DC-DC Converter for Ultra Low Voltage Circuits |
| 文件： | 总22页 (文件大小：8119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 28, 2008
LM3677
3MHz, 600mA Miniature Step-Down DC-DC Converter for
Ultra Low Voltage Circuits
General Description
The LM3677 step-down DC-DC converter is optimized for
powering ultra-low voltage circuits from a single Li-Ion cell
battery and input voltage rails from 2.7V to 5.5V. It provides
up to 600 mA load current over the entire input voltage range.
The LM3677 is configured to different fixed voltage output
options as well as an adjustable output voltage version range
from 1.2V to 3.3V.
Features
16 µA typical quiescent current
■
■
■
■
600 mA maximum load capability
3 MHz PWM fixed switching frequency (typ.)
Automatic PFM/PWM mode switching
Available in 5-bump micro SMD package and 6-pin LLP
■
package
Internal synchronous rectification for high efficiency
■
■
■
■
The device offers superior features and performance for mo-
bile phones and similar portable applications with complex
power management systems. Automatic intelligent switching
between PWM low-noise and PFM low-current mode offers
improved system control. During PWM mode operation, the
device operates at a fixed frequency of 3 MHz (typ). PWM
mode drives loads from ~ 80 mA to 600 mA max. Hysteretic
PFM mode extends the battery life by reducing the quiescent
current to 16 µA (typ.) during light load and standby operation.
Internal synchronous rectification provides high efficiency. In
shutdown mode (Enable pin pulled down), the device turns
off and reduces battery consumption to 0.01 µA (typ.).
Internal soft start
0.01 µA typical shutdown current
Operates from a single Li-Ion cell battery
Only three tiny surface-mount external components
required (solution size less than 20 mm2)
Current overload and thermal shutdown protection
■
■
Applications
Mobile Phones
■
■
■
■
■
■
■
PDAs
The LM3677 is available in a lead-free (NOPB) 5-bump micro
SMD package and 6-pin LLP package. A switching frequency
of 3 MHz (typ.) allows use of tiny surface-mount components.
Only three external surface-mount components, an inductor
and two ceramic capacitors, are required.
MP3 Players
W-LAN
Portable Instruments
Digital Still Cameras
Portable Hard Disk Drives
Typical Application Circuit
Efficiency vs. Output Current
(VOUT = 1.8V)
30008401
FIGURE 1. Typical Application Circuit
30008487
© 2008 National Semiconductor Corporation
300084
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Connection Diagram and Package Mark Information
5-Bump micro SMD Package
NS Package Number TLA05FEA
30008444
FIGURE 2. 5 Bump Micro SMD Package
30008400
FIGURE 3. 6 Pin LLP Package
Pin Descriptions
Pin #
Name
VIN
Description
A1
A3
C1
1
6
3
Power supply input. Connect to the input filter capacitor (Figure 1).
GND
EN
Ground pin.
Enable pin. The device is in shutdown mode when voltage to this pin is < 0.4V and
enabled when > 1.0V. Do not leave this pin floating.
C3
B2
4
FB
Feedback analog input. Connect directly to the output filter capacitor ( FIGURE 1).
2, 5
SW
Switching node connection to the internal PFET switch and NFET synchronous
rectifier.
Ordering Information
Order Number
LM3677TL-1.2 (Note 1)
LM3677TLX-1.2 (Note 1)
LM3677TL-1.3
Spec
Package Marking
Supplied As
250 units, Tape-and-Reel
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
3
3000 units, Tape-and-Reel
250 units, Tape-and-Reel
3000 units, Tape-and-Reel
250 units, Tape-and-Reel
3000 units, Tape-and-Reel
V
X
LM3677TLX-1.3
LM3677TL-1.5
LM3677TLX-1.5
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2
Order Number
LM3677TL-1.8
Spec
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
Package Marking
Supplied As
250 units, Tape-and-Reel
Y
LM3677TLX-1.8
LM3677TL-1.875
LM3677TLX-1.875
LM3677TL-2.5
3000 units, Tape-and-Reel
250 units, Tape-and-Reel
3000 units, Tape-and-Reel
250 units, Tape-and-Reel
3000 units, Tape-and-Reel
250 units, Tape-and-Reel
3000 units, Tape-and-Reel
250 units, Tape-and-Reel
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
250 units, Tape-and-Reel
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
250 units, Tape-and-Reel
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
250 units, Tape-and-Reel
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
9
Z
4
LM3677TLX-2.5
LM3677TL-ADJ
LM3677TLX-ADJ
LM3677LEE-1.2
LM3677LE-1.2
K
L
LM3677LEX-1.2
LM3677LEE-1.5
LM3677LE-1.5
LM3677LEX-1.5
LM3677LEE-1.8
LM3677LE-1.8
N
5
LM3677LEX-1.8
LM3677LEE-1.82
LM3677LE-1.82
LM3677LEX-1.82
Note 1: For output voltage 1.2V or lower, input voltage needs to be derated to the range of 2.7V to 5.0V in order to perform within specification.
3
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ESD Rating (Note 5)
Human Body Model: All Pins
Machine Model: All Pins
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
2.0 kV
200V
Operating Ratings (Note 2), (Note 3)
If Military/Aerospace specified devices are required, please
contact the National Semiconductor Sales Office/Distributor
for availability and specifications.
Input Voltage Range
2.7V to 5.5V
0 mA to 600 mA
−30°C to +125°C
Recommended Load Current
Junction Temperature (TJ) Range
VIN Pin: Voltage to GND
FB, SW, EN Pin:
−0.2V to 6.0V
(GND−0.2V) to
(VIN + 0.2V)
Ambient Temperature (TA) Range (Note −30°C to +85°C
6)
Continuous Power Dissipation
(Note 4)
Internally Limited
Thermal Properties
Junction-to-Ambient Thermal
Junction Temperature (TJ-MAX
Storage Temperature Range
)
+125°C
−65°C to +150°C
260°C
85°C/W
Resistance (θJA) (Note 7)
Maximum Lead Temperature
(Soldering, 10 sec.)
Electrical Characteristics (Note 3), (Note 9), (Note 10) Limits in standard typeface are for TJ = TA = 25°C.
Limits in boldface type apply over the operating ambient temperature range (−30°C ≤ TA ≤ +85°C). Unless otherwise noted,
specifications apply to the LM3677 with VIN = EN = 3.6V.
Symbol
VIN
Parameter
Input Voltage (Note 11)
Feedback Voltage (TL)
Feedback Voltage (LE)
Internal Reference Voltage
Shutdown Supply Current
DC Bias Current into VIN
Pin-Pin Resistance for PFET
Pin-Pin Resistance for NFET
Switch Peak Current Limit
Logic High Input
Condition
Min
2.7
Typ
Max
5.5
Units
V
-2.5
-4.0
+2.5
+4.0
VFB
PWM mode
%
VREF
ISHDN
IQ
0.5
0.01
16
V
EN = 0V
1
µA
µA
No load, device is not switching
VIN= VGS= 3.6V, ISW= 100mA
VIN= VGS= 3.6V, ISW= -100mA
Open Loop(Note 8)
35
RDSON (P)
RDSON (N)
ILIM
350
150
1220
450
250
1375
mΩ
mΩ
mA
V
1085
1.0
VIH
VIL
Logic Low Input
0.4
1
V
IEN
Enable (EN) Input Current
Internal Oscillator Frequency
0.01
3
µA
FOSC
PWM Mode
2.5
3.5
MHz
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 3: All voltages are with respect to the potential at the GND pin.
Note 4: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 150°C (typ.) and disengages at
TJ= 130°C (typ.).
Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin. MIL-STD-883 3015.7
Note 6: In Applications where high power dissipation and/or poor package resistance is present, the maximum ambient temperature may have to be derated.
Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX), the maximum power dissipation of the device in
the application (PD-MAX) and the junction to ambient thermal resistance of the package (θJA) in the application, as given by the following equation: TA-MAX= TJ-MAX
− (θJAx PD-MAX). Refer to Dissipation rating table for PD-MAX values at different ambient temperatures.
Note 7: Junction to ambient thermal resistance is highly application and board layout dependent. In applications where high power dissipation exists, special care
must be given to thermal dissipation issues in board design. Value specified here 85 °C/W is based on measurement results using a 4 layer board as per JEDEC
standards.
Note 8: Refer to datasheet curves for closed loop data and its variation with regards to supply voltage and temperature. Electrical Characteristic table reflects
open loop data (FB=0V and current drawn from SW pin ramped up until cycle by cycle current limit is activated). Closed loop current limit is the peak inductor
current measured in the application circuit by increasing output current until output voltage drops by 10%.
Note 9: Min and Max limits are guaranteed by design, test or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 10: The parameters in the electrical characteristic table are tested under open loop conditions at VIN= 3.6V unless otherwise specified. For performance
over the input voltage range and closed loop condition, refer to the datasheet curves.
Note 11: For output voltage 1.2V or lower, input voltage needs to be derated to the range of 2.7V to 5.0V in order to perform within specification.
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Dissipation Rating Table
TA= 60°C
TA= 85°C
θJA
TA≤ 25°C
Power Rating
1178 mW
Power Rating
Power Rating
85°C/W (4-layer board)
micro SMD
785 mW
470 mW
117°C/W (4-layer board)
LLP
855 mW
556 mW
342 mW
5
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Block Diagram
30008418
FIGURE 4. Simplified Functional Diagram
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Typical Performance Characteristics
LM3677, Circuit of Figure 1, VIN = 3.6V, VOUT = 1.8V, TA = 25°C, unless otherwise noted.
Quiescent Supply Current vs. Supply Voltage
(Switching)
Shutdown Current vs. Temp
30008482
30008481
Switching Frequency vs. Temperature
RDS(ON) vs. Temperature
30008483
30008451
Open/Closed Loop Current Limit
vs. Temperature
Output Voltage vs. Supply Voltage
(VOUT = 1.8V)
30008449
30008484
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Output Voltage vs. Supply Voltage
(VOUT = 2.5V)
Output Voltage vs. Temperature
(VOUT = 1.3V)
30008438
30008468
Output Voltage vs. Temperature
(VOUT = 1.8V)
Output Voltage vs. Temperature
(VOUT = 2.5V)
30008485
30008469
Output Voltage vs. Output Current
(VOUT = 1.8V)
Output Voltage vs. Output Current
(VOUT = 2.5V)
30008486
30008437
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Efficiency vs. Output Current
(VOUT = 1.3V)
Efficiency vs. Output Current
(VOUT = 1.8V)
30008441
30008487
Efficiency vs. Output Current
(VOUT = 2.5V)
Output Current vs. Input Voltage at Mode Change Point
(VOUT = 1.3V)
30008432
30008435
Output Current vs. Input Voltage at Mode Change Point
(VOUT = 1.8V)
Output Current vs. Input Voltage at Mode Change Point
(VOUT = 2.5V)
30008488
30008436
9
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Line Transient Response
VOUT = 1.3V (PWM Mode)
Line Transient Response
VOUT = 1.8V (PWM Mode)
30008477
30008433
Line Transient Response
VOUT = 1.8V (PWM Mode)
Line Transient Response
VOUT = 2.5V (PWM Mode)
30008478
30008439
Load Transient Response (VOUT = 1.3V)
(PFM Mode 1mA to 50mA)
Load Transient Response (VOUT = 1.3V)
(PFM Mode 50mA to 1mA)
30008493
30008494
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Load Transient Response (VOUT = 1.8V)
(PFM Mode 1mA to 50mA)
Load Transient Response (VOUT = 1.8V)
(PFM Mode 50mA to 1mA)
30008473
30008474
Load Transient Response (VOUT = 2.5V)
(PFM Mode 1mA to 50mA)
Load Transient Response (VOUT = 2.5V)
(PFM Mode 50mA to 1mA)
30008498
30008430
Mode Change by Load Transients
VOUT = 1.3V (PFM to PWM)
Mode Change by Load Transients
VOUT = 1.3V (PWM to PFM)
30008495
30008496
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Mode Change by Load Transients
VOUT = 1.8V (PFM to PWM)
Mode Change by Load Transients
VOUT = 1.8V (PWM to PFM)
30008475
30008476
Load Transient Response
VOUT = 1.3V (PWM Mode)
Load Transient Response
VOUT = 1.8V (PWM Mode)
30008472
30008497
Load Transient Response
VOUT = 2.5V (PWM Mode)
Start Up into PWM Mode
VOUT = 1.3V (Output Current= 300mA)
30008431
30008491
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Start Up into PFM Mode
VOUT = 1.3V (Output Current= 1mA)
Start Up into PWM Mode
VOUT = 1.8V (Output Current= 300mA)
30008470
30008492
Start Up into PFM Mode
VOUT = 1.8V (Output Current= 1mA)
Start Up into PWM Mode
VOUT = 2.5V (Output Current= 300mA)
30008471
30008489
Start Up into PFM Mode
VOUT = 2.5V (Output Current= 1mA)
30008490
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control logic turns off the switch. The current limit comparator
can also turn off the switch in case the current limit of the
PFET is exceeded. Then the NFET switch is turned on and
the inductor current ramps down. The next cycle is initiated
by the clock turning off the NFET and turning on the PFET.
Operation Description
DEVICE INFORMATION
The LM3677, a high-efficiency step-down DC-DC switching
buck converter, delivers a constant voltage from a single Li-
Ion battery and input voltage rails from 2.7V to 5.5V to devices
such as cell phones and PDAs. Using a voltage-mode archi-
tecture with synchronous rectification, the LM3677 has the
ability to deliver up to 600 mA depending on the input voltage
and output voltage, ambient temperature, and the inductor
chosen.
There are three modes of operation depending on the current
required: PWM (Pulse Width Modulation), PFM (Pulse Fre-
quency Modulation), and shutdown. The device operates in
PWM mode at load current of approximately 80 mA or higher,
having a voltage precision of ±2.5% with 90% efficiency or
better. Lighter load current causes the device to automatically
switch into PFM mode for reduced current consumption (IQ
=
16 µA typ.) and a longer battery life. Shutdown mode turns off
the device, offering the lowest current consumption
(ISHUTDOWN = 0.01 µA (typ.).
30008480
Additional features include soft-start, under voltage protec-
tion, current overload protection, and thermal shutdown pro-
tection. As shown in Figure 1, only three external power
components are required for implementation.
FIGURE 5. Typical PWM Operation
Internal Synchronous Rectification
The part uses an internal reference voltage of 0.5V. It is rec-
ommended to keep the part in shutdown until the input voltage
exceeds 2.7V.
While in PWM mode, the LM3677 uses an internal NFET as
a synchronous rectifier to reduce rectifier forward voltage
drop and associated power loss. Synchronous rectification
provides a significant improvement in efficiency whenever the
output voltage is relatively low compared to the voltage drop
across an ordinary rectifier diode.
CIRCUIT OPERATION
The LM3677 operates as follows. During the first portion of
each switching cycle, the control block in the LM3677 turns
on the internal PFET switch. This allows current to flow from
the input through the inductor to the output filter capacitor and
load. The inductor limits the current to a ramp with a slope of
(VIN–VOUT)/L, by storing energy in a magnetic field.
Current Limiting
A current limit feature allows the LM3677 to protect itself and
external components during overload conditions. PWM mode
implements current limiting using an internal comparator that
trips at 1220 mA (typ.). If the output is shorted to ground the
device enters a timed current limit mode where the NFET is
turned on for a longer duration until the inductor current falls
below a low threshold, ensuring inductor current has more
time to decay, thereby preventing runaway.
During the second portion of each cycle, the controller turns
the PFET switch off, blocking current flow from the input, and
then turns the NFET synchronous rectifier on. The inductor
draws current from ground through the NFET to the output
filter capacitor and load, which ramps the inductor current
down with a slope of - VOUT/L.
PFM OPERATION
The output filter stores charge when the inductor current is
high, and releases it when inductor current is low, smoothing
the voltage across the load.
At very light loads, the converter enters PFM mode and op-
erates with reduced switching frequency and supply current
to maintain high efficiency.
The output voltage is regulated by modulating the PFET
switch-on time to control the average current sent to the load.
The effect is identical to sending a duty-cycle modulated rect-
angular wave formed by the switch and synchronous rectifier
at the SW pin to a low-pass filter formed by the inductor and
output filter capacitor. The output voltage is equal to the av-
erage voltage at the SW pin.
The part will automatically transition into PFM mode when ei-
ther of the following conditions occurs for a duration of 32 or
more clock cycles:
A.ꢀThe NFET current reaches zero.
B.ꢀThe peak PMOS switch current drops below the IMODE
level, (Typically IMODE < 75 mA + VIN/55Ω ).
PWM OPERATION
During PWM operation, the converter operates as a voltage-
mode controller with input voltage feed forward. This allows
the converter to achieve good load and line regulation. The
DC gain of the power stage is proportional to the input voltage.
To eliminate this dependence, feed forward inversely propor-
tional to the input voltage is introduced.
While in PWM mode, the output voltage is regulated by
switching at a constant frequency and then modulating the
energy per cycle to control power to the load. At the beginning
of each clock cycle the PFET switch is turned on and the in-
ductor current ramps up until the comparator trips and the
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14
is turned on. It remains on until the output voltage reaches the
‘high’ PFM threshold or the peak current exceeds the IPFM
level set for PFM mode. The typical peak current in PFM mode
is: IPFM = 112 mA + VIN/20Ω .
Once the PMOS power switch is turned off, the NMOS power
switch is turned on until the inductor current ramps to zero.
When the NMOS zero-current condition is detected, the
NMOS power switch is turned off. If the output voltage is be-
low the ‘high’ PFM comparator threshold (see Figure 7), the
PMOS switch is again turned on and the cycle is repeated
until the output reaches the desired level. Once the output
reaches the ‘high’ PFM threshold, the NMOS switch is turned
on briefly to ramp the inductor current to zero, and then both
output switches are turned off and the part enters an ex-
tremely low-power mode. Quiescent supply current during
this ‘sleep’ mode is 16 µA (typ.), which allows the part to
achieve high efficiencies under extremely light load condi-
tions.
30008479
FIGURE 6. Typical PFM Operation
If the load current should increase during PFM mode (Figure
7) causing the output voltage to fall below the ‘low2’ PFM
threshold, the part will automatically transition into fixed-fre-
quency PWM mode. When VIN =2.7V the part transitions from
PWM to PFM mode at ~ 35 mA output current and from PFM
to PWM mode at ~ 95 mA , when VIN=3.6V, PWM to PFM
transition occurs at ~ 42 mA and PFM to PWM transition oc-
curs at ~ 115 mA, when VIN =4.5V, PWM to PFM transition
occurs at ~ 60 mA and PFM to PWM transition occurs at ~
135 mA.
During PFM operation, the converter positions the output volt-
age slightly higher than the nominal output voltage during
PWM operation allowing additional headroom for voltage
drop during a load transient from light to heavy load. The PFM
comparators sense the output voltage via the feedback pin
and control the switching of the output FETs such that the
output voltage ramps between ~0.2% and ~1.8% above the
nominal PWM output voltage. If the output voltage is below
the ‘high’ PFM comparator threshold, the PMOS power switch
30008403
FIGURE 7. Operation in PFM Mode and Transfer to PWM Mode
SHUTDOWN MODE
SOFT START
Setting the EN input pin low (<0.4V) places the LM3677 in
shutdown mode. During shutdown the PFET switch, NFET
switch, reference, control and bias circuitry of the LM3677 are
turned off. Setting EN high (>1.0V) enables normal operation.
It is recommended to set EN pin low to turn off the LM3677
during system power up and undervoltage conditions when
the supply is less than 2.7V. Do not leave the EN pin floating.
The LM3677 has a soft-start circuit that limits in-rush current
during start-up. During start-up the switch current limit is in-
creased in steps. Soft start is activated only if EN goes from
logic low to logic high after VIN reaches 2.7V. Soft start is im-
plemented by increasing switch current limit in steps of 200
mA, 400 mA, 600 mA and 1220 mA (typical switch current
limit). The start-up time thereby depends on the output ca-
pacitor and load current demanded at start-up. Typical start-
15
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up times with a 10 µF output capacitor and 300 mA load is
300 µs and with 1 mA load is 200 µs.
A 1.0 µH inductor with a saturation current rating of at least
1375 mA is recommended for most applications. The
inductor’s resistance should be less than 0.15Ω for good ef-
ficiency. Table 1 lists suggested inductors and suppliers. For
low-cost applications, an unshielded bobbin inductor could be
considered. For noise critical applications, a toroidal or shield-
ed-bobbin inductor should be used. A good practice is to lay
out the board with overlapping footprints of both types for de-
sign flexibility. This allows substitution of a low-noise shielded
inductor in the event that noise from low-cost bobbin models
is unacceptable.
Application Information
INDUCTOR SELECTION
There are two main considerations when choosing an induc-
tor: the inductor should not saturate, and the inductor current
ripple should be small enough to achieve the desired output
voltage ripple. Different saturation current rating specifica-
tions are followed by different manufacturers so attention
must be given to details. Saturation current ratings are typi-
cally specified at 25°C. However, ratings at the maximum
ambient temperature of application should be requested form
the manufacturer. The minimum value of inductance to
guarantee good performance is 0.7 µH at ILIM (typ.) DC
current over the ambient temperature range. Shielded in-
ductors radiate less noise and should be preferred.
INPUT CAPACITOR SELECTION
A ceramic input capacitor of 4.7 µF, 6.3V is sufficient for most
applications. Place the input capacitor as close as possible to
the VIN pin of the device. A larger value may be used for im-
proved input voltage filtering. Use X7R or X5R types; do not
use Y5V. DC bias characteristics of ceramic capacitors must
be considered when selecting case sizes like 0603 and 0805.
The minimum input capacitance to guarantee good per-
formance is 2.2 µF at 3V DC bias; 1.5 µF at 5V DC bias
including tolerances and over ambient temperature
range. The input filter capacitor supplies current to the PFET
switch of the LM3677 in the first half of each cycle and re-
duces voltage ripple imposed on the input power source. A
ceramic capacitor’s low ESR provides the best noise filtering
of the input voltage spikes due to this rapidly changing cur-
rent. Select a capacitor with sufficient ripple current rating.
The input current ripple can be calculated as:
There are two methods to choose the inductor saturation cur-
rent rating.
Method 1:
The saturation current is greater than the sum of the maxi-
mum load current and the worst case average to peak induc-
tor current. This can be written as
•
•
•
•
IRIPPLE: average to peak inductor current
IOUTMAX: maximum load current (600 mA)
VIN: maximum input voltage in application
L : min inductor value including worst case tolerances
(30% drop can be considered for method 1)
•
•
f : minimum switching frequency (2.5 MHz)
VOUT: output voltage
Method 2:
A more conservative and recommended approach is to
choose an inductor that has saturation current rating greater
than the max current limit of 1375 mA.
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TABLE 1. Suggested Inductors and Their Suppliers
Model
Vendor
FDK
Dimensions LxWxH(mm)
2.5 x 2.0 x 1.2
D.C.R (max)
100 mΩ
MIPSA2520D 1R0
LQM2HP 1R0
BRL2518T1R0M
Murata
2.5 x 2.0 x 0.95
100 mΩ
Taiyo Yuden
2.5x 1.8 x 1.2
80 mΩ
OUTPUT CAPACITOR SELECTION
Voltage peak-to-peak ripple due to ESR can be expressed as
follows
A ceramic output capacitor of 10 µF, 6.3V is sufficient for most
applications. Use X7R or X5R types; do not use Y5V. DC bias
characteristics of ceramic capacitors must be considered
when selecting case sizes like 0603 and 0805. DC bias char-
acteristics vary from manufacturer to manufacturer and dc
bias curves should be requested from them as part of the ca-
pacitor selection process.
VPP-ESR = (2 * IRIPPLE) * RESR
Because these two components are out of phase the rms (root
mean squared) value can be used to get an approximate val-
ue of peak-to-peak ripple.
Voltage peak-to-peak ripple, rms can be expressed as follow:
The minimum output capacitance to guarantee good per-
formance is 5.75 µF at 2.5V DC bias including tolerances
and over ambient temperature range. The output filter ca-
pacitor smooths out current flow from the inductor to the load,
helps maintain a steady output voltage during transient load
changes and reduces output voltage ripple. These capacitors
must be selected with sufficient capacitance and sufficiently
low ESR to perform these functions.
Note that the output voltage ripple is dependent on the induc-
tor current ripple and the equivalent series resistance of the
output capacitor (RESR).
The RESR is frequency dependent (as well as temperature
dependent); make sure the value used for calculations is at
the switching frequency of the part.
The output voltage ripple is caused by the charging and dis-
charging of the output capacitor and by the RESR and can be
calculated as:
Voltage peak-to-peak ripple due to capacitance can be ex-
pressed as follows
TABLE 2. Suggested Capacitors and Their Suppliers
Case Size
Inch (mm)
Model
4.7 µF for CIN
Type
Vendor
Voltage Rating
C1608X5R0J475
C2012X5R0J475
GRM21BR60J475
JMK212BJ475
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
TDK
TDK
6.3V
6.3V
6.3V
6.3V
0603 (1608)
0805 (2012)
0805 (2012)
0805 (2012)
muRata
Taiyo-Yuden
10 µF for COUT
C1608X5R0J106
C2012X5R0J106
GRM21BR60J106
JMK212BJ106
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
TDK
TDK
6.3V
6.3V
6.3V
6.3V
0603 (1608)
0805 (2012)
0805 (2012)
0805 (2012)
muRata
Taiyo-Yuden
MICRO SMD PACKAGE ASSEMBLY AND USE
package used for LM3677 has 300–micron solder balls and
requires 10.82 mils pads for mounting on the circuit board.
The trace to each pad should enter the pad with a 90° entry
angle to prevent debris from being caught in deep corners.
Initially, the trace to each pad should be 7 mil wide, for a sec-
tion approximately 7 mil long or longer, as a thermal relief.
Then each trace should neck up or down to its optimal width.
The important criteria is symmetry. This ensures the solder
bumps on the LM3677 re-flow evenly and that the device sol-
ders level to the board. In particular, special attention must be
paid to the pads for bumps A1 and A3, because GND and
VIN are typically connected to large copper planes, inade-
quate thermal relief can result in late or inadequate re-flow of
these bumps.
Use of the micro SMD package requires specialized board
layout, precision mounting and careful re-flow techniques, as
detailed in National Semiconductor Application Note 1112.
Refer to the section "Surface Mount Technology (SMD) As-
sembly Considerations". For best results in assembly, align-
ment ordinals on the PC board should be used to facilitate
placement of the device. The pad style used with micro SMD
package must be the NSMD (non-solder mask defined) typ.
This means that the solder-mask opening is larger than the
pad size. This prevents a lip that otherwise forms if the solder-
mask and pad overlap, from holding the device off the surface
of the board and interfering with mounting. See Application
Note 1112 for specific instructions how to do this. The 5-bump
17
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The micro SMD package is optimized for the smallest possi-
ble size in applications with red or infrared opaque cases.
Because the micro SMD package lacks the plastic encapsu-
lation characteristic of larger devices, it is vulnerable to light.
Backside metallization and/or epoxy coating, along with front-
side shading by the printed circuit board, reduce this sensi-
tivity. However, the package has exposed die edges. In
particular, micro SMD devices are sensitive to light, in the red
and infrared range, shining on the package’s exposed die
edges.
BOARD LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter de-
sign. Poor board layout can disrupt the performance of a DC-
DC converter and surrounding circuitry by contributing to EMI,
ground bounce, and resistive voltage loss in the traces. These
can send erroneous signals to the DC-DC converter IC, re-
sulting in poor regulation or instability. Poor layout can also
result in re-flow problems leading to poor solder joints be-
tween the micro SMD package and board pads. Poor solder
joints can result in erratic or degraded performance.
30008454
FIGURE 8. Board Layout Design Rules for the LM3677
Good layout for the LM3677 can be implemented by following
a few simple design rules, as illustrated in Figure 8.
the current curls in the same direction prevents magnetic
field reversal between the two half-cycles and reduces
radiated noise.
1. Place the LM3677 on 10.82 mil pads. As a thermal relief,
connect to each pad with a 7 mil wide, approximately 7
mil long trace, and then incrementally increase each
trace to its optimal width. The important criterion is
symmetry to ensure the solder bumps on the re-flow
evenly (see Micro SMD Package Assembly and Use).
4. Connect the ground pins of the LM3677, and filter
capacitors together using generous component-side
copper fill as a pseudo-ground plane. Then connect this
to the ground-plane (if one is used) with several vias. This
reduces ground-plane noise by preventing the switching
currents from circulating through the ground plane. It also
reduces ground bounce at the LM3677 by giving it a low-
impedance ground connection.
2. Place the LM3677, inductor and filter capacitors close
together and make the traces short. The traces between
these components carry relatively high switching
5. Use wide traces between the power components and for
power connections to the DC-DC converter circuit. This
reduces voltage errors caused by resistive losses across
the traces
currents and act as antennas. Following this rule reduces
radiated noise. Special care must be given to place the
input filter capacitor very close to the VIN and GND pin.
3. Arrange the components so that the switching current
loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor,
through the LM3677 and inductor to the output filter
capacitor and back through ground, forming a current
loop. In the second half of each cycle, current is pulled
up from ground, through the LM3677 by the inductor, to
the output filter capacitor and then back through ground,
forming a second current loop. Routing these loops so
6. Route noise sensitive traces such as the voltage
feedback path away from noisy traces between the
power components. The voltage feedback trace must
remain close to the LM3677 circuit and should be routed
directly from FB to VOUT at the output capacitor and
should be routed opposite to noise components. This
reduces EMI radiated onto the DC-DC converter’s own
voltage feedback trace.
www.national.com
18
7. Place noise sensitive circuitry, such as radio IF blocks,
away from the DC-DC converter, CMOS digital blocks
and other noisy circuitry. Interference with noise-
sensitive circuitry in the system can be reduced through
distance.
CMOS digital circuitry around it (since this also generates
noise), and then place sensitive preamplifiers and IF stages
on the diagonally opposing corner. Often, the sensitive cir-
cuitry is shielded with a metal pan and power to it is post-
regulated to reduce conducted noise, using low-dropout
linear regulators.
In mobile phones, for example, a common practice is to place
the DC-DC converter on one corner of the board, arrange the
19
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Physical Dimensions inches (millimeters) unless otherwise noted
5-Bump (Large) Micro SMD Package, 0.5 mmPitch
NS Package Number TLA05FEA
The dimensions for X1, X2, and X3 are as given:
X1 = 1.107 mm +/- 0.030 mm
X2 = 1.488 mm +/- 0.030 mm
X3 = 0.600 mm +/- 0.075 mm
www.national.com
20
6-pin LLP Package, 0.5 mm Pitch
NS Package Number LEB06A
The dimensions for A, B, and C are as given:
A = 2.0 mm +/- 0.1 mm
B = 1.5 mm +/- 0.1 mm
C = 0.60 mm +/- 0.06 mm
21
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Notes
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