LM3881 [NSC]
Power Sequencer; 电源定序器
| 型号： | LM3881 |
| 厂家： | 
National Semiconductor |
| 描述： | Power Sequencer |
| 文件： | 总14页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 6, 2008
LM3881
Power Sequencer
General Description
The LM3881 Power Sequencer offers the easiest method to
control power up and power down of multiple power supplies
(switching or linear regulators). By staggering the startup se-
quence, it is possible to avoid latch conditions or large in-rush
currents that can affect the reliability of the system.
Features
Easiest method to sequence rails
■
■
■
■
■
■
■
Power up and power down control
Input voltage range of 2.7V to 5.5V
Small footprint MSOP-8 package
Low quiescent current of 80 µA
Available in MSOP-8 package, the Power Sequencer con-
tains a precision enable pin and three open drain output flags.
Upon enabling the LM3881, the three output flags will se-
quentially release, after individual time delays, permitting the
connected power supplies to startup. The output flags will fol-
low a reverse sequence during power down to avoid latch
conditions. Time delays are defined using an external capac-
itor and the output flag states can be inverted by the user.
Output invert feature
Timing controlled by small value external capacitor
Applications
Multiple Supply Sequencing
■
■
■
Microprocessor / Microcontroller Sequencing
FPGA Sequencing
Typical Application Circuit
30048401
© 2008 National Semiconductor Corporation
300484
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Connection Diagram
30048402
Top View
MSOP-8 Package
Ordering Information
Order Number
LM3881MM
Package Type
NSC Package Drawing
Supplied As
MSOP-8
MUA08A
1000 Units on Tape and Reel
3500 Units on Tape and Reel
LM3881MMX
Pin Descriptions
Pin #
Name
VCC
Function
Input Supply
1
2
3
4
5
6
7
8
EN
Precision Enable
Ground
GND
INV
Output Logic Invert
Timer Adjust
TADJ
FLAG3
FLAG2
FLAG1
Open Drain Output #3
Open Drain Output #2
Open Drain Output #1
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2
Absolute Maximum Ratings (Note 1)
Operating Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VCC to GND
2.7V to 5.5V
EN, INV, TADJ, FLAG1, FLAG2,
FLAG3 to GND
Junction Temperature
-0.3V to VCC + 0.3V
-40°C to +125°C
VCC, EN, INV, TADJ, FLAG1,
FLAG2, FLAG3 to GND
Storage Temperature Range
Junction Temperature
-0.3V to +6.0V
-65°C to +150°C
150°C
Lead Temperature (Soldering, 5
sec.)
Minimum ESD Rating (Note 2)
260°C
2 kV
Electrical Characteristics Specifications with standard typeface are for TJ = 25°C, and those in bold face type
apply over the full Operating Temperature Range (TJ = -40°C to +125°C). Minimum and Maximum limits are guaranteed through
test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for
reference purposes only. VCC = 3.3V, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(Note 3) (Note 4) (Note 3)
IQ
Open Drain Flags
IFLAG
Operating Quiescent Current
80
110
µA
FLAGx Leakage Current
VFLAGx = 3.3V
IFLAGx = 1.2 mA
0.001
1
µA
V
VOL
FLAGx Output Voltage Low
0.4
Time Delays
ITADJ_SRC
ITADJ_SNK
VHTH
TADJ Source Current
TADJ Sink Current
High Threshold Level
Low Threshold Level
Clock Cycle
4
12
12
20
20
µA
µA
V
4
1.0
0.3
1.22
0.5
1.2
1.4
0.7
VLTH
V
TCLK
CADJ = 10 nF
ms
TD1, TD4
Flag Time Delay
9
10
Clock
Cycles
TD2, TD3, TD5, TD6 Flag Time Delay
8
Clock
Cycles
ENABLE Pin
VEN
IEN
EN Pin Threshold
1.0
1.22
7
1.5
V
EN Pin Pull-up Current
VEN = 0V
µA
INV Pin
VIH_INV
Invert Pin VIH
Invert Pin VIL
90%
VCC
V
V
VIL_INV
10%
VCC
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 3: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality
Control (SQC) methods. The limits are used to calculate National's Average Outgoing Quality Level (AOQL).
Note 4: Typical numbers are at 25°C and represent the most likely parametric norm.
3
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Typical Performance Characteristics VCC = 3.3V unless otherwise specified.
Quiescent Current vs VCC
Quiescent Current vs Temperature
30048415
30048414
Enable Threshold vs Temperature
Time Delay vs VIN
(CADJ = 10 nF Nominal)
30048416
30048417
Time Delay vs Temperature
(CADJ = 10 nF Nominal)
VFLAG vs VIN
(INV Low, RFLAG = 100 kΩ)
30048418
30048419
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4
FLAG Voltage vs Current
30048420
5
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Block Diagram
30048403
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6
Application Information
OVERVIEW
of the output flags. This pin should be tied to a logic output
high or low and not allowed to remain open circuit. The fol-
lowing discussion assumes the INV pin is held low such that
the flag output is active high.
The LM3881 Power Sequencer provides a simple solution for
sequencing multiple rails in a controlled manner. A clock sig-
nal is established that facilitates control of the power up and
power down of three open drain FET output flags. These flags
permit connection to shutdown or enable pins of linear regu-
lators and/or switching regulators to control the power sup-
plies’ operation. This allows a complete power system to be
designed without worrying about large in-rush currents or
latch-up conditions that can occur during an uncontrolled
startup. An invert (INV) pin is provided that reverses the logic
A small external timing capacitor is connected to the TADJ
pin that establishes the clock waveform. This capacitor is lin-
early charged/discharged by a fixed current source/sink, de-
noted ITADJ_SRC / ITADJ_SNK, of magnitude 12 µA between pre-
defined voltage threshold levels, denoted VLTH and VHTH, to
generate the timing waveform as shown in the following dia-
gram.
30048409
FIGURE 1. TADJ Pin Timing Waveform
Thus, the clock cycle duration is directly proportional to the
timing capacitor value. Considering the TADJ voltage thresh-
old levels and the charge/discharge current magnitude, it can
be shown that the timing capacitor-clock period relationship
is typically 120 µs/nF. For example, a 10 nF capacitor sets up
a clock period of 1.2 ms.
other timer will begin to delay the release of the second flag
(FLAG2). This time delay, denoted TD2, corresponds to ex-
actly eight clock periods. Similarly, FLAG3 is released after
time delay TD3, again eight clock cycles, has expired. Accord-
ingly, a TADJ capacitor of 10 nF generates typical time delays
TD2 and TD3 of 9.6 ms and TD1 of between 10.8 ms and 12.0
ms.
The timing sequence of the LM3881 is controlled by the en-
able (EN) pin. Upon power up, all the flags are held low until
the precision enable pin exceeds its threshold. After the EN
pin is asserted, the power up sequence will commence and
the open-drain flags will be sequentially released.
The power down sequence is the same as power up, but in
reverse order. When the EN pin is de-asserted, a timer will
begin that delays the third flag (FLAG3) from pulling low. The
second and first flag will then follow in a sequential manner
after their appropriate time delays. These time delays, denot-
ed TD4, TD5, TD6, are equal to TD1, TD2, TD3, respectively.
An internal counter will delay the first flag (FLAG1) from rising
until a fixed time period, denoted by TD1 in the following timing
diagram, elapses. This corresponds to at least nine, maxi-
mum ten, clock cycles depending on where EN is asserted
relative to the clock signal. Upon release of the first flag, an-
For robustness, the pull down FET associated with each flag
is designed such that it can sustain a short circuit to VCC.
7
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30048425
FIGURE 2. Power Up Sequence, INV Low
30048405
FIGURE 3. Power Up Sequence, INV High
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8
30048406
FIGURE 4. Power Down Sequence, INV Low
30048424
FIGURE 5. Power Down Sequence, INV High
9
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ENABLE CIRCUIT
The enable circuit is designed with an internal comparator,
referenced to a bandgap voltage (1.22V), to provide a preci-
sion threshold. This allows the timing to be set externally
using a capacitor as shown in the diagram below. Alterna-
tively, sequencing can be based on a certain event such as a
line voltage reaching 90% of its nominal value by employing
a resistor divider from VCC to Enable.
30048410
FIGURE 8. Enable Based On Input Supply Level
One of the features of the enable pin is that it provides glitch
free operation. The timer will start counting at a rising thresh-
old, but will always reset if the enable pin is de-asserted
before the first output flag is released. This is illustrated in the
timing diagram below, assuming INV is low.
30048407
FIGURE 6. Precision Enable Circuit
Using the internal pull-up current source to charge the exter-
nal capacitor CEN, the time delay while the enable voltage
reaches the required threshold, assuming EN is charging
from 0V, can be calculated by the equation as follows.
30048411
FIGURE 9. Enable Glitch Timing, INV Low
If the EN pin remains high for the entire power up sequence,
then the part will operate as shown in the standard timing di-
agrams. However, if the EN signal is de-asserted before the
power-up sequence is completed, the part will enter a con-
trolled shutdown. This allows the system to initiate a con-
trolled power sequence, preventing any latch conditions to
occur. The following timing diagrams describe the flag se-
quence if the EN pin is de-asserted after FLAG1 releases, but
before the entire power-up sequence is completed. INV is as-
sumed low.
30048404
FIGURE 7. Enable Delay Timing
A resistor divider can also be used to enable the LM3881
based on exceeding a certain VCC supply voltage threshold.
Care needs to be taken when sizing the resistor divider to
include the effects of the internal EN pull-up current source.
The supply voltage for which EN is asserted is given by
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30048412
30048413
FIGURE 10. Incomplete Sequence Timing, INV Low
11
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Physical Dimensions inches (millimeters) unless otherwise noted
MSOP-8 Package
NS Package Number MUA08A
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Notes
13
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Notes
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