LM4548VH [NSC]
AC ’97 Rev 2 Codec with Sample Rate Conversion and National 3D Sound; AC '97版本2编解码器采样率转换和国家3D音效
| 型号： | LM4548VH |
| 厂家： | 
National Semiconductor |
| 描述： | AC ’97 Rev 2 Codec with Sample Rate Conversion and National 3D Sound |
| 文件： | 总18页 (文件大小：325K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1999
LM4548
AC ’97 Rev 2 Codec with Sample Rate Conversion and
National 3D Sound
General Description
Key Specifications
The LM4548 is an audio codec for PC systems which is fully
PC98 compliant and performs the analog intensive functions
of the AC97 Rev2 architecture. Using 18-bit Sigma-Delta
A/D’s and D/A’s, the LM4548 provides 90dB of Dynamic
Range.
n Analog Mixer Dynamic Range
n D/A Dynamic Range
97dB (typ)
89dB (typ)
90dB (typ)
n A/D Dynamic Range
The LM4548 was designed specifically to provide a high
quality audio path and provide all analog functionality in a PC
audio system. It features full duplex stereo A/D’s and D/A’s
and an analog mixer with 4 stereo and 3 mono inputs, each
of which has separate gain, attenuation and mute control.
The LM4548 also provides the additional True Line-Level
output and National’s 3D Sound stereo enhancement.
Features
n AC’97 Rev2 compliant
n National’s 3D Sound circuitry
n High quality Sample Rate Conversion (SRC) from 4kHz
to 48kHz in 1Hz increments.
n Multiple Codec Support
n True Line Level Output with volume control in addition to
standard Line Out
n Advanced power management support
n Digital 3V and 5V compliant
The LM4548 supports variable sample rate conversion as
defined in the AC97 Rev2 specification. The sample rate for
the A/D and D/A can be programmed separately to convert
any rate between 4kHz - 48kHz with a resolution of 1Hz. The
AC97 architecture separates the analog and digital functions
of the PC audio system allowing both for system design flex-
ibility and increased performance.
Applications
n Desktop PC Audio Systems
n Portable PC Systems
n Mobile PC Systems
Block Diagram
DS100987-1
FIGURE 1. LM4548 Block Diagram
© 1999 National Semiconductor Corporation
DS100987
www.national.com
Absolute Maximum Ratings (Note 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Soldering Information
TQFP Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
215˚C
220˚C
Supply Voltage
Storage Temperature
Input Voltage
6.0V
−40˚C to +150˚C
−0.3V to VDD +0.3V
2500V
See AN-450 ″Surface Mounting and their Effects on
Product Reliability″ for other methods of
soldering surface mount devices.
θJA (typ) — VBH48A
74˚C/W
ESD Susceptibility (Note 5)
pins 27, 28
1500V
Operating Ratings
pin 3
750V
Temperature Range
TMIN ≤ TA ≤ TMAX
ESD Susceptibility (Note 6)
pin 3
200V
−40˚C ≤ TA ≤ 85˚C
4.2V ≤ AVDD ≤ 5.5V
3.0V ≤ DVDD ≤ 5.5V
100V
Analog Supply Range
Digital Supply Range
Junction Temperature
150˚C
Electrical Characteristics (Notes 1, 3)
The following specifications apply for AVDD = 5V, DVDD = 5V, Fs = 48kHz, single codec configuration, unless otherwise noted.
Limits apply for TA= 25˚C. The reference for 0dB is 1Vrms unless otherwise specified.
Symbol
Parameter
Conditions
Units
(Limits)
LM4548
Typical
(Note 7)
Limit
(Note 8)
AVDD
Analog Supply Range
Digital Supply Range
4.2
5.5
3.0
5.5
V (min)
V (max)
V (min)
V (max)
mA
DVDD
DIDD
Digital Quiescent Power Supply
Current
DVDD = 5V
43
DVDD = 3.3V
20
53
mA
mA
AIDD
Analog Quiescent Power Supply
Current
IDSD
Digital Shutdown Current
Analog Shutdown Current
Reference Voltage
500
30
µA
µA
V
IASD
VREF
PSRR
2.23
40
Power Supply Rejection Ratio
dB
Analog Loopthru Mode
CD Input to Line Output, -60dB Input
THD+N, A-Weighted
Dynamic Range (Note 2)
97
90
dB (min)
% (max)
THD
Total Harmonic Distortion
VO = -3dB, f = 1kHz, RL = 10kΩ
0.01
0.02
Analog Input Section
VIN
Line Input Voltage
1
0.1
1
Vrms
Vrms
Vrms
dB
Mic Input with 20dB Gain
Mic Input with 0dB Gain
Crosstalk
Xtalk
ZIN
CD Left to Right
-95
40
Input Impedance(Note 2)
Input Capacitance
10
kΩ (min)
pF
CIN
15
Interchannel Gain Mismatch
CD Left to Right
0dB to 22.5dB
0.01
dB
Record Gain Amplifier - A/D
AS
Step Size
1.5
dB
Mixer Section
AS
Step Size
+12dB to -34.5dB
1.5
86
dB
dB
AM
Mute Attenuation
Analog to Digital Converters
Resolution
18
Bits
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2
Electrical Characteristics (Notes 1, 3) (Continued)
The following specifications apply for AVDD = 5V, DVDD = 5V, Fs = 48kHz, single codec configuration, unless otherwise noted.
Limits apply for TA= 25˚C. The reference for 0dB is 1Vrms unless otherwise specified.
Symbol
Parameter
Conditions
Units
(Limits)
LM4548
Typical
(Note 7)
Limit
(Note 8)
Analog to Digital Converters
Dynamic Range (Note 2)
Frequency Response
Digital to Analog Converters
-60dB Input THD+N, A-Weighted
-1dB Bandwidth
90
20
86
dB (min)
kHz
Resolution
18
89
Bits
dB (min)
%
Dynamic Range (Note 2)
Total Harmonic Distortion
Frequency Response
Group Delay (Note 2)
Out of Band Energy
Stop Band Rejection
Discrete Tones
-60dB Input THD+N, A-Weighted
85
2
THD
VIN = -3dB, f=1kHz, RL = 10kΩ
0.01
20 - 21k
Hz
mS (max)
dB
-40
70
dB
DT
-96
dB
True Line Level Output Volume Section
AS
Step Size
0dB to -46.5dB
1.5
86
dB
dB
AM
Mute Attenuation
Digital I/O (Note 2)
0.30 x
DVDD
VIL
Low level input voltage
V (max)
V (min)
V (min)
V (max)
0.40 x
DVDD
VHI
VOH
VOL
High level input voltage
High level output voltage
Low level output voltage
0.50 x
DVDD
0.20 x
DVDD
±
±
IL
Input Leakage Current
Tri state Leakage Current
Output drive current
AC Link inputs
10
10
µA
µA
IL
High impedance AC Link outputs
AC Link outputs
IDR
5
mA
Digital Timing Specifications (Note 2)
FBC
BIT_CLK frequency
BIT_CLK period
12.288
81.4
MHz
nS
TBCP
Variation of BIT_CLK period from 50%
duty cycle
±
TCH
BIT_CLK high
20
% (max)
FSYNC
TSP
SYNC frequency
48
kHz
µS
SYNC period
20.8
1.3
TSH
SYNC high pulse width
SYNC low pulse width
µS
TSL
19.5
µS
SDATA_IN, SDATA_OUT to falling
edge of BIT_CLK
TSETUP
THOLD
TRISE
Setup Time
Hold Time
Rise Time
15
nS (min)
nS (min)
nS (max)
Hold time of SDATA_IN, SDATA_OUT
from falling edge of BIT_CLK
5
6
6
BIT_CLK, SYNC, SDATA_IN or
SDATA_OUT
BIT_CLK, SYNC, SDATA_IN or
SDATA_OUT
TFALL
Fall Time
nS (max)
µS (min)
nS (min)
TRST_LOW
TRST2CLK
RESET# active low pulse width
For cold reset
1.0
RESET# inactive to BIT_CLK start
up
For cold reset
162.8
3
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Electrical Characteristics (Notes 1, 3) (Continued)
The following specifications apply for AVDD = 5V, DVDD = 5V, Fs = 48kHz, single codec configuration, unless otherwise noted.
Limits apply for TA= 25˚C. The reference for 0dB is 1Vrms unless otherwise specified.
Symbol
Parameter
Conditions
Units
(Limits)
LM4548
Typical
(Note 7)
Limit
(Note 8)
Digital Timing Specifications (Note 2)
TSH
SYNC active high pulse width
SYNC inactive to BIT_CLK start up
Setup to trailing edge of RESET#
Rising edge of RESET# to Hi-Z
For warm reset
1.3
µS
TSYNC2CLK
TSU2RST
TRST2HZ
For warm reset
162.8
15
nS (min)
nS (min)
nS (max)
For ATE Test Mode
For ATE Test Mode
25
Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 2: These specifications are guaranteed by design and characterization; they are not production tested.
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guar-
antee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is
given, however, the typical value is a good indication of device performance.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
, θ , and the ambient temperature T . The maximum
JMAX JA
A
allowable power dissipation is P
= (T
–T )/θ or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4548, T
= 150˚C. The
JMAX
DMAX
JMAX
A
JA
typical junction-to-ambient thermal resistance is 74˚C/W for package number VBH48A.
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: Machine Model, 220 pF–240 pF discharged through all pins.
Note 7: Typicals are measured at 25˚C and represent the parametric norm.
Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
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4
Timing Diagrams
Clocks
DS100987-10
Data Setup and Hold
DS100987-11
Digital Rise and Fall
DS100987-12
Cold Reset
DS100987-13
Warm Reset
DS100987-14
5
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Typical Application
DS100987-3
FIGURE 2. LM4548 Typical Application Circuit
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6
Connection Diagram
DS100987-2
Top View
Order Number LM4548VH
See NS Package Number VBH48A
Pin Description
Analog I/O
Name
Pin
I / O
Functional Description
This is a mono input which gets summed into both the stereo line out and the true line level
out after the National 3D Sound block. The PC_BEEP level can be adjusted from 0dB to
−45dB in 3dB steps, or muted, via register 0Ah.
PC_BEEP
12
I
This is a mono input which gets summed into both the stereo line out and the true line level
out after the National 3D Sound block. The PHONE level can be adjusted from +12dB to
−34.5dB in 1.5dB steps as well as muted via register 0Ch.
PHONE
AUX_L
13
14
I
I
This line level input can be routed through the Input Mux and recorded by the left ADC. In
addition, this analog input gets summed into the left output stream. The amount of AUX_L
signal mixed in the left output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps
as well as muted via register 16h.
7
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Pin Description (Continued)
Analog I/O (Continued)
Name
Pin
I / O
Functional Description
This line level input can be routed through the Input Mux and recorded by the right ADC. In
addition, this analog input gets summed into the right output stream. The amount of AUX_R
signal mixed in the right output stream can be adjusted from +12dB to −34.5dB in 1.5dB
steps as well as muted via register 16h.
AUX_R
15
I
This line level input can be routed through the Input Mux and recorded by the left ADC. In
addition, this analog input gets summed into the left output stream. The amount of VIDEO_L
signal mixed in the left output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps
as well as muted via register 14h.
VIDEO_L
VIDEO_R
16
17
I
I
This line level input can be routed through the Input Mux and recorded by the right ADC. In
addition, this analog input gets summed into the right output stream. The amount of
VIDEO_R signal mixed in the right output stream can be adjusted from +12dB to −34.5dB in
1.5dB steps as well as muted via register 14h.
This line level input can be routed through the Input Mux and recorded by the left ADC. In
addition, this analog input gets summed into the left output stream. The amount of CD_L
signal mixed in the left output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps
as well as muted via register 12h.
CD_L
CD_GND
CD_R
18
19
20
I
I
I
This input can be used to reject common mode signals on the CD_L and CD_R inputs.
CD_GND is an AC ground point and not a DC ground point. This input must be AC-coupled
to the source signal’s ground.
This line level input can be routed through the Input Mux and recorded by the right ADC. In
addition, this analog input gets summed into the right output stream. The amount of CD_R
signal mixed in the right output stream can be adjusted from +12dB to −34.5dB in 1.5dB
steps as well as muted via register 12h.
Either MIC1 or MIC2 can be selected via software and routed through the Input Mux for
recording. The 20dB boost circuit is enabled/disabled via register 0Eh. Also, the amount of
mic signal mixed in the output stream can be adjusted from +12dB to −34.5dB in 1.5dB
steps as well as muted via register 0Eh.
MIC1
MIC2
21
22
23
24
I
I
I
I
Either MIC1 or MIC2 can be selected via software and routed through the Input Mux for
recording. The 20dB boost circuit is enabled/disabled via register 0Eh. Also, the amount of
mic signal mixed in the output stream can be adjusted from +12dB to −34.5dB in 1.5dB
steps as well as muted via register 0Eh.
This line level input can be routed through the Input Mux and recorded by the left ADC. In
addition, this analog input gets summed into the left output stream. The amount of
LINE_IN_L signal mixed in the left output stream can be adjusted from +12dB to −34.5dB in
1.5dB steps as well as muted via register 10h.
LINE_IN_L
LINE_IN_R
This line level input can be routed through the Input Mux and recorded by the right ADC. In
addition, this analog input gets summed into the right output stream. The amount of
LINE_IN_R signal mixed in the right output stream can be adjusted from +12dB to −34.5dB
in 1.5dB steps as well as muted via register 10h.
This is a post-mixed output for the left audio channel. The level of this output can be
adjusted from 0dB to −45dB in 1.5dB steps as well as muted via register 02h.
LINE_OUT_L
LINE_OUT_R
MONO_OUT
35
36
37
39
41
O
O
O
O
O
This is a post-mixed output for the right audio channel. The level of this output can be
adjusted from 0dB to −45dB in 1.5dB steps as well as muted via register 02h.
This line level output is either the post-mixed output or the mic input. The level of this output
can be adjusted from 0dB to −45dB in 1.5dB steps as well as muted via register 06h.
This is a post-mixed output for the left audio channel. The level of this output can be
adjusted from 0dB to −45dB in 1.5dB steps as well as muted via register 04h.
LNLVL_OUT_L
LNLVL_OUT_R
This is a post-mixed output for the right audio channel. The level of this output can be
adjusted from 0dB to −45dB in 1.5dB steps as well as muted via register 04h.
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8
Pin Description (Continued)
Digital I/O and Clocking
Name
Pin
I / O
Functional Description
24.576 MHz crystal input. Use a fundamental-mode type crystal. When operating from a
crystal, a 1MΩ resistor must be connected across pins 2 and 3.
XTL_IN
2
I
24.576 MHz crystal output. When operating from a crystal, a 1MΩ resistor must be
connected across pins 2 and 3.
XTL_OUT
3
5
O
I
This data stream contains both control data and DAC audio data. This input is sampled by
the LM4548 on the falling edge of BIT_CLK.
SDATA_OUT
OUTPUT when in Primary Codec Mode: This pin outputs a 12.288 MHz clock which is
derived (internally divided by two) from the 24.576MHz crystal input (XTL_IN).
INPUT when in Secondary Codec Mode (Multiple Codec configurations only): 12.288MHz
clock is to be supplied from an external source, such as from the BIT_CLK of a Primary
Codec.
BIT_CLK
6
I/O
This data stream contains both control data and ADC audio data. This output is clocked out
by the LM4548 on the rising edge of BIT_CLK.
SDATA_IN
SYNC
8
O
I
48kHz sync pulse which signifies the beginning of both the SDATA_IN and SDATA_OUT
serial streams. SYNC must be synchronous to BIT_CLK.
10
11
This active low signal causes a hardware reset which returns the control registers to their
default conditions.
RESET#
I
ID0 and ID1 set the codec address for multiple codec use where ID0 is the LSB. Connect
these pins to DVdd or GND as required. If these pins are not connected (NC), they default
to Master Codec setting (same as connecting both pins to GND). These pins are of the
same polarity as their internal ID0, ID1 registers. If pin 45 is connected to GND, then ID0 will
be set to ″0″ internally. Connection to DVdd corresponds to a ″1″ internally.
ID0
ID1
45
46
I
I
ID0 and ID1 set the codec address for multiple codec use where ID1 is the MSB. Connect
these pins to DVdd or GND as required. If these pins are not connected (NC), they default
to Master Codec setting (same as connecting both pins to GND). These pins are of the
same polarity as their internal ID0, ID1 registers. If pin46 is connected to GND, then ID1 will
be set to ″0″ internally. Connection to DVdd corresponds to a ″1″ internally.
Power Supplies and References
Name
AVDD
AVSS
DVDD
DVSS
Pin
25
I / O
Functional Description
I
I
I
I
Analog supply.
Analog ground.
Digital supply.
Digital ground.
26
1,9
4,7
Nominal 2.2V reference output. Not intended to sink or source current. Bypassing of this pin
should be done with short traces to maximize performance.
VREF
VREFOUT
AFILT1
27
28
29
30
O
O
O
O
Nominal 2.2V reference output. Can source up to 5mA of current and can be used to bias a
microphone.
This pin is not used and should be left open (NC). However, a capacitor to ground on this
pin is permitted - it will not affect performance.
This pin is not used and should be left open (NC). However, a capacitor to ground on this
pin is permitted - it will not affect performance.
AFILT2
These pins are used to complete the National 3D Sound circuit. Connect a 0.022µF
capacitor between pins 3DP and 3DN. The National 3D Sound can be turned on and off via
bit D13 in control register 20h. This is a fixed-depth type stereo enhance circuit, thus writing
to register 22h has no effect. If National 3D Sound is not needed, then these pins should be
left as no connect (NC).
3DP, 3DN
33,34
O
9
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Typical Performance Characteristics
Analog Loopthru
Noise Floor
ADC Noise Floor
DAC Noise Floor
DS100987-15
DS100987-16
DS100987-18
ADC Frequency
Response
DAC Frequency
Response
True Line Level Out
Noise Floor (Analog Loopthrough)
DS100987-19
DS100987-18
DS100987-20
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10
11
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Application Information
AC Link Serial Interface Protocol
DS100987-4
FIGURE 3. AC 97 Bidirectional Audio Frame
DS100987-6
FIGURE 4. AC Link Audio Output Frame
AC Link Output Frame: SDATA_OUT (output from
controller, input to LM4548)
The audio output frame (output from AC ’97 Controller) con-
tains control and PCM data targeted for the LM4548 control
registers and stereo DAC. The Tag slot, slot 0, contains 16
bits that tell the AC Link interface circuitry on the LM4548 the
validity of the following data slots.
A new audio output frame is signaled with a low to high tran-
sition of SYNC. SYNC is synchronous to the rising edge of
BIT_CLK. On the next rising edge of BIT_CLK, the AC ’97
Controller drives SDATA_OUT with the first bit of slot 0. The
LM4548 samples SDATA_OUT on the falling edge of BIT-
_CLK. The AC ’97 Controller will continue outputting the
SDATA_OUT stream on each successive rising edge of BIT-
_CLK.
DS100987-5
FIGURE 5. Start of Audio Output Frame
SDATA_OUT Slot 0: Tag Phase
Bit
Description
Comment
The first bit of slot 0 is designated the ″Valid Frame″ bit. If
this bit is 1, it indicates that the current data frame contains
at least one slot of valid data and the LM4548 will further
sample the next four bits to determine which frames do in
fact have valid data. Valid slots are signified by a 1 in their re-
spective slot bit position.
1 = This frame has valid
data.
15
Valid Frame
Control
register
address
1 = Control Address is
valid.
14
Control
register data
13
12
1 = Control Data is valid.
Left Playback
PCM Data
1 = Left PCM Data is
valid.
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12
Application Information (Continued)
Bits
19:4
3:0
Description
Comment
Control
Register Write
Data
Bit
Description
Comment
Set bits to ″0″ if read
operation
Right
Playback
PCM Data
1 = Right PCM Data is
valid.
11
Reserved
Set to ″0″
SDATA_OUT Slot 3: PCM Playback Left Channel
SDATA_OUT Slot 1: Control Address
Slot 3 is a 20 bit field used to transmit data intended for the
left DAC on the LM4548. Any unused bits should be padded
with zeros. The LM4548 DAC’s have 18 bit resolution and
thus will use the first 18 bits of the 20 bit PCM stream.
Slot 1 is used both to write to the LM4548 registers as well
as read back a register’s current value. The MSB of Slot 1
(bit 19) signifies whether the current control operation is a
read or a write. Bits 18 through 12 are used to specify the
register address of the read or write operation. The least sig-
nificant twelve bits are reserved and should be stuffed with
zeros by the AC’97 controller.
Bits
Description
Comment
PCM Audio
Data for Left
DAC
19:0
Set unused bits to ″0″
Bits
Description
Comment
19
Read/Write
0 = Read, 1 = Write
SDATA_OUT Slot 4: PCM Playback Right Channel
Control
Register
Identifies the Control
Register
18:12
11:0
Slot 4 is a 20 bit field used to transmit data intended for the
right DAC on the LM4548. Any unused bits should be pad-
ded with zeros. The LM4548 DAC’s have 18 bit resolution
and thus will use the first 18 bits of the 20 bit PCM stream.
Reserved
Set to ″0″
SDATA_OUT Slot 2: Control Data
Bits
Description
Comment
Slot 2 is used to transmit 16 bit control data to the LM4548 in
the event that the current operation is a write operation. The
least significant four bits should be stuffed with zeros by the
AC ’97 controller. If the current operation is a register read,
the entire slot, bits 19 through 0 should be stuffed with zeros.
PCM Audio
Data for Right
DAC
19:0
Set unused bits to ″0″
SDATA_OUT Slots 5-12: Reserved
Set these SDATA_OUT slots to ″0″ as they are not currently
implemented and are reserved for future use.
DS100987-8
FIGURE 6. AC Link Audio Input Frame
AC Link Input Frame: SDATA_IN (input to controller,
output from LM4548)
SDATA_IN Slot 0: Codec Status Bits
The first bit of SDATA_IN Slot 0 (bit 15) indicates when the
Codec is ready. The digital controller must probe further to
see which other subsections are ready.
The audio input frame (input to the AC ’97 Digital Controller)
contains status and PCM data from the LM4548 control reg-
isters and stereo ADC. The Tag slot, slot 0, contains 16 bits
that tell the AC ’97 Digital Controller whether the LM4548 is
ready and the validity of data from certain device subsec-
tions.
A new audio input frame is signaled with a low to high tran-
sition of SYNC. SYNC is synchronous to the rising edge of
BIT_CLK. On the next rising edge of BIT_CLK, the LM4548
drives SDATA_IN with the first bit of slot 0. The Digital Con-
troller samples SDATA_IN on the falling edge of BIT_CLK.
The LM4548 will continue outputting the SDATA_IN stream
on each successive rising edge of BIT_CLK. The LM4548
outputs data MSB first, in a MSB justified format. All reserved
bits and slots are stuffed with ″0″ ’s by the LM4548.
13
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Application Information (Continued)
Bits
9:2
Description
Comment
Unused
Other Slot
Request bits
1,0
Reserved
Stuff with ″0″
SDATA_IN Slot 2: Status Data
The slot returns the control register data. The data returned
was initiated by a read request in the previous SDATA_OUT
frame, slot 1.
Bits
19:4
3:0
Description
Comment
Control
Register Read
Data
Reserved
Stuffed with ″0″ ’s
DS100987-7
FIGURE 7. Start of Audio Input Frame
SDATA_IN Slot 3: PCM Record Left Channel
This slot contains the left ADC sample data. The signal to be
digitized is selected via register 1Ah and subsequently
routed through the Input Mux for recording by the left ADC.
This is a 20-bit slot, where the digitized 18-bit PCM data is
output from the codec MSB first and the last remaining 2 bits
will zeros.
Bit
Description
Comment
Codec Ready
Bit
15
0=Not Ready, 1=Ready
Slot 1 data
valid
14
13
12
11
Status Address is valid
Status Data is valid
Bits
19:2
1:0
Description
Comment
Slot 2 data
valid
PCM Record
Left Channel
data
18 bit audio sample from
left ADC
Slot 3 data
valid
Left Audio PCM Data is
valid
Reserved
Stuffed with ″0″’s
Slot 4 data
valid
Right Audio PCM Data is
valid
SDATA_IN Slot 4: PCM Record Right Channel
This slot contains the right ADC sample data. The signal digi-
tized is selected via register 1Ah and subsequently routed
through the Input Mux for recording by the right ADC. This is
a 20-bit slot, where the digitized 18-bit PCM data is output
from the codec MSB first and the last remaining 2 bits will ze-
ros.
SDATA_IN Slot 1: Status Address / Slot Request Bits
This slot echoes the control register which a read was re-
quested on. The address echoed was initiated by a read re-
quest in the previous SDATA_OUT frame, slot 1. Bits 11 and
10 are slot request bits that support Sample Rate Conver-
sion (SRC) functionality. If bit 11 is set to 0, then the control-
ler should respond with a valid PCM left sample in slot 3 of
the next frame. If bit 10 is set to 0, then the controller should
respond with a valid PCM right sample in slot 4 of the next
frame. If bits 11 or 10 are set to 1, the controller should not
send data in the next frame. Bits 9 through 2 are unused.
Bits 1 and 0 are reserved and should be set to 0.
Bits
19:2
1:0
Description
Comment
PCM Record
Right Channel
data
18 bit audio sample from
right ADC
Reserved
Stuffed with ″0″’s
Bits
Description
Comment
SDATA_IN Slots 5-12: Reserved
19
Reserved
Stuffed with ″0″
These SDATA_IN slots are set to ″0″ as they are reserved for
future use.
Echo of Control Register
for which data is being
returned.
Control
Register Index
18:12
11
AC Link Low Power Mode
0 = Controller should
send valid slot 3 data in
the next frame, 1 =
Controller should not
send slot 3 data in the
next frame
Slot 3
Request bit
(PCM left)
0 = Controller should
send valid slot 4 data in
the next frame, 1 =
Controller should not
send slot 4 data in the
next frame
DS100987-9
Slot 4
Request bit
(PCM right)
FIGURE 8. AC Link Powerdown Timing
10
www.national.com
14
Application Information (Continued)
SL2:SL0
Left Record Source
Mic
Register Descriptions
0
1
2
3
4
5
6
7
CD In (L)
Reset Register (00h)
Video In (L)
Aux In (L)
Writing any value to this register causes a register reset
which changes all of the registers back to their default val-
ues. If a read is performed on this register, the LM4548 will
return a value of 0D50h indicating that National 3D Sound is
implemented, 18bit data is supported for both the ADC’s and
DAC’s, and the volume control for True Line Level Out is
supported.
Line In (L)
Stereo Mix (L)
Mono Mix (L)
Phone
SR2:SR0
Right Record Source
Mic
Master Volume Registers (02h, 04h, 06h)
0
1
2
3
4
5
6
7
These registers allow the output levels from LINE_OUT, LN-
LVL_OUT and MONO_OUT to be attenuated or muted.
There are 6-bits of volume control, plus one mute bit. It is a
5-bit volume range, where each step is nominally 1.5dB and
each output can be individually muted by either setting the
most significant bit (Mx5), and/or the mute bit (D15) to ″1.″
CD In (R)
Video In (R)
Aux In (R)
Line In (R)
Stereo Mix (R)
Mono Mix (R)
Phone
Mute
Mx5:Mx0
00 0000
01 1111
1X XXXX
XX XXXX
Function
0dB attenuation
46.5dB attenuation
46.5dB attenuation
mute
0
0
0
Record (Input) Gain Register (1Ch)
1
This registers controls the Record (Input) Gain level for the
stereo input selected via the Record Select Control Register
(1Ah). The gain can be programmed from 0dB to +22.5dB in
1.5dB steps. The level for the left and right channel can be
individually controlled. The input can also be muted by set-
ting the MSB to 1.
Default: 8000h
PC Beep Register (0Ah)
This register controls the level of the PC_BEEP input. The
PC_BEEP can be both attenuated and muted via register
0Ah. Step size is nominally 3dB. The signal present after the
attenuation and mute block is summed into both the left and
right channels.
Mute
Gx3:Gx0
1111
Function
22.5dB gain
0dB gain
mute
0
0
0000
Mute
PV3:0
0000
Function
0dB attenuation
45dB attenuation
mute
1
XXXX
0
Default: 8000h
0
1111
General Purpose Register (20h)
1
XXXX
This register controls many miscellaneous functions imple-
mented on the LM4548. The miscellaneous functions include
POP which allows the PCM to bypass the National 3D
Sound circuitry, 3D which enables or disables the National
3D Sound circuitry, MIX which selects the MONO_OUT
source, MS which selects the microphone mux source and
LPBK which connects the output of the stereo ADC to input
of the stereo DAC. LPBK provides for a digital loopthru path
when enabled.
Default: 0000h
Mixer Input Volume Registers (Index 0Ch - 18h)
These registers set the input volume levels including mute.
Each volume control is 5 bit which provides from a range of
+12dB gain to 34.5dB attenuation in 1.5dB steps. For stereo
ports, the left and right levels can be independently set. Mut-
ing a given port is accomplished by setting the MSB to 1.
Setting the MSB to 1 for stereo ports mutes both the left and
right channel. Register 0Eh has an additional 20dB boost for
a microphone level input. This is enabled by setting bit 6 of
register 0Eh to 1.
BIT
Function
PCM out path and mute, 0 = pre 3D, 1 =
post 3D
POP
Mute
Gx4:Gx0
00000
Function
+12dB gain
0dB gain
3D
MIX
MS
National 3D Sound on / off 1 = on
Mono output select 0 = Mix, 1 = Mic
Mic select 0 = Mic1 1 = Mic2
ADC/DAC loopback
0
0
0
1
01000
11111
34.5dB attenuation
mute
LPBK
XXXXX
Powerdown Control / Status Register (26h)
Default: 8008h (mono regs.), 8808h (stereo regs.)
This read/write register is used to monitor subsystem readi-
ness and also to program the LM4548 powerdown states.
The lower half of this register is read only with a ″1″, indicat-
ing the subsection is ready. Writing to the lower 8 bits will
have no effect.
Record Select Register (1Ah)
This register independently controls the source for the right
and left channel which will be recorded by the stereo ADC.
The default value is 0000h which corresponds to Mic in.
15
www.national.com
Application Information (Continued)
SR15:SR0
2B11h
Sample Rate (Hz)
11025
When the AC Link ″Codec Ready″ indicator bit (SDATA_IN
slot 0, bit 15) is a ″1″, it indicates that the AC Link and AC ’97
registers are in a fully operational state. The AC ’97 Control-
ler must further probe the Powerdown Control / Status Reg-
ister to determine exactly which subsections are ready.
3E80h
16000
5622h
22050
AC44h
BB80h
44100
48000
BIT
REF
ANL
DAC
ADC
Function
Reserved Registers
Vref’s up to nominal level
Analog mixers ready
Do not write to these registers as they are reserved.
DAC section ready to accept data
ADC section ready to transmit data
Supported powerdown modes.
BIT
Function
PRO
PR1
PR2
PR3
PCM in ADC’s and Input Mux powerdown
PCM out DAC’s powerdown
Analog Mixer powerdown (VREF still on)
Analog Mixer powerdown (VREF off)
Digital Interface (AC Link) powerdown
(external clk off)
PR4
PR5
PR6
Internal Clk disable
not used
Extended Audio ID Register (28h)
This read only register identifies which AC97 Extended Au-
dio features are supported. The LM4548 provides for VRA
(Variable Rate Audio) and Multiple Codec support. VRA is in-
dicated by a ″1″ in the LSB of register 28h. The two MSB’s,
ID1 and ID0, show the current codec configuration as con-
nected via external pins 45 and 46.
Pin46 (ID1)
Pin45 (ID0)
Reg 28h ID1
Reg 28h ID0
Codec Mode
NC (not
connected)
NC (not
connected)
Primary
0
0
GND
GND
DVdd
DVdd
GND
DVdd
GND
DVdd
0
0
1
1
0
1
0
1
Primary
Secondary 1
Secondary 2
Secondary 3
Extended Audio Status/Control Register (2Ah)
This read/write register provides status and control of the
Variable Sample Rate function. Setting the LSB of this regis-
ter to ″1″ enables Variable Rate Audio (VRA) mode and al-
lows DAC and ADC sample rates to be programmed via reg-
isters 2Ch and 32h.
BIT
Function
VRA
0 = VRA off (48kHz fixed), 1 = VRA on
Sample Rate Control Registers (2Ch, 32h)
These read/write registers are used to set the sample rate
for the left and right channels of the DAC (2Ch) and the ADC
(32h). When Variable Rate Audio is enabled via bit-0 of Reg-
ister 2Ah, the sample rates can be programmed, in 1Hz in-
crements, to be any value from 4kHz to 48kHz. Below is a list
of the most common sample rates and their corresponding
register values.
SR15:SR0
Sample Rate (Hz)
1F40h
8000
www.national.com
16
17
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead , TQFP, 7 X 7 X 1.4mm, JEDEC (M)
Order Number LM4548VH
NS Package Number VBH48A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
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Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
Email: sea.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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