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LM4549B [NSC]

AC ’97 Rev 2.1 Multi-Channel Audio Codec with Sample Rate Conversion and National 3D Sound; AC '97版本2.1多声道音频编解码器采样率转换和国家3D音效
LM4549B
型号： LM4549B
厂家： National Semiconductor    National Semiconductor
描述：

AC ’97 Rev 2.1 Multi-Channel Audio Codec with Sample Rate Conversion and National 3D Sound
AC '97版本2.1多声道音频编解码器采样率转换和国家3D音效

解码器 编解码器
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September 2006  
LM4549B  
AC ’97 Rev 2.1 Multi-Channel Audio Codec with Sample  
Rate Conversion and National 3D Sound  
General Description  
Key Specifications  
n Analog Mixer Dynamic Range  
n DAC Dynamic Range  
97 dB (typ)  
89 dB (typ)  
90 dB (typ)  
The LM4549B is an audio codec for PC systems which is  
fully PC99 compliant and performs the analog intensive  
functions of the AC ’97 Rev 2.1 architecture. Using 18-bit  
Sigma-Delta ADCs and DACs, the LM4549B provides 90 dB  
of Dynamic Range.  
n ADC Dynamic Range  
Features  
The LM4549B was designed specifically to provide a high  
quality audio path and provide all analog functionality in a PC  
audio system. It features full duplex stereo ADCs and DACs  
and analog mixers with access to 4 stereo and 4 mono  
inputs. Each mixer input has separate gain, attenuation and  
mute control and the mixers drive 1 mono and 2 stereo  
outputs, each with attenuation and mute control. The  
LM4549B supports National’s 3D Sound stereo enhance-  
ment and a comprehensive sample rate conversion capabil-  
ity. The sample rate for the ADCs and DACs can be pro-  
grammed separately with a resolution of 1 Hz to convert any  
rate in the range 4 kHz – 48 kHz. Sample timing from the  
ADCs and sample request timing for the DACs are com-  
pletely deterministic to ease task scheduling and application  
software development. These features together with an ex-  
tended temperature range also make the LM4549B suitable  
for non-PC codec applications.  
n AC ’97 Rev 2.1 compliant  
n High quality Sample Rate Conversion from 4 kHz to 48  
kHz in 1 Hz increments  
n Multiple codec support  
n True Line Level Output with separate gain control  
n National’s 3D Sound stereo enhancement circuitry  
n Advanced power management support  
n External Amplifier Power Down (EAPD) control  
n PC-Beep passthrough to Line Out during Initialization or  
Cold Reset  
n Digital 3.3V and 5V supply options  
n Extended Temperature: −40˚C ≤ TA ≤ 85˚C  
Applications  
n Desktop PC audio systems on PCI cards, AMR cards, or  
with motherboard chips sets featuring AC Link  
n Portable PC systems as on MDC cards, or with a  
chipset or accelerator featuring AC Link  
The LM4549B features the ability to connect several codecs  
together using the Extended AC Link configuration of one  
dedicated serial data signal to the Controller per codec.  
LM4549B systems support up to 8 simultaneous channels of  
streaming data on Input Frames (Codec to Controller) while  
Output Frames (Controller to Codec) carry 2 streams to  
multiple codecs. The LM4549B may also be used in systems  
with the National LM4550B to support up to 6 simultaneous  
channels of streaming data on Output Frames.  
n General and Multi-channel audio frequency systems  
n Automotive Telematics  
The AC ’97 architecture separates the analog and digital  
functions of the PC audio system allowing both for system  
design flexibility and increased performance.  
© 2006 National Semiconductor Corporation  
DS201235  
www.national.com  
www.national.com  
2
Absolute Maximum Ratings (Note 1)  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales Office/  
Distributors for availability and specifications.  
Soldering Information  
LQFP Package  
Vapor Phase (60 sec.)  
Infrared (15 sec.)  
215˚C  
220˚C  
Supply Voltage  
6.0V  
−65˚C to +150˚C  
−0.3V to VDD +0.3V  
2000V  
θJA (typ) – VBH48A  
74˚C/W  
Storage Temperature  
Input Voltage  
Operating Ratings  
Temperature Range  
ESD Susceptibility (Note 2)  
pin 3  
750V  
TMIN ≤ TA ≤ TMAX (Note 4)  
Analog Supply Range  
Digital Supply Range  
−40˚C ≤ TA ≤ 85˚C  
4.2V ≤ AVDD ≤ 5.5V  
3.0V ≤ DVDD ≤ 5.5V  
ESD Susceptibility (Note 3)  
pin 3  
200V  
100V  
Junction Temperature  
150˚C  
Electrical Characteristics (Notes 1, 5) The following specifications apply for AVDD = 5V, DVDD = 3.3V, Fs =  
48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for TA= 25˚C. The reference for 0 dB  
is 1 Vrms unless otherwise specified.  
Units  
(Limits)  
LM4549B  
Symbol  
Parameter  
Conditions  
Typical  
(Note 6)  
Limit  
(Note 7)  
4.2  
AVDD  
Analog Supply Range  
Digital Supply Range  
V (min)  
V (max)  
V (min)  
V (max)  
mA  
5.5  
DVDD  
3.0  
5.5  
DVDD = 5 V  
34  
19  
Digital Quiescent Power Supply  
Current  
DIDD  
AIDD  
DVDD = 3.3 V  
mA  
Analog Quiescent Power Supply  
Current  
AVDD = 5.5 V  
53  
mA  
IDSD  
Digital Shutdown Current  
Analog Shutdown Current  
Reference Voltage  
PR543210 = 111111  
PR543210 = 111111  
No pullup resistor  
19  
70  
µA  
µA  
V
IASD  
VREF  
PSRR  
2.16  
40  
Power Supply Rejection Ratio  
dB  
Analog Loopthrough Mode (Note 8)  
CD Input to Line Output, -60 dB Input  
THD+N  
Dynamic Range (Note 9)  
97  
90  
dB (min)  
% (max)  
THD  
Total Harmonic Distortion  
VO = -3 dB, f = 1 kHz, RL = 10 kΩ  
0.013  
0.02  
Analog Input Section  
LINE_IN, AUX, CD, VIDEO, PC_BEEP,  
PHONE  
VIN  
Line Input Voltage  
1
Vrms  
VIN  
Mic Input with 20 dB Gain  
Mic Input with 0 dB Gain  
Crosstalk  
0.1  
1
Vrms  
Vrms  
dB  
VIN  
Xtalk  
ZIN  
CD Left to Right  
All Analog Inputs  
-95  
40  
3.7  
0.1  
Input Impedance(Note 9)  
Input Capacitance(Note 9)  
Interchannel Gain Mismatch  
10  
7
kΩ (min)  
pF  
CIN  
CD Left to Right  
0 dB to 22.5 dB  
dB  
Record Gain Amplifier - ADC  
AS  
Step Size  
1.5  
86  
dB  
dB  
AM  
Mute Attenuation (Note 9)  
Mixer Section  
AS  
Step Size  
+12 dB to -34.5 dB  
1.5  
86  
dB  
dB  
AM  
Mute Attenuation  
3
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Electrical Characteristics (Notes 1, 5) The following specifications apply for AVDD = 5V, DVDD = 3.3V, Fs =  
48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for TA= 25˚C. The reference for 0 dB  
is 1 Vrms unless otherwise specified. (Continued)  
Units  
(Limits)  
LM4549B  
Symbol  
Parameter  
Conditions  
Typical  
Limit  
(Note 6)  
(Note 7)  
Analog to Digital Converters  
Resolution  
18  
90  
20  
Bits  
dB (min)  
kHz  
Dynamic Range (Note 9)  
Frequency Response  
Digital to Analog Converters  
-60 dB Input THD+N, A-Weighted  
-1 dB Bandwidth  
86  
Resolution  
18  
89  
Bits  
dB (min)  
%
Dynamic Range (Note 9)  
Total Harmonic Distortion  
Frequency Response  
Group Delay (Note 9)  
Out of Band Energy (Note 10)  
Stop Band Rejection  
Discrete Tones  
-60 dB Input THD+N, A-Weighted  
82  
1
THD  
VIN = -3 dB, f = 1 kHz, RL = 10 kΩ  
0.01  
20 - 21 k  
0.36  
-40  
Hz  
Sample Frequency = 48 kHz  
ms (max)  
dB  
70  
dB  
DT  
Analog Output Section  
-96  
dB  
AS  
Step Size  
0 dB to -46.5 dB  
1.5  
86  
dB  
dB  
Ω
AM  
Mute Attenuation  
Output Impedance (Note 9)  
ZOUT  
All Analog Outputs  
220  
Digital I/O (Note 9)  
0.65 x  
DVDD  
0.35 x  
DVDD  
0.90 x  
DVDD  
0.10 x  
DVDD  
10  
VIH  
VIL  
High level input voltage  
V (min)  
V (max)  
V (min)  
V (max)  
Low level input voltage  
High level output voltage  
Low level output voltage  
VOH  
VOL  
IO = −2.5 mA.  
IO = 2.5 mA.  
IL  
Input Leakage Current  
AC Link inputs  
µA  
µA  
IL  
Tri state Leakage Current  
AC-Link I/O capacitance(Note 9)  
Output drive current  
High impedance AC Link outputs  
SDout, BitClk, SDin, Sync, Reset# only  
AC Link outputs  
10  
CIN  
IDR  
4
5
7.5  
pF (max)  
mA  
Digital Timing Specifications (Note 9)  
FBC  
BIT_CLK frequency  
BIT_CLK period  
12.288  
81.4  
MHz  
ns  
TBCP  
Variation of BIT_CLK duty cycle from  
50%  
TCH  
BIT_CLK high  
20  
% (max)  
FSYNC  
TSP  
SYNC frequency  
48  
20.8  
1.3  
kHz  
µs  
SYNC period  
TSH  
SYNC high pulse width  
SYNC low pulse width  
Setup Time for codec data input  
µs  
TSL  
19.5  
3.5  
µs  
TDSETUP  
SDATA_OUT to falling edge of BIT_CLK  
10  
10  
ns (min)  
Hold Time for codec data input(Note Hold time of SDATA_OUT from falling  
TDHOLD  
5.3  
3.8  
ns (min)  
ns (min)  
9)  
edge of BIT_CLK  
Setup Time for codec SYNC  
input(Note 9)  
TSSETUP  
SYNC to falling edge of BIT_CLK  
10  
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4
Electrical Characteristics (Notes 1, 5) The following specifications apply for AVDD = 5V, DVDD = 3.3V, Fs =  
48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for TA= 25˚C. The reference for 0 dB  
is 1 Vrms unless otherwise specified. (Continued)  
Units  
(Limits)  
LM4549B  
Symbol  
Parameter  
Conditions  
Typical  
Limit  
(Note 6)  
(Note 7)  
Hold Time for codec SYNC  
inpu(Note 9)t  
Hold time of SYNC from falling edge of  
BIT_CLK  
TSHOLD  
10  
15  
ns (min)  
ns (max)  
ns (max)  
ns (max)  
µs (min)  
ns (min)  
Output Delay of SDATA_IN from rising  
edge of BIT_CLK  
TCO  
Output Valid Delay  
Rise Time(Note 9)  
Fall Time(Note 9)  
5.2  
BIT_CLK, SYNC, SDATA_IN or  
SDATA_OUT  
TRISE  
6
BIT_CLK, SYNC, SDATA_IN or  
SDATA_OUT  
TFALL  
6
RESET# active low pulse width(Note  
TRST_LOW  
TRST2CLK  
For Cold Reset  
For Cold Reset  
For Warm Reset  
1.0  
162.8  
9)  
RESET# inactive to BIT_CLK start  
271  
up  
SYNC active high pulse width(Note  
9)  
TSH  
1.0  
162.8  
1
µs (min)  
ns (min)  
µs (max)  
TSYNC2CLK  
TS2_PDOWN  
SYNC inactive to BIT_CLK start up  
For Warm Reset  
Delay from end of Slot 2 to BIT_CLK,  
SDATA_IN low  
AC Link Power Down Delay  
Time from minimum valid supply levels  
to end of Reset  
TSUPPLY2RST Power On Reset  
Setup to trailing edge of  
1
µs (min)  
ns (min)  
ns (max)  
TSU2RST  
For ATE Test Mode  
For ATE Test Mode  
15  
25  
RESET#(Note 9)  
Rising edge of RESET# to  
Hi-Z(Note 9)  
TRST2HZ  
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is  
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which  
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit  
is given, however, the typical value is a good indication of device performance.  
Note 2: Human body model, 100 pF discharged through a 1.5 kΩ resistor.  
Note 3: Machine Model, 220 pF – 240 pF discharged through all pins.  
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T  
, θ , and the ambient temperature T . The maximum  
A
JMAX JA  
allowable power dissipation is P  
= (T  
– T )/θ or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4549B, T  
= 150˚C.  
DMAX  
JMAX  
A
JA  
JMAX  
The typical junction-to-ambient thermal resistance is 74˚C/W for package number VBH48A.  
Note 5: All voltages are measured with respect to the ground pin, unless otherwise specified.  
Note 6: Typicals are measured at 25˚C and represent the parametric norm.  
Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).  
Note 8: Loopthrough mode describes a path from an analog input through the analog mixer to an analog output  
Note 9: These specifications are guaranteed by design and characterization; they are not production tested.  
Note 10: Out of band energy is measured from 28.8 kHz to 100 kHz relative to a 1 Vrms DAC output.  
5
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Timing Diagrams  
Clocks  
Data Delay, Setup and Hold  
20123510  
20123511  
Digital Rise and Fall  
Legend  
20123530  
20123512  
Power On Reset  
20123529  
Cold Reset  
20123513  
Warm Reset  
20123514  
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Typical Application  
20123503  
FIGURE 1. LM4549B Typical Application Circuit, Single Codec, 1 Vrms inputs  
APPLICATION HINTS  
•
•
•
•
•
The LM4549B must be initialized by using RESET# to perform a Power On Reset as shown in the Power On Reset Timing  
Diagram  
Don’t leave unused Analog inputs floating. Tie all unused inputs together and connect to Analog Ground through a capacitor  
(e.g. 0.1 µF)  
Do not leave CD_GND floating when using the CD stereo input. CD_GND is the AC signal reference for the CD channels and  
should be connected to the CD source ground (Analog Ground may also be acceptable) through a 1 µF capacitor  
If using a non-standard AC Link controller take care to keep the SYNC and SDATA_IN signals low during Cold Reset to avoid  
entering the ATE or Vendor test modes by mistake.  
The PC_Beep input should be muted if not used since it defaults to 0 dB gain on reset, unlike the mute default of the other  
analog inputs  
7
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Connection Diagram  
20123502  
Top View  
Order Number LM4549BVH  
See NS Package Number VBH48A  
Pin Descriptions  
ANALOG I/O  
Name  
Pin  
I / O  
Functional Description  
Mono Input  
This line level (1 Vrms nominal) mono input is mixed equally into both channels of the Stereo  
Mix signal at MIX2 under the control of the PC_Beep Volume control register, 0Ah. The  
PC_BEEP level can be muted or adjusted from 0 dB to -45 dB in 3 dB steps. The Stereo Mix  
signal feeds both the Line Out and Line Level Out analog outputs and is also selectable at  
the Record Select Mux. During Initialization or Cold Reset, (reset pin held active low),  
PC_BEEP is switched directly to both channels of the Line Out stereo output, bypassing all  
volume controls. This allows signals such as PC power-on self-test tones to be heard through  
the PC’s audio system before the codec registers are configured.  
PC_BEEP  
12  
I
Mono Input  
This line level (1 Vrms nominal) mono input is selectable at the Record Select Mux for  
conversion by either channel of the stereo ADC. It can also be mixed equally into both  
channels of the Stereo Mix signal at MIX2 under the control of the Phone Volume register,  
0Ch. The PHONE level can be muted or adjusted from +12 dB to -34.5 dB in 1.5 dB steps.  
The Stereo Mix signal feeds both the Line Out and Line Level Out analog stereo outputs and  
is also selectable at the Record Select Mux.  
PHONE  
13  
I
9
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Pin Descriptions (Continued)  
ANALOG I/O (Continued)  
Name  
Pin  
I / O  
Functional Description  
Left Stereo Channel Input  
This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record  
Select Mux for conversion by the left channel ADC. It can also be mixed into the left channel  
of the Stereo Mix 3D signal at MIX1 under the control of the Aux Volume register, 16h. The  
AUX_L level can be muted (along with AUX_R) or adjusted from +12 dB to -34.5 dB in 1.5 dB  
steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo  
outputs Line Out and Line Level Out.  
AUX_L  
14  
I
Right Stereo Channel Input  
This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Record  
Select Mux for conversion by the right channel ADC. It can also be mixed into the right  
channel of the Stereo Mix 3D signal at MIX1 under the control of the Aux Volume register,  
16h. The AUX_R level can be muted (along with AUX_L) or adjusted from +12 dB to -34.5 dB  
in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to  
the stereo outputs Line Out and Line Level Out.  
AUX_R  
VIDEO_L  
VIDEO_R  
CD_L  
15  
16  
17  
18  
I
I
I
I
Left Stereo Channel Input  
This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record  
Select Mux for conversion by the left channel ADC. It can also be mixed into the left channel  
of the Stereo Mix 3D signal at MIX1 under the control of the Video Volume register, 14h. The  
VIDEO_L level can be muted (along with VIDEO_R) or adjusted from +12 dB to -34.5 dB in  
1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the  
stereo outputs Line Out and Line Level Out.  
Right Stereo Channel Input  
This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Record  
Select Mux for conversion by the right channel ADC. It can also be mixed into the right  
channel of the Stereo Mix 3D signal at MIX1 under the control of the Video Volume register,  
14h. The VIDEO_R level can be muted (along with VIDEO_L) or adjusted from +12 dB to  
-34.5 dB in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for  
access to the stereo outputs Line Out and Line Level Out.  
Left Stereo Channel Input  
This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Input Mux  
for conversion by the left channel ADC. It can also be mixed into the left channel of the  
Stereo Mix 3D signal at MIX1 under the control of the CD Volume register, 12h. The CD_L  
level can be muted (along with CD_R) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps.  
Stereo Mix 3D is mixed into the Stereo Mix signal at MIX2 for access to the stereo outputs  
Line Out and Line Level Out.  
AC Ground Reference  
This input is the reference for the signals on both CD_L and CD_R. CD_GND is not a DC  
ground and should be AC-coupled to the stereo source ground common to both CD_L and  
CD_R. The three inputs, CD_GND, CD_L and CD_R act together as a quasi-differential  
stereo input with CD_GND providing AC common-mode feedback to reject ground noise. This  
can improve the input SNR for a stereo source with a good common ground but precision  
resistors may be needed in any external attenuators to achieve the necessary balance  
between the two channels.  
CD_GND  
19  
I
Right Stereo Channel Input  
This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Input  
Mux for conversion by the right channel ADC. It can also be mixed into the right channel of  
the Stereo Mix 3D signal at MIX1 under the control of the CD Volume register, 12h. The  
CD_R level can be muted (along with CD_L) or adjusted from +12 dB to -34.5 dB in 1.5 dB  
steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo  
outputs Line Out and Line Level Out.  
CD_R  
20  
I
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10  
Pin Descriptions (Continued)  
ANALOG I/O (Continued)  
Name  
Pin  
I / O  
Functional Description  
Mono microphone input  
Either MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the  
MS bit (bit D8) in the General Purpose register, 20h. The boost amplifier gain (0 dB or 20 dB)  
is set by the 20dB bit (D6) in the Mic Volume register, 0Eh. Nominal input levels at the two  
gain settings are 1 Vrms and 0.1 Vrms respectively. The amplifier output is selectable (Record  
Select register, 1Ah) by either the right or left channels of the Record Select Mux for  
conversion on either or both channels of the stereo ADCs. The amplifier output can also be  
accessed at the stereo mixer MIX1 (muting and mixing adjustments via Mic Volume register,  
0Eh) where it is mixed equally into both left and right channels of Stereo Mix 3D for access to  
the stereo outputs Line Out and Line Level Out. Access to the Mono analog output is  
selected by a mux controlled by the MIX bit (D9) in General Purpose register, 20h.  
Mono microphone input  
MIC1  
21  
I
Either MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the  
MS bit (bit D8) in the General Purpose register, 20h. The boost amplifier gain (0 dB or 20 dB)  
is set by the 20dB bit (D6) in the Mic Volume register, 0Eh. Nominal input levels at the two  
gain settings are 1 Vrms and 0.1 Vrms respectively. The amplifier output is selectable (Record  
Select register, 1Ah) by either the right or left channels of the Record Select Mux for  
conversion on either or both channels of the stereo ADCs. The amplifier output can also be  
accessed at the stereo mixer MIX1 (muting and mixing adjustments via Mic Volume register,  
0Eh) where it is mixed equally into both left and right channels of Stereo Mix 3D for access to  
the stereo outputs Line Out and Line Level Out. Access to the Mono analog output is  
selected by a mux controlled by the MIX bit (D9) in General Purpose register, 20h.  
Left Stereo Channel Input  
MIC2  
22  
I
This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record  
Select Mux for conversion by the left channel ADC. It can also be mixed into the left channel  
of the Stereo Mix 3D signal at MIX1 under the control of the Line In Volume register, 10h. The  
LINE_IN_L level can be muted (along with LINE_IN_R) or adjusted from +12 dB to -34.5 dB  
in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to  
the stereo outputs Line Out and Line Level Out.  
LINE_IN_L  
LINE_IN_R  
23  
24  
I
I
Right Stereo Channel Input  
This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Input  
Mux for conversion by the right channel ADC. It can also be mixed into the right channel of  
the Stereo Mix 3D signal at MIX1 under the control of the Line In Volume register, 10h. The  
LINE_IN_R level can be muted (along with LINE_IN_L) or adjusted from +12 dB to -34.5 dB  
in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to  
the stereo outputs Line Out and Line Level Out.  
Left Stereo Channel Output  
This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal  
from MIX2 via the Master Volume register, 02h. The LINE_OUT_L amplitude can be muted  
(along with LINE_OUT_R) or adjusted from 0 dB to -46.5 dB in 1.5 dB steps.  
Right Stereo Channel Output  
LINE_OUT_L  
LINE_OUT_R  
35  
36  
O
O
This line level output (1 Vrms nominal) is fed from the right channel of the Stereo Mix signal  
from MIX2 via the Master Volume register, 02h. The LINE_OUT_R amplitude can be muted  
(along with LINE_OUT_L) or adjusted from 0 dB to -46.5 dB in 1.5 dB steps.  
Mono Output  
This mono line level output (1 Vrms nominal) is fed from either a microphone input (MIC1 or  
MIC2, after boost amplifier) or from the mono sum of the left and right Stereo Mix 3D  
channels from MIX1. The optional National 3D Sound enhancement can be disabled (default)  
by the 3D bit (bit D13) in the General Purpose register, 20h. Choice of input is by the MIX bit  
(D9) in the same register. MIX=0 selects a microphone input. Output level can be muted or  
adjusted from 0 dB to -46.5 dB in 1.5 dB steps via the Mono Volume register, 06h.  
MONO_OUT  
37  
O
11  
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Pin Descriptions (Continued)  
ANALOG I/O (Continued)  
Name  
Pin  
I / O  
Functional Description  
Left Stereo Channel Output  
This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal  
from MIX2 via the Line Level Volume register, 04h. The LNLVL_OUT_L amplitude can be  
muted (along with LNLVL_OUT_R) or adjusted from 0 dB to - 46.5 dB in 1.5 dB steps  
Right Stereo Channel Output  
LNLVL_OUT_L  
39  
O
This line level output (1 Vrms nominal) is fed from the right channel of the Stereo Mix signal  
from MIX2 via the Line Level Volume register, 04h. The LNLVL_OUT_R amplitude can be  
muted (along with LNLVL_OUT_L) or adjusted from 0 dB to - 46.5 dB in 1.5 dB steps  
LNLVL_OUT_R  
41  
O
DIGITAL I/O AND CLOCKING  
Name  
Pin  
I / O  
Functional Description  
24.576 MHz crystal or oscillator input  
To complete the oscillator circuit use a fundamental mode crystal operating in parallel  
resonance and connect a 1MΩ resistor across pins 2 and 3. Choose the load capacitors  
(Figure 2, C1, C2) to suit the crystal (e.g. C1 = C2 = 33 pF for a crystal designed for a 20 pF  
load. Assumes that each ’Input + trace’ capacitance = 7 pF)  
XTL_IN  
2
I
This pin may also be used as the input for an external oscillator (24.576 MHz nominal) at  
standard logic levels (VIH, VIL).  
This pin is only used when the codec is in Primary mode. It may be left open (NC) for any  
Secondary mode.  
24.576 MHz crystal output  
Used with XTAL_IN to configure a crystal oscillator.  
XTL_OUT  
3
5
O
I
When the codec is used with an external oscillator this pin should be left open (NC).  
When the codec is configured in a Secondary mode this pin is not used and may be left open  
(NC).  
Input to codec  
This is the input for AC Link Output Frames from an AC ’97 Digital Audio Controller to the  
LM4549B codec. These frames can contain both control data and DAC PCM audio data. This  
input is sampled by the LM4549B on the falling edge of BIT_CLK.  
AC Link clock  
SDATA_OUT  
An OUTPUT when in Primary Codec mode. This pin provides a 12.288 MHz clock for the AC  
Link. The clock is derived (internally divided by two) from the 24.576 MHz signal at the crystal  
input (XTL_IN).  
BIT_CLK  
6
8
I/O  
O
This pin is an INPUT when the codec is configured in any of the Secondary Codec modes  
and would normally use the AC Link clock generated by a Primary Codec.  
Output from codec  
This is the output for AC Link Input Frames from the LM4549B codec to an AC ’97 Digital  
Audio Controller. These frames can contain both codec status data and PCM audio data from  
the ADCs. The LM4549B clocks data from this output on the rising edge of BIT_CLK.  
AC Link frame marker and Warm Reset  
SDATA_IN  
This input defines the boundaries of AC Link frames. Each frame lasts 256 periods of  
BIT_CLK. In normal operation SYNC is a 48 kHz positive pulse with a duty cycle of 6.25%  
(16/256). SYNC is sampled on the falling edge of BIT_CLK and the codec takes the first  
positive sample of SYNC as defining the start of a new AC Link frame. If a subsequent SYNC  
pulse occurs within 255 BIT_CLK periods of the frame start it will be ignored.  
SYNC is also used as an active high input to perform an (asynchronous) Warm Reset. Warm  
Reset is used to clear a power down state on the codec AC Link interface.  
SYNC  
10  
I
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12  
Pin Descriptions (Continued)  
DIGITAL I/O AND CLOCKING (Continued)  
Name  
Pin  
I / O  
Functional Description  
Cold Reset  
This active low signal causes a hardware reset which returns the control registers and all  
internal circuits to their default conditions. RESET# MUST be used to initialize the LM4549B  
after Power On when the supplies have stabilized. Cold Reset also clears the codec from  
both ATE and Vendor test modes. In addition, while active, it switches the PC_BEEP mono  
input directly to both channels of the LINE_OUT stereo output.  
RESET#  
11  
I
Codec Identity  
ID1# and ID0# determine the Codec Identity for multiple codec use. The Codec Identity  
configures the codec in either Primary or one of three Secondary Codec modes. These  
Identity pins are of inverted polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14)  
in the read-only Extended Audio ID register, 28h. If the ID0# pin (pin 45) is connected to  
ground then the ID0 bit (D14, reg 28h) will be set to “1”. Similarly, connection to DVDD will set  
the ID0 bit to “0”. If left open (NC), ID0# is pulled high by an internal pull-up resistor.  
Codec Identity  
ID0#  
45  
I
ID1# and ID0# determine the codec address for multiple codec use. The Codec Identity  
configures the codec in either Primary or one of three Secondary Codec modes. These  
Identity pins are of inverted polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14)  
in the read-only Extended Audio ID register, 28h. If the ID1# pin (pin 46) is connected to  
ground then the ID1 bit (D15, reg 28h) will be set to “1”. Similarly, connection to DVDD will set  
the ID1 bit to “0”. If left open (NC), ID1# is pulled high by an internal pull-up resistor.  
External Amplifier Power Down control signal  
ID1#  
46  
47  
I
This output is set by the EAPD bit (bit D15) in the Powerdown Control/ Status register, 26h.  
As with the other logic outputs, the output voltage is set by DVDD. This pin is intended to be  
connected to the shutdown pin on an external power amplifier. For normal operation the  
default value of EAPD = 0 will enable the external amplifier allowing an input on PC_BEEP to  
be heard during Cold Reset.  
EAPD  
O
POWER SUPPLIES AND REFERENCES  
Name  
AVDD  
Pin  
25  
26  
1
I / O  
Functional Description  
I
I
I
I
I
I
Analog supply  
AVSS  
Analog ground  
DVDD1  
DVDD2  
DVSS1  
DVSS2  
Digital supply  
9
Digital supply  
4
Digital ground  
7
Digital ground  
Nominal 2.2 V internal reference  
VREF  
27  
28  
O
O
Not intended to sink or source current. Use short traces to bypass (3.3µF, 0.1µF) this pin to  
maximize codec performance. See text.  
Nominal 2.2 V reference output  
VREF_OUT  
Can source up to 5 mA of current and can be used to bias a microphone.  
3D SOUND AND NO-CONNECTS (NC)  
Name  
Pin  
I / O  
Functional Description  
These pins are used to complete the National 3D Sound stereo enhancement circuit. Connect  
a 0.022 µF capacitor between pins 3DP and 3DN. National 3D Sound can be turned on and  
off via the 3D bit (D13) in the General Purpose register, 20h. National 3D Sound uses a  
fixed-depth type stereo enhancement circuit hence the 3D Control register, 22h is read-only  
and is not programmable. If National 3D Sound is not needed, these pins should be left open  
(NC).  
3DP, 3DN  
33,34  
O
13  
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Pin Descriptions (Continued)  
3D SOUND AND NO-CONNECTS (NC) (Continued)  
Name  
Pin  
I / O  
Functional Description  
29, 30  
31, 32  
38, 40  
42, 43  
44, 48  
These pins are not used and should be left open (NC).  
NC  
NC  
For second source applications these pins may be connected to a noise-free supply or  
ground (e.g. AVDD or AVSS), either directly or through a capacitor.  
Typical Performance Characteristics  
ADC Noise Floor  
DAC Noise Floor  
20123515  
20123516  
Line Out Noise Floor  
(Analog Loopthrough)  
Line Level Out Noise Floor  
(Analog Loopthrough)  
20123518  
20123531  
ADC Frequency  
Response  
DAC Frequency  
Response  
20123519  
20123520  
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14  
V o l u m e O u t p u t  
V o l u m I e n p u t  
S o u r c A e D s C  
15  
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Functional Description  
GENERAL  
3D bit (D13) in the General Purpose register, 20h, and is a  
fixed depth implementation. The 3D Control register, 22h, is  
therefore not programmable (read-only). The 3D Sound cir-  
cuitry defaults to disabled after reset.  
The LM4549B codec can mix, process and convert among  
analog (stereo and mono) and digital (AC Link format) inputs  
and outputs. There are four stereo and four mono analog  
inputs and two stereo and one mono analog outputs. A single  
codec supports data streaming on two input and two output  
channels of the AC Link digital interface simultaneously.  
ANALOG MIXING: MIX2  
MIX2 combines the output of MIX1 (Stereo Mix 3D) with the  
two mono analog inputs, PHONE and PC_BEEP; each are  
level-adjusted by the input control registers Phone Volume  
(0Ch) and PC_Beep Volume (0Ah) respectively. If selected  
by the POP bit (D15, reg 20h), the DAC output is also  
summed into MIX2.  
ADC INPUTS AND OUTPUTS  
All four of the stereo analog inputs and three of the mono  
analog inputs can be selected for conversion by the 18-bit  
stereo ADC. Digital output from the left and right channel  
ADCs is always located in AC Link Input Frame slots 3 and  
4 respectively. Input level to either ADC channel can be  
muted or adjusted from the Record Gain register, 1Ch. Ad-  
justments are in 1.5 dB steps over a gain range of 0 dB to  
+22.5 dB and both channels mute together (mute bit D15).  
Input selection for the ADC is through the Record Select Mux  
controlled from the Record Select register, 1Ah, together  
with microphone selection controlled by the MS bit (bit D8) in  
the General Purpose register, 20h. One of the stereo inputs,  
CD_IN, uses a quasi-differential 3-pin interface where both  
stereo channel inputs are referenced to the third pin,  
CD_GND. CD_GND should be AC coupled to the source  
ground and provides common-mode feedback to cancel  
ground noise. It is not a DC ground. The other three stereo  
inputs, LINE_IN, AUX and VIDEO are 2-pin interfaces,  
single-ended for each stereo channel, with analog ground  
(AVSS) as the signal reference. Either of the two mono  
microphone inputs can be muxed to a programmable boost  
amplifier before selection for either channel of the ADC. The  
Microphone Mux is controlled by the Microphone Selection  
(MS) bit (D8) in the General Purpose register (20h) and the  
20 dB programmable boost is enabled by the 20dB bit (D6)  
in register 0Eh. The mono PHONE input may also be se-  
lected for either ADC channel.  
STEREO MIX  
The output of MIX2 is the signal, Stereo Mix. Stereo Mix is  
used to drive both the Line output (LINE_OUT) and the Line  
Level output (LNLVL_OUT) and can also be selected as the  
input to the ADC by the Record Select Mux. In addition, the  
two channels of Stereo Mix are summed to form a mono  
signal (Mono Mix) also selectable by the Record Select Mux  
as an input to either channel of the ADC.  
STEREO OUTPUTS  
The output volume from LINE_OUT and LNLVL_OUT can be  
muted or adjusted by 0 dB to 45 dB in nominal 3 dB steps  
under the control of the output volume registers Master  
Volume (02h) and Line Level Volume (04h) respectively. As  
with the input volume registers, adjustments to the levels of  
the two stereo channels can be made independently but  
both left and right channels share a mute bit (D15).  
MONO OUTPUT  
The mono output (MONO_OUT) is driven by one of two  
signals selected by the MIX bit (D9) in the General Purpose  
register, 20h. The signal selected by default (MIX = 0) is the  
mono summation of the two channels of Stereo Mix 3D, the  
stereo output of the mixer MIX1. Setting the control bit MIX =  
1, selects a microphone input, MIC1 or MIC2. The choice of  
microphone is controlled by the Microphone Select (MS) bit  
(D8) also in the General Purpose register, 20h.  
ANALOG MIXING: MIX1  
Five analog inputs are available for mixing at the stereo  
mixer, MIX1 – all four stereo and one mono, namely the  
microphone input selected by MS (D8, reg 20h). Digital input  
to the codec can be directed to either MIX1 or to MIX2 after  
conversion by the 18-bit stereo DAC and level adjustment by  
the PCM Out Volume control register (18h). Each input to  
MIX1 may be muted or level adjusted using the appropriate  
Mixer Input Volume Register: Mic Volume (0Eh), Line_In  
Volume (10h), CD Volume (12h), Video Volume (14h), Aux  
Volume (16h) and PCM Out Volume (18h). The mono micro-  
phone input is mixed equally into left and right stereo chan-  
nels but stereo mixing is orthogonal, i.e. left channels are  
only mixed with other left channels and right with right. The  
left and right amplitudes of any stereo input may be adjusted  
independently however mute for a stereo input acts on both  
left and right channels.  
ANALOG LOOPTHROUGH AND DIGITAL LOOPBACK  
Analog Loopthrough refers to an all-analog signal path from  
an analog input through the mixers to an analog output.  
Digital Loopback refers to a mixed-mode analog and digital  
signal path from an analog input through the ADC, looped-  
back (LPBK bit – D7, 20h) through the DAC and mixers to an  
analog output. This is an 18 bit digital loopback at 48 kHz,  
bypassing the the SRC logic even if an SRC rate other than  
48 kHz is selected.  
RESETS  
COLD RESET is performed when RESET# (pin 11) is pulled  
>
low for  
1 µs. It is a complete reset. All registers and  
internal circuits are reset to their default state. It is the only  
reset which clears the ATE and Vendor test modes.  
DAC MIXING AND 3D PROCESSING  
Control of routing the DAC output to MIX1 or MIX2 is by the  
POP bit (D15) in the General Purpose register, 20h. If MIX1  
is selected (default, POP=0) then the DAC output is avail-  
able for processing by the National 3D Sound circuitry. If  
MIX2 is selected, the DAC output will bypass the 3D pro-  
cessing. This allows analog inputs to be enhanced by the  
analog 3D Sound circuitry prior to mixing with digital audio.  
The digital audio may then use alternative digital 3D en-  
hancements. National 3D Sound circuitry is enabled by the  
WARM RESET is performed when SYNC (pin 10) is held  
>
high for 1 µs and the codec AC Link digital interface is in  
powerdown (PR4 = 1, Powerdown Control / Status register,  
26h). It is used to clear PR4 and power up the AC Link digital  
interface but otherwise does not change the contents of any  
internal circuitry.  
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16  
default state and will modify circuit configurations accord-  
ingly but does not reset any other internal circuits.  
Functional Description (Continued)  
REGISTER RESET is performed when any value is written  
to the RESET register, 00h. It resets all registers to their  
AC Link Serial Interface Protocol  
20123504  
FIGURE 3. AC Link Bidirectional Audio Frame  
20123506  
FIGURE 4. AC Link Output Frame  
AC LINK OUTPUT FRAME:  
SDATA_OUT, CONTROLLER OUTPUT TO LM4549B INPUT  
The AC Link Output Frame carries control and PCM data to  
the LM4549B control registers and stereo DAC. Output  
Frames are carried on the SDATA_OUT signal which is an  
output from the AC ’97 Digital Controller and an input to the  
LM4549B codec. As shown in Figure 3, Output Frames are  
constructed from thirteen time slots: one Tag Slot followed by  
twelve Data Slots. Each Frame consists of 256 bits with each  
of the twelve Data Slots containing 20 bits. Input and Output  
Frames are aligned to the same SYNC transition. Note that  
since the LM4549B is a two channel codec, it only accepts  
data in 4 of the twelve Data Slots – 2 for control, one each for  
PCM data to the left and right channel DACs. Data Slot 3 &  
4 are used to stream data to the stereo DAC for all modes  
selected by the Identity pins ID1#, ID0#.  
rising edge of BIT_CLK and, as shown in Figure 4 and  
Figure 5, the first tag bit in the Frame (“Valid Frame”) should  
be clocked from the controller by the next rising edge of  
BIT_CLK and sampled by the LM4549B on the following  
falling edge. The AC ’97 Controller should always clock data  
to SDATA_OUT on a rising edge of BIT_CLK and the  
LM4549B always samples SDATA_OUT on the next falling  
edge. SYNC is sampled with the falling edge of BIT_CLK.  
The LM4549B checks each Frame to ensure 256 bits are  
received. If a new Frame is detected (a low-to-high transition  
on SYNC) before 256 bits are received from the old Frame  
then the new Frame is ignored i.e. the data on SDATA_OUT  
is discarded until a valid new Frame is detected.  
The LM4549B expects to receive data MSB first, in an MSB  
justified format.  
A new Output Frame is signaled with a low-to-high transition  
of SYNC. SYNC should be clocked from the controller on a  
17  
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AC Link Serial Interface Protocol  
Bit  
Description  
Comment  
1 = Valid PCM Data in Slot 4  
(Primary & all Secondary  
modes)  
(Continued)  
Right DAC data  
in Slot 4  
11  
SDATA_OUT: Slot 0 – Tag Phase  
The first bit of Slot 0 is designated the "Valid Frame" bit. If  
this bit is 1, it indicates that the current Output Frame con-  
tains at least one slot of valid data and the LM4549B will  
check further tag bits for valid data in the expected Data  
Slots. With the codec in Primary mode, a controller will  
indicate valid data in a slot by setting the associated tag bit  
equal to 1. Since it is a two channel codec the LM4549B can  
only receive data from four slots in a given frame and so only  
checks the valid-data bits for 4 slots. In Primary mode these  
tag bits are for: slot 1 (Command Address), slot 2 (Command  
Data), slot 3 (PCM data for left DAC) and slot 4 (PCM data  
for right DAC).  
Controller should stuff these  
slots with “0”s  
10:2  
1,0  
Not Used  
The codec ID is used in a  
multi-codec system to identify  
the target Secondary codec for  
the Control Register address  
and/or data sent in the Output  
Frame  
Codec ID  
(ID1, ID0)  
SDATA_OUT: Slot 1 – Read/Write, Control Address  
The last two bits in the Tag contain the Codec ID used to  
select the target codec to receive the frame in multiple codec  
systems. When the frame is being sent to a codec in one of  
the Secondary modes the controller does not use bits 14 and  
13 to indicate valid Command Address and Data in slots 1  
and 2. Instead, this role is performed by the Codec ID bits –  
operation of the Extended AC Link assumes that the control-  
ler would not access a secondary codec unless it was pro-  
viding valid Command Address and/or Data. When in one of  
the secondary modes the LM4549B only checks the tag bits  
for the Codec ID and for valid data in the two audio data slots  
3 & 4.  
Slot 1 is used by a controller to indicate both the address of  
a target register in the LM4549B and whether the access  
operation is a register read or register write. The MSB of slot  
1 (bit 19) is set to 1 to indicate that the current access  
operation is ’read’. Bits 18 through 12 are used to specify the  
7-bit register address of the read or write operation. The  
least significant twelve bits are reserved and should be  
stuffed with zeros by the AC ’97 controller.  
SLOT 1, OUTPUT FRAME  
Bits  
Description  
Comment  
When sending an Output Frame to a Secondary mode co-  
dec, a controller should set tag bits 14 and 13 to zero.  
1 = Read  
0 = Write  
19  
Read/Write  
Register  
Address  
Reserved  
Identifies the Status/Command  
register for read/write  
18:12  
11:0  
Controller should set to "0"  
SDATA_OUT: Slot 2 – Control Data  
Slot 2 is used to transmit 16-bit control data to the LM4549B  
when the access operation is ’write’. The least significant  
four bits should be stuffed with zeros by the AC ’97 controller.  
If the access operation is a register read, the entire slot, bits  
19 through 0 should be stuffed with zeros.  
SLOT 2, OUTPUT FRAME  
20123505  
Bits  
Description  
Comment  
Control  
Controller should stuff with  
FIGURE 5. Start of AC Link Output Frame  
19:4 Register Write zeros if operation is “read”  
Data  
SLOT 0, OUTPUT FRAME  
3:0  
Reserved  
Set to "0"  
Bit  
Description  
Comment  
1 = Valid data in at least one  
slot.  
SDATA_OUT: Slots 3 & 4 – PCM Playback Left/Right  
Channels  
15  
Valid Frame  
Slots 3 and 4 are 20-bit fields used to transmit PCM data to  
the left and right channels of the stereo DAC for all codec  
Primary and Secondary modes. Any unused bits should be  
stuffed with zeros. The LM4549B DACs have 18-bit resolu-  
tion and will therefore use the 18 MSBs of the 20-bit PCM  
data (MSB justified).  
1 = Valid Control Address in  
Slot 1 (Primary codec  
only)  
Control register  
address  
14  
13  
12  
Control register 1 = Valid Control Data in Slot  
data  
2 (Primary codec only)  
1 = Valid PCM Data in Slot 3  
(Primary & all Secondary  
modes)  
Left DAC data  
in Slot 3  
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18  
SDATA_OUT: Slots 5 to 12 – Reserved  
AC Link Serial Interface Protocol  
These slots are not used by the LM4549B and should all be  
stuffed with zeros by the AC ’97 Controller.  
(Continued)  
SLOTS 3 & 4, OUTPUT FRAME  
Bits  
Description  
Comment  
Slots used to stream data to  
DACs for all Primary or  
Secondary modes.  
PCM DAC Data  
(Left /Right  
19:0  
Channels)  
Set unused bits to "0"  
20123508  
FIGURE 6. AC Link Input Frame  
AC LINK INPUT FRAME:  
SDATA_IN, CONTROLLER INPUT FROM LM4549B OUTPUT  
The AC Link Input Frame contains status and PCM data from  
the LM4549B control registers and stereo ADC. Input  
Frames are carried on the SDATA_IN signal which is an  
input to the AC ’97 Digital Audio Controller and an output  
from the LM4549B codec. As shown in Figure 3, Input  
Frames are constructed from thirteen time slots: one Tag  
Slot followed by twelve Data Slots. The Tag Slot, Slot 0,  
contains 16 bits of which 5 are used by the LM4549B. One is  
used to indicate that the AC Link interface is fully operational  
and the other 4 to indicate the validity of the data in the four  
of the twelve following Data Slots that are used by the  
LM4549B. Each Frame consists of 256 bits with each of the  
twelve data slots containing 20 bits.  
The LM4549B transmits data MSB first, in a MSB justified  
format. All reserved bits and slots are stuffed with "0"s by the  
LM4549B.  
A new Input Frame is signaled with a low-to-high transition of  
SYNC. SYNC should be clocked from the controller on a  
rising edge of BIT_CLK and, as shown in Figure 6 and  
Figure 7, the first tag bit in the Frame (“Codec Ready”) is  
clocked from the LM4549B by the next rising edge of  
BIT_CLK. The LM4549B always clocks data to SDATA_IN  
on a rising edge of BIT_CLK and the controller is expected to  
sample SDATA_IN on the next falling edge. The LM4549B  
samples SYNC on the falling edge of BIT_CLK.  
20123507  
FIGURE 7. Start of AC Link Input Frame  
Input and Output Frames are aligned to the same SYNC  
transition.  
SDATA_IN: Slot 0 – Codec/Slot Status Bits  
The first bit (bit 15, “Codec Ready”) of slot 0 in the AC Link  
Input Frame indicates when the codec’s AC Link digital  
interface and its status/control registers are fully operational.  
The digital controller is then able to read the LSBs from the  
Powerdown Control/Stat register (26h) to determine the sta-  
tus of the four main analog subsections. It is important to  
The LM4549B checks each Frame to ensure 256 bits are  
received. If a new Frame is detected (a low-to-high transition  
on SYNC) before 256 bits are received from an old Frame  
then the new Frame is ignored i.e. no valid data is sent on  
SDATA_IN until a valid new Frame is detected.  
19  
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48000 Hz, then only those one-in-six audio samples that  
follow a Slot Request will be used by the DAC. The rest will  
be discarded.  
AC Link Serial Interface Protocol  
(Continued)  
check the status of these subsections after Initialization,  
Cold Reset, or the use of the powerdown modes in order to  
minimize the risk of distorting analog signals passed before  
the subsections are ready.  
Bits 9 – 2 are request bits for slots not used by the LM4549B  
and are stuffed with zeros. Bits 1 and 0 are reserved and are  
also stuffed with zeros.  
The 4 bits 14, 13, 12 and 11 indicate that the data in slots 1,  
2, 3 and 4, respectively, are valid.  
SLOT 1, INPUT FRAME  
Bits  
Description  
Comment  
19  
Reserved  
Stuffed with "0" by LM4549B  
SLOT 0, INPUT FRAME  
Status Register Echo of the requested Status  
Bit  
Description  
Codec Ready  
Bit  
Comment  
18:12  
Index  
Register address.  
1 = AC Link Interface Ready  
15  
0 = Controller should send  
valid data in Slot 3 of the  
next Output Frame.  
Slot 3 Request  
bit  
Slot 1 data  
valid  
1 = Valid Status Address or  
Slot Request  
11  
14  
13  
12  
11  
(For left DAC  
PCM data)  
1 = Controller should not  
send Slot 3 data.  
Slot 2 data  
valid  
1 = Valid Status Data  
0 = Controller should send  
valid data in Slot 4 of the  
next Output Frame.  
Slot 4 Request  
bit  
Slot 3 data  
valid  
1 = Valid PCM Data  
(Left ADC)  
10  
(For right DAC  
PCM data)  
Slot 4 data  
valid  
1 = Valid PCM Data  
(Right ADC)  
1 = Controller should not  
send Slot 4 data.  
Unused Slot  
Request bits  
Reserved  
9:2  
1,0  
Stuffed with "0"s by LM4549B  
Stuffed with "0"s by LM4549B  
SDATA_IN: Slot 1 – Status Address / Slot Request Bits  
This slot echoes (in bits 18 – 12) the 7-bit address of the  
codec control/status register received from the controller as  
part of a read-request in the previous frame. If no read-  
request was received, the codec stuffs these bits with zeros.  
SDATA_IN: Slot 2 – Status Data  
Bits 11, 10 are Slot Request bits that support the Variable  
Rate Audio (VRA) capabilities of the LM4549B. For all codec  
Primary and Secondary modes, the left and right channels of  
the DAC take PCM data from slots 3 and 4 in the Output  
Frame respectively. The codec uses bits 11 and 10 to re-  
quest DAC data from these two slots. If bits 11 and 10 are set  
to 0, the controller should respond with valid PCM data in  
slots 3 and 4 of the next Output Frame. If bits 11 and 10 are  
set to 1, the controller should not send data.  
This slot returns 16-bit status data read from a codec control/  
status register. The codec sends the data in the frame fol-  
lowing a read-request by the controller (bit 15, slot 1 of the  
Output Frame). If no read-request was made in the previous  
frame the codec will stuff this slot with zeros.  
SLOT 2, INPUT FRAME  
Bits  
19:4  
3:0  
Description  
Status Data  
Reserved  
Comment  
The codec has full control of the slot request bits. By default,  
data is requested in every frame, corresponding to a sample  
rate equal to the frame rate (SYNC frequency) – 48 kHz  
when XTAL_IN = 24.576 MHz. To send samples at a rate  
below the frame rate, a controller should set VRA = 1 (bit 0  
in the Extended Audio Control/Status register, 2Ah) and  
program the desired rate into the PCM DAC Rate register,  
2Ch. Both DAC channels operate at the same sample rate.  
Values for common sample rates are given in the Register  
Description section (Sample Rate Control Registers, 2Ch,  
32h) but any rate between 4 kHz and 48 kHz (to a resolution  
of 1 Hz) is supported. Slot Requests from the LM4549B are  
issued completely deterministically. For example if a sample  
rate of 8000 Hz is programmed into 2Ch then the LM4549B  
will always issue a slot request in every sixth frame. A  
frequency of 9600 Hz will result in a request every fifth frame  
while a frequency of 8800 Hz will cause slot requests to be  
spaced alternately five and six frames apart. This determin-  
ism makes it easy to plan task scheduling on a system  
controller and simplifies application software development.  
Data read from a codec  
control/status register.  
Stuffed with “0”s if no  
read-request in previous frame.  
Stuffed with "0"s by LM4549B  
SDATA_IN: Slot 3 – PCM Record Left Channel  
This slot contains sampled data from the left channel of the  
stereo ADC. The signal to be digitized is selected using the  
Record Select register (1Ah) and subsequently routed  
through the Record Select Mux and the Record Gain ampli-  
fier to the ADC.  
This is a 20-bit slot and the digitized 18-bit PCM data is  
transmitted in an MSB justified format. The remaining 2  
LSBs are stuffed with zeros.  
SLOT 3, INPUT FRAME  
Bits  
Description  
Comment  
The LM4549B will ignore data in Output Frame slots that do  
not follow an Input Frame with a Slot Request. For example,  
if the LM4549B is expecting data at a 8000 Hz rate yet the  
AC ’97 Digital Audio Controller continues to send data at  
PCM Record 18-bit PCM sample from left  
19:2  
Left Channel ADC  
data  
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20  
SLOT 4, INPUT FRAME  
Description Comment  
PCM Record 18-bit PCM sample from right  
AC Link Serial Interface Protocol  
(Continued)  
Bits  
SLOT 3, INPUT FRAME (Continued)  
19:2 Right Channel ADC  
data  
Bits  
Description  
Comment  
1:0  
Reserved  
Stuffed with "0"s by LM4549B  
1:0  
Reserved  
Stuffed with "0"s by LM4549B  
SDATA_IN: Slot 4 – PCM Record Right Channel  
SDATA_IN: Slots 5 to 12 – Reserved  
This slot contains sampled data from the right channel of the  
stereo ADC. The signal to be digitized is selected using the  
Record Select register (1Ah) and subsequently routed  
through the Record Select Mux and the Record Gain ampli-  
fier to the ADC.  
Slots 5 – 12 of the AC Link Input Frame are not used for data  
by the LM4549B and are always stuffed with zeros.  
This is a 20-bit slot and the digitized 18-bit PCM data is  
transmitted in an MSB justified format. The remaining 2  
LSBs are stuffed with zeros.  
21  
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Register Descriptions  
Default settings are indicated by *.  
PC BEEP VOLUME REGISTER (0Ah)  
This input register adjusts the level of the mono PC_BEEP  
input to the stereo mixer MIX2 where it is summed equally  
into both channels of the Stereo Mix signal. PC_BEEP can  
be both muted and attenuated over a range of 0 dB to –45  
dB in nominal 3 dB steps. Note that the default setting for the  
PC_Beep Volume register is 0 dB attenuation rather than  
mute.  
RESET REGISTER (00h)  
Writing any value to this register causes a Register Reset  
which changes all registers back to their default values. If a  
read is performed on this register, the LM4549B will return a  
value of 0D40h. This value can be interpreted in accordance  
with the AC ’97 Specification to indicate that National 3D  
Sound is implemented and 18-bit data is supported for both  
the ADCs and DACs.  
Mute  
PV3:PV0  
0000  
Function  
*0 dB attenuation  
45 dB attenuation  
mute  
0
MASTER VOLUME REGISTER (02h)  
0
1111  
This output register allows the output level from either chan-  
nel of the stereo LINE_OUT to be muted or attenuated over  
the range 0 dB – 46.5 dB in nominal 1.5 dB steps. There are  
6 bits of volume control for each channel and both stereo  
channels can be individually attenuated. The mute bit (D15)  
acts simultaneously on both stereo channels of LINE_OUT.  
The AC’97 specification states that “support for the MSB of  
the level is optional.” All six bits may be written to the  
register, but if the MSB is a ’1’, the MSB is ignored and the  
register will be set to 0 11111. This will be the value when the  
register is read, allowing the software driver to detect  
whether the MSB is supported or not.  
1
XXXX  
Default: 0000h  
MIXER INPUT VOLUME REGISTERS (Index 0Ch - 18h)  
These input registers adjust the volume levels into the stereo  
mixers MIX1 and MIX2. Each channel may be adjusted over  
a range of +12 dB gain to –34.5 dB attenuation in 1.5 dB  
steps. For stereo ports, volumes of the left and right chan-  
nels can be independently adjusted. Muting a given port is  
accomplished by setting the MSB to 1. Setting the MSB to 1  
for stereo ports mutes both the left and right channels. The  
Mic Volume register (0Eh) controls an additional 20 dB boost  
for the selected microphone input by setting the 20dB bit  
(D6).  
Mute  
Mx5:Mx0  
0 00000  
0 11111  
Function  
0 dB attenuation  
46.5 dB attenuation  
As Written  
0
0
Mute  
Gx4:Gx0  
0 0000  
0 1000  
1 1111  
Function  
+12 dB gain  
0
1 xxxxx  
0
0
0 11111  
As read back  
*mute  
0
0 dB gain  
1
X XXXXX  
0
1
–34.5 dB attenuation  
*mute  
Default: 8000h  
X XXXX  
Default:  
8008h (mono registers)  
8808h (stereo registers)  
LINE LEVEL VOLUME REGISTER (04h)  
This output register allows the level from both channels of  
LNLVL_OUT to be muted or individually attenuated over the  
range 0 dB to –46.5 dB in nominal 1.5 dB steps. There are 6  
bits of volume control for each channel plus one mute bit.  
The mute bit (D15) acts on both channels. Operation of this  
register and LNLVL_OUT matches that of the Master Volume  
register and the LINE_OUT output.  
RECORD SELECT REGISTER (1Ah)  
This register independently controls the sources for the right  
and left channels of the stereo ADC. The default value of  
0000h corresponds to selecting the (mono) Mic input for both  
channels.  
MONO VOLUME REGISTER (06h)  
SL2:SL0  
Source for Left Channel ADC  
*Mic input  
This output register allows the level from MONO_OUT to be  
muted or attenuated over the range 0 dB – 46.5 dB in  
nominal 1.5 dB steps. There are 6 bits of volume control and  
one mute bit (D15). All six bits may be written to the register,  
but if the MSB is a 1, the MSB is ignored and the register will  
be set to 0 11111. This will be the value when the register is  
read, allowing the software driver to detect whether the MSB  
is supported or not.  
0
1
2
3
4
5
6
7
CD input (L)  
VIDEO input (L)  
AUX input (L)  
LINE_IN input (L)  
Stereo Mix (L)  
Mono Mix  
Mute  
MM5:MM0  
0 00000  
0 11111  
Function  
0 dB attenuation  
46.5 dB attenuation  
As written  
PHONE input  
0
0
0
0
1
SR2:SR0  
Source for Right Channel ADC  
*Mic input  
0
1
2
3
4
5
1 xxxxx  
CD input (R)  
0 11111  
As read back  
*mute  
VIDEO input (R)  
AUX input (R)  
X XXXXX  
Default: 8000h  
LINE_IN input (R)  
Stereo Mix (R)  
www.national.com  
22  
POWERDOWN CONTROL / STATUS REGISTER (26h)  
Register Descriptions (Continued)  
This read/write register is used both to monitor subsystem  
readiness and also to program the LM4549B powerdown  
states. The 4 LSBs indicate status and 7 of the 8 MSBs  
control powerdown.  
SR2:SR0  
Source for Right Channel ADC  
Mono Mix  
6
7
PHONE input  
The 4 LSBs of this register indicate the status of the 4 audio  
subsections of the codec: Reference voltage, Analog mixers  
and amplifiers, DAC section, ADC section. When the "Codec  
Ready" indicator bit in the AC Link Input Frame (SDATA_IN:  
slot 0, bit 15) is a "1", it indicates that the AC Link and AC ’97  
registers are in a fully operational state and that control and  
status information can be transferred. It does NOT indicate  
that the codec is ready to send or receive audio PCM data or  
to pass signals through the analog I/O and mixers. To deter-  
mine that readiness, the Controller must check that the 4  
LSBs of this register are set to “1” indicating that the appro-  
priate audio subsections are ready.  
Default: 0000h  
RECORD GAIN REGISTER (1Ch)  
This register controls the input levels for both channels of the  
stereo ADC. The inputs come from the Record Select Mux  
and are selected via the Record Select Control register, 1Ah.  
The gain of each channel can be individually programmed  
from 0dB to +22.5 dB in 1.5 dB steps. Both channels can  
also be muted by setting the MSB to 1.  
The powerdown bits PR0 – PR5 control internal subsections  
of the codec. They are implemented in compliance with AC  
’97 Rev 2.1 to support the standard device power manage-  
ment states D0 – D3 as defined in the ACPI and PCI Bus  
Power Management Specification.  
Record Gain Register (1Ch)  
Mute  
Gx3:Gx0  
1111  
Function  
22.5 dB gain  
0
0
0000  
0 dB gain  
*mute  
PR0 controls the powerdown state of the ADC and associ-  
ated sampling rate conversion circuitry. PR1 controls power-  
down for the DAC and the DAC sampling rate conversion  
circuitry. PR2 powers down the mixer circuits (MIX1, MIX2,  
National 3D Sound, Mono Out, Line Out). PR3 powers down  
VREF in addition to all the same mixer circuits as PR2. PR4  
powers down the AC Link digital interface – see Figure 8 for  
signal powerdown timing. PR5 disables internal clocks. PR6  
is not used. EAPD controls the External Amplifier Power-  
Down bit.  
1
XXXX  
Default: 8000h  
GENERAL PURPOSE REGISTER (20h)  
This register controls many miscellaneous functions imple-  
mented on the LM4549B. The miscellaneous control bits  
include POP which allows the DAC output to bypass the  
National 3D Sound circuitry, 3D which enables or disables  
the National 3D Sound circuitry, MIX which selects the MO-  
NO_OUT source, MS which controls the Microphone Selec-  
tion mux and LPBK which connects the output of the stereo  
ADC to the input of the stereo DAC. LPBK provides a  
mixed-mode analog and digital loopback path between ana-  
log inputs and analog outputs. This is an 18 bit digital loop-  
back at 48 kHz, bypassing the SRC logic, even if a sample  
rate other than 48 kHz is selected.  
BIT#  
BIT  
Function: Status  
1 = ADC section ready to  
transmit data  
0
ADC  
1 = DAC section ready to  
accept data  
1
DAC  
2
3
ANL  
REF  
1 = Analog mixers ready  
1 = VREF is up to nominal level  
BIT  
Function  
*0 = 3D allowed  
PCM Out Path:  
National 3D Sound:  
Mono output select:  
Mic select:  
BIT#  
8
BIT  
PR0  
PR1  
PR2  
Function: Powerdown  
1 = Powerdown ADCs and  
Record Select Mux  
POP  
1 = 3D bypassed  
*0 = off  
3D  
MIX  
MS  
1 = on  
9
1 = Powerdown DACs  
1 = Powerdown Analog Mixer  
(VREF still on)  
*0 = Mix  
10  
1 = Mic  
*0 = MIC1  
1 = MIC2  
1 = Powerdown Analog Mixer  
(VREF off)  
11  
12  
PR3  
PR4  
ADC/DAC Loopback: *0 = No Loopback  
1 = Loopback  
1 = Powerdown AC Link digital  
interface (BIT_CLK off)  
1 = Disable Internal Clock  
Not Used  
LPBK  
13  
14  
PR5  
PR6  
Default: 0000h  
External Amplifier PowerDown  
*0 = Set EAPD Pin to 0 (pin 47)  
3D CONTROL REGISTER (22h)  
15  
EAPD  
This read-only (0101h) register indicates, in accordance with  
the AC ’97 Rev 2.1 Specification, the fixed depth and center  
characteristics of the National 3D Sound stereo enhance-  
ment.  
Default: 000Fh If ready; otherwise 000Xh  
EXTENDED AUDIO ID REGISTER (28h)  
This read-only (X001h) register identifies which AC ’97 Ex-  
tended Audio features are supported. The LM4549B features  
VRA (Variable Rate Audio) and ID1, ID0 (Multiple Codec  
23  
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for Microsoft’s Plug and Play. The last 8 bits are the two  
binary coded decimal characters, 4, 9 and identify the codec  
to be an LM4549B.  
Register Descriptions (Continued)  
support). VRA is indicated by a "1" in bit 0. The two MSBs,  
ID1 and ID0, show the current Codec Identity as defined by  
the Identity pins ID1#, ID0#. Note that the external logic  
connections to ID1#, ID0# (pins 46 and 45) are inverse in  
polarity to the value of the Codec Identity (ID1, ID0) held in  
bits D15, D14. Codec mode selections are shown in the  
table below.  
RESERVED REGISTERS  
Do not write to reserved registers. In particular, do not write  
to registers 24h, 5Ah, 74h and 7Ah. All registers not listed in  
the LM4549B Register Map are reserved. Reserved regis-  
ters will return 0000h if read.  
Pin 46  
(ID1#)  
Pin 45 D15,28h D14,28h Codec Identity  
(ID0#)  
(ID1)  
(ID0)  
Mode  
Primary  
Low Power Modes  
NC/DVDD NC/DVDD  
0
0
1
1
0
1
0
1
The LM4549B provides 6 bits to control the powerdown state  
of internal analog and digital subsections and clocks. It also  
provides one bit intended to control an external analog  
power amplifier. These 7 bits (PR0 – PR5, EAPD) are lo-  
cated in the 8 MSBs of the Powerdown Control/Status reg-  
ister, 26h. The status of the four main analog subsections is  
given by the 4 LSBs in the same register, 26h.  
NC/DVDD  
GND  
GND  
NC/DVDD  
GND  
Secondary 1  
Secondary 2  
Secondary 3  
GND  
EXTENDED AUDIO STATUS/CONTROL REGISTER  
(2Ah)  
The powerdown bits are implemented in compliance with AC  
’97 Rev 2.1 to support the standard device power manage-  
ment states D0 – D3 as defined in the ACPI and PCI Bus  
Power Management Specification.  
This read/write register provides status and control of the  
variable sample rate capabilities in the LM4549B. Setting the  
LSB of this register to "1" enables Variable Rate Audio (VRA)  
mode and allows DAC and ADC sample rates to be pro-  
grammed via registers 2Ch and 32h respectively.  
PR0 controls the powerdown state of the ADC and associ-  
ated sampling rate conversion circuitry. PR1 controls power-  
down for the DAC and the DAC sampling rate conversion  
circuitry. PR2 powers down the mixer circuits (MIX1, MIX2,  
National 3D Sound, Mono Out, Line Out). PR3 powers down  
VREF in addition to all the same mixer circuits as PR2. PR4  
powers down the AC Link Digital Interface – see Figure 8 for  
signal powerdown timing. PR5 disables internal clocks but  
leaves the crystal oscillator and BIT_CLK running (needed  
for minimum Primary mode powerdown dissipation in multi-  
codec systems). PR6 is not used. EAPD controls the Exter-  
nal Amplifier PowerDown pin (pin 47).  
BIT  
Function  
*0 = VRA off (Frame-rate sampling)  
1 = VRA on  
VRA  
Default: 0000h  
SAMPLE RATE CONTROL REGISTERS (2Ch, 32h)  
These read/write registers are used to set the sample rate  
for the left and right channels of the DAC (PCM DAC Rate,  
2Ch) and the ADC (PCM ADC Rate, 32h). When Variable  
Rate Audio is enabled via bit 0 of the Extended Audio  
Control/Status register (2Ah), the sample rates can be pro-  
grammed, in 1 Hz increments, to be any value from 4 kHz to  
48 kHz. The value required is the hexadecimal representa-  
tion of the desired sample rate, e.g. 800010 = 1F40h. Below  
is a list of the most common sample rates and the corre-  
sponding register (hex) values.  
After a subsection has undergone a powerdown cycle, the  
appropriate status bit(s) in the Powerdown Control/Status  
register (26h) must be polled to confirm readiness. In par-  
ticular the startup time of the VREF circuitry depends on the  
value of the decoupling capacitors on pin 27 (3.3 µF, 0.1 µF  
in parallel is recommended).  
When the AC Link Digital Interface is powered down the  
codec output signals SDATA_IN and BIT_CLK (Primary  
mode) are cleared to zero and no control data can be passed  
between controller and codec(s). This powerdown state can  
be cleared in two ways: Cold Reset (RESET# = 0) or Warm  
Reset (SYNC = 1, no BIT_CLK). Cold Reset sets all regis-  
ters back to their default values (including clearing PR4)  
whereas Warm Reset only clears the PR4 bit and restarts  
the AC Link Digital Interface leaving all register contents  
otherwise unaffected. For Warm Reset (see Timing Dia-  
grams), the SYNC input is used asynchronously. The  
LM4549B codec allows the AC Link digital interface power-  
down state to be cleared immediately so that its duration can  
be essentially as short as TSH, the Warm Reset pulse width.  
However for conformance with AC ’97 Rev 2.1, Warm Reset  
should not be applied within four frame times of powerdown  
i.e. the AC Link powerdown state should be allowed to last at  
least 82.8 µs.  
Common Sample Rates  
SR15:SR0  
1F40h  
Sample Rate (Hz)  
8000  
2B11h  
11025  
3E80h  
16000  
5622h  
22050  
AC44h  
*BB80h  
44100  
*48000  
VENDOR ID REGISTERS (7Ch, 7Eh)  
These two read-only (4E53h, 4349h) registers contain Na-  
tional’s Vendor ID and National’s LM45xx codec version  
designation. The first 24 bits (4Eh, 53h, 43h) represent the  
three ASCII characters “NSC” which is National’s Vendor ID  
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24  
Low Power Modes (Continued)  
20123509  
FIGURE 8. AC Link Powerdown Timing  
dB point will still be below 300 Hz. By using a smaller  
capacitor, the package size may be reduced, leading to a  
lower system cost.  
Improving System Performance  
The audio codec is capable of dynamic range performance  
in excess of 90 db., but the user must pay careful attention to  
several factors to achieve this. A primary consideration is  
keeping analog and digital grounds separate, and connect-  
ing them together in only one place. Some designers show  
the connection as a zero ohm resistor, which allows naming  
the nets separately. Although it is possible to use a two layer  
board, it is recommended that a minimum of four layers be  
used, with the two inside layers being analog ground and  
digital ground. If EMI is a system consideration, then as  
many as eight layers have been successfully used. The 12  
and 25 MHz. clocks can have significant harmonic content  
depending on the rise and fall times. Bypass capacitors  
should be very close to the package. The analog VDD pins  
should be supplied from a separate regulator to reduce  
noise. By operating the digital portion on 3.3V instead of 5V,  
an additional 0.5-0.7 db improvement can be obtained.  
Backwards Compatibility  
The LM4549B is improved compared with the LM4549A. If it  
is required to build a board that will use either part, a 10 kΩ  
resistor must be added from the VREF pin (pin 27) to AVDD for  
the LM4549A. It is not required for the LM4549B. Addition of  
this resistor will slightly increase the temperature coefficient  
of the internal bandgap reference and decrease the THD  
performance, but overall performance will still be better than  
the LM4549A. The LM4549A requires that pins 1 and 9  
(DVDD) connect directly to a 27 nH. inductor before going to  
the 3.3 Volt digital supply and the bypass capacitors. The  
inductor is not required for the LM4549B and should not be  
used.  
The bandgap reference and the anti-pop slow turn-on circuit  
were improved in the LM4549B. A pullup resistor is not  
required on VREF, pin 27. For an existing design, the 10 kΩ  
resistor can be left on the pc board, but the temperature  
coefficient will improve with no resistor on this pin. In addi-  
tion, the THD will improve by 0.2–0.5 dB. The external  
capacitor is charged by an internal current source, ramping  
the voltage slowly. This results in slow turn-on of the audio  
stages, eliminating “pops and clicks”. Thus, turn-on perfor-  
mance is also improved. The pullup resistor, in conjunction  
with the internal impedance and the external capacitor, form  
a frequency dependent divider from the analog supply. Noise  
on the analog supply will be coupled into the audio path, with  
approximately 30 dB. of attenuation. Although this is not a  
large amount if the noise on the supply is tens of millivolts, it  
will prevent SNR from exceeding 80 dB.  
Multiple Codecs  
EXTENDED AC LINK  
Up to four codecs can be supported on the extended AC  
Link. These multiple codec implementations should run off a  
common BIT_CLK generated by the Primary Codec. All  
codecs share the AC ’97 Digital Controller output signals,  
SYNC, SDATA_OUT, and RESET#. Each codec, however,  
supplies its own SDATA_IN signal back to the controller, with  
the result that the controller requires one dedicated input pin  
per codec. (Figure 9).  
By definition there can be one Primary Codec and up to  
three Secondary Codecs on an extended AC Link. The  
Primary Codec has a Codec Identity = (ID1, ID0) = ID = 00  
while Secondary Codecs may have identities equal to 01, 10  
or 11. The Codec Identity is used as a chip select function.  
This allows the Command and Status registers in any of the  
codecs to be individually addressed although the access  
mechanism for Secondary Codecs differs slightly from that  
for a Primary.  
In Figure 1 and Figure 2, the input coupling capacitors are  
shown as 1 µF capacitors. This is only necessary for extend-  
ing the response down to 20 Hz. for music applications. For  
telematics or voice applications, thelower 3 dB. point can be  
much higher. Using a guaranteed input resistance of 10 kΩ,  
(40 kΩ typical), a 0.1 µF capacitor may be used. The lower 3  
The Identity control pins, ID1#, ID0# (pins 46 and 45) are  
internally pulled up to DVDD. The Codec may therefore be  
25  
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When reading from a Secondary Codec, the controller must  
send the correct Codec ID bits (i.e. the target Codec Identity  
in slot 0, bits 1 and 0) along with the read-request bit (slot 1,  
bit 19) and target register address (slot 1, bits 18 – 12). To  
write to a Secondary Codec, a controller must send the  
correct Codec ID bits when slot 1 contains a valid target  
register address and “write” indicator bit and slot 2 contains  
valid target register data. A write operation is only valid if the  
register address and data are both valid and sent within the  
same frame. When accessing the Primary Codec, the Codec  
ID bits are cleared and the tag bits 14 and 13 resume their  
role indicating the validity of Command Address and Data in  
slots 1 and 2.  
Multiple Codecs (Continued)  
configured as ’Primary’ either by leaving ID1#, ID0# open  
(NC) or by strapping them externally to DVDD (Digital Sup-  
ply).  
The difference between Primary and Secondary codec  
modes is in their timing source and in the Tag Bit handling in  
Output Frames for Command/Status register access. For a  
timing source, a Primary codec divides down by 2 the fre-  
quency of the signal on XTAL_IN and also generates this as  
the BIT_CLK output for the use of the controller and any  
Secondary codecs. Secondary codecs use BIT_CLK as an  
input and as their timing source and do not use XTAL_IN or  
XTAL_OUT. The use of Tag Bits is described below.  
The use of the tag bits in Input Frames (carried by the  
SDATA_IN signal) is the same for Primary and Secondary  
Codecs.  
SECONDARY CODEC REGISTER ACCESS  
For Secondary Codec access, the controller must set the tag  
bits for Command Address and Data in the Output Frame as  
invalid (i.e. equal to 0). The Command Address and Data tag  
bits are in slot 0, bits 14 and 13 and Output Frames are  
those in the SDATA_OUT signal from controller to codec.  
The controller must also place the non-zero value (01, 10, or  
11) corresponding to the Identity (ID1, ID0) of the target  
Secondary Codec into the Codec ID field (slot 0, bits 1 and 0)  
in that same Output Frame. The value set in the Codec ID  
field determines which of the three possible Secondary Co-  
decs is accessed. Unlike a Primary Codec, a Secondary  
Codec will disregard the Command Address and Data tag  
bits when there is a match between the 2-bit Codec ID value  
(slot 0, bits 1 and 0) and the Codec Identity (ID1, ID0).  
Instead it uses the Codec-ID/Identity match to indicate that  
the Command Address in slot 1 and (if a “write”) the Com-  
mand Data in slot 2 are valid.  
The Codec Identity is determined by the inverting input pins  
ID1#, ID0# (pins 46 and 45) and can be read as the value of  
the ID1, ID0 bits (D15, D14) in the Extended Audio ID  
register, 28h of the target codec.  
Slots in the AC Link Output Frame are always mapped to  
carry data to the left DAC channel in slot 3 and data to the  
right DAC channel in slot 4. Similarly, slots in AC Link Input  
Frames are always mapped such that PCM data from the left  
ADC channel is carried by slot 3 and PCM data from the right  
ADC channel by slot 4. Output Frames are those carried by  
the SDATA_OUT signal from the controller to the codec  
while Input Frames are those carried by the SDATA_IN  
signal from the codec to the controller.  
SLOT 0: TAG bits in Output Frames (controller to codec)  
Bit 15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Valid Slot 1 Slot 2 Slot 3 Slot 4  
Frame Valid Valid Valid Valid  
X
X
X
X
X
X
X
X
X
ID1  
ID0  
Extended Audio ID register (28h): Support for Multiple Codecs  
Reg  
Name  
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1  
ID1 ID0  
D0 Default  
Extended  
Audio ID  
28h  
X
X
X
X
X
X
X
X
X
X
X
X
X
VRA X001h  
www.national.com  
26  
Multiple Codecs (Continued)  
20123523  
FIGURE 9. Multiple Codecs using Extended AC Link  
Test Modes  
AC ’97 Rev 2.1 defines two test modes: ATE test mode and  
Vendor test mode. Cold Reset is the only way to exit either of  
them. The ATE test mode is activated if SDATA_OUT is  
sampled high by the trailing edge (zero-to-one transition) of  
RESET#. In ATE test mode the codec AC Link outputs  
SDATA_IN and BIT_CLK are configured to a high imped-  
ance state to allow tester control of the AC Link interface for  
controller testing. ATE test mode timing parameters are  
given in the Electrical Characteristics table. The Vendor test  
mode is entered if SYNC is sampled high by the zero-to-one  
transition of RESET#. Neither of these entry conditions can  
occur in normal AC Link operation but care must be taken to  
avoid mistaken activation of the test modes when using non  
standard controllers.  
27  
www.national.com  
Physical Dimensions inches (millimeters) unless otherwise noted  
48-Lead , LQFP, 7 X 7 X 1.4mm, JEDEC (M)  
Order Number LM4549BVH  
NS Package Number VBH48A  
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves  
the right at any time without notice to change said circuitry and specifications.  
For the most current product information visit us at www.national.com.  
LIFE SUPPORT POLICY  
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS  
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR  
CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the body, or  
(b) support or sustain life, and whose failure to perform when  
properly used in accordance with instructions for use  
provided in the labeling, can be reasonably expected to result  
in a significant injury to the user.  
2. A critical component is any component of a life support  
device or system whose failure to perform can be reasonably  
expected to cause the failure of the life support device or  
system, or to affect its safety or effectiveness.  
BANNED SUBSTANCE COMPLIANCE  
National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances  
and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at:  
www.national.com/quality/green.  
Lead free products are RoHS compliant.  
National Semiconductor  
Americas Customer  
Support Center  
National Semiconductor  
Europe Customer Support Center  
Fax: +49 (0) 180-530 85 86  
National Semiconductor  
Asia Pacific Customer  
Support Center  
National Semiconductor  
Japan Customer Support Center  
Fax: 81-3-5639-7507  
Email: new.feedback@nsc.com  
Tel: 1-800-272-9959  
Email: europe.support@nsc.com  
Deutsch Tel: +49 (0) 69 9508 6208  
English Tel: +44 (0) 870 24 0 2171  
Français Tel: +33 (0) 1 41 91 8790  
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Tel: 81-3-5639-7560  
www.national.com  

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