LM49101TMX [NSC]
Mono Class AB Audio Subsystem with a True Ground Headphone Amplifier and Earpiece Switch; 单声道AB类音频子系统，具有绝对地耳机放大器和耳机开关
| 型号： | LM49101TMX |
| 厂家： | 
National Semiconductor |
| 描述： | Mono Class AB Audio Subsystem with a True Ground Headphone Amplifier and Earpiece Switch |
| 文件： | 总30页 (文件大小：808K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 23, 2009
LM49101
Mono Class AB Audio Subsystem with a True Ground
Headphone Amplifier and Earpiece Switch
■ꢀOutput Power
General Description
The LM49101 is a fully integrated audio subsystem with a
mono power amplifier capable of delivering 540mW of con-
tinuous average power into an 8Ω BTL speaker load with 1%
THD+N using a 3.3V supply. The LM49101 includes a sepa-
rate stereo headphone amplifier that can deliver 44mW per
channel into 32Ω loads using a 2.75V supply.
The LM49101 has four input channels. A pair of single-ended
inputs and a fully differential input channel with volume control
and amplification stages. Additionally, a bypass differential
input is available that connects directly to the mono speaker
outputs through an analog switch without any amplification or
volume control stages. The LM49101 features a 32–step dig-
ital volume control on the input stage and an 8–step digital
volume control on the headphone output stage.
ꢀꢀVDDLS = 3.3V, VDDHP = 2.75V
ꢀꢀ1% THD+N
RL = 8Ω speaker
540W (typ)
40mW (typ)
RL = 32Ω headphone
■ꢀPSRR:
ꢀꢀVDD = 3.3V, 217Hz ripple, Mono In
■ꢀShutdown power supply current
90dB (typ)
0.01μA (typ)
Features
Differential mono input and stereo single-ended input
Separate earpiece (receiver) differential input
Analog switch for a separate earpiece path
32-step digital volume control (-80 to +18dB)
Three independent volume channels (Left, Right, Mono)
Separate headphone volume control
■
■
■
■
■
■
■
■
The digital volume control and output modes, programmed
through a two-wire I2C compatible interface, allows flexibility
in routing and mixing audio channels.
The LM49101 is designed for cellular phones, PDAs, and
other portable handheld applications. The high level of inte-
gration minimizes external components. The True Ground
headphone amplifier eliminates the physically large DC block-
ing output capacitors reducing required board space and
reducing cost.
Flexible output for speaker and headphone output
True Ground headphone amplifier eliminates large DC
blocking capacitors reducing PCB space and cost.
Hardware reset function
■
■
■
■
■
■
■
RF immunity topology
Key Specifications
“Click and Pop” suppression circuitry
Thermal shutdown protection
Micro-power shutdown
■ꢀSupply Voltage (VDDLS)
■ꢀSupply Voltage (VDDHP)
■ꢀI2C Supply Voltage
■ꢀOutput power
2.7V ≤VDDLS ≤5.5V
1.8V ≤VDDHP ≤2.9V
1.7V ≤I2CVDD ≤5.5V
I2C control interface
Available in space-saving microSMD package
Applications
ꢀꢀVDDLS = 5V, VDDHP = 2.75V
ꢀꢀ 1% THD+N
Portable electronic devices
■
■
Mobile Phones
RL = 8Ω speaker
1.3W (typ)
PDAs
■
RL = 32Ω headphone
45mW (typ)
Boomer® is a registered trademark of National Semiconductor Corporation.
© 2009 National Semiconductor Corporation
300862
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Typical Application
30086203
FIGURE 1. Typical Audio Application Circuit
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Connection Diagrams
25 Bump micro SMD Package
micro SMD Markings
30086204
Top View
XY - Date Code
TT - Die Traceability
G- Boomer Family
L4 - LM49101TM
30086202
Top View
(Bump Side Down)
Order Number LM49101TM, LM49101TMX
See NS Package Number TMD25BCA
Ordering Information
Order
Number
Package
Package DWG
#
Transport Media
MSL Level
Green Status
Features
25 Bump micro
SMD
LM49101TM
TMD25BCA
TMD25BCA
250 units on tape and reel
3000 units on tape and reel
1
1
RoHS and no Sb/Br
RoHS and no Sb/Br
25 Bump micro
SMD
LM49101TMX
3
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Bump Descriptions
Bump
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C5
D1
D2
D3
Name
CPGND
VSSCP
HPR
Pin Function
Charge pump ground terminal
Type
Ground
Negative charge pump power supply
Right headphone output
Power Output
Analog Output
Power Input
Analog Input
Analog Output
Analog Output
Analog Output
Ground
VDDHP
MIN+
C1N
Headphone amplifier power supply
Positive input pin for the mono, differential input
Negative terminal of the charge pump flying capacitor
Positive terminal of the charge pump flying capacitor
Left headphone output
C1P
HPL
HPGND
MIN-
Headphone signal ground
Negative input pin for the mono, differential input
Charge pump power supply
I2C data
Analog Input
Power Input
Digital Input
Ground
VDDCP
SDA
GND
Ground
RIN
Single-ended input for the right channel
Single-ended input for the left channel
Analog Input
Analog Input
Analog Input
Power Input
Digital Input
LIN
BYPASS_IN- Earpiece negative input, bypass volume control and amplifier
I2CVDD
I2C power supply
I2C clock
SCL
Hardware reset function, active low. When pin is low (<0.6V) the
LM49101 goes into shutdown mode and will remain in shutdown
mode until pin goes to logic high (>1.6V) and is activated by I2C
control. When reset all registers are set to the default value of 0.
D4
HW RESET
Digital Input
D5
E1
E2
E3
E4
E5
BYPASS_IN+ Earpiece positive input, bypass volume control and amplifier
Analog Input
Analog Output
Power Input
Ground
MONO+
VDDLS
GND
Positive loudspeaker output
Main power supply
Ground
MONO-
BIAS
Negative loudspeaker output
Half-supply bias, capacitor bypassed
Analog Output
Analog Output
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4
See AN-1112 “Micro SMD Wafer Level Chip Scale
Package”
Thermal Resistance
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ꢁθJA (Note 8)
51°C/W
Supply Voltage (Loudspeaker,
VDDLS)
Operating Ratings
6.0V
3.0V
−65°C to +150°C
Temperature Range
Supply Voltage (Headphone, VDDHP)
Storage Temperature
Voltage at Any Input Pin
Power Dissipation (Note 3)
ESD Rating (Note 4)
TMIN ≤ TA ≤ TMAX
Supply Voltage (VDDLS)
−40°C ≤ TA ≤ 85°C
2.7V ≤VDDLS ≤5.5V
GND − 0.3 to VDD LS + 0.3
Internally Limited
2000V
Supply Voltage (VDDHP)
1.8V ≤VDDHP ≤2.9V
VDDHP ≤ VDDLS
ESD Rating (Note 5)
200V
Supply Voltage (VDDCP)
VDDCP = VDD HP
Junction Temperature (TJMAX
Soldering Information
Vapor Phase (60sec.)
Infrared (15sec.)
)
150°C
Supply Voltage (I2CVDD
)
1.7V ≤I2CVDD ≤5.5V
I2CVDD ≤ VDDLS
215°C
220°C
Electrical Characteristics VDDLS = 3.3V, VDDHP = 2.75V (Notes 1, 2)
The following specifications apply for VDDLS = 3.3V, VDDHP = 2.75V, TA = 25°C, all volume controls set to 0dB, unless otherwise
specified. LS = Loudspeaker, HP = Headphone, EP = Earpiece.
LM49101
Units
Symbol
Parameter
Conditions
VIN = 0, No Load
Typical
Limits
(Limits)
(Note 6)
(Note 7)
EP Receiver
(Output Mode Bit EP Bypass = 1)
0.03
0.045
4.2
mA (max)
LS only (Mode 1), GAMP_SD = 0
VDDLS
VDDHP
2.5
0
mA (max)
mA
LS only (Mode 1), GAMP_SD = 1
VDDLS
VDDHP
2
0
mA
mA
HP only (Mode 8), GAMP_SD = 0
VDDLS
VDDHP
IDD
Quiescent Power Supply Current
1.6
3.1
2.0
4.5
6.45
mA (max)
mA (max)
mA (max)
VDDLS +VDDHP
HP only (Mode 8), GAMP_SD = 1
VDDLS
VDDHP
2.8
3.3
mA
mA
LS+HP (Mode 10), GAMP_SD = 0
VDDLS
VDDHP
2.8
3.1
3.8
4.5
8
mA (max)
mA (max)
mA (max)
VDDLS +VDDHP
ISD
Shutdown Current
Power_On = 0
0.01
2
µA (max)
VIN = 0V, Mode 10
LS output, RL = 8Ω BTL
HP output, RL = 32Ω SE
VOS
Output Offset Voltage
2.5
0.5
22
5
mV (max)
mV (max)
LS output, Mode 1, RL = 8Ω BTL
THD+N = 1%, f = 1kHz, LS_Gain = 6dB
540
44
480
40
mW (min)
mW (min)
PO
Output Power
HP output, Mode 8, RL = 32Ω SE
THD+N = 1%, f = 1kHz
5
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LM49101
Units
(Limits)
Symbol
Parameter
Conditions
Typical
Limits
(Note 6)
(Note 7)
LS output, f = 1kHz, RL = 8Ω BTL
PO = 250mW, Mode 1, LS_Gain = 6dB
0.065
%
%
THD+N
Total Harmonic Distortion + Noise
HP output, f = 1kHz, RL = 32Ω SE
PO = 20mW, Mode 8
0.015
105
LS output, f = 1kHz, Mode 1
VREF = VOUT (1%THD+N)
dB
dB
Vol. Gain & LS_GAIN = 0dB
A-Wtg, LIN & RIN AC terminated
SNR
Signal-to-Noise Ratio
HP output, f = 1kHz, Mode 8
VREF = VOUT (1%THD+N)
Vol. Gain = 0dB, A-weighted
LIN & RIN AC terminated
100
VRIPPLE on VDDLS = 200mVPP, fRIPPLE = 217Hz, CB = 2.2μF
All inputs AC terminated to GND, output referred
LS: Mode 1, 5, 9, 13, RL = 8Ω BTL
LS: Mode 2, 6, 10 ,14, RL = 8Ω BTL
HP: Mode 4, 5, 6, 7, RL = 32Ω SE
90
75
85
81
dB (max)
dB (max)
dB (max)
dB (max)
PSRR
Power Supply Rejection Ratio
HP: Mode 8, 9, 10, 11, RL = 32Ω SE
f = 217Hz, VCM = 1VP-P
LS: RL = 8Ω BTL, Mode 1
HP: RL = 32Ω SE, Mode 4
CMRR
XTALK
Common-Mode Rejection Ratio
Crosstalk
60
60
dB
dB
HP PO = 20mW
f = 1kHz, Mode 8
72
dB
10
15
KΩ (min)
KΩ (max)
Maximum Gain setting
12.5
ZIN
MIN, LIN, and RIN Input Impedance
90
130
KΩ (min)
KΩ (max)
Maximum Attenuation setting
Analog Switch On
110
3.4
RON
VOL
VOL
On Resistance
Ω
dB
dB
Maximum Gain
Maximum Attenuation
18
–80
Digital Volume Control Range
Volume Control Step Size Error
±0.02
30
dB
ms
ms
CB = 2.2μF, HP, Normal Turn-On Mode
CB = 2.2μF, HP, Fast Turn-On Mode
TWU
Wake-Up Time from Shutdown
15
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Electrical Characteristics VDDLS = 5.0V, VDDHP = 2.75V (Notes 1, 2)
The following specifications apply for VDDLS = 5.0V, VDDHP = 2.75V, TA = 25°C, all volume controls set to 0dB, unless otherwise
specified. LS = Loudspeaker, HP = Headphone, EP = Earpiece.
LM49101
Units
Symbol
Parameter
Conditions
VIN = 0, No Load
Typical
Limits
(Limits)
(Note 6)
(Note 7)
EP Receiver
(Output Mode Bit EP Bypass = 1)
0.05
0.07
4.4
mA (max)
LS only (Mode 1), GAMP_SD = 0
VDDLS
VDDHP
mA (max)
mA
2.9
0
LS only (Mode 1), GAMP_SD = 1
VDDLS
VDDHP
2.1
0
mA
mA
HP only (Mode 8), GAMP_SD = 0
VDDLS
VDDHP
IDD
Quiescent Power Supply Current
1.8
3.1
2.15
4.5
6.6
mA (max)
mA (max)
mA (max)
VDDLS+VDDHP
HP only (Mode 8), GAMP_SD = 1
VDDLS
VDDHP
1.3
3.1
mA
mA
LS+HP only (Mode 10), GAMP_SD = 0
VDDLS
VDDHP
VDDLS+VDDHP
3
3.1
4.1
4.5
8.35
mA (max)
mA (max)
mA (max)
ISD
Shutdown Current
Power_On = 0
0.01
2
µA (max)
VIN = 0V, Mode 10
LS output, RL = 8Ω BTL
HP output, RL = 32Ω SE
VOS
Output Offset Voltage
2.5
0.5
22
5
mV (max)
mV (max)
LS output, Mode 1, RL = 8Ω BTL
THD+N = 1%, f = 1kHz, LS_Gain = 6dB
1.3
45
W
mW
%
PO
Output Power
HP output, Mode 8, RL = 32Ω SE
THD+N = 1%, f = 1kHz
LS output, f = 1kHz, RL = 8Ω BTL
PO = 600mW, Mode 1, LS_Gain = 6dB
0.055
0.015
THD+N
Total Harmonic Distortion + Noise
HP output, f = 1kHz, RL = 32Ω SE
PO = 20mW, Mode 8
%
LS output, f = 1kHz, Mode 1
VREF = VOUT (1%THD+N)
108
100
dB
dB
Vol. Gain & LS_GAIN = 0dB
A-Wtg, LIN & RIN AC terminated
SNR
Signal-to-Noise Ratio
HP output, f = 1kHz, Mode 8
VREF = VOUT (1%THD+N)
Vol. Gain = 0dB, A-weighted
LIN & RIN AC terminated
VRIPPLE on VDDLS = 200mVPP, fRIPPLE = 217Hz, CB = 2.2μF
All inputs AC terminated to GND, output referred
LS: Mode 1, 5, 9, 13, RL = 8Ω BTL
LS: Mode 2, 6, 10, 14, RL = 8Ω BTL
HP: Mode 4, 5, 6, 7, RL = 32Ω SE
HP: Mode 8, 9, 10, 11, RL = 32Ω SE
90
74
84
79
dB
dB
dB
dB
PSRR
Power Supply Rejection Ratio
7
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LM49101
Units
(Limits)
Symbol
Parameter
Conditions
f = 217Hz, VCM = 1VP-P
Typical
Limits
(Note 6)
(Note 7)
LS: RL = 8Ω BTL, Mode 1
HP: RL = 32Ω SE, Mode 4
CMRR
XTALK
Common-Mode Rejection Ratio
Crosstalk
60
60
dB
dB
HP PO = 20mW
f = 1kHz, Mode 8
72
dB
10
15
KΩ (min)
KΩ (max)
Maximum Gain setting
12.5
ZIN
MIN, LIN, and RIN Input Impedance
90
130
KΩ (min)
KΩ (max)
Maximum Attenuation setting
Analog Switch On
110
2
RON
VOL
VOL
On Resistance
Ω
dB
dB
Maximum Gain
Maximum Attenuation
18
–80
Digital Volume Control Range
Volume Control Step Size Error
±0.02
30
dB
ms
ms
CB = 2.2μF, HP, Normal Turn-On Mode
CB = 2.2μF, HP, Fast Turn-On Mode
TWU
Wake-Up Time from Shutdown
15
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I2C Interface 2.2V ≤ I2C_VDD ≤ 5.5V, (Notes 1, 2)
The following specifications apply for VDDLS = 5.0V and 3.3V, 2.2V ≤ I2C_VDD ≤ 5.5V, TA = 25°C, unless otherwise specified.
LM49101
Units
(Limits)
Symbol
Parameter
Conditions
Typical
Limits
(Notes 7, 9)
(Note 4)
t1
t2
I2C Clock Period
2.5
100
µs (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
V (min)
I2C Data Setup Time
I2C Data Stable Time
Start Condition Time
Stop Condition Time
I2C Data Hold Time
I2C Input Voltage High
I2C Input Voltage Low
t3
0
t4
100
t5
100
t6
100
VIH
VIL
0.7xI2CVDD
0.3xI2CVDD
V (max)
I2C Interface 1.7V ≤ I2C_VDD ≤ 2.2V, (Notes 1, 2)
The following specifications apply for VDDLS = 5.0V and 3.3V, TA = 25°C, 1.7V ≤ I2C_VDD ≤ 2.2V, unless otherwise specified.
LM49101
Units
(Limits)
Symbol
Parameter
Conditions
Typical
Limits
(Notes 7, 9)
(Note 6)
t1
t2
I2C Clock Period
2.5
250
µs (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
V (min)
I2C Data Setup Time
I2C Data Stable Time
Start Condition Time
Stop Condition Time
I2C Data Hold Time
I2C Input Voltage High
I2C Input Voltage Low
t3
0
t4
250
t5
250
t6
250
VIH
VIL
0.7xI2CVDD
0.3xI2CVDD
V (max)
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever
Note 4: Human body model, applicable std. JESD22-A114C.
Note 5: Machine model, applicable std. JESD22-A115-A.
Note 6: Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis.
Note 8: The given θJA is for an LM49101 mounted on a demonstration board.
Note 9: Refer to the I2C timing diagram, Figure 2.
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Typical Performance Characteristics
THD+N vs Frequency
VDDLS = 3.3V, RL = 8Ω BTL, PO = 250mW
Mode 1 (Mono), 80kHz BW
THD+N vs Frequency
VDDLS = 3.3V, RL = 8Ω BTL, PO = 250mW
Mode 2 (Left + Right), 80kHz BW
30086219
30086220
THD+N vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, RL = 32Ω SE,
PO = 5mW/Ch, Mode 4 (Mono), 80kHz BW
THD+N vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, RL = 32Ω SE,
PO = 5mW/Ch, Mode 8 (Left/Right ), 80kHz BW
30086221
30086222
THD+N vs Frequency
THD+N vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, RL = 8Ω BTL, RL = 32Ω SE,
PO = 250mW BTL, PO = 5mW/Ch SE, Mode 5 (Mono)
LS (EP Mode) = 0, 80kHz BW
VDDLS = 3.3V, VDDHP = 1.8V, RL = 8Ω BTL, RL = 32Ω SE,
PO = 250mW BTL, PO = 5mW/Ch SE, Mode 10 (L/R)
LS (EP Mode) = 0, 80kHz BW
30086226
30086229
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THD+N vs Frequency
VDDLS = 5V, RL = 8Ω BTL, PO = 600mW,
Mode 1 (Mono), 80kHz BW
THD+N vs Frequency
VDDLS = 5V, RL = 8Ω BTL, PO = 600mW,
Mode 2 (Let + Right), 80kHz BW
30086223
30086224
THD+N vs Frequency
VDDLS = 5V, VDDHP = 2.75V, RL = 32Ω SE,
PO = 20mW/Ch, Mode 4 (Mono), 80kHz BW
THD+N vs Frequency
VDDLS = 5V, VDDHP = 2.75V, RL = 32Ω SE,
PO = 20mW/Ch, Mode 8 (Left/Right), 80kHz BW
30086225
30086228
THD+N vs Frequency
THD+N vs Frequency
VDDLS = 5V, VDDHP = 2.75V, RL = 8Ω BTL, RL = 32Ω SE,
PO = 600mW BTL, PO = 20mW/Ch SE, Mode 5 (Mono)
LS (EP Mode) = 0, 80kHz BW
VDDLS = 5V, VDDHP = 2.75V, RL = 8Ω BTL, RL = 32Ω SE,
PO = 600mW BTL, PO = 20mW/Ch SE, Mode 10 (L/R)
LS (EP Mode) = 0, 80kHz BW
30086227
30086230
11
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THD+N vs Output Power
VDDLS = 3.3V & 5V, f = 1kHz, RL = 8Ω BTL
Mode 1 (Mono), 80kHz BW
THD+N vs Output Power
VDDLS = 3.3V & 5V, f = 1kHz, RL = 8Ω BTL
Mode 2 (Left + Right), 80kHz BW
30086243
30086244
THD+N vs Output Power
VDDLS = 3.3V, VDDHP = 1.8V & 2.75V, f = 1kHz,
THD+N vs Output Power
VDDLS = 3.3V, VDDHP = 1.8V & 2.75V, f = 1kHz,
RL = 32Ω SE, Mode 4 (Mono), 80kHz BW
RL = 32Ω SE, Mode 8 (Left/Right), 80kHz BW
30086245
30086246
THD+N vs Output Power
VDDLS = 3.3V & 5V, VDDHP = 2.75V, f = 1kHz,
THD+N vs Output Power
VDDLS = 3.3V, VDDHP = 1.8V & 2.75V, f = 1kHz,
RL = 8Ω BTL, Mode 5 (Mono), 80kHz BW
RL = 32Ω SE, Mode 10 (Left/Right), 80kHz BW
30086242
30086247
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PSRR vs Frequency
VDDLS = 3.3V, VRIPPLELS = 200mVPP, RL = 8Ω BTL,
Mode 1 (Mono), 80kHz BW
PSRR vs Frequency
VDDLS = 3.3V, VRIPPLELS = 200mVPP, RL = 8Ω BTL,
Mode 2 (Left + Right), 80kHz BW
30086211
30086213
PSRR vs Frequency
VDDLS = 5V, VRIPPLELS = 200mVPP, RL = 8Ω BTL,
Mode 1 (Mono), 80kHz BW
PSRR vs Frequency
VDDLS = 5V, VRIPPLELS = 200mVPP, RL = 8Ω BTL,
Mode 2 (Left + Right), 80kHz BW
30086212
30086214
PSRR vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, VRIPPLEHP = 200mVPP
PSRR vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, VRIPPLEHP = 200mVPP,
,
RL = 32Ω SE, Mode 4 (Mono), 80kHz BW
RL = 32Ω SE, Mode 8 (Left/Right), 80kHz BW
30086215
30086217
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PSRR vs Frequency
VDDLS = 3.3V, VDDHP = 2.75V, VRIPPLEHP = 200mVPP
PSRR vs Frequency
VDDLS = 3.3V, VDDHP = 2.75V, VRIPPLEHP = 200mVPP,
,
RL = 32Ω SE, Mode 4 (Mono), 80kHz BW
RL = 32Ω SE, Mode 8 (Left/Right), 80kHz BW
30086248
30086249
Power Dissipation vs Output Power
VDDLS = 3.3V & 5V, VDDHP = 2.75V, RL = 8Ω BTL,
Mode 3 (Mono + Left + Right), 80kHz BW
Power Dissipation vs Output Power
VDDLS = 5V, VDDHP = 1.8V & 2.75V, RL = 32Ω SE,
Mode 12 (Mono + Left/ Right), 80kHz BW
30086236
30086235
Crosstalk vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, VIN = 1VPP
Crosstalk vs Frequency
VDDLS = 3.3V, VDDHP = 2.75V, VIN = 1VPP,
,
RL = 32Ω SE, Mode 8 (Left/Right), 80kHz BW
RL = 32Ω SE, Mode 8 (Left/Right), 80kHz BW
30086231
30086232
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14
Supply Current vs Supply Voltage (VDDLS)
VDDHP = 2.75V, No Load, Gain_SD = 0 & 1
LS (EP_Mode) = 0 & 1, Mode 1
Supply Current vs Supply Voltage (VDDLS)
VDDHP = 2.75V, No Load, Gain_SD = 0 & 1
LS (EP_Mode) = 0 & 1, Mode 2
30086237
30086239
Supply Current vs Supply Voltage (VDDHP)
VDDLS = 3.3V, No Load, Gain_SD = 0 or 1
HPR_SD = 0 & 1, Modes 4, 8, 15
Supply Current vs Supply Voltage (VDDLS)
VDDHP = 2.75V, No Load, Gain_SD = 0 or 1
LS (EP_Mode) = 0 & 1, Mode 15
30086238
30086240
Output Power vs Supply Voltage (VDDLS)
VDDHP = 2.75V, RL = 8Ω BTL,
Mode 1
Output Power vs Supply Voltage (VDDHP)
VDDLS = 3.3V, RL = 32Ω SE,
Mode 4
30086234
30086233
15
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Application Information
I2C BUS FORMAT
The I2C bus format is shown in Figure 4. The START signal,
the transition of SDA from HIGH to LOW while SCL is HIGH,
is generated, alerting all devices on the bus that a device ad-
dress is being written to the bus.
I2C COMPATIBLE INTERFACE
The LM49101 is controlled through an I2C compatible serial
interface that consists of a serial data line (SDA) and a serial
clock (SCL). The clock line is uni-directional. The data line is
bi-directional (open drain). The LM49101 and the master can
communicate at clock rates up to 400kHz. Figure 2 shows the
I2C interface timing diagram. Data on the SDA line must be
stable during the HIGH period of SCL. The LM49101 is a
transmit/receive slave-only device, reliant upon the master to
generate the SCL signal. Each transmission sequence is
framed by a START condition and a STOP condition (Figure
3). Each data word, device address and data, transmitted
over the bus is 8 bits long and is always followed by an ac-
knowledge pulse (Figure 4). The LM49101 device address is
11111000.
The 7-bit device address is written to the bus, most significant
bit (MSB) first, followed by the R/W bit. R/W = 0 indicates the
master is writing to the slave device, R/W = 1 indicates the
master wants to read data from the slave device. Set R/W =
0; the LM49101 is a WRITE-ONLY device and will not re-
spond to the R/W = 1. The data is latched in on the rising edge
of the clock. Each address bit must be stable while SCL is
HIGH. After the last address bit is transmitted, the master de-
vice releases SDA, during which time, an acknowledge clock
pulse is generated by the slave device. If the LM49101 re-
ceives the correct address, the device pulls the SDA line low,
generating an acknowledge bit (ACK).
I2C INTERFACE POWER SUPPLY PIN (I2CVDD
)
Once the master device registers the ACK bit, the 8-bit reg-
ister data word is sent. Each data bit should be stable while
SCL is HIGH. After the 8-bit register data word is sent, the
LM49101 sends another ACK bit. Following the acknowl-
edgement of the register data word, the master issues a
STOP bit, allowing SDA to go high while SCL is high.
The LM49101's I2C interface is powered up through the
I2CVDD pin. The LM49101's I2C interface operates at a volt-
age level set by the I2CVDD pin which can be set independent
to that of the main power supply pin VDDLS. This is ideal
whenever logic levels for the I2C interface are dictated by a
microcontroller or microprocessor that is operating at a lower
supply voltage than the VDDLS voltage.
300862s0
FIGURE 2. I2C Timing Diagram
300862s1
FIGURE 3. Start and Stop Diagram
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300862s2
FIGURE 4. Start and Stop Diagram
TABLE 1. Chip Address
A7
A6
A5
A4
A3
A2
A1
A0
Chip
Address
1
1
1
1
1
0
0
0
TABLE 2. Control Registers
Register
General Control
D7
D6
D5
1
D4
D3
D2
D1
D0
Power_On (4)
LS
Turn_On
_Time (3)
GAMP_SD (1)
0
0
0
(EP_Mode) (2)
EP
Bypass (5)
HPR_SD (6)
Mode_ Control (7)
Output Mode Control
Output Gain Control
0
1
1
1
0
0
Input_Mute (8)
LS_Gain (9)
HP_Gain (10)
0
Mono Input Volume
Control
Mono_Vol (11)
1
0
1
Left Input Volume
Control
Left_Vol (11)
1
1
1
1
Right Input Volume
Control
Right_Vol (11)
Notes: All registers default to 0 on initial power-up.
7. Mode_Control: Sets the output mode. See Table 4.
1. GAMP_SD: Is used to shut down gain amplifiers not in use
and reduce current consumption. See Table 3.
8. Input Mute: Controls muting of the inputs except the BY-
PASS inputs. See Table 5.
2. LS (EP_Mode): Loudspeaker power amplifier bias current
reduction. See Table 3.
9. LS_Gain: Sets the gain of the loudspeaker amplifier to 0dB
or 6dB. See Table 5.
3. Turn_On_Time: Reduces the turn on time for faster acti-
vation. See Table 3.
10. HP_Gain: Sets the headphone amplifier output gain. See
Table 5.
4. Power_On: Master Power on bit. See Table 3.
11. Mono_Vol/Left_Vol/Right_Vol: Sets the input volume for
Mono, Left and Right inputs. See Table 6.
5. EP Bypass: Earpiece bypass mode to allow BYPASS in-
puts to drive speaker outputs. See Table 4
6. HPR_SD: Will shutdown one channel of the headphone
amplifier. See Table 4.
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TABLE 3. General Control Register
Value
Bit
Name
Description
This bit is a master shutdown control bit and sets the device to be on or off.
Value
Status
Master power off, device disable.
Master power on, device enable.
0
Power_On
0
1
This bit sets the turn on time of the device.
Value
Status
1
3
Turn_On_Time
LS (EP Mode)
0
1
Normal Turn-on time
Fast Turn-on time
This bit enables EP Mode reducing loudspeaker output stage bias current by 500μA.
Value
0
Status
Normal loudspeaker power amplifier operation.
Enables EP Mode reducing loudspeaker output stage bias current
by 500μA.
1
This bit is used to reduce IDD by shutting down gain amplifiers not in use.
0
Normal operation of all gain amplifiers.
4
GAMP_SD
Disables the input gain amplifiers that are not in use to reduce
current from VDDLS. Recommended for Output Modes 1, 2, 4, 5,
8, 10.
1
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TABLE 4. Output Mode Control Register (see key below table)
Description
Bits
Field
3:0
Mode_Control These bits determine how the input signals are mixed and routed to the outputs.
D3
D2
D1
D0
Headphone
Loudspeaker
Left
Headphone
Right
Headphone
D3D2D1D0
Mode
0000
0001
0010
0
1
2
SD
SD
SD
SD
SD
SD
SD
GM x M
2 x (GL x L + GR x R)
2 x (GL x L + GR x R)
+ GM x M
0011
3
SD
SD
0100
0101
0110
GM x M/2
GM x M/2
GM x M/2
GM x M/2
GM x M/2
GM x M/2
4
5
6
SD
GM x M
2 x (GL x L + GR x R)
2 x (GL x L + GR x R)
+ GM x M
GM x M/2
GM x M/2
0111
7
1000
1001
1010
GL x L
GL x L
GL x L
GR x R
GR x R
GR x R
8
9
SD
GM x M
10
2 x (GL x L + GR x R)
2 x (GL x L + GR x R)
+ GM x M
GL x L
GR x R
1011
1100
1101
1110
1111
11
12
13
14
15
GL x L + GM
M/2
x
GR x R + GM
M/2
x
x
x
x
SD
GL x L + GM
M/2
x
x
x
GR x R + GM
M/2
GM x M
GL x L + GM
M/2
GR x R + GM
M/2
2 x (GL x L + GR x R)
2 x (GL x L + GR x R)
+ GM x M
GL x L + GM
M/2
GR x R + GM
M/2
This bit sets the headphone amplifiers to normal mode or mono mode.
Value
Status
4
5
HPR_SD
0
1
Normal stereo headphone operation.
Disable right headphone output.
This bit is used to control the analog switch to have the BYPASS inputs drive the loudspeaker outputs.
Value
0
Status
EP Bypass
Normal output mode operation with analog switch off.
Loudspeaker and headphone amplifiers go into shutdown mode and Bypass (Receiver) path
enable with the analog switch on.
1
M : MIN, Mono differential input
L : LIN, Left single-ended input
R : RIN, Right single-ended input
SD : Shutdown
GM : Mono_Vol setting determined by the Mono Input Volume Control register, See Table 6.
GL : Left_Vol setting determined by the Left Input Volume Control register, See Table 6.
GR : Right_Vol setting determined by the Right Input Volume Control register, See Table 6.
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TABLE 5. Output Gain Control Register
Description
These bits set the gain of the headphone output amplifiers.
Bits
Field
Value
000
001
010
011
100
101
110
111
Gain (dB)
0
–1.2
–2.5
–4.0
–6.0
–8.5
–12
2:0
HP_GAIN
–18
This bit sets the loudspeaker output amplifier gain.
Value
Status
3
4
LS_GAIN
0
1
Loudspeaker output amplifier gain is set to 0dB.
Loudspeaker output amplifier gain is set to 6dB.
This bit will set all the inputs except the BYPASS inputs to be in Mute mode.
Value
0
Status
Normal operation of all inputs.
Mutes all inputs except BYPASS with over 80dB of attenuation
with out adjusting the volume settings. This bit can be used to
mute the inputs to eliminate noise or transients from other
systems and ICs. See the section Input Mute Bit in the
Application Information section for a detailed explanation.
INPUT MUTE
1
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20
TABLE 6. Input Volume Control Registers
Description
These bits set the input volume for each input volume register listed.
Bits
Fields
4:0
Mono_Vol
Right_Vol
Left_Vol
Volume Step
Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Gain (dB)
–80.0
–46.5
–40.5
–34.5
–30.0
–27.0
–24.0
–21.0
–18.0
–15.0
–13.5
–12.0
–10.5
–9.0
–7.5
–6.0
–4.5
–3.0
–1.5
0.0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
13.5
15.0
16.5
18.0
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HW RESET FUNCTION
the rest of the IC blocks except for the I2C circuitry will go into
shutdown for minimal current consumption.
The LM49101 can be globally reset without using the I2C con-
trols. When the HW RESET pin is set to a logic low the
LM49101 will enter into shutdown, the mode control bits of the
Output Mode Control register, volume control registers and
Power_On bits will be set to the default value of zero. The
other bits will retain their values. The LM49101 cannot be ac-
tivated until the HW RESET pin is set to a logic high voltage.
When the HW RESET is set to a logic high then the I2C con-
trols can activate and set the register control bits.
HPR_SD BIT
The HPR_SD bit will deactivate the right headphone output
amplifier. This bit is provided to reduce power consumption
when only one headphone output is needed.
MODE_CONTROL BITS
The LM49101 includes a comprehensive mixer multiplexer
controlled through the I2C interface. The mixer/multiplexer al-
lows any input combination to appear on any output of
LM49101. Multiple input paths can be selected simultane-
ously. Under these conditions, the selected inputs are mixed
together and output on the selected channel. Table 4 shows
how the input signals are mixed together for each possible
input selection.
GAMP_SD BIT
The GAMP_SD bit allows for reduced power consumption.
When set to '1' the gain amplifiers on unused inputs will be
shutdown saving approximately 0.4mA per input in shutdown.
For example, in Mode 1 only the mono inputs are in use. Set-
ting GAMP_SD to '1' will shut down the gain amplifiers for the
left and right inputs reducing current draw from the VDDLS
supply by approximately 0.8mA. The GAMP_SD bit does not
need to be set each time when changing modes as the
LM49101 will automatically activate and deactivate the need-
ed inputs based on the mode selected.
INPUT MUTE BIT
The Input Mute bit will mute all inputs except the Bypass in-
puts when set to a '1'. This allows complete and quick mute
of the Mono, Left, and Right inputs without changing the Vol-
ume Control registers or HP_Gain bits. The volume and
HP_Gain bits retain their values when the Input Mute is en-
abled or disabled.
When operating with GAMP_SD set to '1', a transient may be
observed on the outputs when changing modes. During pow-
er up, the LM49101 uses a start up sequence to eliminate any
pops and clicks on the outputs. The volume control circuitry
is powered up first followed by the other internal circuitry with
the output amplifiers being powered up last. If a mode change
requires a gain amplifier to turn on then a potential transient
may be created that is amplified on the already active outputs.
To eliminate unwanted noise on the outputs the Power_On
bit should be used to turn off the LM49101 before changing
modes, perform a mode change, then turn the LM49101 back
on. This procedure will cause the LM49101 to follow the start
up sequence.
The Input Mute bit can be used to mute all the inputs when
other chips in a system, such as the baseband IC, create
transients causing unwanted noise on the outputs of the
LM49101. This added feature eliminates the need for power
cycling the LM49101.
LS_GAIN BIT
The loudspeaker amplifier can have an additional gain of 0dB
or 6dB by using the LS_Gain bit. The Mono input has 6dB of
attenuation before the volume control (see Figure 1) while the
Left and Right inputs do not. The LS_Gain bit is used to ac-
count for the different attenuation levels for each input and to
achieve maximum output power. To obtain maximum output
power on the loudspeaker outputs, the LS_Gain bit should be
se to '1' for Modes 1, 5, 9, 13.
LS (EP_MODE) BIT
The LS (EP_Mode) bit selects the amount of bias current in
the loudspeaker amplifier. Setting the LS (EP_Mode) bit to a
'1' will reduce the amount of current from the VDDLS supply
by approximately 0.5mA. The THD performance of the loud-
speaker amplifier will be reduced as a result of lower bias
current. See the performance graphs in the Typical Perfor-
mance Characteristics section above.
HP_GAIN BITS
The headphone outputs have an additional, single volume
control set by the three HP_Gain bits in the Output Gain Con-
trol register. The HP_Gain volume setting controls the output
level for both the left and the right headphone outputs.
TURN_ON_TIME BIT
The Turn_On_Time bit determines the delay time from the
Power_On bit set to '1' and the internal circuits ready. For
input capacitor values up to 0.47μF the Turn_On_Time bit can
be set to fast mode by setting the bit to a '1'. When the input
capacitor values are larger than 0.47μF then the
Turn_On_Time bit should be set to '0' for normal turn-on time
and higher delay. This allows sufficient time to charge the in-
put capacitors to the ½ VDDLS bias voltage.
VOLUME CONTROL BITS
The LM49101 has three independent 32-step volume con-
trols, one for each of the inputs. The five bits of the Volume
Control registers sets the volume for the specified input chan-
nel.
SHUTDOWN FUNCTION
The LM49101 features the following shutdown controls.
Bit D4 (GAMP_SD) of the GENERAL CONTROL register
controls the gain amplifiers. When GAMP_SD = 1, it disables
the gain amplifiers that are not in use. For example, in Modes
1, 4 and 5, the Mono inputs are in use, so the Left and Right
input gain amplifiers are disabled, causing the IDD to be min-
imized.
POWER_ON BIT
The Power_On bit is the master control bit to activate or de-
activate the LM49101. All registers can be loaded indepen-
dent of the Power_On bit setting as long as the IC is powered
correctly. Cycling the Power_On bit does not change the val-
ues of any registers nor return all bits to the default power on
value of zero. The Power_On bit only determines whether the
IC is on or off.
Bit D0 (Power_On) of the GENERAL CONTROL register is
the global shutdown control for the entire device. Set
Power_On = 0 for normal operation. Power_On = 1 overrides
any other shutdown control bit.
EP BYPASS BIT
The EP Bypass bit is used to set the LM49101 to earpiece
mode. When this bit is set the analog switch is activated and
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22
DIFFERENTIAL AMPLIFIER EXPLANATION
power dissipation information for different output powers and
output loading.
The LM49101 features a differential input stage, which offers
improved noise rejection compared to a single-ended input
amplifier. Because a differential input amplifier amplifies the
difference between the two input signals, any component
common to both signals is cancelled. An additional benefit of
the differential input structure is the possible elimination of the
DC input blocking capacitors. Since the DC component is
common to both inputs, and thus cancelled by the amplifier,
the LM49101 can be used without input coupling capacitors
when configured with a differential input signal.
POWER SUPPLY BYPASSING
As with any amplifier, proper supply bypassing is critical for
low noise performance and high power supply rejection. The
capacitor location on both the bypass and power supply pins
should be as close to the device as possible. Typical appli-
cations employ a 5V regulator with 10µF tantalum or elec-
trolytic capacitor and a ceramic bypass capacitor which aid in
supply stability. This does not eliminate the need for bypass-
ing the supply nodes of the LM49101. The selection of a
bypass capacitor, especially CB, is dependent upon PSRR
requirements, click and pop performance, system cost, and
size constraints.
BRIDGE CONFIGURATION EXPLAINED
By driving the load differentially through the MONO outputs,
an amplifier configuration commonly referred to as “bridged
mode” is established. Bridged mode operation is different
from the classical single-ended amplifier configuration where
one side of the load is connected to ground.
GROUND REFERENCED HEADPHONE AMPLIFIER
The LM49101 features a low noise inverting charge pump that
generates an internal negative supply voltage. This allows the
headphone outputs to be biased about GND instead of a
nominal DC voltage, like traditional headphone amplifiers.
Because there is no DC component, the large DC blocking
capacitors (typically 220μF) are not necessary. The coupling
capacitors are replaced by two small ceramic charge pump
capacitors, saving board space and cost. Eliminating the out-
put coupling capacitors also improves low frequency re-
sponse. In traditional headphone amplifiers, the headphone
impedance and the output capacitor from a high-pass filter
that not only blocks the DC component of the output, but also
attenuates low frequencies, impacting the bass response.
Because the LM49101 does not require the output coupling
capacitors, the low frequency response of the device is not
degraded by external components. In addition to eliminating
the output coupling capacitors, the ground referenced output
nearly doubles the available dynamic range of the LM49101
headphone amplifiers when compared to a traditional head-
phone amplifier operating from the same supply voltage.
A bridge amplifier design has a few distinct advantages over
the single-ended configuration, as it provides differential drive
to the load, thus doubling output swing for a specified supply
voltage. Four times the output power is possible as compared
to a single-ended amplifier under the same conditions. This
increase in attainable output power assumes that the ampli-
fier is not current limited or clipped.
A bridge configuration, such as the one used in LM49101,
also creates a second advantage over single-ended ampli-
fiers. Since the differential outputs are biased at half-supply,
no net DC voltage exists across the load. This eliminates the
need for an output coupling capacitor which is required in a
single supply, single-ended amplifier configuration. Without
an output coupling capacitor, the half-supply bias across the
load would result in both increased internal IC power dissipa-
tion and also possible loudspeaker damage.
POWER DISSIPATION
Power dissipation is a major concern when designing a suc-
cessful amplifier, whether the amplifier is bridged or single-
ended. A direct consequence of the increased power
delivered to the load by a bridge amplifier is an increase in
internal power dissipation. The power dissipation of the
LM49101 varies with the mode selected. The maximum pow-
er dissipation occurs in modes where all inputs and outputs
are active (Modes 6, 7, 8, 9, 10, 11, 13, 14, 15). The power
dissipation is dominated by the Class AB amplifier. The max-
imum power dissipation for a given application can be derived
from the power dissipation graphs or from Equation 1.
HEADPHONE & CHARGE PUMP SUPPLY VOLTAGE
(VDDHP & VDDCP)
The headphone outputs are centered at ground by using dual
supply voltages for the headphone amplifier. The positive
power supply is set by the voltage on the VDDHP pin while the
negative supply is created with an internal charge pump. The
negative supply voltage is equal in magnitude but opposite in
voltage to the voltage on the VDDCP pin.
INPUT CAPACITOR SELECTION
Input capacitors may be required for some applications, or
when the audio source is single-ended. Input capacitors block
the DC component of the audio signal, eliminating any conflict
between the DC component of the audio source and the bias
voltage of the LM49101. The input capacitors create a high-
pass filter with the input resistors RIN. The -3dB point of the
high-pass filter is found using Equation (2) below.
2
PDMAX = 4*(VDD)2/(2π RL)
(1)
It is critical that the maximum junction temperature (TJMAX) of
150°C is not exceeded. TJMAX can be determined from the
power derating curves by using PDMAX and the PC board foil
area. By adding additional copper foil, the thermal resistance
of the application can be reduced from the free air value, re-
sulting in higher PDMAX. Additional copper foil can be added
to any of the leads connected to the LM49101. It is especially
effective when connected to VDD, GND, and the output pins.
Refer to the application information on the LM49101 refer-
ence design board for an example of good heat sinking. If
TJMAX still exceeds 150°C, then additional changes must be
made. These changes can include reduced supply voltage,
higher load impedance, or reduced ambient temperature. In-
ternal power dissipation is a function of output power. Refer
to the Typical Performance Characteristics curves for
f = 1 / 2πRINCIN (Hz)
(2)
Where the value of RIN is given in the Electrical Characteris-
tics Table as ZIN.
When the LM49101 is using a single-ended source, power
supply noise on the ground is seen as an input signal. Setting
the high-pass filter point above the power supply noise fre-
quencies, 217Hz in a GSM phone, for example, filters out the
noise such that it is not amplified and heard on the output.
23
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Capacitors with a tolerance of 10% or better are recommend-
ed for impedance matching and improved CMRR and PSRR.
drop and reduced power to the load on the loudspeaker out-
puts.
The current through the FET switch should not exceed 500mA
or die heating may cause thermal shut down activation and
potential IC damage.
CHARGE PUMP FLYING CAPACITOR (C1)
The flying capacitor (C1), see Figure 1, affects the load regu-
lation and output impedance of the charge pump. A C1 value
that is too low results in a loss of current drive, leading to a
loss of amplifier headroom. A higher valued C1 improves load
regulation and lowers charge pump output impedance to an
extent. Above 2.2μF, the RDS(ON) of the charge pump switches
and the ESR of C1 and Cs3 dominate the output impedance.
A lower value capacitor can be used in systems with low max-
imum output power requirements.
MINIMUM POWER OPERATION
The LM49101 has several options to reduce power consump-
tion and is designed to conserve power when possible. When
a speaker only mode is selected the headphone sections are
shutdown and the current drawn from the VDDHP/VDDCP
power supply will be zero. When a headphone mode is se-
lected the current drawn from the VDDLS supply is also re-
duced by shutting down unused circuitry. See the various
Supply Current vs Supply Voltage graphs in the Typical Per-
formance Characteristics section.
CHARGE PUMP HOLD CAPACITOR (CS3
)
The value and ESR of the hold capacitor Cs3 directly affects
the ripple on VSSCP. Increasing the value of Cs3 reduces out-
put ripple. Decreasing the ESR of Cs3 reduces both output
ripple and charge pump output impedance. A lower value ca-
pacitor can be used in systems with low maximum output
power requirements.
To reduce power consumption further, the additional control
bits GAMP_SD, LS (EP Mode), and HPR_SD are provided.
When low power consumption is more important than the
THD performance of the loudspeaker the LS (EP_mode) bit
should be set to '1' saving approximately 0.5mA from the
VDDLS supply. The GAMP_SD bit should be set on to save
approximately 0.4mA for each input shut down. For modes
where only the mono input is used, up to 0.8mA can be saved
from the VDDLS supply. Also, the HPR_SD bit can be used to
shut down the right headphone channel reducing power con-
sumption when only one amplifier headphone output is need-
ed.
SELECTION OF INPUT RESISTORS
The Bypass_In inputs connect to the loudspeaker output
through an FET switch when EP Bypass is active (see Figure
5). Because THD through this path is mainly dominated by
the switch impedance variation, adding input resistors (R3 and
R4 in Figure 5) will help reduce impedance effects resulting in
improved THD. For example, a change in the switch
impedance from 2Ω to 3Ω is a 67% change in impedance. If
10Ω input resistors are used then the impedance change is
from 12Ω to 13Ω, only 7.7% impedance variation. The analog
switch impedance is typically 2Ω to 3.4Ω. The switch
impedance change is a result of heating and the increase in
RDS(ON) of the FETs.
Additionally, the supply voltages for the different VDD pins
(VDDLS, VDDHP, and VDDCP) can be set to the minimum
needed values to obtain the output power levels required by
the design. By reducing the supply voltage the total power
consumption will be reduced.
For best system efficiency, a DC-DC converter (buck) can be
used to power the VDDHP and VDDCP voltages from the
VDDLS supply instead of a linear regulator. DC-DC converters
achieve much higher efficiency (> 90%) than even a low
dropout regulator (LDO).
The value of the input resistors must be balanced against the
amount of output current and the load impedance on the loud-
speaker outputs. A higher value input resistor reduces the
effects of switch impedance variation but also causes voltage
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24
Demo Board Circuit
30086201
FIGURE 5. Demo Board Circuit
it. When powered from the USB bus the I2CVDD will be set to
3.3V and the VDDLS will be set to 5V. Jumper headers J13 and
J12 must be set accordingly. If a single power supply for
I2CVDD and VDDLS is desired then header J5 should be used
with a jumper added to header J11 to connect I2CVDD to the
external supply voltage connected to J5 (see Figure 5).
Demonstration Board
The demonstration board (see Figure 5) has connection and
jumper options to be powered partially from the USB bus or
from external power supplies. Additional options are to power
the I2C logic and loudspeaker amplifier (VDDLS) from a single
power supply or separate power supplies. The headphone
amplifier and charge pump can also be powered from the
same supply as long as the voltage limits for each power sup-
ply are not exceeded, although the option is not built into the
board. See theOperating Ratings for each supply's range lim-
Connection headers J1 and J2 are provided along with the
stereo headphone jack J4 for easily connection and monitor-
ing of the headphone outputs.
25
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LM49101 microSMD Demo Board Views
30086209
30086205
30086208
30086210
Composite View
Silk Screen
Internal Layer 1
Bottom Layer
30086206
Top Layer
30086207
Internal Layer 2
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26
LM49101 Reference Demo Board Bill Of Materials
TABLE 7. Bill Of Materials
Designator
R1, R2
R3, R4
R5
Vlaue
5.1kΩ
10Ω
Tolerance
5%
Part Description
1/10W, 0603 Resistors
1/10W, 0603 Resistors
1/10W, 0805 Resistor
Comment
1%
5%
100kΩ
CIN1, CIN2
CIN3, CIN4
10%
10%
1206, X7R Ceramic Capacitor
Size A, Tantalum Capacitor
1μF
CS1, CS4
CS5, CB
2.2μF
CS2
CS3, C1
U1
10%
10%
0805, 16V, X7R Ceramic Capacitor
0603, 10V, X7R Ceramic Capacitor
LM49101TM
0.1μF
2.2μF
J1, J2, J3
J5, J7, J8
Input, Output, VDD, GND
0.100" 1x2 header, vertical mount
J9, J10, J14
VDD Selects, VDD, I2CVDD
GND
,
J11, J12, J13
0.100" 1x3 header, vertical mount
J6
J4
I2C Connector
16 pin header
Headphone Jack
SW1
Momentary Push Switch
RESET function
log and digital sections. It is further recommended to put
digital and analog power traces over the corresponding digital
and analog ground traces to minimize noise coupling.
PCB Layout Guidelines
This section provides practical guidelines for mixed signal
PCB layout that involves various digital/analog power and
ground traces. Designers should note that these are only
"rule-of-thumb" recommendations and the actual results will
depend heavily on the final layout.
PLACEMENT OF DIGITAL AND ANALOG COMPONENTS
All digital components and high-speed digital signals traces
should be located as far away as possible from analog com-
ponents and circuit traces.
General Mixed Signal Layout
Recommendations
AVOIDING TYPICAL DESIGN AND LAYOUT PROBLEMS
Avoid ground loops or running digital and analog traces par-
allel to each other (side-by-side) on the same PCB layer.
When traces must cross over each other do it at 90 degrees.
Running digital and analog traces at 90 degrees to each other
from the top to the bottom side as much as possible will min-
imize capacitive noise coupling and cross talk.
SINGLE-POINT POWER AND GROUND CONNECTIONS
The analog power traces should be connected to the digital
traces through a single point (link). A "Pi-filter" can be helpful
in minimizing high frequency noise coupling between the ana-
27
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Revision History
Rev
Date
10/18/08
Description
0.01
Initial released.
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28
Physical Dimensions inches (millimeters) unless otherwise noted
25 Bump micro SMD Package
NS Package Number TMD25BCA
X1 = 2.040±0.030mm X2 = 2.066±0.030mm, X3 = 0.600±0.075mm
29
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Notes
For more National Semiconductor product information and proven design tools, visit the following Web sites at:
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