LM5001MA/NOPB [NSC]

IC 1.2 A SWITCHING REGULATOR, 900 kHz SWITCHING FREQ-MAX, PDSO8, ROHS COMPLIANT, SOP-8, Switching Regulator or Controller;


型号：	LM5001MA/NOPB
厂家：	National Semiconductor
描述：	IC 1.2 A SWITCHING REGULATOR, 900 kHz SWITCHING FREQ-MAX, PDSO8, ROHS COMPLIANT, SOP-8, Switching Regulator or Controller 开关光电二极管
文件：	总18页 (文件大小：323K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

March 9, 2009

LM5001

High Voltage Switch Mode Regulator

General Description

Features

The LM5001 high voltage switch mode regulator features all

of the functions necessary to implement efficient high voltage

Boost, Flyback, SEPIC and Forward converters, using few

external components. This easy to use regulator integrates a

75 Volt N-Channel MOSFET with a 1 Amp peak current limit.

Current mode control provides inherently simple loop com-

pensation and line-voltage feed-forward for superior rejection

of input transients. The switching frequency is set with a single

resistor and is programmable up to 1.5MHz. The oscillator

can also be synchronized to an external clock. Additional pro-

tection features include: current limit, thermal shutdown, un-

der-voltage lockout and remote shutdown capability. The

device is available in both SO-8 and LLP-8 packages.

Integrated 75 volt N-Channel MOSFET

■

Ultra-wide input voltage range from 3.1V to 75V

Integrated high voltage bias regulator

Adjustable output voltage

■

1.5% output voltage accuracy

Current mode control with selectable compensation

Wide bandwidth error amplifier

Integrated current sensing and limiting

Integrated slope compensation

85% maximum duty cycle limit

Single resistor oscillator programming

Oscillator synchronization capability

Enable / Undervoltage Lockout (UVLO) pin

Thermal shutdown

Packages

SO-8

■

LLP-8 (4mm x 4mm)

■

Typical Application Circuit

20215701

Boost Regulator Application Schematic

202157

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Connection Diagrams

Top View

SO-8 Package

Top View

LLP-8 Package

20215703

20215702

Ordering Information

Order Number

LM5001MA

Package Type

SO-8

NSC Package Drawing

Supplied As

M08A

95 Units in a Rail

LM5001MAX

LM5001SD

SO-8

2500 Units on Tape and Reel

1000 Units on Tape and Reel

4500 Units on Tape and Reel

250 Units on Tape and Reel

LLP-8

SDC08A

LM5001SDX

LM5001SDE

LLP-8

Pin Descriptions

Name

Description

Application Information

LLP

VIN

Switch pin

The drain terminal of the internal power MOSFET.

Nominal operating range: 3.1V to 75V.

Input supply pin

VCC

Bias regulator output, or input for external VCC tracks VIN up to 6.9V. Above VIN = 6.9V, VCC is

bias supply

regulated to 6.9 Volts. A 0.47 µF or greater ceramic

decoupling capacitor is required. An external voltage (7V –

12V) can be applied to this pin which disables the internal

VCC regulator to reduce internal power dissipation and

improve converter efficiency.

GND

Ground

Internal reference for the regulator control functions and the

power MOSFET current sense resistor connection.

Oscillator frequency programming and

optional synchronization pulse input

The internal oscillator is set with a resistor, between this pin

and the GND pin. The recommended frequency range is

50KHz to 1.5 MHz. The RT pin can accept synchronization

pulses from an external clock. A 100 pF capacitor is

recommended for coupling the synchronizing clock to the

RT pin.

Feedback input from the regulated output This pin is connected to the inverting input of the internal

voltage

error amplifier. The 1.26V reference is internally connected

to the non-inverting input of the error amplifier.

COMP

Open drain output of the internal error

amplifier

The loop compensation network should be connected

between the COMP pin and the FB pin. COMP pull-up is

provided by an internal 5 kΩ resistor which may be used to

bias an opto-coupler transistor (while FB is grounded) for

isolated ground applications.

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Name

Description

Application Information

LLP

Enable / Under Voltage Lock-Out /

Shutdown input

An external voltage divider can be used to set the line

undervoltage lockout threshold. If the EN pin is left

unconnected, a 6 µA pull-up current source pulls the EN pin

high to enable the regulator.

Exposed Pad, LLP only

Exposed metal pad on the underside of the package with a

resistive connection to pin 6. It is recommended to connect

this pad to the PC board ground plane in order to improve

heat dissipation.

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Storage Temperature

ESD Rating (Note 2)

Human Body Model

−65°C to +150°C

2kV

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Operating Conditions

VIN to GND

SW to GND (Steady State)

VCC, EN to GND

COMP, FB, RT to GND

Maximum Junction Temperature

76V

-0.3V to 76V

14V

-0.3V to 7V

150°C

VIN

3.1V to 75V

Operating Junction

Temperature

−40°C to +125°C

Electrical Characteristics Limits in standard type are for T_J= 25°C only; limits in boldface type apply over the

junction temperature (T_J) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical

correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference purposes only.

V_VIN= 10V, R_RT= 48.7kΩ unless otherwise stated. See (Note 3).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

STARTUP REGULATOR

V_VCC-REG

VCC Regulator Output

6.55

6.85

7.15

VCC Current Limit

V_VCC= 6V

VCC UVLO Threshold

VCC Undervoltage Hysteresis

Bias Current (I_IN)

V_VCCincreasing

2.6

2.8

0.1

3.1

V_FB= 1.5V

V_EN= 0V

4.5

µA

I_Q

Shutdown Current (I_IN)

130

EN THRESHOLDS

EN Shutdown Threshold

EN Shutdown Hysteresis

EN Standby Threshold

EN Standby Hysteresis

EN Current Source

V_ENincreasing

0.25

1.2

0.45

0.1

1.26

0.1

0.65

1.32

µA

MOSFET CHARACTERISTICS

MOSFET R_DS(ON)plus

I_D= 0.5A

490

800

mΩ

Current Sense Resistance

MOSFET Leakage Current

MOSFET Gate Charge

V_SW= 75V

0.05

4.5

µA

V_VCC= 6.9V

CURRENT LIMIT

I_LIM

Cycle by Cycle Current Limit

0.8

1.0

1.2

Cycle by Cycle Current Limit Delay

100

200

OSCILLATOR

F_SW1

Frequency1

225

660

2.2

260

780

2.6

295

900

3.2

KHz

R_RT= 48.7 kΩ

R_RT= 15.8 kΩ

F_SW2

Frequency2

V_RT-SYNC

SYNC Threshold

SYNC Pulse Width Minimum

V_RT> V_RT-SYNC+ 0.5V

PWM COMPARATOR

Maximum Duty Cycle

Min On-time

V_COMP> V_COMP-OS

V_COMP< V_COMP-OS

Min On-time

V_COMP-OS

COMP to PWM Comparator Offset

0.9

1.30

1.55

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

ERROR AMPLIFIER

V_FB-REF

Feedback Reference Voltage

Internal reference

V_FB= V_COMP

1.241

1.260

1.279

FB Bias Current

DC Gain

COMP Sink Current

COMP Short Circuit Current

COMP Open Circuit Voltage

COMP to SW Delay

Unity Gain Bandwidth

V_COMP= 250mV

V_FB= 0, V_COMP= 0

V_FB= 0

2.5

0.9

4.8

1.2

5.5

1.5

6.2

MHz

THERMAL SHUTDOWN

T_SDThermal Shutdown Threshold

Thermal Shutdown Hysteresis

THERMAL RESISTANCE

165

°C

Junction to Case, SO-8

140

4.5

°C/W

θ_JC

θ_JA

θ_JC

θ_JA

Junction to Ambient, SO-8

Junction to Case, LLP-8

Junction to Ambient, LLP-8

Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended

to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Test Method is per JESD-22-A114.

Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical

Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

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Typical Performance Characteristics

Efficiency, Boost Converter

V_FBvs Temperature

20215718

20215719

20215721

20215723

I_Q(non-switching) vs V_IN

V_CCvs V_IN

20215720

R_DS(ON)vs V_CC

R_DS(ON)vs Temperature

20215722

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I_LIMvs V_CC

F_SWvs R_RT

F_SWvs V_CC

I_LIMvs V_CCvs Temperature

20215724

20215725

20215727

20215729

F_SWvs Temperature

20215726

I_ENvs V_VINvs Temperature

20215728

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Block Diagram

20215704

ceeding 1A. This feature can also be used to soft-start the

regulator. Thermal Shutdown circuitry holds the driver logic in

reset when the die temperature reaches 165°C, and returns

to normal operation when the die temperature drops by ap-

proximately 20°C. The EN pin can be used as an input voltage

under voltage lockout (UVLO) during start-up to prevent op-

eration with less than the minimum desired input voltage.

Functional Description

The LM5001 high voltage switching regulator features all the

functions necessary to implement an efficient boost, flyback,

SEPIC or forward current mode power converter. The oper-

ation can be best understood by referring to the block dia-

gram. At the start of each cycle, the oscillator sets the driver

logic and turns on the power MOSFET to conduct current

through the inductor or transformer. The peak current in the

MOSFET is controlled by the voltage at the COMP pin. The

COMP voltage will increase with larger loads and decrease

with smaller loads. This voltage is compared with the sum of

a voltage proportional to the power MOSFET current and an

internally generated Slope Compensation ramp. Slope Com-

pensation is used in current mode PWM architectures to

eliminate sub-harmonic current oscillation that occurs with

static duty cycles greater than 50%. When the summed signal

exceeds the COMP voltage, the PWM comparator resets the

driver logic, turning off the power MOSFET. The driver logic

is then set by the oscillator at the end of the switching cycle

to initiate the next power period.

High Voltage VCC Regulator

The LM5001 VCC Low Drop Out (LDO) regulator allows the

LM5001 to operate at the lowest possible input voltage. The

VCC pin voltage is very nearly equal to the input voltage from

2.8V up to approximately 6.9V. As the input voltage continues

to increase, the VCC pin voltage is regulated at the 6.9V set-

point. The total input operating range of the VCC LDO regu-

lator is 3.1V to 75V.

The output of the VCC regulator is current limited to 20mA.

During power-up, the VCC regulator supplies current into the

required decoupling capacitor (0.47 µF or greater ceramic

capacitor) at the VCC pin. When the voltage at the VCC pin

exceeds the VCC UVLO threshold of 2.8V and the EN pin is

greater than 1.26V the PWM controller is enabled and switch-

The LM5001 has dedicated protection circuitry to protect the

IC from abnormal operating conditions. Cycle-by-cycle cur-

rent limiting prevents the power MOSFET current from ex-

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ing begins. The controller remains enabled until VCC falls

below 2.7V or the EN pin falls below 1.16V.

15ns and less than 5% of the switching period. The sync pulse

rising edge initiates the internal CLK signal rising edge, which

turns off the power MOSFET. The RT resistor is always re-

quired, whether the oscillator is free running or externally

synchronized. The RT resistor should be located very close

to the device and connected directly to the RT and GND pins

of the LM5001.

An auxiliary supply voltage can be applied to the VCC pin to

reduce the IC power dissipation. If the auxiliary voltage is

greater than 6.9V, the internal regulator will essentially shut-

off, and internal power dissipation will be decreased by the

VIN voltage times the operating current. The overall converter

efficiency will also improve if the VIN voltage is much higher

than the auxiliary voltage. The externally applied VCC voltage

should not exceed 14V. The VCC regulator series pass MOS-

FET includes a body diode (see the Block Diagram) between

VCC and VIN that should not be forward biased in normal

operation. Therefore, the auxiliary VCC voltage should never

exceed the VIN voltage.

Enable / Standby

The LM5001 contains a dual level Enable circuit. When the

EN pin voltage is below 450 mV, the IC is in a low current

shutdown mode with the VCC LDO disabled. When the EN

pin voltage is raised above the shutdown threshold but below

the 1.26V standby threshold, the VCC LDO regulator is en-

abled, while the remainder of the IC is disabled. When the EN

pin voltage is raised above the 1.26V standby threshold, all

functions are enabled and normal operation begins. An inter-

nal 6 µA current source pulls up the EN pin to activate the IC

when the EN pin is left disconnected.

In high voltage applications extra care should be taken to en-

sure the VIN pin does not exceed the absolute maximum

voltage rating of 76V. Voltage ringing on the VIN line during

line transients that exceeds the Absolute Maximum Ratings

will damage the IC. Both careful PC board layout and the use

of quality bypass capacitors located close to the VIN and GND

pins are essential.

An external set-point resistor divider from VIN to GND can be

used to determine the minimum operating input range of the

regulator. The divider must be designed such that the EN pin

exceeds the 1.26V standby threshold when VIN is in the de-

sired operating range. The internal 6 µA current source should

be included when determining the resistor values. The shut-

down and standby thresholds have 100 mV hysteresis to

prevent noise from toggling between modes. When the VIN

voltage is below 3.5VDC during start-up and the operating

temperature is below -20°C, the EN pin should have a pull-up

resistor that will provide 2 µA or greater current. The EN pin

is internally protected by a 6V Zener diode through a 1 kΩ

resistor. The enabling voltage may exceed the Zener voltage,

however the Zener current should be limited to less than 4mA.

Oscillator

A single external resistor connected between RT and GND

pins sets the LM5001 oscillator frequency. To set a desired

oscillator frequency (F_SW), the necessary value for the RT re-

sistor can be calculated from the following equation:

The tolerance of the external resistor and the frequency tol-

erance indicated in the Electrical Characteristics must be

taken into account when determining the worst case frequen-

cy range.

Error Amplifier and PWM

Comparator

An internal high gain error amplifier generates an error signal

proportional to the difference between the regulated output

voltage and an internal precision reference. The output of the

error amplifier is connected to the COMP pin allowing the user

to add loop compensation, typically a Type II network, as il-

lustrated in Figure 1. This network creates a low frequency

pole that rolls off the high DC gain of the amplifier, which is

necessary to accurately regulate the output voltage.

F_{DC_POLE}is the closed loop unity gain (0 dB) frequency of this

pole. A zero provides phase boost near the closed loop unity

gain frequency, and a high frequency pole attenuates switch-

ing noise. The PWM comparator compares the current sense

signal from the current sense amplifier to the error amplifier

output voltage at the COMP pin.

External Synchronization

The LM5001 can be synchronized to the rising edge of an

external clock. The external clock must have a higher fre-

quency than the free running oscillator frequency set by the

RT resistor. The clock signal should be coupled through a

100pF capacitor into the RT pin. A peak voltage level greater

than 2.6V at the RT pin is required for detection of the sync

pulse. The DC voltage across the RT resistor is internally

regulated at 1.5 volts. The negative portion of the AC voltage

of the synchronizing clock is clamped to this 1.5V by an am-

plifier inside the LM5001 with ~100Ω output impedance.

Therefore, the AC pulse superimposed on the RT resistor

must have positive pulse amplitude of 1.1V or greater to suc-

cessfully synchronize the oscillator. The sync pulse width

measured at the RT pin should have a duration greater than

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20215706

FIGURE 1. Type II Compensator

When isolation between primary and secondary circuits is re-

quired, the Error Amplifier is usually disabled by connecting

the FB pin to GND. This allows the COMP pin to be driven

directly by the collector of an opto-coupler. In isolated designs

the external error amplifier is located on the secondary circuit

and drives the opto-coupler LED. The compensation network

is connected to the secondary side error amplifier. An exam-

ple of an isolated regulator with an opto-coupler is shown in

Figure 7.

volts when the power MOSFET turns on, and 450mV at the

end of the PWM clock cycle) adds a fixed slope to the current

sense ramp to prevent oscillation.

To prevent erratic operation at low duty cycle, a leading edge

blanking circuit attenuates the current sense signal when the

power MOSFET is turned on. When the MOSFET is initially

turned on, current spikes from the power MOSFET drain-

source and gate-source capacitances flow through the cur-

rent sense resistor. These transient currents normally cease

within 50 ns with proper selection of rectifier diodes and prop-

er PC board layout.

Current Amplifier and Slope

Compensation

Thermal Protection

The LM5001 employs peak current mode control which also

provides a cycle-by-cycle over current protection feature. An

internal 50 mΩ current sense resistor measures the current

in the power MOSFET source. The sense resistor voltage is

amplified 30 times to provide a 1.5V/A signal into the current

limit comparator. Current limiting is initiated if the internal cur-

rent limit comparator input exceeds the 1.5V threshold, cor-

responding to 1A. When the current limit comparator is

triggered, the SW output pin immediately switches to a high

impedance state.

Internal Thermal Shutdown circuitry is provided to protect the

IC in the event the maximum junction temperature is exceed-

ed. When the 165°C junction temperature threshold is

reached, the regulator is forced into a low power standby

state, disabling all functions except the VCC regulator. Ther-

mal hysteresis allows the IC to cool down before it is re-

enabled. Note that since the VCC regulator remains function-

al during this period, the soft-start circuit shown in Figure 5

should be augmented if soft-start from Thermal Shutdown

state is required.

The current sense signal is reduced to a scale factor of 1.05V/

A for the PWM comparator signal. The signal is then summed

with a 450mV peak slope compensation ramp. The combined

signal provides the PWM comparator with a control signal that

reaches 1.5V when the MOSFET current is 1A. For duty cy-

cles greater than 50%, current mode control circuits are sub-

ject to sub-harmonic oscillation (alternating between short

and long PWM pulses every other cycle). Adding a fixed slope

voltage ramp signal (slope compensation) to the current

sense signal prevents this oscillation. The 450mV ramp (zero

Power MOSFET

The LM5001 switching regulator includes an N-Channel

MOSFET with 440 mΩ on-resistance. The on-resistance of

the LM5001 MOSFET varies with temperature as shown in

the Typical Performance Characteristics graph. The typical

total gate charge for the MOSFET is 4.5 nC which is supplied

from the VCC pin when the MOSFET is turned on.

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stored in parasitic inductance and capacitance which cause

switching spikes that negatively effect efficiency, and con-

ducted and radiated emissions. These connections should be

as short as possible to reduce inductance and as wide as

possible to reduce resistance. The loop area, defined by the

SW and GND pin connections, the transformer or inductor

terminals, and their respective return paths, should be mini-

mized.

Application Information

The following information is intended to provide guidelines for

the power supply designer using the LM5001.

VIN

The voltage applied to the VIN pin can vary within the range

of 3.1V to 75V. The current into the VIN pin depends primarily

on the gate charge of the power MOSFET, the switching fre-

quency, and any external load on the VCC pin. It is recom-

mended the filter shown in Figure 2 be used to suppress

transients which may occur at the input supply. This is par-

ticularly important when VIN is operated close to the maxi-

mum operating rating of the LM5001.

EN / UVLO VOLTAGE DIVIDER SELECTION

Two dedicated comparators connected to the EN pin are used

to detect under-voltage and shutdown conditions. When the

EN pin voltage is below 0.45V, the controller is in a low current

shutdown mode where the VIN current is reduced to 95 µA.

For an EN pin voltage greater than 0.45V but less than 1.26V

the controller is in standby mode, with all internal circuits op-

erational, but the PWM gate driver signal is blocked. Once the

EN pin voltage is greater than 1.26V, the controller is fully

enabled. Two external resistors can be used to program the

minimum operational voltage for the power converter as

shown in Figure 3. When the EN pin voltage falls below the

1.26V threshold, an internal 100 mV threshold hysteresis pre-

vents noise from toggling the state, so the voltage must be

reduced to 1.16V to transition to standby. Resistance values

for R1 and R2 can be determined from the following equa-

tions:

When power is applied and the VIN voltage exceeds 2.8V with

the EN pin voltage greater than 0.45V, the VCC regulator is

enabled, supplying current into the external capacitor con-

nected to the VCC pin. When the VIN voltage is between 2.8V

and 6.9V, the VCC voltage is approximately equal to the VIN

voltage. When the voltage on the VCC pin exceeds 6.9V, the

VCC pin voltage is regulated at 6.9V. In typical flyback appli-

cations, an auxiliary transformer winding is connected

through a diode to the VCC pin. This winding must raise the

VCC voltage above 6.9V to shut off the internal start-up reg-

ulator. The current requirements from this winding are rela-

tively small, typically less than 20 mA. If the VIN voltage is

much higher than the auxiliary voltage, the auxiliary winding

will significantly improve conversion efficiency. It also reduces

the power dissipation within the LM5001. The externally ap-

plied VCC voltage should never exceed 14V. Also the applied

VCC should never exceed the VIN voltage to avoid reverse

current through the internal VCC to VIN diode shown in the

LM5001 block diagram.

where V_PWRis the desired turn-on voltage and I_DIVIDERis an

arbitrary current through R1 and R2.

For example, if the LM5001 is to be enabled when V_PWR

reaches 16V, I_DIVIDERcould be chosen as 501 µA which would

set R1 to 29.4 kΩ and R2 to 2.49 kΩ. The voltage at the EN

pin should not exceed 10V unless the current into the 6V pro-

tection Zener diode is limited below 4 mA. The EN pin voltage

should not exceed 14V at any time. Be sure to check both the

power and voltage rating (some 0603 resistors are rated as

low as 50V) for the selected R1 resistor.

20215707

FIGURE 2. Input Transient Protection

SW PIN

Attention must be given to the PC board layout for the SW pin

which connects to the power MOSFET drain. Energy can be

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20215710

FIGURE 3. Basic EN (UVLO) Configuration

Remote configuration of the controller’s operational modes

can be accomplished with open drain device(s) connected to

the EN pin as shown in Figure 4. A MOSFET or an NPN tran-

sistor connected to the EN pin can force the regulator into the

low power ‘off’ state. Adding a PN diode in the drain (or col-

lector) provides the offset to achieve the standby state. The

advantage of standby is that the VCC LDO is not disabled and

external circuitry powered by VCC remains functional.

20215711

FIGURE 4. Remote Standby and Disable Control

SOFTSTART

resistor (~5 kΩ) will supply the charging current to the SS ca-

pacitor. The SS capacitor will cause the COMP voltage to

gradually increase, until the output voltage achieves regula-

tion and FB assumes control of the COMP and the PWM duty

cycle. The SS capacitor continues charging through a large

resistance, R_SS, preventing the SS circuit from interfering with

the normal error amplifier function. During shutdown, the VCC

diode discharges the SS capacitor.

Soft-start (SS) can be implemented with an external capacitor

connected to COMP through a diode as shown in Figure 5.

The COMP discharge MOSFET conducts during Shutdown

and Standby modes to keep the COMP voltage below the

PWM offset (1.3V), which inhibits PWM pulses. The error am-

plifier will attempt to raise the COMP voltage after the EN pin

exceeds the 1.26V standby threshold. Because the error am-

plifier output can only sink current, the internal COMP pull-up

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20215712

FIGURE 5. Soft-Start

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soft-start circuit can be adjusted to limit the power-on output

voltage overshoot. If the output capacitance is sufficiently

large, no soft-start circuit is needed because the LM5001 will

gradually charge the output capacitor by current limiting at

approximately 1A (I_LIM) until regulation is achieved.

Printed Circuit Board Layout

The LM5001 Current Sense and PWM comparators are very

fast and may respond to short duration noise pulses. The

components at the SW, COMP, EN and the RT pins should

be as physically close as possible to the IC, thereby minimiz-

ing noise pickup on the PC board tracks.

ISOLATED FLYBACK

The Isolated Flyback converter (Figure 7) utilizes a 2.5V volt-

age reference (LM431) located on the isolated secondary

side for the regulation setpoint. The LM5001 internal error

amplifier is disabled by grounding the FB pin. The LM431

controls the current through the opto-coupler LED, which sets

the COMP pin voltage. The R4 and C3 network boosts the

phase response of the opto-coupler to increase the loop

bandwidth. The output is +5V at 1A and the input voltage

ranges from 16V to 42V. The switching frequency is set to

250kHz.

The SW output pin of the LM5001 should have a short, wide

conductor to the power path inductors, transformers and ca-

pacitors in order to minimize parasitic inductance that reduces

efficiency and increases conducted and radiated noise. Ce-

ramic decoupling capacitors are recommended between the

VIN pin to the GND pin and between the VCC pin to the GND

pin. Use short, direct connections to avoid clock jitter due to

ground voltage differentials. Small package surface mount

X7R or X5R capacitors are preferred for high frequency per-

formance and limited variation over temperature and applied

voltage.

BOOST

If an application using the LM5001 produces high junction

temperatures during normal operation, multiple vias from the

GND pin to a PC board ground plane will help conduct heat

away from the IC. Judicious positioning of the PC board within

the end product, along with use of any available air flow will

help reduce the junction temperatures. If using forced air

cooling, avoid placing the LM5001 in the airflow shadow of

large components, such as input capacitors, inductors or

transformers.

The Boost converter (Figure 8) utilizes the internal voltage

reference for the regulation setpoint. The output is +48V at

150mA, while the input voltage can vary from 16V to 36V. The

switching frequency is set to 250kHz. The internal VCC reg-

ulator provides 6.9V bias power, since there isn’t a simple

method for creating an auxiliary voltage with the boost topol-

ogy. Note that the boost topology does not provide output

short-circuit protection because the power MOSFET cannot

interrupt the path between the input and the output.

Application Circuit Examples

24V SEPIC

The 24V SEPIC converter (Figure 9) utilizes the internal volt-

age reference for the regulation setpoint. The output is +24V

at 250mA while the input voltage can vary from 16V to 48V.

The switching frequency is set to 250kHz. The internal VCC

regulator provides 6.9V bias power for the LM5001. An aux-

iliary voltage can be created by adding a winding on L2 and

a diode into the VCC pin.

The following schematics present examples of a Non-Isolated

Flyback, Isolated Flyback, Boost, 24V SEPIC and a 12V Au-

tomotive range SEPIC converters utilizing the LM5001

switching regulator.

NON-ISOLATED FLYBACK

The Non-Isolated Flyback converter (Figure 6) utilizes the in-

ternal voltage reference for the regulation setpoint. The output

is +5V at 1A while the input voltage can vary from 16V to 42V.

The switching frequency is set to 250kHz. An auxiliary wind-

ing on transformer (T1) provides 7.5V to power the LM5001

when the output is in regulation. This disables the internal high

voltage VCC LDO regulator and improves efficiency. The in-

put under-voltage threshold is 13.9V. The converter can be

shut down by driving the EN input below 1.26V with an open-

collector or open-drain transistor. An external synchronizing

frequency can be applied to the SYNC input. An optional soft-

start circuit is connected to the COMP pin input. When power

is applied, the soft-start capacitor (C7) is discharged and lim-

its the voltage applied to the PWM comparator by the internal

error amplifier. The internal ~5 kΩ COMP pull-up resistor

charges the soft-start capacitor until regulation is achieved.

The VCC pull-up resistor (R7) continues to charge C7 so that

the soft-start circuit will not affect the compensation network

in normal operation. If the output capacitance is small, the

12V AUTOMOTIVE SEPIC

The 12V Automotive SEPIC converter (Figure 10) utilizes the

internal bandgap voltage reference for the regulation setpoint.

The output is +12V at 50mA while the input voltage can vary

from 3.1V to 60V. The output current rating can be increased

if the minimum VIN voltage requirement is increased. The

switching frequency is set to 750kHz. The internal VCC reg-

ulator provides 6.9V bias power for the LM5001. The output

voltage can be used as an auxiliary voltage if the nominal VIN

voltage is greater than 12V by adding a diode from the output

into the VCC pin. In this configuration, the minimum input

voltage must be greater than 12V to prevent the internal VCC

to VIN diode from conducting. If the applied VCC voltage ex-

ceeds the minimum VIN voltage, then an external blocking

diode is required between the VIN pin and the power source

to block current flow from VCC to the input supply.

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20215713

FIGURE 6. Non-Isolated Flyback

20215714

FIGURE 7. Isolated Flyback

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20215715

20215716

20215717

FIGURE 8. Boost

FIGURE 9. 24V SEPIC

FIGURE 10. 12V SEPIC

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Physical Dimensions inches (millimeters) unless otherwise noted

8-Lead SO-8 Package

NS Package Number M08A

8-Lead LLP Package

NS Package Number SDC08A

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Notes

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