LM5025AMTCX/NOPB [NSC]
IC 3 A SWITCHING CONTROLLER, 650 kHz SWITCHING FREQ-MAX, PDSO16, TSSOP-16, Switching Regulator or Controller;
| 型号： | LM5025AMTCX/NOPB |
| 厂家： | 
National Semiconductor |
| 描述： | IC 3 A SWITCHING CONTROLLER, 650 kHz SWITCHING FREQ-MAX, PDSO16, TSSOP-16, Switching Regulator or Controller 控制器 |
| 文件： | 总16页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2004
LM5025
Active Clamp Voltage Mode PWM Controller
General Description
Features
n Internal Start-up Bias Regulator
n 3A Compound Main Gate Driver
The LM5025 PWM controller contains all of the features
necessary to implement power converters utilizing the Active
Clamp / Reset technique. The device can be configured to
control either a P-Channel clamp switch or an N-Channel
clamp switch. With the active clamp technique, higher effi-
ciencies and greater power densities can be realized com-
pared to conventional catch winding or RDC clamp / reset
techniques. Two control outputs are provided, the main
power switch control (OUT_A) and the active clamp switch
control (OUT_B). The active clamp output can be configured
for either a guaranteed overlap time (for P-Channel switch
applications) or a guaranteed deadtime (for N_Channel ap-
plications). The two internal compound gate drivers parallel
both MOS and Bipolar devices, providing superior gate drive
characteristics. This controller is designed for high-speed
operation including an oscillator frequency range up to 1MHz
and total PWM and current sense propagation delays less
than 100ns. The LM5025 includes a high-voltage start-up
regulator that operates over a wide input range of 13V to
90V. Additional features include: Line Under Voltage Lockout
(UVLO), softstart, oscillator UP/DOWN sync capability, pre-
cision reference and thermal shutdown.
n Programmable Line Under-Voltage Lockout (UVLO) with
Adjustable Hysteresis
n Voltage Mode Control with Feed-Forward
n Adjustable Dual Mode Over-Current Protection
n Programmable Overlap or Deadtime between the Main
and Active Clamp Outputs
n Volt x Second Clamp
n Programmable Soft-start
n Leading Edge Blanking
n Single Resistor Programmable Oscillator
n Oscillator UP / DOWN Sync Capability
n Precision 5V Reference
n Thermal Shutdown
Packages
n TSSOP-16
n LLP-16 (5x5 mm) Thermally Enhanced
Typical Application Circuit
20086901
Simplified Active Clamp Forward Power Converter
© 2004 National Semiconductor Corporation
DS200869
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Connection Diagram
20086916
16-Lead TSSOP, LLP
Ordering Information
Order Number
LM5025MTC
LM5025MTCX
LM5025SD
Package Type
NSC Package Drawing
MTC-16
Supplied As
TSSOP-16
TSSOP-16
LLP-16
92 Units per anti-static tube
2500 Units on Tape and Reel
1000 Units on Tape and Reel
4500 Units on Tape and Reel
MTC-16
SDA-16A
LM5025SDX
LLP-16
SDA-16A
Pin Description
PIN
NAME
DESCRIPTION
APPLICATION INFORMATION
1
VIN
Source Input Voltage
Input to start-up regulator. Input range 13V to 90V,
with transient capability to 100V.
2
3
4
RAMP
CS1
Modulator ramp signal
An external RC circuit from Vin sets the ramp slope.
This pin is discharged at the conclusion of every
cycle by an internal FET, initiated by either the
internal clock or the V*Sec Clamp comparator.
Current sense input for cycle-by-cycle limiting If CS1 exceeds 0.25V the outputs will go into
Cycle-by-Cycle current limit. CS1 is held low for
50ns after OUT_A switches high providing leading
edge blanking.
CS2
Current sense input for soft restart
Output overlap/Deadtime control
Precision 5 volt reference output
If CS2 exceeds 0.25V the outputs will be disabled
and a softstart commenced. The soft-start capacitor
will be fully discharged and then released with a
pull-up current of 1µA. After the first output pulse
(when SS =1V), the SS charge current will revert
back to 20µA. CS2 is held low for 50ns after OUT_A
switches high, providing leading edge blanking.
An external resistor (RSET) sets either the overlap
time or dead time for the active clamp output. An
RSET resistor connected between TIME and GND
produces in-phase OUT_A and OUT_B pulses with
overlap. An RSET resistor connected between TIME
and REF produces out-of-phase OUT_A and OUT_B
pulses with deadtime.
5
TIME
6
REF
Maximum output current: 10mA Locally decouple
with a 0.1µF capacitor. Reference stays low until the
line UVLO and the VCC UV comparators are
satisfied.
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2
Pin Description (Continued)
PIN
NAME
DESCRIPTION
APPLICATION INFORMATION
7
VCC
Output from the internal high voltage start-up If an auxiliary winding raises the voltage on this pin
regulator. The VCC voltage is regulated to
7.6V.
above the regulation setpoint, the internal start-up
regulator will shutdown, reducing the IC power
dissipation.
8
9
OUT_A
OUT_B
Main output driver
Output of the main switch PWM output gate driver.
Output capability of 3A peak sink current.
Output of the Active Clamp switch gate driver.
Capable of 1.25A peak sink current..
Active Clamp output driver
10
11
PGND
AGND
Power ground
Analog ground
Connect directly to analog ground.
Connect directly to power ground. For the LLP
package option the exposed pad is electrically
connected to AGND.
12
13
SS
Soft-start control
An external capacitor and an internal 20µA current
source set the softstart ramp. The SS current source
is reduced to 1uA initially following a CS2
over-current event or an over temperature event.
An internal 5KΩ resistor pull-up is provided on this
pin. The external opto-coupler sinks current from
COMP to control the PWM duty cycle.
COMP
Input to the Pulse Width Modulator
14
15
RT
Oscillator timing resistor pin
An external resistor connected from RT to ground
sets the internal oscillator frequency.
SYNC
Oscillator UP/DOWN synchronization input
The internal oscillator can be synchronized to an
external clock with a frequency 20% lower than the
internal oscillator’s free running frequency. There is
no constraint on the maximum sync frequency.
An external voltage divider from the power source
sets the shutdown comparator levels. The
comparator threshold is 2.5V. Hysteresis is set by an
internal current source (20µA) that is switched on or
off as the UVLO pin potential crosses the 2.5V
threshold.
16
UVLO
Line Under-Voltage shutdown
3
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Block Diagram
Simplified Block Diagram
20086902
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4
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Machine Model
200V
Storage Temperature Range
Junction Temperature
-55˚C to 150˚C
150˚C
VIN to GND
-0.3V to 100V
-0.3V to 16V
-0.3 to 1.00V
-0.3 to 7V
Operating Ratings (Note 1)
VIN Voltage
VCC to GND
13 to 90V
CS1, CS2 to GND
All other inputs to GND
ESD Rating (Note 2)
Human Body Model
External Voltage Applied to VCC
Operating Junction Temperature
8 to 15V
-40˚C to +125˚C
2kV
Electrical Characteristics
Specifications with standard typeface are for TJ = 25˚C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 31.3kΩ, RSET = 27.4kΩ) unless otherwise stated (Note 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Startup Regulator
VCC Reg
I-VIN
VCC Regulation
VCC Current Limit
Startup Regulator
Leakage (external Vcc
Supply)
No Load
7.3
20
7.6
25
7.9
V
(Note 4)
mA
µA
VIN = 100V
165
500
Shutdown Current (Iin) UVLO = 0V
350
450
µA
V
VCC Supply
VCC Under-voltage
Lockout Voltage
VCC Reg
- 220mV
VCC Reg -
120mV
(positive going Vcc
)
VCC Under-voltage
Hysteresis
1.0
1.5
2.0
4.2
V
VCC Supply Current
Cgate = 0
mA
(ICC
Reference Supply
VREF Ref Voltage
)
IREF = 0 mA
4.85
10
5
5.15
50
V
Ref Voltage
IREF = 0 to 10mA
25
mV
Regulation
Ref Current Limit
20
40
mA
ns
Current Limit
CS1 Prop CS1 Delay to Output
CS1 Step from 0 to 0.4V
Time to onset of OUT
Transition (90%)
Cgate = 0
CS2 Prop CS2 Delay to Output
CS2 Step from 0 to 0.4V
Time to onset of OUT
Transition (90%)
Cgate = 0
50
ns
V
Cycle by Cycle
Threshold Voltage
(CS1)
0.22
0.22
0.25
0.28
0.28
Cycle Skip Threshold
Voltage (CS2)
Leading Edge
Blanking Time
CS Sink Impedance
(clocked)
Resets SS capacitor;
auto restart
0.25
50
V
ns
Ω
ICS = 10mA
30
50
5
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Electrical Characteristics (Continued)
Specifications with standard typeface are for TJ = 25˚C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 31.3kΩ, RSET = 27.4kΩ) unless otherwise stated (Note 3)
Symbol
Parameter
Conditions
Min
Typ
22
1
Max
Units
Soft-Start
Soft-start Current
Source Normal
Soft-start Current
Source following a
CS2 event
17
27
µA
0.5
1.5
µA
Oscillator
Frequency1
TA = 25˚C
180
175
500
200
220
225
660
kHz
TJ = Tlow to Thigh
Frequency2
RT = 10.4KΩ
580
2
kHz
V
Sync threshold
Min Sync Pulse Width
Sync Frequency
Range
100
ns
160
kHz
PWM Comparator
Delay to Output
COMP step 5V to 0V
Time to onset of OUT_A
transition low
40
ns
Duty Cycle Range
COMP to PWM Offset
COMP Open Circuit
Voltage
0
80
1.3
5.9
%
V
0.7
4.3
1
1
V
COMP Short Circuit
Current
COMP = 0V
0.6
2.4
1.4
2.6
mA
V
Volt x Second Clamp
Ramp Clamp Level
Delta RAMP measured
from onset of OUT_A to
Ramp peak.
2.5
COMP = 5V
UVLO Shutdown
Undervoltage
2.44
16
2.5
20
2.56
24
V
Shutdown Threshold
Undervoltage
µA
Shutdown Hysteresis
Output Section
@
OUT_A High
Saturation
MOS Device Iout =
5
3
6
10
9
Ω
A
-10mA,
@
Bipolar Device Vcc/2
OUTPUT_A Peak
Current Sink
OUT_A Low
Saturation
@
MOS Device Iout =
Ω
10mA,
OUTPUT_A Rise Time Cgate = 2.2nF
20
15
10
ns
ns
Ω
OUTPUT_A Fall Time
OUT_B High
Saturation
Cgate = 2.2nF
@
MOS Device Iout =
20
18
-10mA,
@
OUTPUT_B Peak
Current Sink
Bipolar Device Vcc/2
1
A
Ω
@
OUT_B Low
MOS Device Iout =
12
20
Saturation
10mA,
OUTPUT_B Rise Time Cgate = 1nF
ns
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6
Electrical Characteristics (Continued)
Specifications with standard typeface are for TJ = 25˚C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 31.3kΩ, RSET = 27.4kΩ) unless otherwise stated (Note 3)
Symbol
Parameter
Conditions
Cgate = 1nF
Min
Typ
Max
Units
OUTPUT_B Fall Time
15
ns
Output Timing Control
Overlap Time
RSET = 38 kΩ connected
to GND, 50% to 50%
transitions
75
75
105
105
135
135
ns
ns
Deadtime
RSET = 29.5 kΩ
connected to REF, 50%
to 50% transitions
Thermal Shutdown
TSD
Thermal Shutdown
165
25
˚C
˚C
Threshold
Thermal Shutdown
Hysteresis
Thermal Resistance
θJA Junction to Ambient
MTC Package
SDA Package
125
32
˚C/W
˚C/W
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: For detailed information on soldering plastic TSSOP and LLP packages, refer to the Packaging Data Book available from National Semiconductor
Corporation.
Note 3: All limits are guaranteed. All electrical characteristics having room temperature limits are tested during production with T = T = 25˚C. All hot and cold limits
A
J
are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Note 4: Device thermal limitations may limit usable range.
7
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Typical Performance Characteristics
VCC Regulator Start-up Characteristics, VCC vs Vin
VCC vs ICC
20086903
20086904
VREF vs IREF
Oscillator Frequency vs RT
20086905
20086906
Overlap Time vs Temperature
RSET = 38K
Overlap Time vs RSET
20086907
20086908
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8
Typical Performance Characteristics (Continued)
Dead Time vs Temperature
RSET = 29.5K
Dead Time vs RSET
20086909
20086910
SS Pin Current vs Temperature
20086911
9
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An external start-up regulator or other bias rail can be used
instead of the internal start-up regulator by connecting the
VCC and the VIN pins together and feeding the external bias
voltage into the two pins.
Detailed Operating Description
The LM5025 PWM controller contains all of the features
necessary to implement power converters utilizing the Active
Clamp Reset technique. The device can be configured to
control either a P-Channel clamp switch or an N-Channel
clamp switch. With the active clamp technique higher effi-
ciencies and greater power densities can be realized com-
pared to conventional catch winding or RDC clamp / reset
techniques. Two control outputs are provided, the main
power switch control (OUT_A) and the active clamp switch
control (OUT_B). The active clamp output can be configured
for either a guaranteed overlap time (for P-Channel switch
applications) or a guaranteed dead time (for N_Channel
applications). The two internal compound gate drivers paral-
lel both MOS and Bipolar devices, providing superior gate
drive characteristics. This controller is designed for high-
speed operation including an oscillator frequency range up
to 1MHz and total PWM and current sense propagation
delays less than 100ns. The LM5025 includes a high-voltage
start-up regulator that operates over a wide input range of
13V to 90V. Additional features include: Line Under Voltage
Lockout (UVLO), softstart, oscillator UP/DOWN sync capa-
bility, precision reference and thermal shutdown.
Line Under-Voltage Detector
The LM5025 contains a line Under Voltage Lock Out (UVLO)
circuit. An external set-point voltage divider from Vin to GND,
sets the operational range of the converter. The divider must
be designed such that the voltage at the UVLO pin will be
greater than 2.5V when Vin is in the desired operating range.
If the undervoltage threshold is not met, all functions of the
controller are disabled and the controller remains in a low
power standby state. UVLO hysteresis is accomplished with
an internal 20uA current source that is switched on or off into
the impedance of the set-point divider. When the UVLO
threshold is exceeded, the current source is activated to
instantly raise the voltage at the UVLO pin. When the UVLO
pin voltage falls below the 2.5V threshold, the current source
is turned off causing the voltage at the UVLO pin to fall. The
UVLO pin can also be used to implement a remote enable /
disable function. Pulling the UVLO pin below the 2.5V
threshold disables the converter.
PWM Outputs
High Voltage Start-Up Regulator
The relative phase of the main (OUT_A) and active clamp
outputs (OUT_B) can be configured for the specific applica-
tion. For active clamp configurations utilizing a ground refer-
enced P-Channel clamp switch, the two outputs should be in
phase with the active clamp output overlapping the main
output. For active clamp configurations utilizing a high side
N-Channel switch, the active clamp output should be out of
phase with main output and there should be a dead time
between the two gate drive pulses. A distinguishing feature
of the LM5025 is the ability to accurately configure either
dead time (both off) or overlap time (both on) of the gate
driver outputs. The overlap / deadtime magnitude is con-
trolled by the resistor value connected to the TIME pin of the
controller. The opposite end of the resistor can be connected
to either REF for deadtime control or GND for overlap con-
trol. The internal configuration detector senses the connec-
tion and configures the phase relationship of the main and
active clamp outputs. The magnitude of the overlap/dead
time can be calculated as follows:
The LM5025 contains an internal high voltage start-up regu-
lator that allows the input pin (VIN) to be connected directly to
the line voltage. The regulator output is internally current
limited to 20mA. When power is applied, the regulator is
enabled and sources current into an external capacitor con-
nected to the VCC pin. The recommended capacitance range
for the VCC regulator is 0.1µF to 100µF. When the voltage on
the VCC pin reaches the regulation point of 7.6V and the
internal voltage reference (REF) reaches its regulation point
of 5V, the controller outputs are enabled. The outputs will
remain enabled until VCC falls below 6.2V or the line Under
Voltage Lock Out detector indicates that VIN is out of range.
In typical applications, an auxiliary transformer winding is
connected through a diode to the VCC pin. This winding must
raise the VCC voltage above 8V to shut off the internal
start-up regulator. Powering VCC from an auxiliary winding
improves efficiency while reducing the controller power dis-
sipation.
The external VCC capacitor must be sized such that the
capacitor and VCC self-bias will maintain a VCC voltage
greater than 6.2V during the initial start-up. During a fault
mode when the converter auxiliary winding is inactive, exter-
nal current draw on the VCC line should be limited so the
power dissipated in the start-up regulator does not exceed
the maximum power dissipation of the controller.
Overlap Time (ns) = 2.8 x RSET - 1.2
Dead Time (ns) = 2.9 x RSET +20
RSET in kΩ, Time in ns
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10
PWM Outputs (Continued)
20086912
FIGURE 1.
the internal 5V reference and COMP, can be used as the
pull-up for an optocoupler. The comparator polarity is such
that 0V on the COMP pin will produce a zero duty cycle on
both gate driver outputs.
Compound Gate Drivers
The LM5025 contains two unique compound gate drivers,
which parallel both MOS and Bipolar devices to provide high
drive current throughout the entire switching event. The Bi-
polar device provides most of the drive current capability and
provides a relatively constant sink current which is ideal for
driving large power MOSFETs. As the switching event nears
conclusion and the Bipolar device saturates, the internal
MOS device continues to provide a low impedance to com-
pete the switching event.
Volt Second Clamp
The Volt x Second Clamp comparator compares the ramp
signal (RAMP) to a fixed 2.5V reference. By proper selection
of RFF and CFF, the maximum ON time of the main switch
can be set to the desired duration. The ON time set by Volt
x Second Clamp varies inversely with the line voltage be-
cause the RAMP capacitor is charged by a resistor con-
nected to Vin while the threshold of the clamp is a fixed
voltage (2.5V). An example will illustrate the use of the Volt x
Second Clamp comparator to achieve a 50% duty cycle limit,
at 200KHz, at a 48V line input: A 50% duty cycle at a 200KHz
requires a 2.5µs of ON time. At 48V input the Volt x Second
product is 120V x µs (48V x 2.5µs). To achieve this clamp
level:
During turn-off at the Miller plateau region, typically around
2V - 3V, is where gate driver current capability is needed
most. The resistive characteristics of all MOS gate drivers
are adequate for turn-on since the supply to output voltage
differential is fairly large at the Miller region. During turn-off
however, the voltage differential is small and the current
source characteristic of the Bipolar gate driver is beneficial to
provide fast drive capability.
RFF x CFF = VIN x TON / 2.5V
48 x 2.5µ / 2.5 = 48µ
Select CFF = 470pF
RFF = 102kΩ
The recommended capacitor value range for CFF is 100pF
to 1000pF.
The CFF ramp capacitor is discharged at the conclusion of
every cycle by an internal discharge switch controlled by
either the internal clock or by the V x S Clamp comparator,
whichever event occurs first.
Current Limit
The LM5025 contains two modes of over-current protection.
If the sense voltage at the CS1 input exceeds 0.25V the
present power cycle is terminated (cycle-by-cycle current
limit). If the sense voltage at the CS2 input exceeds 0.25V,
the controller will terminate the present cycle, discharge the
softstart capacitor and reduce the softstart current source to
1µA. The softstart (SS) capacitor is released after being fully
discharged and slowly charges with a 1µA current source.
When the voltage at the SS pin reaches approximately 1V,
20086913
PWM Comparator
The PWM comparator compares the ramp signal (RAMP) to
the loop error signal (COMP). This comparator is optimized
for speed in order to achieve minimum controllable duty
cycles. The internal 5kΩ pull-up resistor, connected between
11
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sufficient to reach the CS2 threshold before the CS1 function
turns off the main output switch. This requires a high dv/dt at
the current sense pin. The signal must be fast enough to
reach the second level threshold before the first threshold
detector (CS1) turns off the gate driver. Excessive filtering on
the CS pin, an extremely low value current sense resistor or
an inductor that does not saturate with excessive loading
may prevent the second level threshold from ever being
reached.
Current Limit (Continued)
the PWM comparator will produce the first output pulse at
OUT_A. After the first pulse occurs, the softstart current
source will revert to the normal 20µA level. Fully discharging
and then slowly charging the SS capacitor protects a con-
tinuously over-loaded converter with a low duty cycle hiccup
mode.
These two modes of over-current protection allow the user
great flexibility to configure the system behavior in over-load
conditions. If it is desired for the system to act as a current
source during an over-load, then the CS1 cycle-by-cycle
current limiting should be used. In this case the current
sense signal should be applied to the CS1 input and the CS2
input should be grounded. If during an overload condition it is
desired for the system to briefly shutdown, followed by soft-
start retry, then the CS2 hiccup current limiting mode should
be used. In this case the current sense signal should be
applied to the CS2 input and the CS1 input should be
grounded. This shutdown / soft-start retry will repeat indefi-
nitely while the over-load condition remains. The hiccup
mode will greatly reduce the thermal stresses to the system
during heavy overloads. The cycle-by-cycle mode will have
higher system thermal dissipations during heavy overloads,
but provides the advantage of continuous operation for short
duration overload conditions.
A small RC filter, located near the controller, is recom-
mended for each of the CS pins. Each CS input has an
internal FET which discharges the current sense filter ca-
pacitor at the conclusion of every cycle, to improve dynamic
performance. This same FET remains on an additional 50ns
at the start of each main switch cycle to attenuate the leading
edge spike in the current sense signal.
The LM5025 CS comparators are very fast and may respond
to short duration noise pulses. Layout considerations are
critical for the current sense filter and sense resistor. The
capacitor associated with the CS filter must be placed very
close to the device and connected directly to the pins of the
IC (CS and GND). If a current sense transformer is used,
both leads of the transformer secondary should be routed to
the filter network , which should be located close to the IC. If
a sense resistor in the source of the main switch MOSFET is
used for current sensing, a low inductance type of resistor is
required. When designing with a current sense resistor, all of
the noise sensitive low power ground connections should be
connected together near the IC GND and a single connec-
tion should be made to the power ground (sense resistor
ground point).
In some systems it is possible utilize both modes concur-
rently, whereby slight overload conditions activate the CS1
cycle-by cycle mode while more severe overloading acti-
vates the CS2 hiccup mode. Operating both modes concur-
rently, requires that the slope of the inductor current be
20086914
will act directly as the master clock for the controller. Both the
frequency and the maximum duty cycle of the PWM control-
ler can be controlled by the SYNC signal (within the limita-
tions of the Volt x Second Clamp). The maximum duty cycle
(D) will be (1-D) of the SYNC signal.
Oscillator and Sync Capability
The LM5025 oscillator is set by a single external resistor
connected between the RT pin and GND. To set a desired
oscillator frequency (F), the necessary RT resistor can be
calculated from:
RT = (5725/F)1.026
Feed-Forward Ramp
where F is in kHz and RT in kΩ.
An external resistor (RFF) and capacitor (CFF) connected to
VIN and GND are required to create the PWM ramp signal.
The slope of the signal at the RAMP pin will vary in propor-
tion to the input line voltage. This varying slope provides line
feedforward information necessary to improve line transient
response with voltage mode control. The RAMP signal is
compared to the error signal at the COMP pin by the pulse
width modulator comparator to control the duty cycle of the
main switch output. The Volt Second Clamp comparator also
monitors the RAMP pin and if the ramp amplitude exceeds
2.5V the present cycle is terminated. The ramp signal is
reset to GND at the end of each cycle by either the internal
clock or the Volt Second comparator,which ever occurs first.
The RT resistor should be located very close to the device
and connected directly to the pins of the IC (RT and GND).
A unique feature of LM5025 is the ability to synchronize the
oscillator to an external clock with a frequency that is either
higher or lower than the frequency of the internal oscillator.
The lower frequency sync frequency range is 80% of the free
running internal oscillator frequency. There is no constraint
on the maximum SYNC frequency. A minimum pulse width of
100ns is required for the synchronization clock . If the syn-
chronization feature is not required, the SYNC pin should be
connected to GND to prevent any abnormal interference .
The internal oscillator can be completely disabled by con-
necting the RT pin to REF. Once disabled, the sync signal
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12
Soft-start
Thermal Protection
The softstart feature allows the power converter to gradually
reach the initial steady state operating point, thus reducing
start-up stresses and surges. At power on, a 20µA current is
sourced out of the softstart pin (SS) into an external capaci-
tor. The capacitor voltage will ramp up slowly and will limit
the COMP pin voltage and therefore the PWM duty cycle. In
the event of a fault as determined by VCC undervoltage, line
undervoltage (UVLO) or second level current limit, the output
gate drivers are disabled and the softstart capacitor is fully
discharged. When the fault condition is no longer present a
softstart sequence will be initiated. Following a second level
current limit detection (CS2), the softstart current source is
reduced to 1µA until the first output pulse is generated by the
PWM comparator. The current source returns to the nominal
Internal Thermal Shutdown circuitry is provided to protect the
integrated circuit in the event the maximum junction tem-
perature is exceeded. When activated, typically at 165˚C,
the controller is forced into a low power standby state with
the output drivers and the bias regulator disabled. The de-
vice will restart after the thermal hysteresis (typically 25˚C).
During a restart after thermal shutdown, the softstart capaci-
tor will be fully discharged and then charged in the low
current mode (1µA) similar to a second level current limit
event. The thermal protection feature is provided to prevent
catastrophic failures from accidental device overheating.
~
20µA level after the first output pulse ( 1V at the SS pin).
13
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14
Physical Dimensions inches (millimeters)
unless otherwise noted
Molded TSSOP-16
NS Package Number MTC16
Note: It is recommended that the exposed pad be connected to Pin 11 (AGND)
16-Lead LLP Surface Mount Package
NS Package Number SDA16A
15
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Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
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Support Center
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Fax: +49 (0) 180-530 85 86
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www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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