LM98722CCMTX/NOPB [NSC]
IC SPECIALTY ANALOG CIRCUIT, PDSO56, ROHS COMPLIANT, TSSOP-56, Analog IC:Other;
| 型号： | LM98722CCMTX/NOPB |
| 厂家： | 
National Semiconductor |
| 描述： | IC SPECIALTY ANALOG CIRCUIT, PDSO56, ROHS COMPLIANT, TSSOP-56, Analog IC:Other 时钟发生器 传感器 CD |
| 文件： | 总14页 (文件大小：453K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 24, 2009
LM98722
3 Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/
CMOS Output, Integrated CCD/CIS Sensor Timing
Generator and Spread Spectrum Clock Generation
General Description
Features
The LM98722 is a fully integrated, high performance 16-Bit,
45 MSPS signal processing solution for digital color copiers,
scanners, and other image processing applications. High-
speed signal throughput is achieved with an innovative archi-
tecture utilizing Correlated Double Sampling (CDS), typically
employed with CCD arrays, or Sample and Hold (S/H) inputs
(for higher speed CCD or CMOS image sensors). The signal
paths utilize 8 bit Programmable Gain Amplifiers (PGA), a
+/-9-Bit offset correction DAC and independently controlled
Digital Black Level correction loops for each input. The PGA
and offset DAC are programmed independently allowing
unique values of gain and offset for each of the three analog
inputs. The signals are then routed to a 45MHz high perfor-
mance analog-to-digital converter (ADC). The fully differential
processing channel shows exceptional noise immunity, hav-
ing a very low noise floor of -74dB. The 16-bit ADC has
excellent dynamic performance making the LM98722 trans-
parent in the image reproduction chain.
LVDS/CMOS Outputs
■
■
■
■
■
■
■
■
LVDS/CMOS/Crystal Clock Source with PLL Multiplication
Integrated Flexible Spread Spectrum Clock Generation
CDS or S/H Processing for CCD or CIS sensors
Independent Gain/Offset Correction for Each Channel
Automatic per-Channel Gain and Offset Calibration
Programmable Input Clamp Voltage
Flexible CCD/CIS Sensor Timing Generator
Key Specifications
Maximum Input Level
1.2 or 2.4 Volt Modes
(both with + or - polarity option)
16-Bit
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
ADC Resolution
ADC Sampling Rate
INL
45 MSPS
+18/-25 LSB (typ)
22.5/22.5/15 MSPS
256 Steps
Channel Sampling Rate
PGA Gain Steps
PGA Gain Range
Analog DAC Resolution
Analog DAC Range
Digital DAC Resolution
Digital DAC Range
SNR
A very flexible integrated Spread Spectrum Clock Generation
(SSCG) modulator is included to assist with EM compliance
and reduce system costs.
0.64 to 8.3x
+/-9 Bits
+/-307mV or +/-614mV
+/-6 Bits
Applications
Multi-Function Peripherals
■
■
■
■
-2048 LSB to + 2016 LSB
-74dB (@0dB PGA Gain)
630mW (LVDS)
0 to 70°C
High-speed Currency/Check Scanners
Flatbed or Handheld Color Scanners
Power Dissipation
Operating Temp
Supply Voltage
High-speed Document Scanners
3.3V Nominal (3.0V to 3.6V range)
System Block Diagram
30099570
© 2009 National Semiconductor Corporation
300995
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LM98722 Overall Chip Block Diagram
30099501
FIGURE 1. Chip Block Diagram
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LM98722 Pin Out Diagram
30099502
FIGURE 2. LM98722 Pin Out Diagram
3
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Typical Application Diagram
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Pin Descriptions
Pin
Name
PHIC2
I/O
Typ
Res
PU
Description
Configurable high speed sensor timing output.
1
2
3
4
O
D
PHIC1
SH1
CE
O
O
I
D
D
D
PD
PU
Configurable high speed sensor timing output.
Configurable low speed sensor timing output.
Chip Serial Interface Address Setting Input
CE Level
VD
Address
01
10
00
Float
DGND
5
6
7
8
9
CAL
I
D
D
D
D
D
D
D
P
P
P
A
A
P
P
A
PD
PU
PD
PD
Initiate calibration sequence. Leave unconnected or tie to DGND if unused.
Active-low master reset. NC when function not being used.
External request for an SH interval.
RESET
SH_R
SDI
I
I
I
Serial Interface Data Input.
SDO
SCLK
SEN
O
I
Serial Interface Data Output.
10
11
12
13
14
15
16
17
18
19
PD
PU
Serial Interface shift register clock.
I
Active-low chip enable for the Serial Interface.
VA
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
Analog ground return.
AGND
VA
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
Bottom of ADC reference. Bypass with a 0.1μF capacitor to ground.
Top of ADC reference. Bypass with a 0.1μF capacitor to ground.
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
Analog ground return.
VREFB
VREFT
VA
O
O
AGND
VCLP
IO
Input Clamp Voltage. Normally bypassed with a 0.1μF , and a 4.7μF capacitor to AGND.
An external reference voltage may be applied to this pin.
20
21
22
23
24
25
26
27
28
VA
P
A
P
A
P
A
P
A
A
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
Bias setting pin. Connect a 9.0 kOhm 1% resistor to AGND.
Analog ground return.
IBIAS
AGND
OSR
O
I
Analog input signal. Typically sensor Red output AC-coupled thru a capacitor.
Analog ground return.
AGND
OSG
I
Analog input signal. Typically sensor Green output AC-coupled thru a capacitor.
Analog ground return.
AGND
OSB
I
Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor.
CPOFILT2
Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1μF capacitor to
CPOFILT1.
29
30
DGND
P
A
Digital ground return.
CPOFILT1
Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1μF capacitor to
CPOFILT2.
31
32
DVB
O
I
D
D
Digital Core Voltage bypass. Not an input. Bypass with 0.1μF capacitor to DGND.
Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is
selected when pin 29 is held at DGND, otherwise clock is configured for LVDS operation.
INCLK+
33
34
INCLK-
I
D
D
Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock.
Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS Mode.
DOUT7/
TXCLK+
DOUT6/
TXCLK-
DOUT5/
TXOUT2+
O
35
36
O
O
D
D
Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS Mode.
Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS Mode.
5
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Pin
37
Name
DOUT4/
I/O
Typ
Res
Description
O
D
Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS Mode.
TXOUT2-
DOUT3/
TXOUT1+
DOUT2/
TXOUT1-
DOUT1/
TXOUT0+
DOUT0/
TXOUT0-
DGND
38
39
40
41
O
O
O
O
O
D
D
D
D
Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS Mode.
Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS Mode.
Bit 1 of the digital video output bus in CMOS Mode, LVDS Data Out0+ in LVDS Mode.
Bit 0 of the digital video output bus in CMOS Mode, LVDS Data Out0- in LVDS Mode.
Configurable sensor control output.
42
43
D
P
PD
VD
Power supply for the digital circuits. Bypass this supply pin with 0.1μF capacitor. A single
4.7μF capacitor should be used between the supply and the VD, VR and VC pins.
44
45
VC
P
D
Power supply for the sensor control outputs. Bypass this supply pin with 0.1μF capacitor.
Output clock for registering output data when using CMOS outputs, or a configurable
low speed sensor timing output.
CLKOUT/SH2 O
46
47
48
49
50
51
52
SH3
RS
O
O
O
O
O
D
D
D
D
D
P
P
Configurable low speed sensor timing output.
Configurable high speed sensor timing output.
Configurable high speed sensor timing output.
Configurable high speed sensor timing output.
Configurable high speed sensor timing output.
Digital ground return.
CP
PHIA1
PHIA2
DGND
VC
Power supply for the sensor control outputs.
Bypass this supply pin with 0.1μF capacitor.
Configurable high speed sensor timing output.
Configurable high speed sensor timing output.
Configurable low speed sensor timing output.
Configurable low speed sensor timing output.
53
54
55
56
PHIB1
PHIB2
SH4
O
O
O
O
D
D
D
D
SH5
(I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down with an internal resistor.).
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<66°C/W
>1.89W
Thermal Resistance (θJA
Package Dissipation at TA = 25°C
(Note 4)
)
Absolute Maximum Ratings (Note 1, Note
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Rating (Note 5)
Human Body Model
Machine Model
2500V
250V
Supply Voltage (VA,VR,VD,VC)
4.2V
Storage Temperature
−65°C to +150°C
Voltage on Any Input Pin
(Not to exceed 4.2V)
Voltage on Any Output Pin
−0.3V to
(VA + 0.3V)
−0.3V to
(VA + 0.3V)
Soldering process must comply with National
Semiconductor’s Reflow Temperature Profile
specifications. Refer to www.national.com/packaging.
(Note 6)
(execpt DVB and not to exceed 4.2V)
DVB Output Pin Voltage
2.0V
Operating Ratings (Note 1, Note 2)
Input Current at any pin other than
Supply Pins (Note 3)
Package Input Current (except Supply
Pins) (Note 3)
±25 mA
Operating Temperature Range
0°C ≤ TA ≤ +70°C
±50 mA
150°C
All Supply Voltage
+3.0V to +3.6V
Maximum Junction Temperature (TA)
Electrical Characteristics
The following specifications apply for VA = VD = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface
limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
Min
(Note 9)
Typ
(Note 8)
Max
(Note 9)
Symbol
Parameter
Conditions
Units
CMOS Digital Input DC Specifications (RESETb, SH_R, SCLK, SENb)
VIH
VIL
Logical “1” Input Voltage
Logical “0” Input Voltage
Logic Input Hysteresis
Logical “1” Input Current
2.0
V
V
0.8
VIHYST
IIH
0.6
VIH = VD
RESET,SEN
SH_R, SCLK, SDI, CAL
CE
100
65
nA
μA
nA
30
IIL
Logical “0” Input Current
VIL = DGND
RESETSEN
-65
-100
-30
μA
nA
μA
SH_R, SCLK, SDI, CAL
CE
CMOS Digital Output DC Specifications (SH1 to SH5, RS, CP, PHIA, PHIB, PHIC)
VOH
VOL
IOS
Logical “1” Output Voltage
Logical “0” Output Voltage
Output Short Circuit Current
IOUT = -0.5mA
IOUT = 1.6mA
VOUT = DGND
VOUT= VD
3.0
V
V
0.21
18
-25
20
mA
IOZ
CMOS Output TRI-STATE Current
VOUT = DGND
VOUT = VD
nA
-25
CMOS Digital Output DC Specifications (CMOS Data Outputs)
VOH
VOL
IOS
Logical “1” Output Voltage
Logical “0” Output Voltage
Output Short Circuit Current
IOUT = -0.5mA
IOUT = 1.6mA
VOUT = DGND
VOUT= VD
2.3
0.12
12
V
V
mA
-14
20
IOZ
CMOS Output TRI-STATE Current
VOUT = DGND
VOUT = VD
nA
-25
7
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Min
(Note 9)
Typ
(Note 8)
Max
(Note 9)
Symbol
Parameter
Conditions
Units
LVDS/CMOS Clock Receiver DC Specifications (INCLK+ and INCLK- Pins)
VIHL
Differential LVDS Clock
High Threshold Voltage
200
mV
RL = 100Ω
VCM (LVDS Input Common Mode
Voltage)= 1.25V
VILL
VIHC
VILC
IIHL
Differential LVDS Clock
Low Threshold Voltage
CMOS Clock
-200
2.0
mV
V
INCLK- = DGND
High Threshold Voltage
CMOS Clock
0.8
V
Low Threshold Voltage
CMOS Clock
230
260
μA
μA
Input High Current
CMOS Clock
IILC
-135
-120
Input Low Current
LVDS Output DC Specifications
VOD
VOS
IOS
Differential Output Voltage
280
390
1.20
8.5
490
mV
V
RL = 100Ω
LVDS Output Offset Voltage
Output Short Circuit Current
1.08
1.33
mA
VOUT = 0V, RL = 100Ω
LVDS Output Data Format
Power Supply Specifications
IA
VA Analog Supply Current
139
3.1
162
4.5
mA
mA
LVDS Output Data Format
(Powerdown)
CMOS Output Data Format
(40 MHz)
137
161
mA
ID
VD Digital Output Driver Supply
Current
LVDS Output Data Format
50
65
8
mA
mA
LVDS Output Data Format
(Powerdown)
5.5
CMOS Output Data Format
(ATE Loading of CMOS Outputs
> 50 pF) (40 MHz)
48
1
62
4
mA
mA
IC
VC CCD Timing Generator Output
Driver Supply Current
Typical sensor outputs:
SH1-SH5, PHIA, PHIB, PHIC,
RS, CP
(ATE Loading of CMOS
Outputs > 50pF)
PWR
Average Power Dissipation
LVDS Output Data Format
630
28
736
32
mW
mW
LVDS Output Data Format
(Powerdown)
CMOS Output Data Format
(ATE Loading of CMOS Outputs
> 50pF) (40 MHz)
600
740
mW
Input Sampling Circuit Specifications
VIN
Input Voltage Level
CDS Gain=1x, PGA Gain=1x
CDS Gain=2x, PGA Gain= 1x
2.3
Vp-p
1.22
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Min
(Note 9)
Typ
(Note 8)
Max
(Note 9)
Symbol
Parameter
Conditions
Units
IIN_SH
Sample and Hold Mode
Input Leakage Current
Source Followers Off
CDS Gain = 1x
19
25
μA
(-103)
(-152)
(-250)
(-95)
OSX = VA (OSX = AGND)
Source Followers Off
CDS Gain = 2x
33
50
μA
nA
pF
(-141)
OSX = VA (OSX = AGND)
Source Followers On
CDS Gain = 2x
20
250
(-50)
OSX = VA (OSX = AGND)
CSH
Sample/Hold Mode
CDS Gain = 1x
2.5
Equivalent Input Capacitance
CDS Gain = 2x
Source Followers Off
OSX = VA (OSX = AGND)
4
pF
nA
IIN_CDS
RCLPIN
CDS Mode
10
250
55
Input Leakage Current
(-250)
(-50)
CLPIN Switch Resistance
(OSX to VCLP Node)
16
Ω
VCLP Reference Circuit Specifications
VCLP Voltage 000
VCLP Voltage Setting = 000
VCLP Voltage Setting = 001
VCLP Voltage Setting = 010
VCLP Voltage Setting = 011
VCLP Voltage Setting = 100
VCLP Voltage Setting = 101
VCLP Voltage Setting = 110
VCLP Voltage Setting = 111
0.85VA
0.9VA
0.95VA
0.6VA
0.55VA
0.4VA
0.35VA
0.15VA
30
V
V
VCLP Voltage 001
VCLP Voltage 010
V
VCLP Voltage 011
VVCLP
V
VCLP Voltage 100
V
VCLP Voltage 101
VCLP Voltage 110
VCLP Voltage 111
V
V
V
ISC
VCLP DAC Short Circuit Output
Current
0001 xxxxb VCLP Config.
Register =
mA
Black Level Offset DAC Specifications
Resolution
10
Bits
Monotonicity
Guaranteed by characterization
Offset Adjustment Range
Referred to AFE Input
CDS Gain = 1x
Minimum DAC Code = 0x000
Maximum DAC Code = 0x3FF
CDS Gain = 2x
-614
614
mV
mV
Minimum DAC Code = 0x000
Maximum DAC Code = 0x3FF
Minimum DAC Code = 0x000
-307
307
Offset Adjustment Range
Referred to AFE Output
DAC LSB Step Size
-17500
-16130
+17500
1.2
LSB
mV
Maximum DAC Code = 0x3FF +16130
CDS Gain = 1x
Referred to AFE Output
-0.85
(32)
(LSB)
LSB
DNL
INL
Differential Non-Linearity
Integral Non-Linearity
+0.74/
-0.37
+2.4
+2.5
-2.5
+0.72/
-0.56
LSB
Bits
PGA Specifications
Gain Resolution
Monotonicity
8
Guaranteed by characterization
Maximum Gain
CDS Gain = 1x
CDS Gain = 1x
7.7
8.3
8.8
V/V
dB
17.7
18.4
18.9
9
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Min
(Note 9)
Typ
(Note 8)
Max
(Note 9)
Symbol
Parameter
Conditions
Units
Minimum Gain
CDS Gain = 1x
CDS Gain = 1x
0.58
-4.7
0.64
-4.2
0.70
-3.5
V/V
dB
PGA Function
Gain (V/V) = (180/(277-PGA Code))
Gain (dB) = 20LOG10(180/(277-PGA Code))
Channel Matching
Minimum PGA Gain
3
%
Maximum PGA Gain
12.7
ADC Specifications
VREFT
VREFB
Top of Reference
2.07
0.89
1.18
V
V
V
Bottom of Reference
VREFT
-
Differential Reference Voltage
1.06
1.30
VREFB
Overrange Output Code
Underrange Output Code
65535
0
Digital Offset “DAC” Specifications
Resolution
7
32
Bits
Digital Offset DAC LSB Step Size
Referred to AFE Output
Min DAC Code =7b0000000
Mid DAC Code =7b1000000
Max DAC Code = 7b1111111
LSB
Offset Adjustment Range
Referred to AFE Output
-2048
0
LSB
+2016
Full Channel Performance Specifications
DNL
INL
Differential Non-Linearity
Integral Non-Linearity
(Note 10)
(Note 10)
-0.999
-75
+0.8/-0.7
+18/-25
-76
2.5
75
LSB
LSB
Minimum PGA Gain
dB
(Note 10)
10
26
LSB RMS
dB
SNR
Total Output Noise
Maximum PGA Gain
-56
(Note 10)
96
LSB RMS
Channel to Channel Crosstalk
Mode 3
Mode 2
26
LSB
17
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AC Timing Specifications
The following specifications apply for VA = VD = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface
limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
Min
(Note
9)
Typ
(Note 8)
Max
(Note 9)
Symbol
Parameter
Conditions
Units
Input Clock Timing Specifications
INCLK = PIXCLK
(Pixel Rate Clock)
0.66
1
15 (Mode 3)
22.5 (Mode 2)
22.5 (Mode 1)
45 (Mode 3)
45 (Mode 2)
22.5 (Mode 1)
60/40
MHz
1
fINCLK
Input Clock Frequency
Input Clock Duty Cycle
INCLK = ADCCLK
(ADC Rate Clock)
2
MHz
%
Tdc
40/60
50/50
Full Channel Latency Specifications
PIXPHASE0
PIXPHASE1
PIXPHASE2
PIXPHASE3
PIXPHASE0
PIXPHASE1
PIXPHASE2
PIXPHASE3
PIXPHASE0
PIXPHASE1
PIXPHASE2
PIXPHASE3
24
23 1/2
23
3 Channel Mode Pipeline Delay
tLAT3
TADC
TADC
TADC
22 1/2
21
2 Channel Mode Pipeline Delay
tLAT2
20 1/2
20
19 1/2
19
1 Channel Mode Pipeline Delay
tLAT1
18 1/2
18
17 1/2
SH_R Timing Specifications
tSHR_S
tSHR_H
SH_R Setup Time
SH_R Hold Time
2
2
ns
ns
LVDS Output Timing Specifications
TXpp0
TXpp1
TXpp2
TXpp3
TXpp4
TXpp5
TXpp6
TXCLK to Pulse Position 0
TXCLK to Pulse Position 1
TXCLK to Pulse Position 2
TXCLK to Pulse Position 3
TXCLK to Pulse Position 4
TXCLK to Pulse Position 5
TXCLK to Pulse Position 6
-0.46
2.71
0
0.46
3.63
ns
ns
ns
ns
ns
ns
ns
LVDS Output
Specifications not
tested in production.
Min/Max guaranteed
by design,
3.17
6.35
9.52
12.70
15.87
19.05
5.89
6.81
9.06
9.98
12.24
13.16
16.33
19.51
characterization and statistical 15.41
analysis.
18.59
ꢀ
ꢀ
CMOS Output Timing Specifications
fINCLK = 40MHz
INCLK = ADCCLK
(ADC Rate Clock)
CLKOUT Rising Edge to CMOS
tCRDO
2
6
9
ns
Output Data Transition
Serial Interface Timing Specifications
11
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Min
(Note
9)
Typ
(Note 8)
Max
(Note 9)
Symbol
Parameter
Conditions
Units
fSCLK <= fINCLK
INCLK = PIXCLK
(Pixel Rate Clock)
Mode 3/2/1
15/22.5/22.5
45/45/22.5
MHz
fSCLK
Input Clock Frequency
fSCLK <= fINCLK
INCLK = ADCCLK
(ADC Rate Clock)
Mode 3/2/1
MHz
SCLK Duty Cycle
Input Hold Time
50/50
ns
ns
ns
ns
tIH
tIS
1.5
2.5
1.5
Input Setup Time
tSENSC
SCLK Start Time After SEN Low
SEN High after last SCLK Rising
Edge
tSCSEN
2.5
ns
TINCLK
ns
INCLK present
6
tSENW
SEN Pulse Width
INCLK stopped
50
(Note 11, Note 12)
tOD
tHZ
Output Delay Time
11
14
ns
TSCLK
Data Output to High Z
0.5
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions. Operation of the device beyond the Operating Ratings is not recommended.
Note 2: All voltages are measured with respect to AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to 25 mA.
The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25
mA to two.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJMAX – TA)/θJA. The values for maximum power dissipation listed above will be reached only when the
device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 7: The analog inputs are protected as shown below. Input voltage magnitudes beyond the supply rails will not damage the device, provided the current is
limited per note 3. However, input errors will be generated If the input goes above VA and below AGND.
30099571
Note 8: Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not
guaranteed.
Note 9: Test limis are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 10: This parameter guaranteed by design and characterization.
Note 11: If the input INCLK is divided down to a lower internal clock rate via the PLL, the parameter tSENW will be increased by the same factor.
Note 12: When the Spread Spectrum Clock Generation feature is enabled, tSENW should be increased by 1.
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12
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead TSSOP
NS Package Number MTD56
13
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