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LM98725

SNAS474H –APRIL 2009–REVISED MARCH 2015

LM98725 3 Channel, 16-Bit, 81 MSPS Analog Front End with LVDS/CMOS Output,

Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock Generation

1 Features

3 Description

The LM98725 is a fully integrated, high performance

16-Bit, 81 MSPS signal processing solution for digital

color copiers, scanners, and other image processing

applications. The LM98725 achieves high-speed

signal throughput with an innovative architecture

utilizing Correlated Double Sampling (CDS), typically

employed with CCD arrays, or Sample and Hold

(S/H) inputs (for higher speed CCD or CMOS image

sensors). The signal paths utilize 8 bit Programmable

Gain Amplifiers (PGA), a ±9-Bit offset correction

DAC, and independently controlled Digital Black

Level correction loops for each input. The

independently programmed PGA and offset DAC

allow unique values of gain and offset for each of the

three analog inputs. The signals are then routed to a

81 MHz high performance analog-to-digital converter

(ADC). The fully differential processing channel

shows exceptional noise immunity with a very low

noise floor of –74 dB. The 16-bit ADC has excellent

dynamic performance making the LM98725

transparent in the image reproduction chain.

1

•

LVDS/CMOS Outputs

LVDS/CMOS/Crystal Clock Source with PLL

Multiplication

•

Integrated Flexible Spread Spectrum Clock

Generation

•

CDS or S/H Processing for CCD or CIS Sensors

Independent Gain/Offset Correction for Each

Channel

•

Automatic per-Channel Gain and Offset

Calibration

•

Programmable Input Clamp Voltage

Flexible CCD/CIS Sensor Timing Generator

2 Applications

•

Multi-Function Peripherals

High-speed Currency/Check Scanners

Flatbed or Handheld Color Scanners

High-speed Document Scanners

Key Specifications:

A very flexible integrated Spread Spectrum Clock

Generation (SSCG) modulator is included to assist

with EM compliance and reduce system costs.

–

Maximum Input Level

–

1.2 or 2.4 Volt Modes

Device Information⁽¹⁾

(Both with + or - Polarity Option)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

–

ADC Resolution: 16-Bit

LM98725

TSSOP (56)

14.0 mm × 6.10 mm

ADC Sampling Rate: 81 MSPS

INL: +17/- 28 LSB (typ)

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Channel Sampling Rate: 30/30/27 MSPS

PGA Gain Steps: 256 Steps

System Block Diagram

CCD/CIS Sensor

PGA Gain Range: 0.62 to 8.3x

Analog DAC Resolution: ±9 Bits

Analog DAC Range: ±307 mV or ±614 mV

Digital DAC Resolution: ±6 Bits

Digital DAC Range: -2048 LSB to + 2016 LSB

SNR: –74dB (@0 dB PGA Gain)

Power Dissipation: 755 mW (LVDS)

Operating Temp: 0 to 70°C

Analog Front End

SPI

Image Processor/

LM98725

ASIC

Data Output

CCD Timing

Sensor Drivers

Generator

Motor

Controllers

CLK

SSCG

Supply Voltage: 3.3 V Nominal (3.0-V to 3.6-V

Range)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM98725

SNAS474H –APRIL 2009–REVISED MARCH 2015

www.ti.com

Table of Contents

7.1 Overview ................................................................. 14

7.2 Functional Block Diagrams ..................................... 15

7.3 Feature Description................................................. 16

7.4 Device Functional Modes........................................ 24

7.5 Register Maps......................................................... 88

Layout ................................................................. 136

8.1 Layout Example .................................................... 136

Device and Documentation Support................ 137

9.1 Trademarks........................................................... 137

9.2 Device Support...................................................... 137

9.3 Electrostatic Discharge Caution............................ 137

9.4 Glossary................................................................ 137

1

2

3

4

5

6

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 Handling Ratings....................................................... 6

6.3 Recommended Operating Conditions....................... 6

6.4 Electrical Characteristics........................................... 7

6.5 AC Timing Specifications ........................................ 11

6.6 Serial Interface Timing Details................................ 13

Detailed Description ............................................ 14

8

9

10 Mechanical, Packaging, and Orderable

7

Information ......................................................... 137

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision G (October 2014) to Revision H

Page

•

Changed "29" to "33" for Pin number 32 in Pin Functions ..................................................................................................... 4

Deleted "Boldface limits apply..." statement in Electrical Characteristics and AC Timing Specifications ............................. 7

Changed "internal" to "external" and "external" to "internal" for "SH_R Capture Clock Select (Page 0, Register 0x00,

Bit 5)" heading in Clock Sources - Additional Settings and Flexibility ................................................................................. 18

•

Changed 25 MHz to 27 MHz and 75 MHz to 81 MHz for Table 3 ...................................................................................... 24

Changed "Page 2" to "Page 0" in CCD Timing Generator Master/Slave Modes ................................................................ 63

Changed "Page 2" to "Page 0" in Master Timing Generator Mode ..................................................................................... 63

Changed "1100 0000" to " 1100 0010" in Table 18............................................................................................................ 101

Changes from Revision F (January 2014) to Revision G

Page

•

Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and Functions;

Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information ....................................... 1

Added "Note" in Serial Interface........................................................................................................................................... 84

Changes from Revision E (April 2013) to Revision F

Page

•

Added content from System Overview section to end of document. .................................................................................. 16

Changes from Revision D (April 2009) to Revision E

Page

•

Changed layout of National Data Sheet to TI format ........................................................................................................... 13

2

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SNAS474H –APRIL 2009–REVISED MARCH 2015

5 Pin Configuration and Functions

56-Pin TSSOP

Package DGG

Top View

PHIC2

PHIC1

SH1

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

SH5

2

SH4

3

PHIB2

PHIB1

CE

4

CAL

5

V

C

6

DGND

PHIA2

PHIA1

CP

RESET

SH_R

7

SDI

SDO

SCLK

SEN

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

RS

SH3

CLKOUT/SH2

V

A

AGND

V

C

56 Pin TSSOP

(not to scale)

V

A

D

VREFB

VREFT

DGND

DOUT0/TXOUT0-

DOUT1/TXOUT0+

DOUT2/TXOUT1-

DOUT3/TXOUT1+

DOUT4/TXOUT2-

DOUT5/TXOUT2+

DOUT6/TXCLK-

DOUT7/TXCLK+

INCLK-

V

A

AGND

VCLP

V

A

IBIAS

AGND

OS

R

AGND

OS

INCLK+

G

AGND

OS

DVB

CPOFILT1

B

CPOFILT2

DGND

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SNAS474H –APRIL 2009–REVISED MARCH 2015

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Pin Functions

I/O

TYP RES

DESCRIPTION

NO.

1

NAME

PHIC2

O

I

D

Configurable high speed sensor timing output.

Configurable low speed sensor timing output.

Chip Serial Interface Address Setting Input

2

PHIC1

SH1

CE

3

4

CE Level

VD

Address

01

10

00

Float

DGND

5

CAL

I

D

P

A

P

A

PD

PU

PD

Initiate calibration sequence. Leave unconnected or tie to DGND if unused.

Active-low master reset. NC when function not being used.

External request for an SH pulse.

6

RESET

SH_R

SDI

7

I

8

I

Serial Interface Data Input. Can be tied to SDO for compatibility with LM98714 designs.

Serial Interface Data Output. Can be tied to SDI for compatibility with LM98714 designs.

Serial Interface shift register clock.

9

SDO

SCLK

SEN

O

I

10

11

12

13

14

15

16

17

18

19

PD

PU

I

Active-low chip enable for the Serial Interface.

V_A

Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.

Analog ground return.

AGND

V_A

Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.

Bottom of ADC reference. Bypass with a 0.1μF capacitor to ground.

Top of ADC reference. Bypass with a 0.1μF capacitor to ground.

Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.

Analog ground return.

VREFB

VREFT

V_A

O

AGND

VCLP

IO

Input Clamp Voltage. Normally bypassed with a 0.1μF , and a 4.7μF capacitor to AGND.

An external reference voltage may be applied to this pin.

20

21

22

23

24

25

26

27

28

V_A

P

A

P

A

P

A

P

A

Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.

Bias setting pin. Connect a 9.0 kΩ 1% resistor to AGND.

Analog ground return.

IBIAS

AGND

OS_R

O

I

Analog input signal. Typically sensor Red output AC-coupled thru a capacitor.

Analog ground return.

AGND

OS_G

I

Analog input signal. Typically sensor Green output AC-coupled thru a capacitor.

Analog ground return.

AGND

OS_B

I

Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor.

CPOFILT2

Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1μF capacitor to

CPOFILT1.

29

30

DGND

P

A

Digital ground return.

CPOFILT1

Charge Pump Filter Capacitor.

Bypass this supply pin with a 0.1μF capacitor to CPOFILT2.

31

32

DVB

O

I

D

Digital Core Voltage bypass. Not an input. Bypass with 0.1μF capacitor to DGND.

INCLK+

Clock Input.

When XTALEN=0

Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is selected when

pin 33 is held at DGND. Otherwise clock is configured for LVDS operation.

When XTALEN=1

Connection to terminal 2 of crystal.

An 18 pF capacitor should be connected from terminal 1 of the crystal to ground.

33

INCLK-

I

D

Clock Input.

When XTALEN=0

Inverting input for LVDS clocks, connect to DGND for CMOS clock.

When XTALEN=1

Connection to terminal 1 of crystal. A 18 pF capacitor should be connected from terminal 1

of the crystal to ground.

4

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SNAS474H –APRIL 2009–REVISED MARCH 2015

Pin Functions (continued)

NAME

DOUT7/

I/O

TYP RES

DESCRIPTION

NO.

34

O

D

Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS Mode.

Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS Mode.

Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS Mode.

Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS Mode.

Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS Mode.

Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS Mode.

Bit 1 of the digital video output bus in CMOS Mode, LVDS Data Out0+ in LVDS Mode.

Bit 0 of the digital video output bus in CMOS Mode, LVDS Data Out0- in LVDS Mode.

Digital ground return.

TXCLK+

DOUT6/

TXCLK-

DOUT5/

TXOUT2+

DOUT4/

TXOUT2-

DOUT3/

TXOUT1+

DOUT2/

TXOUT1-

DOUT1/

TXOUT0+

DOUT0/

TXOUT0-

DGND

35

36

37

38

39

40

41

O

D

42

43

p

V_D

P

Power supply for the digital circuits. Bypass this supply pin with 0.1μF capacitor. A single

4.7μF capacitor should be used between the supply and the VD, VR and VC pins.

44

45

V_C

P

D

Power supply for the sensor control outputs. Bypass this supply pin with 0.1μF capacitor.

CLKOUT/SH2

O

Output clock for registering output data when using CMOS outputs, or a configurable low

speed sensor timing output.

46

47

48

49

50

51

52

SH3

RS

O

D

P

Configurable low speed sensor timing output.

Configurable high speed sensor timing output.

Digital ground return.

CP

PHIA1

PHIA2

DGND

V_C

Power supply for the sensor control outputs.

Bypass this supply pin with 0.1μF capacitor.

53

54

55

56

PHIB1

PHIB2

SH4

O

D

Configurable high speed sensor timing output.

Configurable low speed sensor timing output.

SH5

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SNAS474H –APRIL 2009–REVISED MARCH 2015

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6 Specifications

6.1 Absolute Maximum Ratings^(1)(2)(3)

MIN

MAX

4.2

UNIT

V

Any Positive Supply Voltage (VA, VR, VD, VC)

Voltage on Any Input or Output Pin (except DVB) (Not to exceed 4.2V)

DVB Output Voltage

−0.3

4.2

V

2.0

V

Input Current at any pin⁽⁴⁾

Package Input Current⁽⁴⁾

Package Dissipation at T_A= 25°C⁽⁵⁾

Soldering Temperature, Infrared, 10 seconds⁽⁶⁾

±25

±50

1.9

mA

W

235

°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions. Operation of the device beyond the Operating Ratings is not

recommended.

(2) All voltages are measured with respect to A_GND= D_GND= 0V, unless otherwise specified.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(4) When the input voltage (V_IN) at any pin exceeds the power supplies (V_IN< GND or V_IN> V_Aor V_D), the current at that pin should be

limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the

power supplies with an input current of 25 mA to two.

(5) The absolute maximum junction temperature (T_JMAX) for this device is 150°C. The maximum allowable power dissipation is dictated by

T_JMAX, the junction to ambient thermal resistance (R_θJA), and the ambient temperature (TA), and can be calculated using the formula

PDMAX = (T_JMAX- TA)/R_θJA. The values for maximum power dissipation listed will be reached only when the LM98725 is operated in a

severe faulty condition.

(6) See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any

post 1986 Texas Instruments Semiconductor Linear Data Book, for other methods of soldering surface mount devices.

6.2 Handling Ratings

MIN

MAX

+150

2500

UNIT

T_stg

Storage temperature range

−65

°C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins⁽²⁾

V_(ESD)

Electrostatic discharge⁽¹⁾

V

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins⁽³⁾

250

(1) Human body model is 100 pF capacitor discharged through a 1.5-kΩ resistor. Machine model is 220-pF discharged through 0Ω.

(2) JEDEC document JEP155 states that 2500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions⁽¹⁾⁽²⁾

MIN

MAX

0 ≤ T_A≤ +70

+3.6

UNIT

°C

Operating Temperature Range

All Supply Voltage

+3.0

V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions. Operation of the device beyond the Operating Ratings is not

recommended.

(2) All voltages are measured with respect to AGND = DGND = 0V, unless otherwise specified.

6

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SNAS474H –APRIL 2009–REVISED MARCH 2015

6.4 Electrical Characteristics

The following specifications apply for VA = VD = VR = VC = 3.3 V, C_L= 10 pF, and f_INCLK= 27 MHz unless otherwise

specified. all other limits T_A= 25°C.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN⁽²⁾TYP⁽³⁾MAX⁽²⁾UNIT

CMOS DIGITAL INPUT DC SPECIFICATIONS (RESETb, SH_R, SCLK, SENb)

V_IH

Logical “1” Input Voltage

Logical “0” Input Voltage

Logic Input Hysteresis

2.0

V

V_IL

0.8

V_IHYST

0.6

V_IH= VD:

RESET, SEN

100

65

nA

I_IH

Logical “1” Input Current

Logical “0” Input Current

SH_R, SCLK, SDI, CAL

CE

μA

30

V_IL= DGND:

RESET, SEN

SH_R, SCLK, SDI, CAL

CE

–65

–100

–30

μA

nA

μA

I_IL

CMOS DIGITAL OUTPUT DC SPECIFICATIONS (SH1 to SH5, RS, CP, PHIA, PHIB, PHIC)

V_OH

V_OL

I_OS

Logical “1” Output Voltage

Logical “0” Output Voltage

Output Short Circuit Current

I_OUT= -0.5 mA

I_OUT= 1.6 mA

V_OUT= DGND

V_OUT= VD

3.0

V

0.21

18

–25

20

mA

nA

I_OZ

CMOS Output TRI-STATE

Current

V_OUT= DGND

V_OUT= VD

–25

CMOS DIGITAL OUTPUT DC SPECIFICATIONS (CMOS DATA OUTPUTS)

V_OH

V_OL

I_OS

Logical “1” Output Voltage

Logical “0” Output Voltage

Output Short Circuit Current

I_OUT= -0.5 mA

I_OUT= 1.6 mA

V_OUT= DGND

V_OUT= VD

2.3

0.12

12

V

mA

nA

–14

20

I_OZ

CMOS Output TRI-STATE

Current

V_OUT= DGND

V_OUT= VD

–25

LVDS/CMOS CLOCK RECEIVER DC SPECIFICATIONS (INCLK+ and INCLK-PINS)

V_IHL

V_ILL

V_IHC

V_ILC

I_IHL

Differential LVDS Clock

High Threshold Voltage

Differential LVDS Clock

Low Threshold Voltage

CMOS Clock

200 mV

R_L= 100 Ω

V_CM(LVDS Input Common Mode Voltage)= 1.25 V

–200

2.0

mV

V

High Threshold Voltage

CMOS Clock

INCLK- = DGND

0.8

V

Low Threshold Voltage

CMOS Clock

230

260

μA

Input High Current

CMOS Clock

I_ILC

–135

–120

Input Low Current

(1) The analog inputs are protected as shown in Figure 2. Input voltage magnitudes beyond the supply rails will not damage the device,

provided the current is limited per Note 4 under the Absolute Maximum Ratings Table. However, input errors will be generated If the

input goes above VA and below AGND.

(2) Test limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).

(3) Typical figures are at T_A= 25°C, and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

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Electrical Characteristics (continued)

The following specifications apply for VA = VD = VR = VC = 3.3 V, C_L= 10 pF, and f_INCLK= 27 MHz unless otherwise

specified. all other limits T_A= 25°C.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN⁽²⁾TYP⁽³⁾MAX⁽²⁾UNIT

LVDS OUTPUT DC SPECIFICATIONS

V_OD

V_OS

I_OS

Differential Output Voltage

LVDS Output Offset Voltage

Output Short Circuit Current

R_L= 100 Ω

280

390

1.20

8.5

490 mV

1.08

1.33

V

V_OUT= 0 V, R_L= 100 Ω

mA

POWER SUPPLY SPECIFICATIONS

LVDS Output Data Format

152

3.6

180 mA

mA

LVDS Output Data Format

(Powerdown)

6

IA

VA Analog Supply Current

CMOS Output Data Format

(40 MHz)

136

76

168 mA

94 mA

17 mA

LVDS Output Data Format

(Powerdown)

VD Digital Output Driver

Supply Current

8.5

ID

CMOS Output Data Format

46

68 mA

(ATE Loading of CMOS Outputs > 50 pF) (40 MHz)

VC CCD Timing Generator

Output Driver Supply Current RS, CP (ATE Loading of CMOS Outputs > 50 pF)

Typical sensor outputs: SH1-SH5, PHIA, PHIB, PHIC,

IC

1

755

40

4

mA

LVDS Output Data Format

885 mW

70 mW

LVDS Output Data Format

(Powerdown)

PWR

Average Power Dissipation

CMOS Output Data Format

(ATE Loading of CMOS Outputs > 50 pF) (40 MHz)

600

740 mW

INPUT SAMPLING CIRCUIT SPECIFICATIONS

CDS Gain=1x, PGA Gain=1x

CDS Gain=2x, PGA Gain= 1x

2.3

V_IN

Input Voltage Level

Vp-p

1.22

Source Followers Off

CDS/SH Gain = 1x

OS_X= VA (OS_X= AGND)

32

(-165)

(–200)

(–290)

(–250)

50

70

μA

nA

Sample and Hold Mode

Input Leakage Current

(Vclamp = Default = 2.6 V)

Source Followers Off

CDS/SH Gain = 2x

OS_X= VA (OS_X= AGND)

55

(–240)

I_{IN_SH}

Source Followers On

CDS/SH Gain = 2x

OS_X= VA (OS_X= AGND)

20

(–50)

250

Sample/Hold Mode

Equivalent Input Capacitance

(see Figure 12)

CDS Gain = 1x

CDS Gain = 2x

2.5

4

pF

C_SH

CDS Mode

Input Leakage Current

Source Followers Off

OS_X= VA (OS_X= AGND)

10

(–50)

I_{IN_CDS}

(–250)

250

55

nA

CLPIN Switch Resistance

(OS_Xto VCLP Node in

Figure 9)

R_CLPIN

16

Ω

8

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Electrical Characteristics (continued)

The following specifications apply for VA = VD = VR = VC = 3.3 V, C_L= 10 pF, and f_INCLK= 27 MHz unless otherwise

specified. all other limits T_A= 25°C.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN⁽²⁾TYP⁽³⁾MAX⁽²⁾UNIT

VCLP REFERENCE CIRCUIT SPECIFICATIONS

VCLP Voltage 000

VCLP Voltage 001

VCLP Voltage 010

VCLP Voltage 011

VCLP Voltage 100

VCLP Voltage 101

VCLP Voltage 110

VCLP Voltage 111

VCLP Voltage Setting = 000

VCLP Voltage Setting = 001

0.85VA

0.9VA

V

VCLP Voltage Setting = 010

VCLP Voltage Setting = 011

VCLP Voltage Setting = 100

VCLP Voltage Setting = 101

VCLP Voltage Setting = 110

VCLP Voltage Setting = 111

0.95VA

0.6VA

V

V_VCLP

0.55VA

0.4VA

V

0.35VA

0.15VA

V

I_SC

VCLP DAC Short Circuit

Output Current

mA

30

BLACK LEVEL OFFSET DAC SPECIFICATIONS

Resolution

10

Bits

mV

Monotonicity

Ensured by

characterization

CDS Gain = 1x

Minimum DAC Code = 0x000

Maximum DAC Code = 0x3FF

CDS Gain = 2x

–614

614

Offset Adjustment Range

Referred to AFE Input

Minimum DAC Code = 0x000

Maximum DAC Code = 0x3FF

Minimum DAC Code = 0x000

Maximum DAC Code = 0x3FF

–307

307

mV

–17500

–16130

+17500

Offset Adjustment Range

Referred to AFE Output

LSB

+16130

CDS Gain = 1x

Referred to AFE Output

1.2

mV

(LSB)

LSB

DAC LSB Step Size

(32)

DNL

INL

+0.74/

–0.37

Differential Non-Linearity

Integral Non-Linearity

–0.84

–2.5

+2.4

+2.5

+0.72/

–0.56

LSB

Bits

PGA SPECIFICATIONS

Gain Resolution

8

Ensured by

characterization

Monotonicity

CDS Gain = 1x

7.7

8.3

18.4

0.62

–4.2

8.8 V/V

Maximum Gain

17.7

0.58

–4.7

18.9

dB

0.67 V/V

Minimum Gain

PGA Function

–3.5

dB

Gain (V/V) = (180/(277-PGA Code))

Gain (dB) = 20LOG10(180/(277-PGA Code))

Minimum PGA Gain

Maximum PGA Gain

3%

Channel Matching

12.7%

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Electrical Characteristics (continued)

The following specifications apply for VA = VD = VR = VC = 3.3 V, C_L= 10 pF, and f_INCLK= 27 MHz unless otherwise

specified. all other limits T_A= 25°C.⁽¹⁾

PARAMETER

ADC SPECIFICATIONS

TEST CONDITIONS

MIN⁽²⁾TYP⁽³⁾MAX⁽²⁾UNIT

V_REFT

V_REFB

Top of Reference

2.07

0.89

V

Bottom of Reference

V_REFT

V_REFB

-

Differential Reference Voltage

1.06

1.18

1.30

Over range Output Code

Under range Output Code

65535

0

DIGITAL OFFSET “DAC” SPECIFICATIONS

Resolution

7

Bits

Digital Offset DAC LSB Step

Size

Referred to AFE Output

LSB

32

Min DAC Code =7'b0000000

Mid DAC Code =7'b1000000

Max DAC Code = 7'b1111111

–2048

0

Offset Adjustment Range

Referred to AFE Output

LSB

+2016

FULL CHANNEL PERFORMANCE SPECIFICATIONS

(4)

DNL

See

+0.8/

–0.7

LSB

dB

Differential Non-Linearity

Integral Non-Linearity

-0.999

–75

2.5

75

(4)

INL

See

+18/

–25

–76

Minimum PGA Gain⁽⁴⁾

Maximum PGA Gain⁽⁴⁾

LSB

RMS

10

26

SNR

Total Output Noise

–56

96

dB

LSB

RMS

Mode 3

Mode 2

26

17

Channel to Channel Crosstalk

LSB

(4) This parameter ensured by design and characterization.

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6.5 AC Timing Specifications

The following specifications apply for VA = VD = VR = VC = 3.3 V, C_L= 10 pF, and f_INCLK= 27 MHz unless otherwise

specified. All other limits T_A= 25°C.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN⁽²⁾

TYP⁽³⁾

MAX⁽²⁾

UNIT

INPUT CLOCK TIMING SPECIFICATIONS

27

(Mode 3)

0.66

30

(Mode 2)

INCLK = PIXCLK (Pixel Rate Clock)

1

2

MHz

30

(Mode 1)

f_INCLK

Input Clock Frequency

Input Clock Duty Cycle

81

(Mode 3)

60

(Mode 2)

INCLK = ADCCLK (ADC Rate Clock)

MHz

30

(Mode 1)

2

T_dc

40/60%

50/50%

60/40%

FULL CHANNEL LATENCY SPECIFICATIONS

3 Channel Mode Pipeline Delay

PIXPHASE0

PIXPHASE1

PIXPHASE2

PIXPHASE3

PIXPHASE0

PIXPHASE1

PIXPHASE2

PIXPHASE3

PIXPHASE0

PIXPHASE1

PIXPHASE2

PIXPHASE3

24

23.5

23

Figure 54 (LVDS)

t_LAT3

T_ADC

Figure 59 (CMOS)

22.5

21

2 Channel Mode Pipeline Delay

Figure 55 (LVDS)

t_LAT2

20.5

20

Figure 60 (CMOS)

19.5

19

1 Channel Mode Pipeline Delay

Figure 56 (LVDS)

t_LAT1

18.5

18

Figure 61 (CMOS)

17.5

(1) The analog inputs are protected as shown in Figure 2. Input voltage magnitudes beyond the supply rails will not damage the device,

provided the current is limited per Note 4 under the Absolute Maximum Ratings Table. However, input errors will be generated If the

input goes above VA and below AGND.

(2) Test limits are specified to AOQL (Average Outgoing Quality Level).

(3) Typical figures are at T_A= 25°C, and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

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AC Timing Specifications (continued)

The following specifications apply for VA = VD = VR = VC = 3.3 V, C_L= 10 pF, and f_INCLK= 27 MHz unless otherwise

specified. All other limits T_A= 25°C.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN⁽²⁾

TYP⁽³⁾

MAX⁽²⁾

UNIT

SH_R TIMING SPECIFICATIONS (Figure 44)

t_{SHR_S}

t_{SHR_H}

SH_R Setup Time

SH_R Hold Time

2

ns

LVDS OUTPUT TIMING SPECIFICATIONS (Figure 53)

TX_pp0

TX_pp1

TX_pp2

TX_pp3

TX_pp4

TX_pp5

TX_pp6

TXCLK to Pulse Position 0

TXCLK to Pulse Position 1

TXCLK to Pulse Position 2

TXCLK to Pulse Position 3

TXCLK to Pulse Position 4

TXCLK to Pulse Position 5

TXCLK to Pulse Position 6

-0.26

1.50

3.26

5.03

6.80

8.56

10.32

0

1.76

3.53

5.29

7.06

8.82

10.58

0.26

2.02

3.79

5.55

7.32

9.08

10.84

ns

CMOS OUTPUT TIMING SPECIFICATIONS

CLKOUT Rising Edge to CMOS Output

Data Transition

f_INCLK= 40 MHz, INCLK = ADCCLK

(ADC Rate Clock)

t_CRDO

2

4.5

9

ns

SERIAL INTERFACE TIMING SPECIFICATIONS

f_SCLK<= f_INCLK,

INCLK = PIXCLK

(Pixel Rate Clock)

Mode 3/2/1

27/30/30

81/60/30

MHz

f_SCLK

Input Clock Frequency

f_SCLK<= f_INCLK,

INCLK = ADCCLK

(ADC Rate Clock)

Mode 3/2/1

SCLK Duty Cycle

50/50

ns

t_IH

Input Hold Time

1.5

2.5

1.5

2.5

6

t_IS

Input Setup Time

ns

t_SENSC

t_SCSEN

SCLK Start Time after SEN Low

SEN High after last SCLK Rising Edge

ns

INCLK present⁽⁴⁾⁽⁵⁾

INCLK stopped⁽⁴⁾⁽⁵⁾

T_INCLK

ns

t_SENW

SEN Pulse Width

50

t_OD

t_HZ

Output Delay Time

11

14

ns

Data Output to High Z

0.5

T_SCLK

(4) If the input INCLK is divided down to a lower internal clock rate via the PLL, the parameter t_SENWwill be increased by the same factor.

(5) When the Spread Spectrum Clock Generation feature is enabled, t_SENWshould be increased by 1.

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6.6 Serial Interface Timing Details

t_SENSC

t_SCSEN

t_IS

SCLK

t_HZ

t_OD

t_IH

SEN

SDIO

(R)

1

DO DO DO DO DO DO

[7] [6] [5] [4] [3] [2]

DO DO DO DO DO DO DO DO

[7] [6] [5] [4] [3] [2] [1] [0]

CE CE

[1] [0]

A4 A3 A2 A1 A0

x

t_SENW

INCLK

Figure 1. Serial Interface Specification Diagram

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7 Detailed Description

7.1 Overview

The LM98725 is a 16-bit, three-input, complete Analog Front End (AFE) for digital color copier and Multi-Function

Peripheral (MFP) applications. The system block diagram of the LM98725, shown in LM98725 Overall Chip

Block Diagram highlights the main features of the device. Each input has its own Input Bias and Clamping

Network which are routed through a selectable Sample/Hold (S/H) or Correlated Double Sampler (CDS)

amplifier. A ±9-Bit Offset DAC applies independent offset correction for each channel. A -3 to 17.9dB

Programmable Gain Amplifier (PGA) applies independent gain correction for each channel. The LM98725 also

provides independent Digital Black Level Correction Feedback Loops for each channel. The Black Level

Correction Loop can be configured to run in Manual Mode (where the user inputs their own values of DAC offset)

or in Automatic Mode where the LM98725 calculates each channel’s Offset DAC value during optical black pixels

and then adjusts the Offset register accordingly. The signals are routed to a single high performance 16-bit,

81MHz analog-to-digital converter.

The analog inputs are protected as shown in Figure 2. Input voltage magnitude up to 500 mV beyond the supply

rails will not damage this device. However, input errors will be generated if the input goes above VA and below

AGND.

VA

I/O

To Internal Circuitry

AGND

Figure 2. Analog Input Protection

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7.2 Functional Block Diagrams

7.2.1 LM98725 Overall Chip Block Diagram

SH5

SH4

SH3

SH1

RS

CP

PHIC2

PHIC1

PHIB2

PHIB1

PHIA2

PHIA1

SH_R

VREFT

VREFB

VCLP

Figure 3. Chip Block Diagram

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Functional Block Diagrams (continued)

CCD/CIS Sensor

Analog Front End

SPI

Image Processor/

ASIC

LM98725

Data Output

CLK

CCD Timing

Generator

Sensor Drivers

Motor

Controllers

SSCG

Figure 4. System Block Diagram

7.3 Feature Description

7.3.1 Modes of Operation Introduction

The LM98725 can be configured to operate in several different operating modes. The following sections are a

brief introduction to these modes of operation. A more rigorous explanation of the operating modes is contained

in the Device Functional Modes section, including input sampling diagrams for each mode as well as a

description of the operating conditions.

7.3.2 Mode 3 - Three Channel Input/Synchronous Pixel Sampling

OS_B, OS_G, and OS_Rinputs are sampled synchronously at a pixel rate. The sampled signals are processed with

each channel’s offset and gain adjusted independently via the control registers. The order in which pixels are

processed from the input to the ADC is fully programmable and is synchronized by the SH pulse. In this mode,

the maximum channel speed is 27MSPS per channel with the ADC running at 81MSPS yielding a three color

throughput of 81MSPS.

7.3.3 Mode 2 - Two Channel Input/Synchronous Pixel Sampling

Mode 2 is useful for CCD sensors with a Black and White mode with Even and Odd outputs. In its default

configuration, Mode 2 samples the Even output via the OSB channel input, and the Odd output via the OSG

channel input. Sampling of the Even and Odd pixels is performed synchronously at a maximum sample rate of

30MSPS per input with the ADC running at 60MSPS.

7.3.4 Mode 1 - One Channel Input

In Mode 1, all pixels are processed through a single input (OS_R, OS_G, or OS_B) chosen through the control

register setup. This mode is useful in applications where only one input channel is used. The selected input is

programmable through the control register.

7.3.5 CIS Lamp and Coefficient Modes

In additional to Modes 3, 2, and 1 above, two different CIS sensor modes (CISa and CISb) can be enabled.

These allow color sequential lamp control, as well as synchronized color sequential gain/offset coefficient usage

for multi-output color sequential sensors.

7.3.6 Clock Sources

7.3.6.1 User Provided Clock Signal

When XTALEN = 0 (Page 0, Register 0, Bit 2) the clock input to the LM98725 can be a differential LVDS clock

on the INCLK+ and INCLK- pins or a CMOS level clock applied to the INCLK+ pin with the INCLK- pin connected

to DGND. The external clock signal format is auto sensed internally.

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Feature Description (continued)

7.3.6.2 Crystal Oscillator Driver On-Chip

When XTALEN = 1 (Page 0, Register 0, Bit 2), an on-chip crystal oscillator driver circuit can be paired with an

external crystal. Terminal 2 of the crystal should connect to INCLK+ and terminal 1 of the crystal should connect

to INCLK-. 18 pF capacitors should connect from each terminal of the crystal to ground.

7.3.6.3 Clock Multiplication - Basic

For any of the available clock sources, the input clock can be applied at the Pixel frequency (PIXCLK) or at the

ADC frequency (ADCCLK). The LM98725 can perform internal clock multiplication when a Pixel frequency clock

is applied, or no multiplication when an ADC frequency clock is applied. The internal configuration registers need

to be written to perform the proper setup of the input clock. The available input clock configurations for each

operating mode are outlined in Table 1.

Table 1. Input Clock Configurations for Operating Modes

INCLK

MAX

FREQ.

CONFIGURATION

REGISTER

AFE

MODE

INTERNAL

MULTIPLIER

INPUT CLOCK TYPE

SETTINGS

INCLK = Pixel Freq. (PIXCLK)

INCLK = ADC Freq. (ADCCLK)

3x

1x

27MHz

81MHz

TBD

Mode 3

Mode 2

Mode 1

INCLK = Pixel Freq. (PIXCLK)

INCLK = ADC Freq. (ADCCLK)

2x

1x

30MHz

60MHz

TBD

INCLK = Pixel Freq. = ADC Freq

(ADCCLK = PIXCLK in Mode 1)

1x

30MHz

TBD

7.3.6.4 Clock Multiplication - Flexible

There are a variety of situations where it is desirable to multiply the base frequency by a selected amount to

achieve the proper pixel frequency for a given application and set of system conditions.

•

Applications using the onchip Crystal Oscillator driver will have much more flexibility of pixel frequencies.

Reducing the input MCLK frequency can significantly reduce the EMI generated by the MCLK signals being

sent up the cable from the host board to the imaging board.

To ease this task a flexible multiplying PLL architecture is incorporated. When the 2 PLL architecture is enabled

(Page 2, Register 0x1Bh, Bit 1=0) the source clock frequency is multiplied by the ratio M/N. Two registers are

used to set these values:

M = Value(Page 2, Register 0x1Ch) + 1

N = Value(Page 2, Register 0x1Dh) + 1

N(max) = 64

M/N(max) = 64

M/N(min) = 1/64

Note: Since the 8 bit register values can be from 0 to 255, the resulting Numerator and Denominator values

could be from 1 to 256. However, the maximum recommended multiply or divide ratios are 64x or x/64. In

addition, the maximum recommended value for N is 64.

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Clock

Receiver

INCLK+

Fin

Fout

SSCG LVDS Only, 2

PLL Mode

PLL1

Fout = Fin x (M/N)

Crystal or

INCLK from Host

Crystal

Oscillator

Driver

Clock to CCDTG

and AFE

M

U

X

INCLK-

Spread All, 1 PLL Mode

Data from AFE

SSCG

Enable

2 PLLs – Use M/N, Use M/N

and SSCG All, SSCG LVDS

Only

M

U

X

PLL2

SSCG modulation

21

1 PLL – No M/N and SSCG

All, No M/N and no SSCG

FIFO

21

M

U

X

Use FIFO

LVDS

Serializer

Clock/Data to Host

Bypass FIFO

Clock System Configuration Options

Source

INCLK

PLL (Dual/Single)

Single

Spreading (On/Off)

ON

SpreadMode (LVDS/All)

ALL

N/A

OFF

ON

Dual (Use M/N)

LVDS*

ALL

N/A

ON

OFF

XTAL

Single

ON

ALL

N/A

OFF

ON

Dual (Use M/N)

LVDS*

ALL

N/A

ON

OFF

*If SpreadMode is LVDS, then FIFO is used to move data from CCDTG/AFE clock domain to LVDS clock domain.

Figure 5. Clock System Block Diagram

7.3.7 Clock Sources - Additional Settings and Flexibility

To support the new crystal oscillator feature, some additional flexibility was added. In Crystal Oscillator mode, the

master clock source is now on the AFE (rather than in the system ASIC or main processor). If Slave Timing

Mode (see CCD Timing Generator Master/Slave Modes) is still needed (to synchronize the AFE to the line timing

of the system), the external SH_R signal must now be captured with the internal clock source. The SH_R

Capture Clock Select bit has been added to support this case.

In addition, in these systems, it may be difficult to adjust the host SH_R timing to get the best Setup and Hold

times with respect to the internal CLK. The SH_R, INCLK Monitor Override and SH_R Capture Edge Select

controls have been added to support these needs. The INCLK Monitor Override allows the internal SH_R and

CLK signals to be monitored, to aid in selected the best edge (rising or falling) of CLK to latch the SH_R signal.

•

SH_R Capture Clock Select (Page 0, Register 0x00, Bit 5)

–

0 - Use internal INCLK source to latch SH_R

1 - Use external CLK source to latch SH_R

•

SH_R Capture Edge Select (Page 0, Register 0x00, Bit 4)

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–

0 - Use rising edge of selected clock source

1 - Use falling edge of selected clock source

•

SH_R and INCLK Monitor Override (Page 0, Register 0x14, Bit 6)

–

0 - Timing monitor selections unaltered

1 - Timing monitors for CLAMPB and SAMPB are replaced with monitor of SH_R_Internal and SH_R

Capture_Clock_Internal.

7.3.8 Spread Spectrum Clock Generation (SSCG)

NOTE

When using SSCG, ensure that INCLK = ADCCLK is selected at Page 0, Register 0x02,

Bit 2 = 0. Then set the flexible clock multiplication PLL settings to achieve the desired

internal clock frequency from the applied clock.

EMI is a problem faced by any system designer. In a typical imaging system, data must be sent over a relatively

long cable to the main system board. To minimize the amount of measured EMI caused by system clocking and

data transmission, a flexible Spread Spectrum Clock Generation system is included in the LM98725.

The spread spectrum feature is configured by the registers at Page 2, Registers 0x1Ah, 0x1Bh and 0x1Eh.

The following key SSCG modes of operation and features are provided:

•

Spread output data/clock only (Internal FIFO used to transfer data between clock domains) or spread internal

system clock as well as output data/clock

•

Spread synchronized to CCD line length (SH period or frequency) or unsychronized.

Spread widths of 0.625, 1.25, 2.5 and 5 % selectable

Spread gain of 1x to 2x can double the selected spread widths

3 selectable modulation frequency multipliers to increase the spreading modulation frequency

Spread “boost” provides a cleaner spread for 1 channel and 2 channel modes of AFE operation.

Spread MaxRate allows the most effective spreading modulation for Output Only spreading. When this bit is

set, the spreading waveform is NOT synchronized to the CCD line timing.

•

Spreading modulation waveform and FIFO reset by SH_R event. (Page 8, Register 0x1Eh, Bit 7) This

ensures that the spreading waveform is synchronized to the CCD line timing, even if SH_R to SH_R period is

varied by system ASIC.

Spreading SH_R Reset can be delayed from SH_R event by a “Holldoff” amount. (Page 8, Register 0x1Eh,

Bits6:0)

7.3.9 Typical EMI Cases and Recommended SSCG Settings

•

Case 1: Majority of EMI coming from LVDS outputs

–

Usage: Spread output data/clock only. FIFO used to move data between non-spread and spread clock

domains. If Slave Mode is also used, ensure that the Line Length and Line Length Multiplier settings

correspond to the SH_R period. If the SH_R period may vary, then set FIFO Reset (Page 2, Register

0x1Bh, Bit 6 =1) to ensure the FIFO counters are reset every SH Interval.

•

Case 2: EMI from LVDS outputs and CCD timing signals - Master Mode Application

–

Usage: Spread internal system clock as well as output data/clock. Synchronize spread waveform to SH

Interval. Best to use Master mode timing to ensure spread waveform is always smoothly synchronized to

the SH Interval timing.

Case 3: EMI from LVDS outputs and CCD timing signals - Slave Mode Application

–

Usage: Spread internal system clock as well as output data/clock. Use minimal amount of spreading to

reduce CCD timing emissions, in combination with data scrambling to further reduce data cable emissions.

The small amount of spreading minimizes effects on image data, therefore, spreading is not required to be

synchronized with SH Intervals.

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7.3.10 Recommended Master/Slave, Clock Source and SSCG Combinations and Settings

7.3.10.1 Master Mode Operation (LM98725 Controls Line Timing)

(These are easiest cases to implement SSCG)

Clock from host board

1. Use SSCG - Spread All

2. Use SSCG - Spread LVDS Only

3. No SSCG

Clock from local crystal

1. Use SSCG - Spread All

2. Use SSCG - Spread LVDS Only

3. No SSCG

7.3.10.2 Slave Mode Operation (Host FPGA or ASIC Controls Line Timing)

NOTE: These SSCG cases are more challenging as received LVDS data timing will not be synchronous with the

clock of the FPGA/ASIC. Clock from host board. If a local clock is present on the FPGA/ASIC, an internal FIFO

must be implemented to transfer the received data from the spread LVDS clock domain, to the internal

FPGA/ASIC clock domain. If the AFE LVDS clock is used as the system clock, care must be taken to ensure that

settings are not loaded which disable this clock, and therefore lock up the system.)

1. Use SSCG - Spread All - Need spreading start to be SH gated, and SH period to be consistent to ensure

consistent capture of SH_R by the spread INCLK.

2. Use SSCG - Spread LVDS Only - In this case ensure that Line Length Register is set to same number of

pixels as that or SH_R period. In addition, if SH_R period will vary, set FIFO Reset (Page 2, Register 0x1Bh,

Bit 6 = 1) to reset FIFO at SH Interval.

3. No SSCG

Clock from local crystal (Not recommended, difficult to meet CLK to SH_R setup and hold times. Use Master

Mode instead)

1. Use SSCG - Spread All

2. Use SSCG - Spread LVDS Only

3. No SSCG

7.3.10.3 SSCG Configuration/Usage Flow

•

Unlock Registers (Page 0, Register 0, Bit 0 = 0)

Ensure PIXCLK/ADCCLK Configuration is set to ADCCLK. Page 0, Register 0x02, Bit 2 = 0.

Set Override PLL2 Lock Detector (Page 2, Register 0x1B, Bit 4) = 1

Set PLL2 Charge Pump Current Control (Page 2, Register 0x19, Bits 4:3) = 00

Set PLL2 Filter Bandwidth Control (Page 2, Register 0x19, Bits 2:0) = 111

Set SSCG Spread Boost (Page 2, Register 0x1A, Bit 5) = 0 or 1 (0 = default, recommended for most

applications)

•

Set SSCG Spread Gain (Page 2, Register 0x1A, Bit 4) = 0 or 1 (0 = default, recommended for most

applications)

Set SSCG Spread Width (Page 2, Register 0x1A, Bits 3:2) = 0.625% to 2.5% (Beyond 2.5% most LVDS

deserializers will not track the clock properly)

•

Set SSCG SH Sync Enable (Page 2, Register 0x1A, Bit 1) = 0 or 1 (Set to 1 for Spread All)

Set PLL Mode Select (Page 2, Register 0x1B, Bits 1:0) = 00, 01 or 11. Spread Output Only or Spread All

Clocks

•

If PLL Clock Multiplication Enabled, Set Clock Mult M (Page 2, Register 0x1C) and N (Page 2, Register 0x1D)

to desired values. If a pixel rate clock is applied, set the PLL multiplication to the same factor as the AFE

Mode selected at Page 0, Register 0x03, Bits 7:6. ie. The multiplication factor should be 3x for Mode 3, 2x for

Mode 2 and 1x for Mode 1.

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•

Set SSCG Enable (Page 2, Register 0x1A, Bit 0) = 1 (enable spreading, load spreading state machines)

Lock Registers (Page 0, Register 0, Bit 0 = 1)

If spreading is synchronized to SH interval, the spreading function will wait until the next SH Interval before

beginning.

•

Set SSCG Enable (Page 2, Register 0x1A, Bit 0) = 1 (enable spreading, load spreading state machines)

Lock Registers (Page 0, Register 0, Bit 0 = 1)

If spreading is synchronized to SH interval, the spreading function will wait until the next SH Interval before

beginning.

7.3.10.4 Changing SSCG Settings

To Change SSCG Settings:

•

Un-Lock Registers ((Page 0, Register 0, Bit 0 = 0)

Set SSCG Enable = 0 (disable spreading)

Change desired SSCG settings.

Set SSCG Enable = 1 (enable spreading, reload spreading state machines)

Lock Registers (Page 0, Register 0, Bit 0 = 1)

Table 2. SSCG and Clock Multiplication Register Settings

PAGE

2

REGISTER

DEFAULT

BITS

NAME

DESCRIPTION

Master PLL Range Setting for PLL1 and PLL2 when

Autorange is off. Set to 111.

24

18

1111 1000

[7:5]

[4:3]

PLL1 Charge Pump Current Control

Default = 11

PLL Control 1

[2:0]

[7:5]

PLL1 Filter Bandwidth Control

Default = 000

2

25

19

0001 1000

Reserved

Default = 000

[4:3]

[2:0]

PLL2 Charge Pump Current Control

Default = 11

PLL Control 2

Set to 00 when using SSCG.

PLL2 Filter Bandwidth Control

Default = 000

Set to 111 when using SSCG.

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Table 2. SSCG and Clock Multiplication Register Settings (continued)

PAGE

REGISTER

DEFAULT

BITS

NAME

DESCRIPTION

Spread Rate Multiplier

2

26

1A

0000 0000

[7:6]

(Increases modulation frequency in low pixel frequency

applications)

00 1x - Default

01 2x

10 4x

11 Reserved

[5]

SSCG Spread Boost

0 Normal, PLL divide step is 1/28

1 Boost, PLL divide step is 1/56. Narrower and cleaner

spread for 1ch and 2ch modes, but limits max pixel freq

to 25 MHz.

[4]

SSCG Spread Gain

0 Spread widths as specified in [3:2]

1 Spread widths are 2x [3:2] settings

SSCG Control 1

[3:2]

SSCG Spread Width (Fmod = Fcenter+/- Width/2)

00 5%

01 2.5%

10 1.25%

11 0.625%

[1]

[0]

SSCG SH Sync Enable

0 Spread unsynched, once SSCG Enable and Register

Lock Control are set, SSCG wil begin immediately.

1 Spread synched to SH interval, once SSCG Enable is

set, the SSCG will begin at the first SH Interval.

SSCG Enable

0 Spread off

1 Spread on

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Table 2. SSCG and Clock Multiplication Register Settings (continued)

REGISTER

DEFAULT

BITS

NAME

DESCRIPTION

Load SSCG state machine

2

27

1B

0000 0010

[7]

(SSCG Enable 0->1 also performs this function)

0 Normal

1 Load state machine (self clearing)

[6]

FIFO Reset at SH_R

0 FIFO is only reset when SSCG started

1 FIFO is reset at SH_R. Only useful in Slave Mode

with Spread LVDS Only set. Ensures that FIFO

counters are centered if SH_R period is consistenly

shorter or longer than Line Length settings.

[5]

[4]

Spread Waveform Reset at SH_R

0 Spread waveform not reset by SH_R

1 Spread waveform reset by SH_R

Override PLL2 Lock Detector

0 PLL2 Lock Detector Normal

SSCG Control 2 1 Force PLL2 Lock Detect = 1. Set to 1 when using

SSCG.

[3]

Override PLL1 Lock Detector

0 PLL1 Lock Detector Normal

1 Force PLL1 Lock Detect = 1. Useful only if using a

large multiplication factor and a lot of jitter is present in

the source clock.

[2]

Spread MaxRate

0 Spread Normal

1 Force Spreading to highest modulation frequency

instead of tied to Line Length Setting.

[1:0]

PLL Mode Select

11 Spread All System Clocks, No Multiplication

10 PLLs and SSCG Disabled - Default

01 Spread All System Clocks, Multiplication Enabled

00 Spread Output Clocks Only, Multiplication Enabled

2

28

29

30

1C

1D

1E

0000 0000

Multiplying PLL. Fout = Fin x M/N

Clock Mult M

M = mmmmmmmm + 1 (1 to 256)

Multiplying PLL. Fout = Fin x M/N

Clock Mult N

N = nnnnnnnn + 1 (1 to 256)

[7]

FIFO Reset

0 FIFO normal operating

1 Force reset of FIFO (self clearing)

[6:0]

FIFO and Spread Waveform SH_R Reset Holdoff

SSCG Control 3

Delay reset of FIFO and Spread Waveform from 0 to

127 ADC clock cycles after the internal synchronized

SH_R. To allow this event to occur during SH Interval

after all valid pixels in the pipeline have been pro-

cessed.

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7.4 Device Functional Modes

7.4.1 Mode 3 - Three Channel Input/Synchronous Pixel Sampling

In Mode 3, the OS_R, OS_G, and OS_Binput channels are sampled synchronously. The sampled input signals are

then processed in parallel through their respective channels with each channel offset and gain adjusted by their

respective control registers. The signals are then routed through a 3-1 MUX to the ADC. The order in which

pixels are processed through the MUX to the ADC is programmable (OS_R-OS_G-OS_B, or OS_B-OS_G-OS_R) and is

synchronized by the SH pulse.

Black

Level

COLOR1DAC[9:0]

COLOR1PGA[7:0]

Offset

DAC

CDS

or

Input Bias/

Clamping

OS_R

OS_G

OS_B

PGA

Sample/Hold

Amplifier

Black

COLOR2PGA[7:0]

Level

Offset

DAC

COLOR2DAC[9:0]

CDS

or

Input Bias/

Clamping

3:1

MUX

Sample/Hold

Amplifier

Black

COLOR3PGA[7:0]

Level

Offset

DAC

COLOR3DAC[9:0]

CDS

or

Input Bias/

Clamping

Sample/Hold

Amplifier

Figure 6. Synchronous Three Channel Pixel Mode Signal Routing

Table 3. Mode 3 Operating Details

DETAIL

Channels Active

Channel Sample Rate

ADC Sample Rate

f_ADC: f_INCLK

OS_B& OS_G& OS_R

27

3 channel synchronous pixel sampling

MSPS per Channel (max)

MSPS (max)

81

3:1

1:1

Internal 3x Clock Selected

Internal 1x Clock Selected

f_INCLK= 27 MHz (max)

f_INCLK= 81 MHz (max)

Output Sequencing

SH Signal --> R-G-B-R-G-B-R-G-B→

or

SH Signal --> B-G-R-B-G-R-B-G-R→

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7.4.2 Mode 2 - Two Channel Input/Synchronous Pixel Sampling

Mode 2 is useful for CCD sensors with a Black and White line with Even and Odd pixels. In its default

configuration, Mode 2 samples Even sensor pixels via the Blue Channel Input, and Odd sensor pixels via the

Green Channel Input. The selection of Even/Odd inputs can be changed through the serial interface registers.

Sampling of the Even and Odd inputs is performed synchronously.

Black

Level

COLOR1DAC[9:0]

COLOR1PGA[7:0]

Offset

DAC

CDS

or

Input Bias/

Clamping

OS_R

OS_G

OS_B

PGA

Sample/Hold

Amplifier

Black

COLOR2PGA[7:0]

Level

Offset

DAC

COLOR2DAC[9:0]

CDS

or

Input Bias/

Clamping

3:1

MUX

Sample/Hold

Amplifier

Black

COLOR3PGA[7:0]

Level

Offset

DAC

COLOR3DAC[9:0]

CDS

or

Input Bias/

Clamping

Sample/Hold

Amplifier

Figure 7. Mode 2 Signal Routing

Table 4. Mode 2 Operating Details

DETAIL

Channels Active

OS_Gand OS_B(Default)

Two inputs synchronously

processed as Even and Odd

Pixels. Channel inputs are

configurable.

or

OS_Rand OS_G

or

OS_Band OS_R

Channel Sample Rate

ADC Sample Rate

f_ADC: f_INCLK

30

MSPS per Channel (max)

MSPS (max)

60

2:1

1:1

f_INCLK= 30 MHz (max)

f_INCLK= 60 MHz (max)

Internal 2x Clock Selected

Internal 1x Clock Selected

Output Sequencing

SH Signal --> Even-Odd-Even-Odd-Even-Odd-Even→

or

SH Signal --> Odd-Even-Odd-Even-Odd-Even-Odd→

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7.4.3 Mode 1 - One Channel Input

In Mode 1a, all pixels are processed through a single input (OS_R, OS_G, or OS_B) chosen through the control

register setup. This mode is useful in applications where only one input channel is used. The selected input is

programmable through the control register. In this mode, the maximum channel speed is 30MSPS per channel

with the ADC running at 30MSPS.

Black

Level

COLOR1DAC[9:0]

COLOR1PGA[7:0]

Offset

DAC

CDS

or

Input Bias/

Clamping

OS_R

OS_G

OS_B

PGA

Sample/Hold

Amplifier

Black

COLOR2PGA[7:0]

Level

Offset

DAC

COLOR2DAC[9:0]

CDS

or

Input Bias/

Clamping

3:1

MUX

Sample/Hold

Amplifier

Black

COLOR3PGA[7:0]

Level

Offset

DAC

COLOR3DAC[9:0]

CDS

or

Input Bias/

Clamping

Sample/Hold

Amplifier

Figure 8. Mode 1a Signal Routing

Table 5. Mode 1 Operating Details

DETAIL

Channels Active

Channel Sample Rate

ADC Sample Rate

f_ADC: f_INCLK

OS_Ror OS_Gor OS_B

One color active for all lines.

MSPS per Channel (max)

MSPS (max)

30

1:1

Internal 1x Clock Selected

f_INCLK= 25MHz (max)

Output Sequencing

SH Signal → Color 1 → Color 1 → Color 1 → Color 1 → Color 1 →

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Table 6. Modes of Operation Register Settings Table

SAMPLING

INPUT(S)

SIGNAL

PATH(S)

OUTPUT SEQUENCING

MODE 3 AND 2 = PIXEL SEQ

OPERATING MODE

Mode3-RGB Forward

Mode3-RGB Reverse

OS_R||OS_G||OS_B

RGB

Pixel_R→ Pixel_G→ Pixel_B→

Pixel_B→ Pixel_G→ Pixel_B

→

Mode2-RG Forw.

Mode2-RG Rev.

OS_R||OS_G

RG

Pixel_R→ Pixel_G

Pixel_G→ Pixel_R

→

Mode2-GB Forw.

Mode2-GB Rev.

OS_G||OS_B

GB

Pixel_G→ Pixel_B→

Pixel_B→ Pixel_G→

Mode2-RB Forw.

Mode2-RB Rev.

OS_R||OS_B

RB

PixelR → PixelB →

PixelB → PixelR →

Mode1-R Mono

Mode1-G Mono

Mode1-B Mono

CISa

OS_R

OS_G

R

G

Color Line Seq: R→R→R→R→

Color Line Seq: G→G→G→G→

Color Line Seq: B→B→B→B→

2, 3, or 4 lines in sequence

OS_B

B

Mode 1 or 2 or 3

Any

Gain and Offset are channel specific.

LM98714 style CB bits indicate channel used to process

data. Additional CB bits can be used to identify current line in

sequence.

CISb

Mode 1 or 2 or 3

Any

2 or 3 lines in sequence

Gain and Offset for all channels are common, and change

from line to line based on current color in sequence.

LM98714 style CB bits indicate channel used to process

data. Additional CB bits can be used to identify current line in

sequence.

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7.4.4 Input Bias and Clamping

VA

Input Bias Enable

Configuration 3, Bit[6]

V_BIAS

SAMPLE

20kΩ

OS_Ror

OS_Gor

OS_B

Source Follower Enable

Configuration 3, Bit[7]

C_S

20kΩ

Auto CLPIN Enable

Configuration 4, Bit[5]

SAMPLE

CLPIN

AGND

HOLD

VA

CLPIN Gating Enable

Configuration 4, Bit[4]

V_BIAS

CLAMP

VCLP

C_S

VCLP Reference Select

Configuration 4, Bits[3:0]

VCLP

Sampling Mode Select

(CDS or Sample/Hold Mode)

Configuration 2, Bit[1]

Pixel rate switches to sample OS signal and reference voltages.

Optional line rate switch to clamp OS input to VCLP node.

Static switches controlled by Configuration Registers

SAMPLE, CLAMP, HOLD, CLPIN are internally generated timing signals.

Figure 9. Input Bias and Clamping Diagram

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7.4.4.1 Input Bias and Clamping - AC Coupled Applications

The inputs to the LM98725 are typically AC coupled through a film capacitor and can be sampled in either

Sample and Hold Mode (S/ H Mode) or Correlated Double Sampling Mode (CDS Mode). In either mode, the DC

bias point for the LM98725 side of the AC coupling capacitor is set using the circuit of Figure 8 which can be

configured to operate in a variety of different modes. A typical CCD waveform is shown in Figure 9. Also shown

in Figure 9 is an internal signal “SAMPLE” which can be used to “gate” the CLPIN signal so that it only occurs

during the “signal” portion of the CCD pixel waveform.

SH

Invalid

Pixels

Dummy Pixels

Optical Black Pixels

Valid Pixels

OS_X

Auto CLPIN Start Register

Page 2, Reg. 6, Bits[7:0]

Auto CLPIN End Register

Page 2, Reg. 7, Bits[7:0]

CLPIN

SAMPLE

CLPIN_GATED

Figure 10. Typical CCD Waveform and LM98725 Input Clamp Signal (CLPIN)

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7.4.5 Sample/Hold Mode

SAMPLE

OS_Ror

OS_Gor

OS_B

C_S

C_PAR

HOLD

CLAMP

VCLP

C_S

C_PAR

Figure 11. Sample and Hold Mode Simplified Input Diagram

Proper DC biasing of the CCD waveform in Sample and Hold mode is critical for realizing optimal operating

conditions. In Sample/ Hold mode, the Signal Level of the CCD waveform is compared to the DC voltage on the

VCLP pin. In order to fully utilize the range of the input circuitry, it is desirable to cause the Black Level signal

voltage to be as close to the VCLP voltage as possible, resulting in a near zero scale output for Black Level

pixels.

In Sample/Hold Mode, the DC bias point of the input pin is typically set by actuating the input clamp switch (see

Figure 9) during optical black pixels which connects the input pins to the VCLP pin DC voltage. The signal

controlling this switch is an auto-generated pulse, CLPIN. CLPIN is generated with a programmable pixel delay

with respect to the SH Interval and a programmable # of pixels Duration. These parameters are available through

the serial interface control registers.

Actuating the input clamp will force the average value of the CCD waveform to be centered around the VCLP DC

voltage. During Optical Black Pixels, the CCD output has roughly three components. The first component of the

pixel is a “Reset Noise” peak followed by the Reset (or Pedestal) Level voltage, then finally the Black Level

voltage signal. Taking the average of these signal components will result in a final “clamped” DC bias point that

is close to the Black Level signal voltage.

To provide a more precise DC bias point (that is, a voltage closer to the Black Level voltage), the CLPIN pulse

can be “gated” by the internally generated SAMPLE clock. This resulting CLPIN_GATEDsignal is the logical “AND”

of the SAMPLE and CLPIN signals as shown in Figure 10. By using the CLPIN_GATEDsignal, the higher Reset

Noise peak will not be included in the clamping period and only the average of the Reset Level and Black Level

components of the CCD waveform will be centered around VCLP.

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7.4.6 DC Coupled Applications

In some applications, particularly with CIS sensors, the output voltage is within a voltage range that will allow DC

coupling of the signal. When using Sample/Hold mode, DC coupling eliminates any problems with signal droop

across the line caused by voltage changes across the coupling capacitor. When DC coupling, the Auto CLPIN

should be disabled.

There are two ways of setting the proper DC levels in this type of application. If the sensor has a Vref output pin,

this can be connected to the VCLP pin of the LM98725. The internal VCLP generation should be disabled to

allow this external reference to set the Black Level for the chip close to the black pixel level of the sensor.

Many CIS sensors will not have a Vref output. In these applications, the internal VCLP voltage of the LM98725

can be set to the level that is closest to the black pixel level of the sensor.

OS_Ror

OS_Gor

OS_B

f_PIXEL

C_SH

VCLP

Figure 12. Equivalent Input Switched Capacitance S/H Mode

In Sample and Hold Mode, the impedance of the analog input pins is dominated by the switched capacitance of

the CDS/Sample and Hold amplifier. The amplifier switched capacitance, shown as C_Sin Figure 11, and internal

parasitic capacitances can be estimated by a single capacitor switched between the analog input and the VCLP

reference pin for Sample and Hold mode. During each pixel cycle, the modeled capacitor, C_SH, is charged to the

OS_X-VCLP voltage then discharged. The average input current at the OS_Xpin can be calculated knowing the

input signal amplitude and the frequency of the pixel. If the application requires AC coupling of the CCD output to

the LM98725 analog inputs, the Sample and Hold Mode input bias current may degrade the DC bias point of the

coupling capacitor. To overcome this, Input Source Follower Buffers are available to isolate the larger Sample

and Hold Mode input bias currents from the analog input pin (as discussed in the following section). As shown in

CDS Mode, the input bias current is much lower for CDS mode, eliminating the need for the source follower

buffers.

7.4.7 Input Source Follower Buffers

The OS_R, OS_G, OS_Binputs each have an optional Source Follower Buffer which can be selected with Main

Configuration Register 3 at Page 0, Register 3, Bit[7]. These source followers provide a much higher impedance

seen at the inputs. In some configurations, such as Sample and Hold Mode with AC coupled inputs, the DC bias

point of the input nodes must remain as constant as possible over the entire length of the line to ensure a

uniform comparison to reference level (VCLP in this case). The Source Followers effectively isolate the AC input

coupling capacitor from the switched capacitor network internal to the LM98725’s Sample and Hold/ CDS

Amplifier. This results in a greatly reduced charge loss or gain on the AC Input coupling capacitor over the length

of a line, thereby preserving its DC bias point.

The Source Followers should only be used in the 1.2V input range (that is, Gain Mode Register at Page 1,

Register 0, Bit[0] = 1, CDS Gain = 2x). Using the Source Followers in the 2.4V (that is, Gain Mode Register at

Page 1, Register 0, Bit[0] = 0, CDS Gain = 1x). input range will result in a loss of performance (mainly linearity

performance at the high and low ends of the input range).

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7.4.8 CDS Mode

SAMPLE

OS_Ror

OS_Gor

OS_B

C_S

C_PAR

HOLD

CLAMP

C_S

C_PAR

Figure 13. CDS Mode Simplified Input Diagram

Correlated Double Sampling mode does not require as precise a DC bias point as does Sample and Hold mode.

This is due mainly to the nature of CDS itself, that is, the Video Signal voltage is referenced to the Reset Level

voltage instead of the static DC VCLP voltage. The common mode voltage of these two points on the CCD

waveform have little bearing on the resulting differential result. However, the DC bias point does need to be

established to ensure the CCD waveform’s common mode voltage is within rated operating ranges.

The CDS mode biasing can be performed in the same way as described in the Sample/Hold Mode , or, an

alternative method is available which precludes the need for a CLPIN pulse. Internal resistor dividers can be

switched in across the OS_R, OS_G, and/or OS_Binputs to provide the DC bias voltage.

SAMPLE

I_BIAS

OS_Ror

OS_Gor

OS_B

C_S

C_PAR

HOLD

CLAMP

C_S

C_PAR

Figure 14. CDS Mode Input Bias Current

Unlike in Sample and Hold Mode, the input bias current in CDS Mode is relatively small. Due to the architecture

of CDS switching, the average charge loss or gain on the input node is ideally zero over the duration of a pixel.

This results in a much lower input bias current, whose main source is parasitic impedances and leakage

currents.

As a result of the lower input bias current in CDS Mode, maintaining the DC Bias point the input node over the

length of a line will require a much smaller AC input coupling capacitor.

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7.4.9 VCLP DAC

The VCLP pin provides the reference level for incoming signals in Sample and Hold Mode. The pin’s voltage can

be set by writing to the VCLP Configuration Register on register page 0. By default, the VCLP pin voltage is

established by an internal resistor divider which sets the voltage to 0.85 V_A.

The VCLP buffer can also be disconnected and the pin driven externally by the another voltage in the

application, such as Vref from some CIS sensors.

Table 7. VCLP Voltage Setting

VCLP CONFIGURATION

TYPICAL VCLP OUTPUT

PAGE 0, REGISTER 0x04, BITS[2:0

(FINAL SILICON TARGETS)

000

001

010

011

100

101

110

111

0.85V_A(Default)

0.9 V_A

0.95 V_A

0.6 V_A

0.55 V_A

0.4 V_A

0.35 V_A

0.15 V_A

7.4.10 Gain and Offset Correction

Each input channel has individual settings for offset (DAC) and gain (PGA and CDS/SH gain).

7.4.10.1 Analog Offset

Analog offset (DAC) settings are individually adjustable for each color. In addition, there are (optionally) separate

settings for Even and Odd pixels being processed through each color channel. This feature is designed to

support specific CCD sensors that have two CCD transfer arrays per color, which may introduce different offset

for the Even versus Odd pixels.

COLOR1PGA[7:0]

COLOR1EVENDAC[9:0]

COLOR1ODDDAC[9:0]

Black

Level

Offset

DAC

M

U

X

CDS

or

Input Bias/

Clamping

PGA

OS

R

Sample/Hold

Amplifier

Figure 15. Analog Offset Applied Prior to POA

The Black Level Offset DACs are set with a 9 bit plus sign value. This gives an approximate adjustment range of

±300 mV or ±600mV when the CDS/SH Gain is set to 1x or 2x.

The analog offset registers are found at Page 1, Registers 0x04h to 0x0Fh.

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7.4.10.2 Digital Offset

In addition, digital offset can be added to color data at the output of the ADC in the Digital Offset block. The

digital offsets are a ±6 bit value. This value is summed with the upper 11 bits of the ADC output. Therefore, the

effective offset range is from +2016 to -2048 lsbs of the ADC output.

The digital offset registers are found at Page 1, Registers 0x10h to 0x15h.

16 Bit ADC

16

Digital

Offset

Figure 16. Digital Offset Applied to ADC Output

7.4.10.3 Even/Odd Offset Coefficients

Certain CCD sensors may have different offset voltages for the Even versus the Odd pixels. To optimize the

image processing of these pixels, separate coefficients can be stored, and applied for the Even and Odd pixels.

The Even/Odd offset feature is enabled by setting Page 0, Register 0x02h, Bit 0 = 1. Bimodal correction,

discussed below, is automatically disabled when Even/Odd offset coefficients are enabled.

Color 1 Even Offset

Color 2 Even Offset

Color 3 Even Offset

Color 1 Odd Offset

Figure 17. Digital Offset - Details of Color and Even/Odd Coefficients

•

Analog Gain

The gain of each input channel can be adjusted at two points in the signal chain.

CDS/SH Gain - Page 1, Register 0x00h

–

A 1x or 2x gain setting is available in the CDS/SH amplifier.

By default, one common CDS/SH gain setting is used for all input channels. If desired, individual CDS/SH

gain settings can be used for each input. To enable this feature, set Page 1, Register 0x00h, Bit 2 = 1.

•

PGA Gain - Page 1, Registers 0x01h, 0x02h, 0x03h

–

An 8 bit PGA (Programmable Gain Amplifier) is also available. The PGA gain curve is non-linear for

optimal performance in imaging applications, and is shown on the following plot. The approximate gain

equation is: Gain (V/V) = 180/(277-PGA_Code), Gain (dB) = 20log10(180/(277-PGA_Code)).

The gain setting registers are found at Page 1, Registers 0x00h, 0x01h, 0x02h and 0x03h.

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18

17

16

15

14

13

12

11

10

9

Gain (V/V) =

(180/(277-PGA Code))

Gain (dB) =

20LOG₁₀(180/(277-PGA Code))

8

7

6

5

4

3

2

1

0

32

64

96

128

160

192

224

-1

-2

-3

-4

PGA Register Value

Overall Gain (dB) Overall Gain (V/V)

Figure 18. PGA Gain vs. PGA Gain Code

Dual Gain Mode - Page 1, Register 0x00h, Bit 1, and Registers 0x16h, 0x17h, 0x18h

•

–

In many scanning systems, the system illumination and optics characteristics will result in a much higher

optical efficiency in the pixels near the middle of the sensor, compared with the pixels at the beginning

and end of the sensor. If a single gain setting is used for all pixels, the middle pixels will be near clipping,

while the ones at the edges can be at 1/2 scale or lower. This results in lower signal to noise for the edge

pixels. To combat this problem, the LM98725 incorporates an optional Dual Gain system. When enabled,

the system provides a second set of PGA gain registers to set the “high” gain for each input channel. The

“normal” gain settings will be applied during the “active/white” pixels, while the “high” gain settings will be

applied for all pixels before and after the “active/white” pixels (see LM98725 Typical Line Timing and Pixel

Gain Regions ).

–

The Dual Gain enable bit is found at Page 1, Register 0x00h, Bit 1. The High Gain PGA settings are found

at Page 1, Registers 0x16h to 0x18h.

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7.4.11 LM98725 Typical Line Timing and Pixel Gain Regions

Figure 19. Typical Line Timing and Pixel Gain Regions

7.4.12 Automatic Black and White Level Calibration Loops

7.4.12.1 Calibration Overview

The offset and gain settings in the AFE will normally be set to optimize the range of the sensor output signal

within the ADC input range. These settings can be calculated in a host ASIC and loaded into the AFE during the

calibration procedure. To reduce the processing required to do these calculations, the LM98725 has built in

feedback or calibration loops that will automatically adjust the offset and gain settings. A number of register

values must be initially set to optimize the calibration for the particular application.

7.4.12.2 Different Modes for Different Needs

The calibration features of the LM98725 are not intended to be used during active scanning, but rather before

scanning begins, or in the page gap between images. Generally, more time is available to perform the initial

calibration before scanning begins. Page gap calibration must be necessariliy short to ensure the process

finishes in the limited number of scan lines available.

The Black and White Fine Tuning, and Black Calibration Only modes can be used during the page gap to adjust

for small differences in offset/gain that occur over time.

Black and White Full Calibration should be run before the initial scanning process, or periodically between major

jobs to take care of larger shifts in offset/gain of the input signal.

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7.4.12.3 Calibration Initiation

Once these settings have been made, the Register Lock Control bit (Page 0, Register 0, Bit 0) should be set to

begin converting pixels. Once the sensor data from the test image is stable the calibration process can be started

by either setting the CAL register bit at Page 0, Register 0x01h, Bit 5, or by applying a logic high to the CAL input

pin. (Both of these inputs are active when the Register Lock Control is set.) The CAL input pin is particularly

useful for implementing page gap calibration.

7.4.12.4 Key Calibration Settings

Table 8. Key Calibration Settings

● General Settings

● Calibration Mode

Black Calibration Only

Page 2, Register 0, Bits[1:0]

00

Black and White Full Calibration

Black and White Fine Tuning

01

10

● Number of Lines

Page 2, Register 1

● Black Loop Specific Settings

● # Black Pixels Averaged

● B lack Target

Page 2, Register 2, Bits[1:0]

Page 2, Register 3

● Black Pixels Start

● ADAC Scaling

Page 2, Register 8

Page 2, Register 2, Bits[3:2]

Page 2, Register 2, Bits[5:4]

Page 2, Register 0, Bit 2

● DDAC Scaling

● DDAC enable/disable

● White Loop Specific Settings

● White Target

Page 2, Register 5

● White Loop Tolerance

Page 2, Register 4, Bits[6:3]

Page 2, Register 4, Bits[2:0]

Page 2, Register 0x09h, 0x0Ah

Page 2, Registers 0x0Bh, 0x0Ch

● White Pixel Averaging Window Size

● Active/White Pixels Start

● Active/White Pixels End

The calibration loops are intended to be used prior to scanning the page or between pages being scanned. The

black loop calibrates the channel offset such that the ADC outputs the desired code for Optical Black Pixels. The

white loop calibrates the channel gain such that the ADC outputs the desired maximum white value when

scanning a white target image.

The Black Loop and White loop will both update until the # Lines setting is met. Settings of 1 to 254 lines will

cause the loops to run for that many lines, and then stop. A setting of 255 will cause the calibration loops to run

indefinitely.

While using the Auto Black Level Correction Loop, the DAC registers are re-written as required every line the

loop is running.

While using the Auto White Level Correction Loop, the PGA registers are re-written as required every line the

loop is running.

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7.4.12.5 General Black Loop Operation

During calibration, the following general process is performed:

•

Beginning at Black Pixels Start, the selected number of black pixels are averaged.

This Black Average value is compared with the Black Target to give the Black Error value.

In general, if the Black Average > Black Target, the new DAC values will be lower than the previous ones. If

the Black Average < Black Target the new DAC values will be higher than the previous ones.

•

The ADAC Scaling and DDAC Scaling values are used to balance the speed of convergence against the

tolerance for noise in the data. The smallest (1/8) scaling values will give slower convergence, but will make

the system respond more slowly to noisy data. The highest (1/2) will result in the fastest convergence, but will

respond more quickly to noisy data. The DDAC scaling factor of Linear - 1LSB adjust will result in a maximum

change of one lsb of the DDAC value, regardless of how great the difference between Black Average and

Black Target

•

The number of Black Pixels to be processed by the algorithm is set at Page 2, Register 2, Bits[1:0]. 4, 8, 16

or 32 pixels can be averaged together to determine the current Black Value. Averaging the highest number of

pixels possible for the sensor in use will improve the accuracy and repeatability of the Black Average value.

The delay from the end of the SH Interval to the first Black Pixel to be processed is set at Page 2, Register 8. A

delay of up to 255 pixels can be set.

7.4.12.6 ADAC/DDAC Convergence

At the beginning of the calibration process, the ADAC will be used to reduce the Black Error as much as

possible. Once further adjustments of the ADAC can no longer reduce the Black Error, the ADAC adjustments

will stop and the DDAC will be used. *If users would rather apply digital offset corrections in their ASIC, the

DDAC corrections can be omitted by setting the DDAC disable bit at Page 2, Register 0x00h, Bit 2.

Figure 20. Black Loop Timing

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7.4.12.7 General White Loop Operation

The White Peak value is determined by a moving window average done throughout the Active/White pixels

region of the line (Refer to LM98725 Typical Line Timing and Pixel Gain Regions). The size of the moving

window is set at Page 2, Register 4, Bits[2:0]. 4, 8, 16 or 32 (default) pixels are averaged together at a time and

compared with the previous Peak White value. If the new White Average is greater than the previous Peak White

value, then the Peak White value is set equal to the White Average. The window is then shifted over to the next

group of pixels (one window width) and a new average is calculated. This process is repeated until the

Active/White Pixels End value is reached. The final Peak White value is then compared with the White Target

value (Page 2, Register 5). The gain settings are then adjusted to make the Peak White value closer to the White

Target value.

7.4.12.8 White Loop Modes

•

White Full Calibration (Cold start or Pre-Job) - In this mode, the gain settings are completely reset to

default at the beginning of the loop. The first change or gain decision is whether the CDS/SH gain setting will

be 1x or 2x. Subsequent decisions are made to adjust the PGA setting to the provide the Peak White value

that is closest to the White Target value.

•

White Fine Tuning (Page Gap Calibration) - In this mode, the previous gain settings are used as the

starting point. The CDS/ SH gain setting will not be changed. The PGA gain will be increased or decreased

by one step at a time, to fine tune the gain. This mode is normally used where only minor changes in the

white level are expected.

7.4.12.9 Bimodal (Automatic) Correction

Due to the architecture of the ADC used in the LM98725, it is possible that a small offset in the resulting data will

be present between the Even and Odd pixels processed by the device. This offset is referred to as a Bimodal

distribution in the data. It can occur because the signals being procesed go through two different paths to

achieve the required throughput. Each of these paths can give a slightly different signal offset, resulting in the

bimodal distribution in output data, for a given fixed input voltage.

When the automatic Black Level (offset) correction circuit is engaged, a portion of that circuitry automatically

corrects the bimodal distribution. The bimodal correction applied is stored at Page 1, Registers 0x1Ch, 0x1Dh,

and 0x1Eh. The stored value is divided by two. Half is added to the Even pixels, and half is subtracted from the

Odd pixels.

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7.4.13 Coarse Pixel Phase Alignment

Precise placement of the CCD video signal sampling point is a critical aspect in any typical imaging application.

Many factors such as logic gate propagation delays and signal skew increase the difficulty in properly aligning

the CCD pixel output signals with the AFE input sampling points. The LM98725 provides two powerful features to

aid the system level designer in properly sampling the CCD video signal under a large range of conditions. The

first feature, discussed in this section, is the Coarse Pixel Phase Alignment block. As the name implies, this block

provides a very coarse range of timing adjustment to align the phase of the CCD Pixel output with the phase of

the LM98725 sample circuit. The second feature, discussed in Internal Sample Timing, is the block which is

designed for fine tuning of the sampling points within the selected Coarse Pixel Alignment Phase. A small portion

of a typical imaging application is shown in Figure 21.

SH

φ1Α

LM98724 CCD

Timing Generator

Outputs

φ2Α

OS3

CCD/CIS

Sensor

OS2

LM98724

Output Data Bus

OS1

Input Clock

(INCLK)

Figure 21. Typical AFE/CCD Interface

As shown in Figure 21, the LM98725 provides the timing signals to drive the CCD using external logic gates to

drive the high capacitance CCD clock pins. The pixels are shifted out of the CCD, through the emitter follower

buffers and received by the LM98725 inputs for processing.

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In an ideal application, depicted in Figure 22, the Pixel output signal would be in phase with the timing signals

that drove the CCD. The LM98725 input sampling clocks (CLAMP and SAMPLE) are adjustable within a pixel

period. By default, the pixel period (or pixel “phase”) is defined to be in line with the input clock. As shown in the

ideal case in Figure 22, CLAMP and SAMPLE can be properly adjusted to their ideal positions within the pixel

phase, shown below at the stable region near the end of the pedestal and data phases.

Figure 22. Clock Alignment in an Ideal Application

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However, in a real system , propagation delays exist in all stages of the signal chain. These propagation delays

will lead to a shift in the CCD Pixel outputs with respect to the LM98725 input clock. The phase shift of the CCD

Pixel output, demonstrated in Figure 23, can lead to significant sample timing issues if not properly corrected.

Figure 23. CCD Output Phase Shift in a Real Application

In the default mode, the LM98725 sampling is performed during a clock period whose phase is aligned with the

input clock (ignoring any clock tree skew for the moment). The actual sampling clocks are adjustable within the

clock period, as shown in Figure 23 (shown for CDS mode in the diagram) and further described in the Internal

Sample Timing section. As shown in the diagram, the delay of the CCD Pixel output is shifted far enough that the

fine CLAMP and SAMPLE clocks cannot be placed in a stable portion of the waveform. To remedy this situation,

the LM98725’s Coarse Pixel Phase Alignment feature allows the designer to shift the entire phase of the analog

front end with respect to the input clock. This allows the designer to choose one of four sampling phases which

best matches the delay in the external circuitry. Once the “Coarse Pixel Phase” has been chosen, the designer

can then fine tune the sampling clocks using the fine adjustment (see Internal Sample Timing.)

The four available Coarse Pixel Phases (PIXPHASE0 - PIXPHASE3) are depicted in Figure 24 (Mode 3),

Figure 25 (Mode 2) and Figure 26 (Mode 1). Also shown in the diagrams are the external input clock (INCLK)

and a typical CCD output delayed from the input clock.

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Figure 24. Mode 3 Coarse Pixel Adjustment

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Figure 25. Mode 2 Coarse Pixel Phase Adjustment

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Figure 26. Mode 1 Coarse Pixel Phase Adjustment

7.4.14 Internal Sample Timing

A typical CCD input signal is depicted in Figure 27 and Figure 28. Also shown are the internally generated

SAMPLE and CLAMP pulses. These signals provide the sampling points of the input signal (OSX). The timing of

SAMPLE and CLAMP is derived from an internal system clock (SYSCLK).

The pixel’s reference level input (depicted as V_REF) is captured by the falling edge of the CLAMP pulse. In

Sample/Hold Mode the V_REFinput is a sample of the VCLP DC voltage. In CDS Mode the CLAMP pulse samples

the pedestal Level of the CCD output waveform.

The pixel’s signal level input (depicted as V_SIG) is captured by the SAMPLE pulse. In either Sample/Hold or CDS

Mode, the V_SIGinput is the signal level of the CCD output waveform.

The LM98725 provides fine adjustment of the CLAMP and SAMPLE pulse placement within the pixel period. This

allows the user to program the optimum location of the CLAMP and SAMPLE falling edges. The available fine

tuning locations for CLAMP and SAMPLE are shown in Figure 29 and Figure 30 for each sampling mode (CDS

or S/H) and channel mode (3, 2, or 1 Channel).

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Figure 27. Pixel Sampling in CDS Mode

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Figure 28. Pixel Sampling in S/H Mode

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Figure 29. 3 Channel (Mode 3) CLAMP and SAMPLE Timing

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Figure 30. 1 or 2 Channel (Mode 1, Mode 2) CLAMP and SAMPLE Timing

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7.4.14.1 CCD Timing Generation

A flexible internal timing generator is included to provide clocking signals to CCD and CIS sensors. A block

diagram of the CCD Timing Generator is shown in Figure 32.

Figure 31. CCD Timing Generation

l o r t n o C t r e v n I

e c n e u q e S l a v r e t n I l e x i P

Figure 32. CCD Timing Generator Block Diagram

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Examples of the various operating modes and settings are shown in Figure 33 through Figure 36. The detailed

pixel timing is somewhat dependent on the operating modes of the AFE circuitry regarding the number of

adjustment points for the on and off points of the different timing outputs.

NOTE: In addition to the timing adjustments shown, the polarity of all sensor clock signals can be adjusted by

register control.

Figure 33. Pixel Timing - 42 Timing Points Per Pixel in Mode 3

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Figure 34. Pixel Timing - 28 Timing Points Per Pixel in Mode 2 and Mode 1

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Figure 35. Pixel Timing - Normal or 1/2 Rate Timing for High Resolution Sensors

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Figure 36. Pixel Timing - Independent Inversion of Each Output

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7.4.14.2 SH Interval Details - Multiple States Defined within SH Interval

In the LM98725, each SH Interval (the period when the high speed pixel timing is stopped) can have a selected

number of “States”, with each “State” having a specified duration. In the most common usage, each SH Interval

is the same, and there can be as many as 31 defined States within the SH Interval. During each State, the logic

level of each output signal can be defined as 1 or 0. The duration of the State, and the logic levels of the signals

are defined in configuration registers on register pages 3, 4 and 5.

Each State basic duration can be from 1 to 255 pixel periods. There is also a multiplier of 2x, 4x, 8x or 16x (Page

2, Register 0x17) that will increase SH State durations for sensors that require long SH pulse widths.

If less than the maximum number of states are required, the first 0 duration State in the SH Interval will terminate

processing. At the end of the SH Interval, a glitchless transition to pixel timing will occur. Similarly, at the end of

the pixel timing, a glitchless transition to the first state in the SH Interval will occur.

Some more complex sensors require different SH Interval timing in some sequence. The LM98725 can support

up to 4 different SH Interval Timings. The available 31 states are divided as follows when higher numbers of SH

Intervals are used:

Table 9. States within SH Intervals

AVAILABLE STATES

# of SH Intervals

SH Interval 1

0 to 30

0 to14

SH Interval 2

n/a

SH Interval 3

n/a

SH Interval 4

1

2

3

4

n/a

15 to 30

10 to 19

7 to 14

n/a

0 to 9

20 to 30

15 to 22

n/a

0 to 6

23 to 30

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Figure 37. Sensor Timing SH Interval Details - Single SH Interval

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An example showing a 4 SH Interval sequence is shown in Figure 38 through Figure 41.

Figure 38. Sensor Timing SH Interval Details - Multiple SH Intervals - 1 of 4

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Figure 39. Sensor Timing SH Interval Details - Multiple SH Intervals - 2 of 4

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Figure 40. Sensor Timing SH Interval Details - Multiple SH Intervals - 3 of 4

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Figure 41. Sensor Timing SH Interval Details - Multiple SH Intervals - 4 of 4

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7.4.14.3 SH Outputs - Low Speed Line Timing Usage

While the PHI, RS and CP outputs generate high speed timing during the pixel portion of the line, the SH outputs

can be used to generate low frequency signals during this period. This can be useful to generate “mode” or

“resolution” control signals for certain sensors.

Each SH output has a programmed ON and OFF point within the line. These points are programmed with a 16

bit value that sets the pixel number where the transition occurs.

Programming ON and OFF in different orders will allow pulses that are normally low or normally high, always

high, always low, and so on. A common 1x, 2x, or 4x multiplier (Page 2, Register 0x15) can be used to increase

the range (and reduce the resolution) of these ON/ OFF points, as well as the White/Active and Line Length

pixels settings.

SH Interval

Waveform set by SH

Interval Sequence

ON < OFF

ON > OFF

ON

OFF

ON

OFF

ON < OFF

ON

OFF

ON < OFF, OFF = 0xFFFFFFFF

ON > OFF, ON = 0xFFFFFFFF

ON = 0, OFF = 0xFFFFFFFF

OFF = 0, ON = 0xFFFFFFFF

OFF

ON

OFF

Figure 42. Sensor Timing SH ON/OFF Details - Example Settings and Waveforms

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7.4.14.4 Controlled Inversion

When using multiple SH Intervals, it is possible to invert the pixel portion of the line for any of the output signals

in any of the 4 Lines in the sequence. There is one bit per signal (or pair of signals for PHIA, PHIB and PHIC),

for each of the 1 to 4 lines in the sequence. Setting the bit for a particular output and line in the sequence will

cause the pixel portion of that line to be inverted. The transition to the next line in the sequence occurs at the

end of the SH Interval. Inversion can affect both the high speed timing signals (PHIx, RS, CP) and the low speed

ON/OFF behavior of the SH signals.

Below is an example of Polarity Override with a 2 Line sequence. Note that the PHIA1, SH1, SH2 and SH3

signals are inverted in Line 2, while all other signals are at the default polarity for both lines.

SH Interval 1

Line 1

SH Interval 2

Line 2

SH Interval 1

RS

PHIA1

SH1

SH2

SH3

SH4

SH5

0

1

0

Polarity

Override

Settings

Polarity

Override

Settings

SH Interval signal levels are set by SH Interval Information

Polarity for pixel portion of lines can be adjusted by Polarity Override Settings – Page 7, Registers 0x14 to 0x1D

Figure 43. Sensor Timing Mode Pin Output Details - Active Programmed Transition

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7.4.15 CCD Timing Generator Master/Slave Modes

The internal Sensor Timing generator is capable of operating in Master Mode or in Slave Mode. The

Master/Slave operation is configured with the Master Mode Select bit (Page 0, Register 0x00, bit 1). In either

Master or Slave Mode, control bit data can be included in the LM98725 output data to indicate when each new

scan is starting as well as pixel information such as color, type (active, black, dummy, and so on), and the

beginning of each line.

7.4.15.1 Master Timing Generator Mode

In Master Timing Mode (Page 0, Register 0x00, bit 1 = 1), the LM98725 controls the entire CCD Timing

Generation based on INCLK and the Register Lock Bit (Page 0, Register 0, Bit 0) state. The Register Lock bit is

set by the user to initiate a new scan. The LM98725 controls when each new line of the scan begins and ends

based on the CCD Timing Generator register settings. Scanning is enabled as long as the Register Lock bit = 1.

The period of the line (integration time) is controlled by the SH Interval State Length settings (Page 3 Registers)

and the Line Length setting (Page 3, Registers 0x0D and 0x0E) as well as the Pixel Multiplier Factor (Page 2,

Register 0x0F) and SH State Length Multiplier (Page 2, Register 0x11) .

The line period from end of one SH Interval to the end of the next SH Interval is equal to:

Line Period = (Sum of SH Interval States x SH State Length Multiplier) + (Line Length Setting x Pixel Multiplier

Factor) pixels

7.4.15.2 Slave Timing Generator Mode

In Slave Timing Mode (Page 2, Register 0x00, bit 1 = 0), the LM98725 CCD Timing Generator is controlled by

the external SH_R pin. Each new line of a scan is initiated by an SH_R pulse. The period of the line (integration

time) is mainly controlled by the period of the incoming SH_R signal. The minimum period between SH_R pulses

should be at least the SH Interval duration as calculated above, plus the number of pixels to be clocked out of

the CCD or CIS sensor.

t_{SHR_H}

t_{SHR_S}

SH_R

INCLK

Figure 44. SH_R to INCLK (PIXCLK or ADCCLK) Timing

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7.4.15.3 Multiple SH Intervals

Multiple SH Intervals are supported for those CCD sensors that has different waveform and timing requirements

during successive SH Intervals. Up to 4 different SH Intervals are supported.

In the Multiple SH Interval mode, the Line Period can be different for each line, due to the possible different

settings for SH Interval duration. In that case the Line Periods would be calculated as follows:

Line Period1 = (Sum of SH Interval States1 x SH State Length Multiplier) + (Line Length Setting x Pixel Multiplier

Factor) pixels

Line Period2 = (Sum of SH Interval States2 x SH State Length Multiplier) + (Line Length Setting x Pixel Multiplier

Factor) pixels

Line Period3 = (Sum of SH Interval States3 x SH State Length Multiplier) + (Line Length Setting x Pixel Multiplier

Factor) pixels

Line Period4 = (Sum of SH Interval States4 x SH State Length Multiplier) + (Line Length Setting x Pixel Multiplier

Factor) pixels

In multiple SH Interval mode, the SH Interval States are subdivided as follows:

Table 10. SH Interval States Subdivision

SH INTERVAL 1

STATES

SH INTERVAL 2

STATES

SH INTERVAL 3

STATES

SH INTERVAL 4

STATES

# SH INTERVALS

1

2

3

4

0 to 30

0 to 14

0 to 9

15 to 30

10 to 19

7 to 14

20 to 30

15 to 22

0 to 6

23 to 30

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7.4.15.4 Support for CIS Sensors

In CIS Sensor modes, the SH (LampR), SH2 (LampG), SH3 (LampB) and SH4 (LampIR) outputs are configured

as Lamp illumination control outputs. In CIS mode, the number of lines/colors in the lamp sequence is selected

by the Multiple SH Interval setting at Page 2, Register 10h, Bits 1:0. Sequences of 2, 3 or 4 lines/colors are

supported in CIS mode. By definition, the standard CCD timing mode is equivalent to a CIS mode with length =

1.

Two different CIS modes are supported (CISa and CISb, selected at Page 2, Register 0x10h, Bits 4:3):

In CISa, there can be 2, 3 or 4 colors in the sequence, to support sensors with as many as 4 different lamp

colors. In this mode, the PGA and DAC settings are controlled by the channel settings, regardless of what line in

the sequence is being processed.

Figure 45. Mode 3, 3 Color Sequence, CISa Default

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In CISb, there are 2 or 3 colors in the sequence. In this mode, the PGA and DAC settings are controlled by the

color in the sequence that is being processed. For example, when a Red line of data (exposed using the SH1 or

LampR output) is being processed, the Red channel PGA and DAC settings are used for all input channels.

When the SH2/LampG (Green) line of data is being processed, the Green PGA and DAC settings are used for all

input channels. and so on.

Figure 46. Mode 3, 3 Color Sequence, CISb

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In CISb, when a 2 line sequence is selected, it is necessary to choose which coefficients are used during the 2

different lines in the sequence. this selection is made with the CISb Color Coefficient Select at Page 2, Register

10h, Bits 6:5. Following is an example of a 2 color sequence, where Red and Green are the selected colors:

Use Page 2, Register 10h, Bits 6:5 to choose which SHx Lampx outputs are used, and which coefficients are used in

CISb 2 color sequence.

Figure 47. Mode 3, 2 Color Sequence, CISb

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To support monochrome scanning with an RGB CIS, select Mode 3, and a 1 line sequence. The LampR, LampG

and LampB On/Off times will apply for every line. The On/Off times and relative channel gains can both be

adjusted to achieve the desired white balance. Lamps can be on either simultaneously if the CIS and power

budget allow, or sequentially.

Figure 48. Mode 3, Mono – 1 Color, CCD Timing Lamps can be on simultaneously , or sequentially within

each line

7.4.15.5 LVDS Output Format - LM98714 Mode

7 Bit Frame

TXCLK

TXOUT2

TXOUT1

TXOUT0

CB[1]

CB[0]

DB[9]

DB[15]

DB[8]

DB[14]

DB[7]

CB[4]

CB[3]

CB[2]

CB[1]

CB[0]

DB[9]

DB[15]

DB[8]

DB[14]

DB[7]

n-1

n

DB[10]

DB[3]

DB[13]

DB[6]

DB[12]

DB[5]

DB[11]

DB[4]

DB[10]

DB[3]

n-1

n

DB[2]

DB[1]

DB[0]

DB[2]

DB[1]

DB[0]

n

n-1

n

Pixel “n-1”

Pixel “n”

Figure 49. LVDS Output Bit Alignment and Data Format

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7.4.16 LVDS Control Bit Coding - LM98714 Mode

The 5 control bits included in the LVDS data stream are coded as follows:

The "active" and "black" pixel tags are programmable tags that the LM98725 provides in order to identify how

many pixels have been processed since the falling edge of SH.

Which pixels are given "Active" and "Black" CB tags is controlled by Page 2, Registers 0x02, 0x08-0x0C, and

0x0F. (# Black Pixels Averaged, Black Pixels Start, Active/White Pixels Start, Active/White Pixels End, and Line

Length Multiplier).

The LM98725 counts the number of pixel periods after the SH Interval: If the number of pixel periods after the

SH Interval is greater than (Black Pixels Start) and less than (Black Pixels Start + # Black Pixels Averaged) the

CB bits will indicate that the pixel is a Black pixel. If the number of pixel periods after the falling edge of SH is

between Active/White Pixels Start and Active/White Pixels End, the CB bits will indicate that the pixel is an Active

pixel.

7.4.16.1 Latency Compensation of CB Bits

By default, the CB bits will be compensated for the latency through the AFE signal chain. This compensation can

be turned off by setting Page 8, Register 0x08, Bit 2 = 1.

Table 11. Latency Compensation of CB Bits, CB[4]

CB[4]

DESCRIPTION

Not the beginning of line

0

1

Beginning of Line (This bit is high during the SH Interval)

Table 12. Latency Compensation of CB Bits, CB[3:0]

CB[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

DESCRIPTION

Dummy Pixels

Red Active Pixels

Green Active Pixels

Blue Active Pixels

IR1 Active Pixels

IR2 Active Pixels

Red Black Pixels

Green Black Pixels

Blue Black Pixels

IR1 Black Pixels

IR2 Black Pixels

Beginning of Scan

1111

(This bit is high during the SH Interval of the first line after the Lock Bit transitions from low to high)

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7.4.17 Flexible LVDS Formatting Mode: Mapping

7 Bit Frame

TXCLK

TXOUT2

TXOUT1

TXOUT0

DB[12]

DB[4]

DB[11]

DB[7]

DB[10]

DB[3]

DB[9]

DB[2]

DB[15]

DB[8]

DB[14]

n

DB[13]

DB[6]

DB[12]

DB[5]

DB[11]

DB[4]

DB[10]

DB[3]

DB[9]

DB[2]

n-1

n

DB[7]

n

n-1

n

CB[3]

CB[2]

CB[1]

CB[0]

DB[1]

DB[0]

n

CB[4]

CB[3]

CB[2]

CB[1]

CB[0]

n

n-1

n

Pixel “n-1”

Pixel “n”

Figure 50. LVDS Output Bit Alignment and Data Format

In Flexible LVDS Formatting Mode, the values highlighted in red can be substituted with other CB tag

information. The table below shows the different CB information that can be selected:

Table 13. Selectable CB Tag Information

SETTING

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1100

1111

CB TAG INFORMATION

Original CB or Data

CBO0 from LM98714 definition

CBO1 from LM98714 definition

CBO2 from LM98714 definition

CBO3 from LM98714 definition

CBO4 from LM98714 definition

R - High for a red channel pixel

G - High for a green channel pixel

B - High for a blue channel pixel

Parity - 21 bit if TXOUT0 Enabled, 14 bit if TXOUT0 Disabled

Ping - High for pixels processed by the Ping section of a channel, low for Pong

Line# lsb - Line = 0 to 3 for lines 0 to 3 in multiline sequences

Line# msb

Black Loop Pixels - High for pixels processed by the Black Loop

White Loop Pixels - High for pixels process by the White Loop

CLP Pixels - High for pixels where the input CLP switch is closed

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7.4.17.1 TXOUT0 Disable

The TXOUT0 data pair can be disabled. In combination with the new Flexible LVDS Formatting Mode, this can

support applications where only the upper 14 MSB of data are required. This will save one pair of LVDS wires in

the cable, and reduce the LM98725 slightly.

In addition, if fewer than 14 bits are required, the D2 and D3 bits can be replaced with the desired CB

information, selected from the above table.

7.4.17.2 Parity

A parity bit is available for use as one of the CB bits. Parity is calculated based on all bits being sent via the 21

or 14 bit LVDS link except:

•

If any bit is selected to transmit CB Parity, it will not be used in the calculation

If any bit is transmitting a scrambler key bit when scrambler mode 2 is selected, it will not be used in the

calculation.

The total parity across the 21 or 14 output bits (excluding any scrambler key bit) will be even.

7.4.17.3 Latency Compensation of CB Bits

By default, the CB bits will be compensated for the latency through the AFE signal chain. This compensation can

be turned off by setting Page 8, Register 0x08, Bit 2 = 1.

7.4.18 LVDS Data Randomization for EMI Reduction

While LVDS transmissions will inherently reduce the amount of electromagnetic energy, further reductions can be

achieved by randomizing the data being sent over the link. A built in “scrambler” feature provides a number of

different modes to suit different applications and host processing capabilities. One key part of the scrambler is a

linear feedback shift register (LFSR) implementation to provide pseudo-random sequence “keys” to randomize

the image data. The basic implementation of an LFSR is shown below:

XOR

...

20 19 18

2

1

0

Figure 51. LFSR Implementation

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The LFSR algorithm used in the LM98725 is an n=21 maximal length right-shift implementation as shown above.

As a reference for FPGA and ASIC developers, the sequence is the same as that created by the Synopsys DW

component DW03_lfsr_load with inverted outputs. The preload or starting value for the sequence is 0x000001h.

If the prs (serial-type) output is selected (MODE = 01, SUB_MODE = 0X), the 21 bits of the LFSR are shifted one

position to the right on each TXCLK.

For clarity, the first 11 values in the prs sequence are:

0x000001h

0x100000h

0x080000h

0x040000h

0x020000h

0x010000h

0x008000h

0x004000h

0x002000h

0x001000h

0x000800h

If the pprs (parallel-type) output is selected (MODE = 01, SUB_MODE = 1X), the next 21 coefficients of the shift-

in term are calculated in parallel, and the LFSR is loaded with these coefficients: the effect is equivalent to

clocking the LFSR 21 times in serial mode. For clarity, the first 11 values in the pprs sequence are:

0x000001h

0x080001h

0x020001h

0x0A8001h

0x002001h

0x082801h

0x022201h

0x0AAA81h

0x000021h

0x080029h

0x120023h

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A summary and description of each of the modes and submodes is shown in Table 14.

Table 14. Mode and Submode Summary

MODE

PAGE 0

REGISTER 0x05

BITS 4:3

SUB_MODE

PAGE 0

REGISTER 0x05

BITS 2:1

DESCRIPTION

00

Scrambler Disabled

full scrambler enabled. sub-mode settings select:

send lvds_data[20:0] bitwise XOR with prs[20:0]

send prs[20:0]

00

01

10

11

01

send lvds_data[20:0] bitwise XOR with pprs[20:0]

send pprs[20:0]

1 bit scrambler with key of prs[0]

send lvds_data[20:0] bitwise XOR with prs[0], with lvds_data[k] = 0

send prs[0] on lvds_out[k]

k is selected with following settings:

00

01

10

11

k = 0 (DB0 in CMOS and 714 modes, CB0 in flexible, 16 bit mode)

10

k = 5 (DB0 (LSB) in flexible, 16 bit mode)

k = 7 (DB2 (LSB) in flexible, 14 bit mode)

k = 16 (CB0 in 714 mode)

k = 20 (CB4 in 714 mode)

1 bit scrambler with key of lvds_data[k].

send lvds_data[20:0] bitwise XOR with lvds_data[k]

with lvds_out[k] = lvds_data[k]

00

k = 0 (DB0 in CMOS and 714 modes, CB0 in flexible, 16 bit mode)

11

01 (TXOUT0 Disable = 0) k = 5 (DB0 (LSB) in flexible, 16 bit mode)

01 (TXOUT0 Disable = 1) k = 7 (DB2 (LSB) in flexible, 14 bit mode)

10

11

k = 16 (CB0 in 714 mode)

k = 20 (CB4 in 714 mode)

7.4.18.1 Mode 00: Scrambler Disabled

Mode 00: Scrambler Disabled

7.4.18.2 Mode 01: Full Scrambler Using the full 21-bit Pseudo Random Sequence

There are 4 sub-modes: (a) the 21-bit output will be bit-wise XORed with the 21-bit serial pseudo-random

sequence. that is, lvds_data[20:0] ^ prs[20:0]; (b) the 21-bit serial pseudo random sequence will be output

directly; (c) the 21-bit output will be bit-wise XORed with the 21-bit parallel pseudo-random sequence. that is,

lvds_data[20:0] ^ pprs[20:0]; (d) the 21-bit parallel pseudo random sequence will be output directly. In all sub-

modes, the sequences start m clock cycles after the de-assertion of the bol where m is defined as the analog

latencies in 1-ch, 2-ch and 3-ch modes. In other words, the output starts the same way as the up-count test

pattern mode. Unlike the up-count test pattern mode, the 21-bit pseudo-random sequence runs at the ADC

(same as TXCLK) rate, not pixel or line rate.

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7.4.18.3 Mode 10: One Bit Scrambler Using the PRS Shift Bit Only, Sending This Bit Out on a CB Bit

Each bit of lvds_data[20:0] is XORed with prs[0]. One selected bit, lvds_data[k] is replaced with 0 before the

XOR procedure. The resulting output lvds_out[20:0] has bit k replaced by prs[0]. The bit k selection is flexible to

support different mappings of lvds_out depending on output settings as follows:

•

LVDS Mapping - 714 Default Mode versus Flexible Mode (Since the location of CB bits changes depending

on which is selected) Mapping select is at Page 8, Register 8, Bit 0.

CMOS Mode versus LVDS Mode (since only lvds_out[15:0] are available in CMOS mode) CMOS/LVDS mode

select at Page 0, Register 5, Bit 7.

LVDS 3 Pair Mode versus LVDS 2 Pair Mode (Since TXOUT0 pair is disabled in 2 Pair Mode(txout0_dis=1))

TXOUT0 Disable at Page 8, Register 8, Bit 1.

(1) If an output bit is replaced with the scrambler key, that bit position/value is excluded from the calculation of the parity.

Figure 52. lvds_out[20:0] Mapping in Different Modes

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7.4.18.4 Mode 11: “LSB” Scrambler

The “LSB” selected from lvds_data[k] is used to scramble the output. The lvds_data[20:0] key bit k, as selected

in Mode 10 above is used (as the “LSB”) to XOR the other bits. The key bit itself is not replaced.

7.4.18.5 Scrambler Inhibit Bit Select

This feature allows individual bits in the LVDS output stream to be non-scrambled. This can be used as a setup

and debugging aid during initial system development, or as a permanent feature to simplify the data decoding

task. The tradeoff will be somewhat compromised EMI reduction over a fully scrambled LVDS data stream.

The controls for this feature are located as follows:

Scrambler Inhibit 0 - Page 8, Register 0x12h, Bits 6:0 - LVDS[6:0]

Scrambler Inhibit 1 - Page 8, Register 0x13h, Bits 6:0 - LVDS[13:7]

Scrambler Inhibit 2 - Page 8, Register 0x14h, Bits 6:0 - LVDS[20:14]

7.4.19 LVDS Drive Strength Adjust

The LVDS outputs may be decreased in strength to reduce EMI generation, or increased in strength to improve

noise immunity.

Page 8, Register 8, Bits 5:4 can be adjusted as follows (in terms of VOD into 100 Ω termination):

Table 15. LVDS Strength

00

01

10

11

Decrease of approximately 100 mV

Decrease of approximately 50 mV

Default - approximately 350 mV

Increase of approximately 50 mV

7.4.20 LVDS Output Timing Details

INCLK

t

IDO

7 Bit Frame Period

TXCLK

(single ended)

Pixel “n-1”

Pixel “n”

TXOUT2

(single ended)

CB[1]

CB[0]

DB[9]

DB[15]

DB[14]

CB[4]

CB[3]

CB[2]

CB[1]

n

CB[0]

DB[9]

DB[15]

DB[8]

DB[14]

DB[7]

n-1

n

TXOUT1

(single ended)

DB[10]

DB[3]

DB[8]

DB[7]

DB[13]

DB[12]

DB[5]

DB[11]

DB[4]

DB[10]

n

n-1

n

TXOUT0

(single ended)

DB[2]

DB[1]

TX

DB[0]

DB[6]

DB[3]

n

DB[2]

DB[1]

DB[0]

n

n-1

n

TX

pp0

pp1

TX

pp2

TX

pp3

TX

pp4

TX

pp5

TX

pp6

Figure 53. LVDS Data Output Mode Specification Diagram

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7.4.20.1 Optional TXCLK Delay

The LM98725 includes a selectable (off by default) delay of TXCLK. This delay can be enabled (Page 8, Register

0x08, Bit 3) to improve timing margin between the TXCLK and TXOUTx signals when using certain LVDS

deserializers. The default/off setting is intended to be compatible with the LM98714 LVDS timing.

7.4.21 LVDS Data Latency Diagrams

Figure 54. Mode 3 LVDS Data Latency

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Figure 55. Mode 2 LVDS Data Latency

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Figure 56. Mode 1 LVDS Data Latency

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7.4.22 Data Test Patterns

The data test patterns present different data to the input of the LVDS serializer block. There are two basic groups

of test patterns:

•

LVDS Output Pattern Modes - These patterns are applicable to all 21 bits of the LVDS interface.

AFE Output Pattern Modes (Default) - These patterns are applicable to the 16 bit AFE data sent to the LVDS

interface.

•

All Test Pattern Modes are selected at Page 0, Register 6.

7.4.22.1 LVDS Output Pattern Modes

7.4.22.1.1 Worst Case Transitions (Alternating 0x2A/0x55 on Each LVDS Pair)

This test mode provides an LVDS output with the maximum possible transitions. This mode is useful for system

EMI evaluations, and for ATE timing tests.

The effective data values are an alternating pattern between 21’b101010101010101010101 (0x155555) and

21’b010101010101010101010 (0x0AAAAA). This test pattern resets to 0x155555 at the selected event (BOL or

BOS).

Figure 57. LVDS Output Pattern Modes

7.4.22.1.2 Fixed Output Data

This mode sends a fixed repeating data pattern to each of the indicated LVDS output pairs. This is useful for

system debugging of the LVDS link and receiver circuitry. There are 4 different choices within this mode:

•

0x2A (0101010b) (All 3 data pairs)

0x55 (1010101b) (All 3 data pairs)

(0000000b) (*All 3 data pairs + clock pair)

0x7F (1111111b) (*All 3 data pairs + clock pair)

*Since the 0x00 and 0x7F patterns also affect the clock pair, they cannot be used for deserializer and

downstream testing. They are useful for DC measurements of the LVDS outputs.

7.4.22.2 AFE Output Pattern Modes

There are 3 different types of AFE Output Patterns:

•

Normal ADC/AFE output (Default)

Up-Counter Data

Fixed AFE Patterns

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7.4.22.2.1 Up-Counter Data

The counter will be reset to 0xFFFF during the BOS (Beginning Of Scan) SH Interval. When the AFE up-counter

is selected, the ramp begins at the BOS, and increments by 1 at either the pixel rate or at the line rate (every

BOL). This data can be useful as it can provide a grayscale image that increases in intensity down the “page”.

Alternately, it can provide data that increments at the pixel rate. Either of these forms can be very useful in

debugging the downstream data processing system.

7.4.22.2.2 Fixed AFE Pattern

The fixed AFE patterns allow the CB coding information to be sent normally, while specific data is used to

replace the AFE output. This can be useful in debugging portions of the downstream data processing system.

•

0xFF00 (0x1111111100000000b) fixed data

0xAA55 (0x1010101001010101b) fixed data

0x0000 (0x0000000000000000b) fixed data

0xFFFF (0x1111111111111111b) fixed data

0x00FF (0x0000000011111111b) fixed data

0x55AA (0x0101010110101010b) fixed data

7.4.23 CMOS Output Format

Figure 58. CMOS Data Output Format (Mode 3 Shown)

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7.4.24 CMOS Output Data Latency Diagrams

INCLK =

ADCCLK

t_LAT3

PIXPHASE0

PIXPHASE1

PIXPHASE2

PIXPHASE3

OS_R

OS_G

OS_B

CLKOUT

DOUTx

MSB

LSB

Data latency shown is for Mode 3 in relation to PIXPHASE0 with the processing order set to OS_RDOS_GDOS_B. If the incoming pixels are not aligned with

PIXPHASE0, one of the remaining PIXPHASEs can be selected as the sampling phase without effecting the output data location.

Figure 59. Mode 3 CMOS Output Latency

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INCLK =

ADCCLK

t_LAT2

PIXPHASE0

PIXPHASE1

PIXPHASE2

PIXPHASE3

OS_R

OS_G

OS_B

CLKOUT

DOUTx

MSB

LSB

Data latency shown is for Mode 2 in relation to PIXPHASE0 with the processing order set to OS_GDOS_B. If the incoming pixels are not aligned with

PIXPHASE0, one of the remaining PIXPHASEs can be selected as the sampling phase without effecting the output data location.

Figure 60. Mode 2 CMOS Output Latency

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INCLK =

ADCCLK

t_LAT1

PIXPHASE0

PIXPHASE1

PIXPHASE2

PIXPHASE3

OS_R

OS_G

OS_B

CLKOUT

DOUTx

MSB

LSB

Data latency shown is for Mode 1 in relation to PIXPHASE0 with the processing channel configured to OS_R. If the incoming pixels are not aligned with

PIXPHASE0, one of the remaining PIXPHASEs can be selected as the sampling phase without effecting the output data location.

Figure 61. Mode 1 CMOS Output Latency

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7.4.25 Serial Interface

A serial interface is used to write and read the configuration registers. The interface is a four wire interface using

SCLK, SEN, SDI and SDO connections. SDI and SDO can be connected together to support the same format

and connectivity as previous LM98714 designs. The CE pin should be tied to GND to support LM98714

compatible communications. This will set the device address bits to 00.

Table 16. Serial Interface "CE" Pin Definition

CE LEVEL

VD

ADDRESS

01

10

00

Float

GND

The main input clock (INCLK) to the LM98725 can be active or stopped when accessing the Serial Interface.

Care should be taken to avoid stopping or starting the INCLK during Serial Interface communication.

NOTE

After either starting or stopping INCLK, or after Software Reset (Register Page 0, Address

1, [4:3]), users should wait for 50 ms to allow the internal PLL and logic to stabilize before

resuming Serial Interface communications.

7.4.25.1 Serial Interface Operating Modes

•

LM98714 Compatible Mode (Default) - By default the serial interface is compatible with the LM98714

interface, allowing SDI and SDO to be connected and driving by a single pin on the host.

•

LM98725 4 Wire 16+ Clock Mode (Default) - The 4 Wire 16+ Clock Mode is essentially the same as the

LM98714 Compatible Mode, but using all 4 wires, with separate SDO and SDI signals between the Host and

Slave. This requires additional wires, but removes the need for a bidirectional signal. A valid transaction is

recognized after a minimum of 16 SCLK while SEN is low.

•

LM98725 25+ Clock Mode (Selected when Page 0, Register 0x01h, Bit 7=1) - This mode forces the serial

interface logic to only process a transaction with 25 or more SCLK while SEN is low. This mode can be used

with either 3 or 4 wire connections.

In all of the above cases, the final 16 bits on SDI (before the rising edge of SEN) are processed by the serial

interface logic. Any earlier information on SDI is ignored.

7.4.25.2 Serial Interface in Absence of MCLK

•

Clockless (MCLK stopped) Mode (always enabled if MCLK stopped) - When the input MCLK is stopped,

Data Read operation is exactly the same as MCLK present mode. The Data Write operation no longer

provides a free readback of the previously written data. See Figure 64 and Figure 66.

7.4.25.3 Writing to the Serial Registers

To write to the serial registers, the timing diagram shown in Figure 62 must be met. First, SEN is toggled low.

The *previously addressed device assumes control of the SDO pin during the first eight clocks of the command.

During this period, data is clocked out of the device at the rising edge of SCLK. At the rising edge of ninth clock,

the LM98725 releases control of the SDO pin. At the falling edge of the ninth clock period, the master should

assume control of the SDI pin and begin issuing the new command. SDI is clocked into the LM98725 at the

rising edge of SCLK. The remaining bits are composed of the “write” command bit (a zero), two device address

bits (00, 01 or 10 for the LM98725), five bit register address to be written, and the eight bit register value to be

written. When SEN toggles high, the register is written to, and the LM98725 now functions with this new data.

*The previously addressed device could be another device on a shared serial interface or this device. If the

previous command was to this device, and was a read, then the SDO pin will be driven during the first eight

clocks. If the previous command was to this device and was a write, then the SDO pin will only be driven if the

serial interface is in “MCLK active” mode.

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7.4.25.4 Reading the Serial Registers

To read to the serial registers, the timing diagram shown in Figure 63 must be met. First, SEN is toggled low.

The LM98725 assumes control of the SDO pin during the first eight clocks of the command. During this period,

data is clocked out of the device at the rising edge of SCLK. The eight bit value clocked out is the contents of the

previously addressed register, regardless if the previous command was a read or a write. At the rising edge of

ninth clock, the LM98725 releases control of the SDO pin. At the falling edge of the ninth clock period, the

master should assume control of the SDI pin and begin issuing the new command. SDI is clocked into the

LM98725 at the rising edge of SCLK. The remaining bits are composed of the “read” command bit (a one), two

device address bits (zeros for the LM98725), five bit register address to be read, and the eight bit “don’t care”

bits. When SEN toggles high, the register is not written to, but its contents are staged to be outputted at the

beginning of the next command.

Examples of Serial Writes and Reads in the various modes are shown in Figure 62 through Figure 67.

7.4.25.5 LM98714 Compatible 3 Wire Serial Signaling

Figure 62. Serial Write - LM98714 Compatible Connection

1

9

n-15

n

SCLK

SEN

DO DO DO DO DO DO DO DO

[7] [6] [5] [4] [3] [2] [1] [0]

CE CE

0

DI DI DI DI DI DI DI DI

[7] [6] [5] [4] [3] [2] [1] [0]

DO DO DO DO DO DO DO DO

[7] [6] [5] [4] [3] [2] [1] [0]

X

1

A4 A3 A2 A1 A0

X

SDIO

1

(R)

Previously addressed slave

outputting register contents from

previous command.

Master issues “read” bit (1), 2 “chip enable” bits (00, 01 or 10), five bit register

address, and eight “don’t care” bits. Register contents are not altered.

Only final 16 bits of SDI data before rising edge of /SEN are processed.

Device outputting register contents

addressed in read command.

Figure 63. Serial Read - LM98714 Compatible Connection

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1

9

n-15

n

SCLK

SEN

SDO

DO DO DO DO DO DO DO DO

[7] [6] [5] [4] [3] [2] [1] [0]

DO DO DO DO DO DO DO DO

[7] [6] [5] [4] [3] [2] [1] [0]

Device outputting register contents from this

write command if MCLK is present.

If MCLK is not present, no data output will occur.

Previously addressed slave

outputting register contents from

previous command.

(W)

0

CE CE

0

DI DI DI DI DI DI DI DI

[7] [6] [5] [4] [3] [2] [1] [0]

X

A4 A3 A2 A1 A0

X

SDI

1

Master issues “write” bit (0), 2 “chip enable” bits (00, 01 or 10), five bit

register address, and eight bit register value to be written.

Only final 16 bits of SDI data before rising edge of /SEN are processed.

Figure 64. Serial Write - 4 Wire Connection - 25+ Clock Mode

1

9

n-15

n

SCLK

SEN

SDO

DO DO DO DO DO DO DO DO

[7] [6] [5] [4] [3] [2] [1] [0]

DO DO DO DO DO DO DO DO

[7] [6] [5] [4] [3] [2] [1] [0]

Device outputting register contents

addressed in read command.

Previously addressed slave

outputting register contents from

previous command.

CE CE

0

X

1

A4 A3 A2 A1 A0

X

SDI

1

(R)

Master issues “read” bit (1), 2 “chip enable” bits (00, 01 or 10), five bit register

address, and eight “don’t care” bits. Register contents are not altered.

Only final 16 bits of SDI data before rising edge of /SEN are processed.

Figure 65. Serial Read - 4 Wire Connection - 25+ Clock Mode

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1

n-15

9

n

SCLK

SEN

SDO

DO DO DO DO DO DO DO DO

[7] [6] [5] [4] [3] [2] [1] [0]

DO DO DO DO DO DO DO DO

[7] [6] [5] [4] [3] [2] [1] [0]

Previously addressed slave outputting

register contents from last command.

Device outputting register contents from this write

command if MCLK is present.

If MCLK is not present, no data output will occur.

(W)

CE CE

0

DI DI DI DI DI DI DI DI

[7] [6] [5] [4] [3] [2] [1] [0]

0

A4 A3 A2 A1 A0

X

SDI

1

Master issues “write” bit (0), 2 “chip enable” bits (00, 01 or 10), five bit

register address, and eight bit register value to be written.

Only final 16 bits of SDI data before rising edge of /SEN are processed.

Figure 66. Serial Write - 4 Wire Connection - 16+ Clock Mode

1

n-15

9

n

SCLK

SEN

SDO

DO DO DO DO DO DO DO DO

[7] [6] [5] [4] [3] [2] [1] [0]

DO DO DO DO DO DO DO DO

[7] [6] [5] [4] [3] [2] [1] [0]

Previously addressed slave outputting

register contents from last command.

Device outputting register contents

addressed in read command.

CE CE

0

DI DI DI DI DI DI DI DI

[7] [6] [5] [4] [3] [2] [1] [0]

1

A4 A3 A2 A1 A0

X

SDI

1

(R)

Master issues “read” bit (1), 2 “chip enable” bits (00, 01 or 10), five bit register

address, and eight “don’t care” bits. Register contents are not altered.

Only final 16 bits of SDI data before rising edge of /SEN are processed.

Figure 67. Serial Read - 4 Wire Connection - 16+ Clock Mode

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7.5 Register Maps

7.5.1 Configuration Registers

The LM98725 operation is very flexible to support a wide variety of sensors and system designs. This flexibility is

controlled through configuration registers which are first summarized, then described in full in the following

tables. Because the serial interface only allows 5 address bits, a register paging system is used to support the

larger number of required registers.

The page register is present at the highest address (1Fh or 11111b) of the currently selected page. The power

on default setting of the page register is 00. Writing other values to this register allows the other pages to be

accessed.

Once all registers are written, the Register Lock Control bit (Page 0, Register 0, Bit 0) is set to 1 to start the state

machines and initiate the converting of pixels. If Slave mode is selected, SH_R pulses must also be input to

trigger this process.

NOTE

When Register Lock Control = 1, many registers are locked to prevent state machines

from becoming corrupted, while others are accessible to allow control of necessary

functions. The registers and bits that are still writable are indicated in Boldface print in the

Bits and Register Description columns of the Register Definition Details table.

Operational Setup Sequence:

Ensure Lock Bit (Page 0, Register 0, Bit 0) = 0 for following setting writes

Apply either no INCLK or a stable INCLK to ensure accurate serial communications

Page 0

•

Set AFE mode (# of input channels)

Set output data format

Enable data outputs

Set AFE biasing

Set AFE Clamp and Sample timing

Setup Slave or Master Mode

Page 1

•

Set Gain Mode (Singe or Dual)

Set CDS/SH Gain

Set PGA

Set DAC settings

Page 2

•

Set Input Clamping Settings

Set Black Pixel Start and # Black Pixels Averaged

Set Active White Pixels Start and End

Set Line Length (Master Mode Only)

Set # Pixel Multiplier, SH Line Sequence # and SH State Length Multiplier

Set PHI, RS, CP On and Off delay settings

Set Spread Spectrum control settings

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Page 3

Set SH Slate Length Settings

Page 4

Set SH Interval State Settings for PHI, RS, CP

Page 5

Set SH Interval State Settings for SH1 to SH5

Page 6

Set PHI, RS. CP pattern bit fields and rate (normal or 1/2 rate)

Page 7

•

Set SHx On, Off settings if needed

Set CLK invert settings for multi-line sequences if needed

Page 8

•

Set CLK output activity, polarity, enable

Set LVDS output format

Set CB coding

Set PHI, RS, CP, SH unlock output state

Begin Scanning:

•

Ensure stable INCLK applied and PLL is locked (read back Page 0, Register 0, Bit 7)

Set Register Lock Control bit = 1

In Master Mode, conversions will begin after the Lock Bit is set. In Slave Mode, SH_R pulses can begin af ter

the Lock Bit is set. SH Intervals will be generated in response to the SH_R input pulses.

•

Registers and Bits marked in Boldface print may be adjusted while scanning is in progress. More major

changes (that is, color mode, CCDTG details) should be done by writing a 0 to the Register Lock Control Bit

to pause scanning.

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Register Maps (continued)

7.5.1.1 Register Summary Table

Table 17. Register Summary Table

Default

Addr (hex)

Page (dec)

Addr (dec)

Register Title

(binary)

PAGE 0

0

1

0

0010 0000

0100 0000

1100 0000

1000 0010

0011 0000

0000 0000

0001 0000

0000 0000

0001 0000

0000 0000

0001 0000

0001 0110

0010 0110

0001 0110

0010 0110

0001 0110

0010 0110

0000 0000

Main Configuration 0

Main Configuration 1

Main Configuration 2

Main Configuration 3

Main Configuration 4

Main Configuration 5

Configuration 6

1

2

3

4

5

6

7

Configuration 7

8

OSR CLAMP Start Edge

OSR CLAMP Stop Edge

OSG CLAMP Start Edge

OSG CLAMP Stop Edge

OSB CLAMP Start Edge

OSB CLAMP Stop Edge

OSR SAMPLE Start Edge

OSR SAMPLE Stop Edge

OSG SAMPLE Start Edge

OSG SAMPLE Stop Edge

OSB SAMPLE Start Edge

OSB SAMPLE Stop Edge

Sample & Clamp Monitor 0

Sample & Clamp Monitor 1

Reserved

9

A

10

11

12

13

14

15

16

17

18

19

20

21

22 to 29

30

31

B

C

D

E

F

10

11

12

13

14

15

16 to 1D

1E

1F

XX00 0011

0000 0000

Revision

Page Register

90

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Register Maps (continued)

Table 17. Register Summary Table (continued)

Default

(binary)

Page (dec)

Addr (dec)

Addr (hex)

Register Title

PAGE 1

1

0

1

0000 0000

0110 0001

1000 0000

0000 0000

1000 0000

0000 0000

1000 0000

0000 0000

1000 0000

0000 0000

1000 0000

0000 0000

1000 0000

0000 0000

0100 0000

0110 0001

0100 0000

0000 0000

Gain Mode

1

Red PGA

2

Green PGA

3

Blue PGA

4

Red Even DAC MSB

Red Even DAC LSB

Green Even DAC MSB

Green Even DAC LSB

Blue Even DAC MSB

Blue Even DAC LSB

Red Odd DAC MSB

Red Odd DAC LSB

Green Odd DAC MSB

Green Odd DAC LSB

Blue Odd DAC MSB

Blue Odd DAC LSB

Red Even Digital Offset

Green Even Digital Offset

Blue Even Digital Offset

Red Odd Digital Offset

Green Odd Digital Offset

Blue Odd Digital Offset

Red High Gain PGA

Green High Gain PGA

Blue High Gain PGA

Red Channel Bimodal

Green Channel Bimodal

Blue Channel Bimodal

Page Register

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

28

29

30

31

A

B

C

D

E

F

10

11

12

13

14

15

16

17

18

1C

1D

1E

1F

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Register Maps (continued)

Table 17. Register Summary Table (continued)

Default

(binary)

Page (dec)

Addr (dec)

Addr (hex)

Register Title

PAGE 2

2

0

1

0

1

0000 0000

0001 0100

0100 0000

0100 0011

1000 0000

0000 0100

0000 1100

0001 0000

0000 0000

0001 0100

0001 0000

0000 0000

0001 0000

0100 0000

0000 0000

Calibration Mode

Calibration # Lines

Black Cal Config

Black Target

2

3

4

White Cal Config

White Target

5

6

AutoCLPIN Start

AutoCLPIN End

Black Loop Start

7

8

9

Active/White Pixels Start - MSB

Active/White Pixels Start - LSB

Active/White Pixels End - MSB

Active/White Pixels End - LSB

Line Length MSB

Line Length LSB

10

11

12

13

14

15

16

17

18

19

20 to 23

24

25

26

27

28

29

30

31

A

B

C

D

E

F

Line Length Multiplier

Line Mode

10

11

12

13

14 to 17

18

19

1A

1B

1C

1D

1E

1F

SH State Length Multiplier

PHIA/B/C Delays

RS/CP Delays

Reserved

1111 1000

0001 1000

0000 0000

0000 0010

0000 0000

PLL Control 1

PLL Control 2

SSCG Control 1

SSCG Control 2

Clock Mult M

Clock Mult N

SSCG Control 3

Page Register

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Register Maps (continued)

Table 17. Register Summary Table (continued)

Default

(binary)

Page (dec)

Addr (dec)

Addr (hex)

Register Title

PAGE 3

3

0

1

0000 0000

SH State 0 Length

SH State 1 Length

SH State 2 Length

SH State 3 Length

SH State 4 Length

SH State 5 Length

SH State 6 Length

SH State 7 Length

SH State 8 Length

SH State 9 Length

SH State 10 Length

SH State 11 Length

SH State 12 Length

SH State 13 Length

SH State 14 Length

SH State 15 Length

SH State 16 Length

SH State 17 Length

SH State 18 Length

SH State 19 Length

SH State 20 Length

SH State 21 Length

SH State 22 Length

SH State 23 Length

SH State 24 Length

SH State 25 Length

SH State 26 Length

SH State 27 Length

SH State 28 Length

SH State 29 Length

SH State 30 Length

Page Register

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

A

B

C

D

E

F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

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Register Maps (continued)

Table 17. Register Summary Table (continued)

Default

(binary)

Page (dec)

Addr (dec)

Addr (hex)

Register Title

PAGE 4

4

0

1

0000 0000

SH State 0 PHI, RS, CP

SH State 1 PHI, RS, CP

SH State 2 PHI, RS, CP

SH State 3 PHI, RS, CP

SH State 4 PHI, RS, CP

SH State 5 PHI, RS, CP

SH State 6 PHI, RS, CP

SH State 7 PHI, RS, CP

SH State 8 PHI, RS, CP

SH State 9 PHI, RS, CP

SH State 10 PHI, RS, CP

SH State 11 PHI, RS, CP

SH State 12 PHI, RS, CP

SH State 13 PHI, RS, CP

SH State 14 PHI, RS, CP

SH State 15 PHI, RS, CP

SH State 16 PHI, RS, CP

SH State 17 PHI, RS, CP

SH State 18 PHI, RS, CP

SH State 19 PHI, RS, CP

SH State 20 PHI, RS, CP

SH State 21 PHI, RS, CP

SH State 22 PHI, RS, CP

SH State 23 PHI, RS, CP

SH State 24 PHI, RS, CP

SH State 25 PHI, RS, CP

SH State 26 PHI, RS, CP

SH State 27 PHI, RS, CP

SH State 28 PHI, RS, CP

SH State 29 PHI, RS, CP

SH State 30 PHI, RS, CP

Page Register

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

A

B

C

D

E

F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

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Register Maps (continued)

Table 17. Register Summary Table (continued)

Default

(binary)

Page (dec)

Addr (dec)

Addr (hex)

Register Title

PAGE 5

5

0

1

0000 0000

SH State 0 SH1-SH5

SH State 1 SH1-SH5

SH State 2 SH1-SH5

SH State 3 SH1-SH5

SH State 4 SH1-SH5

SH State 5 SH1-SH5

SH State 6 SH1-SH5

SH State 7 SH1-SH5

SH State 8 SH1-SH5

SH State 9 SH1-SH5

SH State 10 SH1-SH5

SH State 11 SH1-SH5

SH State 12 SH1-SH5

SH State 13 SH1-SH5

SH State 14 SH1-SH5

SH State 15 SH1-SH5

SH State 16 SH1-SH5

SH State 17 SH1-SH5

SH State 18 SH1-SH5

SH State 19 SH1-SH5

SH State 20 SH1-SH5

SH State 21 SH1-SH5

SH State 22 SH1-SH5

SH State 23 SH1-SH5

SH State 24 SH1-SH5

SH State 25 SH1-SH5

SH State 26 SH1-SH5

SH State 27 SH1-SH5

SH State 28 SH1-SH5

SH State 29 SH1-SH5

SH State 30 SH1-SH5

Page Register

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

A

B

C

D

E

F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

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Register Maps (continued)

Table 17. Register Summary Table (continued)

Default

(binary)

Page (dec)

Addr (dec)

Addr (hex)

Register Title

PAGE 6

6

0

1

0000 0000

PHIA0

PHIA1

PHIA2

PHIA3

PHIA4

PHIA5

PHIB0

PHIB1

PHIB2

PHIB3

PHIB4

PHIB5

PHIC0

PHIC1

PHIC2

PHIC3

PHIC4

PHIC5

RS0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

A

B

C

D

E

F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

RS1

RS2

RS3

RS4

RS5

CP0

CP1

CP2

CP3

CP4

CP5

HSPIX Rate Select

Page Register

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Register Maps (continued)

Table 17. Register Summary Table (continued)

Default

(binary)

Page (dec)

Addr (dec)

Addr (hex)

Register Title

PAGE 7

7

0

1

0000 0000

SH1 PIXEL ON MSB

SH1 PIXEL ON LSB

SH1 PIXEL OFF MSB

SH1 PIXEL OFF LSB

SH2 PIXEL ON MSB

SH2 PIXEL ON LSB

SH2 PIXEL OFF MSB

SH2 PIXEL OFF LSB

SH3 PIXEL ON MSB

SH3 PIXEL ON LSB

SH3 PIXEL OFF MSB

SH3 PIXEL OFF LSB

SH4 PIXEL ON MSB

SH4 PIXEL ON LSB

SH4 PIXEL OFF MSB

SH4 PIXEL OFF LSB

SH5 PIXEL ON MSB

SH5 PIXEL ON LSB

SH5 PIXEL OFF MSB

SH5 PIXEL OFF LSB

PHIA Polarity Override

PHIB Polarity Override

PHIC Polarity Override

RS Polarity Override

CP Polarity Override

SH1 Polarity Override

SH2 Polarity Override

SH3 Polarity Override

SH4 Polarity Override

SH5 Polarity Override

Reserved

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

A

B

C

D

E

F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

Page Register

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Register Maps (continued)

Table 17. Register Summary Table (continued)

Default

(binary)

Page (dec)

Addr (dec)

Addr (hex)

Register Title

PAGE 8

8

0

1

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

0000 0000

0010 0000

0000 0000

PHIA1, PHIA2 Polarity / State

PHIB1, PHIB2 Polarity / State

PHIC1, PHIC2 Polarity / State

RS, CP Polarity / State

SH1, SH2 Polarity / State

SH3, SH4 Polarity / State

SH5 Polarity / State

2

3

4

5

6

7

Reserved

8

LVDS Configuration

CB1/CB0 CB Mapping

CB3/CB2 CB Mapping

D2/CB4 CB Mapping

D4/D3 CB Mapping

9

10

11

12

13

14

D5 CB Mapping

Unlock State Output Values

PHIA, PHIB, PHIC, RS, CP

8

15

F

0000 0000

Unlock State Output Values

SH1, SH2, SH3, SH4, SH5

8

16 to 17

18

10 to 11

12

0000 0000

Reserved

Scrambler Inhibit 0 (LVDS[6:0])

Scrambler Inhibit 1 (LVDS[13:7])

Scrambler Inhibit 2 (LVDS[20:14])

Reserved

19

13

20

14

16 to 30

31

15 to 1E

1F

Page Register

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Table 18 describes all available registers in the LM98725 register bank, and their functions .

NOTE: Registers and/or Bits Marked in Boldface are Writeable when Register 0, Bit 0 = 1. All others are

“Locked".

Table 18. Register Definitions

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

PAGE 0

0

0010 0000

[7]

PLL Locked (READ ONLY) Status Bit

0 PLL is not locked

1 PLL is locked

[6]

[5]

Not Used

SH_R Capture Clock Select

0 Use internal CLK from XTAL source.

1 Use external INCLK source.

[4]

SH_R Capture Edge Select

0 Use rising edge of selected Clock source.

1 Use falling edge of selected Clock source.

[3]

[2]

Main

Not Used

Configuration 0

XTALEN

0 Use autodetecting CMOS/LVDS clock receiver

1 Enable crystal driver. INCLK+ is output, INCLK- is input.

[1]

[0]

Master Mode Select Bit

0 Slave/SH_R

1 Master/Line Length

Register Lock Control

0 Registers are unlocked (i.e. writeable) and

CCDTG state machines are stopped

1 Registers are locked (default) and CCDTG state machines are

operating

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

0

1

0100 0000

[7]

Serial Interface Mode Select

0 16+ Clock Mode [Default]

1 25+ Clock Mode

[6]

[5]

Enable PLL Range Autocalibration

0 PLL Range Autocal OFF

1 PLL Range Autocalibrates (Default)

Calibrate Gain/Offset (self clearing)

0 Calibration is off

1 Calibration is active

[4]

[3]

Main

Software Reset - FSM

Configuration 1 Set to 1 to reset all state machines. Self clearing.

Software Reset - FSM + Registers

Set to 1 to reset all state machines and registers. Self clearing.

Power Down CDS/SH Amplifier

[2]

[1]

[0]

Reference Buffer Power Down

Master Power Down

0 Master Power Down Disable

1 Master Power Down Enable

100

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

0

2

1100 0010

[7:6]

Mode Select Bits

11 Mode 3 (Default) (3 Channel Mode)

10 Mode 2 (2 Channel Mode)

01 Mode 1 (1 Channel Mode)

00 Not Used

[5:4]

Color Select Bits. Used to determine the inputs sampled during a scan.

11 Reserved

10 Mode 2 = OSR & OSB Mode 1 = OSB

01 Mode 2 = OSG & OSB Mode 1 = OSG

00 Mode 2 = OSR & OSG Mode 1 = OSR

Color Order. Configures the sequence of the pixel processing

0 Forward (default)

[3]

[2]

Main

Configuration 2 1 Reverse

PIXCLK/ADCCLK Configuration.

Selects appropriate multiplier for given input clock frequency

Mode 3: ADC Frequency = 3x Pixel Frequency

Mode 2: ADC Frequency = 2x Pixel Frequency

Mode 1: ADC Frequency = 1x Pixel Frequency

0 User supplies ADC rate clock, LM98725 performs no multiplication.

1 User supplies Pixel rate clock, LM98725 performs clock multiplication.

[1]

[0]

Sampling Mode Select

0 Sample and Hold Mode

1 Correlated Double Sampling Mode (Default)

Even/Odd CCD Sensor Enable

Dedicated Even and Odd DACs and Digital Offsets would be applied to

every other pixels.

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

[7]

REGISTER DESCRIPTION

0

3

1000 0010

Source Follower Enable.

0 Disable

1 Enable (Default)

[6]

[5]

Input Bias Enable. Enables the Input Bias Resistor ladder.

0 Disable (Default)

1 Enable

Bit CLP mode enable (black clamping done in reference portion of

every pixel of line)

0 Disabled (Default)

1 Enable

Main

[4:2] Configuration 3 Pixel Phase Clock Select. Coarse adjustment for Pixel phase

relative to INCLK. Useful in systems where Pixel inputs arrive with

significant delay relative to INCLK.

[1]

Sensor Polarity Select

0 Voltage increases with increasing white level

1 Voltage decreases with increasing white level

[0]

Reserved

102

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

[7]

REGISTER DESCRIPTION

0

4

0011 0000

Reserved

[6]

Enable VCLP Buffer

0 Use resistor divider voltages directly

1 Use buffered resistor divider voltage

[5]

[4]

Auto CLPIN Enable

0 Auto CLPIN Disabled

1 Auto CLPIN Enabled - (Default) - CLPIN generated according to Start

and End position settings at Page 2, Registers 0x06 and 0x07

CLPIN Gating Enable

0 Auto CLPIN not gated by the SAMPLE pulse timing

1 Auto CLPIN gated by the SAMPLE pulse timing

(Default)

[3]

Main

VCLP Power Down

Configuration 4 0 VCLP Normal Operation

1 No circuit is tied to the VCLP output and no current is drawn

[2:0]

VCLP Voltage Setting/Source

000 0.85V_A(Default)

001 0.9V_A

010 0.95V_A

011 0.6V_A

100 0.55V_A

101 0.4V_A

110 0.35V_A

111 0.15V_A

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

0

5

0000 0000

[7]

Output Format

0 LVDS (Default)

1 CMOS

[6]

[5]

Output Enable. Enables the Data Output pins.

0 Disabled (Default)

1 Enable

CMOS Data CLK Override Enable

0 - SH2 output as normal

1 - CMOS Data CLK on SH2

[4:3]

[2:1]

Data Scrambler Enable/Mode

00 - Scrambler Disabled

01, 10, 11 - Scrambler Enabled see 1:0 description below for details:

Data Scrambler Submode

Main

Configuration 5

If Scrambler Mode = 01, Full scrambler enabled as follows:

00 Send lvds_data[20:0]^prs[20:0]

01 Send prs[20:0]

10 Send lvds_data[20:0]^pprs[20:0]

11 Send pprs[20:0]

If Scrambler Mode = 10, 1 bit scrambler with key of prs[0]

Send lvds_data[20:0]^prs[0], with lvds_data[k] = 0

00 k = 0 (DBO in CMOS and 714 modes, CB0 in flexible, 16 bit mode)

01, txout0 disable = 0, k = 5 (DB0(lsb) in flexible, 16 bit mode)

01, txout0 disable = 1, k = 7 (DB2(lsb) in flexible, 14 bit mode)

10 k = 16 (CB0 in 714 mode)

11 k = 20 (CB4 in 714 mode)

If Scrambler Mode = 11, 1 bit scrambler with key of lvds_data[k].

Send lvds_data[20:0]^lvds_data[k], with lvds_out[k] = lvds_data[k]

00 k = 0 (DBO in CMOS and 714 modes, CB0 in flexible, 16 bit mode)

01, txout0 disable = 0, k = 5 (DB0(lsb) in flexible, 16 bit mode)

01, txout0 disable = 1, k = 7 (DB2(lsb) in flexible, 14 bit mode)

10 k = 16 (CB0 in 714 mode)

11 k = 20 (CB4 in 714 mode)

[0]

Reserved

104

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

0

6

0000 0000

[7]

LVDS Test Pattern Synchronization Select

0 Synchronizes at (held at initial state during) BOL & BOS

1 Synchronizes at (held at initial state during) BOS only

[6:4]

LVDS Output Pattern Select

000 Select AFE output (normal operation) (Must be 00 for AFE Test

Patterns)

001 Select 0x2A & 0x55 alternating patterns (all 3 pairs)

010 Selects 0x2A (all 3 pairs)

011 Selects 0x55 (all 3 pairs)

100 Selects 0x00 (all 4 pairs) (Differential 0 on all outputs)

101 Selects 0x7F (all 4 pairs) (Differential 1 on all outputs)

[3]

AFE Test Pattern - Up-count Rate Select

0 Up-count at pixel rate

Configuration 6 1 Up-count at BOL

[2:0]

Test Pattern - AFE Data Select - (Bits 6:4 must be 000 for AFE Test

Patterns)

000 Selects ADC output (normal operation)

001 Selects up-counter output

010 Selects 0xFF00 - fixed data

011 Selects 0xAA55 - fixed data

100 Selects 0x0000 - fixed data

101 Selects 0xFFFF - fixed data

110 Selects 0x00FF - fixed data

111 Selects 0x55AA - fixed data

Timing Generator Output Driver Strength

0

7

0000 0000

[5]

[4]

[3]

[2]

[1]

[0]

PHIA1, PHIA2 - 0 = Normal, 1 = High

PHIB1, PHIB2 - 0 = Normal, 1 = High

Configuration 7 PHIC1, PHIC2 - 0 = Normal, 1 = High

RS - 0 = Normal, 1 = High

CP - 0 = Normal, 1 = High

SH1, SH2, SH3, SH4, SH5 - 0 = Normal, 1 = High

0

8

0000 0000

0001 0000

0000 0000

0001 0000

0000 0000

0001 0000

0001 0110

[7:6]

[5:0]

[7:6]

[5:0]

[7:6]

[5:0]

[7:6]

[5:0]

[7:6]

[5:0]

[7:6]

[5:0]

[7:6]

[5:0]

OSR CLAMP Not Used

Start Edge

CLAMP_R Start Edge - Default = 0d

9

OSR CLAMP Not Used

Stop Edge

CLAMP_R Stop Edge - Default = 16d

10

11

12

13

14

A

B

C

D

E

OSG CLAMP Not Used

Start Edge

CLAMP_G Start Edge - Default = 0d

OSG CLAMP Not Used

Stop Edge

CLAMP_G Stop Edge - Default = 16d

OSB CLAMP Not Used

Start Edge

CLAMP_B Start Edge - Default = 0d

OSB CLAMP Not Used

Stop Edge

CLAMP_B Stop Edge - Default = 16d

OSR SAMPLE Not Used

Start Edge

SAMPLE_R Start Edge - Default = 22d

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

0

15

16

17

18

19

F

0010 0110

0001 0110

0010 0110

0001 0110

0010 0110

[7:6]

[5:0]

[7:6]

[5:0]

[7:6]

[5:0]

[7:6]

[5:0]

[7:6]

OSR SAMPLE Not Used

Stop Edge

SAMPLE_R Stop Edge - Default = 38d

10

11

12

13

OSG SAMPLE Not Used

Start Edge

SAMPLE_G Start Edge - Default = 22d

OSG SAMPLE Not Used

Stop Edge

SAMPLE_G Stop Edge - Default = 38d

OSB SAMPLE Not Used

Start Edge

SAMPLE_B Start Edge - Default = 22d

OSB SAMPLE Not Used

[5:0]

Stop Edge

SAMPLE_B Stop Edge - Default = 38d

Not Used

0

20

14

0000 0000

[7]

[6]

SH_R Capture Monitor Override

0 SAMPB=SAMPB, CLAMPB=CLAMPB - Default

1 SAMPB = INCLK, CLAMPB = SH_R

[5:3]

Selection bits for RS (user test mode)

000 Normal output

001 SAMPR Output

010 SAMPG Output

Sample &

Clamp

011 SAMPB Output

100 CLAMPR Output

101 CLAMPG Output

110 CLAMPB Output

111 PIXPHASE Output

Monitor 0

[2:0]

Selection bits for CP (user test mode)

000 Normal output

001 SAMPR Output

010 SAMPG Output

011 SAMPB Output

100 CLAMPR Output

101 CLAMPG Output

110 CLAMPB Output

111 PIXPHASE Output

106

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

[7:6]

[5:3]

REGISTER DESCRIPTION

0

21

15

0000 0000

Not Used

Selection bits for SH2 (user test mode)

000 Normal output

001 SAMPR Output

010 SAMPG Output

011 SAMPB Output

100 CLAMPR Output

101 CLAMPG Output

110 CLAMPB Output

111 PIXPHASE Output

Sample &

Clamp

Monitor 1

[2:0]

Selection bits for SH3 (user test mode)

000 Normal output

001 SAMPR Output

010 SAMPG Output

011 SAMPB Output

100 CLAMPR Output

101 CLAMPG Output

110 CLAMPB Output

111 PIXPHASE Output

0

22 to

29

16 to

1D

0000 0000

Reserved

Revision

0

30

31

1E

1F

XX00 0011

0000 0000

[7:0]

[3:0]

Used to select desired page of registers being accessed

0000 Page 0

0001 Page 1

0010 Page 2

0011 Page 3

0100 Page 4

0101 Page 5

0110 Page 6

0111 Page 7

1000 Page 8

Page

Register

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

PAGE 1

1

0

0000 0000

[7]

[6]

[5]

CDS/SH Gain Blue - 0 = 1x Gain, 1 = 2x Gain

CDS/SH Gain Green - 0 = 1x Gain, 1 = 2x Gain

CDS/SH Gain Blue - 0 = 1x Gain, 1 = 2x Gain

[4:3]

[2]

Not used

Individual CDS/SH Gain Enable

0 Use Bit 0 for CDS/SH Gain

1 Use Bits 7:5 for CDS/SH Gains

Gain Mode

[1]

Dual Gain Mode Enable

0 Single Gain Setting Within Each Line

1 Two Gain Settings Within Each Line

[0]

Gain Select

0 1x CDS/SH Gain - Default

1 2x CDS/SH Gain

1

2

3

4

1

2

3

4

0110 0001

1000 0000

[7:0]

Red PGA

Green PGA

Blue PGA

Red Even

DAC MSB

Red Even

DAC LSB

Default = 97d for Gain = 1

DAC[9:2]

1

5

0000 0000

[7:2]

Not Used

[1:0]

[7:0]

DAC[1:0]

DAC[9:2]

1

6

7

6

7

1000 0000

0000 0000

Green Even

DAC MSB

Green Even

DAC LSB

[7:2]

Not Used

[1:0]

[7:0]

DAC[1:0]

DAC[9:2]

1

8

9

8

9

1000 0000

0000 0000

Blue Even

DAC MSB

Blue Even

DAC LSB

[7:2]

Not Used

[1:0]

[7:0]

DAC[1:0]

DAC[9:2]

1

10

11

A

B

1000 0000

0000 0000

Red Odd

DAC MSB

Red Odd

DAC LSB

[7:2]

Not Used

[1:0]

[7:0]

DAC[1:0]

DAC[9:2]

1

12

13

C

D

1000 0000

0000 0000

Green Odd

DAC MSB

[7:2]

Not Used

Green Odd

DAC LSB

Blue Odd

DAC MSB

[1:0]

[7:0]

DAC[1:0]

DAC[9:2]

1

14

E

1000 0000

108

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

[7:2]

REGISTER DESCRIPTION

1

15

16

17

18

19

20

21

22

F

0000 0000

0100 0000

0110 0001

Blue Odd

DAC LSB

Not Used

[1:0]

[7]

DAC[1:0]

Not Used

10

11

12

13

14

15

16

Red Even

Digital

[6:0]

[7]

Offset

Digital Offset

Not Used

Green Even

Digital

[6:0]

[7]

Offset

Digital Offset

Not Used

Blue Even

Digital

[6:0]

[7]

Offset

Digital Offset

Not Used

Red Odd

Digital Offset

[6:0]

[7]

Digital Offset

Not Used

Green Odd

Digital

Offset

[6:0]

[7]

Digital Offset

Not Used

Blue Odd

Digital

Offset

[6:0]

[7:0]

Digital Offset

Red

PGA setting during high gain portion of line

when dual gain mode is enabled

High

Gain

PGA

Default = 97d for Gain = 1

1

23

24

28

17

18

1C

0110 0001

0100 0000

[7:0]

[7]

Green High

PGA setting during high gain portion of line when dual gain mode is

enabled

Gain PGA

Blue High

Default = 97d for Gain = 1

PGA setting during high gain portion of line when dual gain mode is

enabled

Gain PGA

Red

Default = 97d for Gain = 1

Not Used

Channel

Bimodal

Green

[6:0]

[7]

Offset Binary Digital Offset for Bimodal Correction

Not Used

1

29

30

31

1D

1E

1F

0100 0000

0000 0000

Channel

Bimodal

Blue

[6:0]

[7]

Offset Binary Digital Offset for Bimodal Correction

Not Used

Channel

Bimodal

Page

[6:0]

[3:0]

Offset Binary Digital Offset for Bimodal Correction

Used to select desired page of registers being accessed.

Register

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

PAGE 2

2

0

0000 0000

[7:3]

[2]

Not Used

DDAC Disable

0 AFE output includes DDAC (digital DAC offset)

correction

1 AFE output does not include DDAC correction

Calibration

Mode

[1:0]

Calibration Mode

00 Black Calibration Only

01 White and Black Calibration - Full/Binary White Cal

10 White and Black Calibration - Fine Tuning

11 Reserved

2

1

2

1

2

0000 0000

0001 0100

[7:0]

[5:4]

Calibration is active for this number of lines

Calibration # 0 Reserved

Lines

1d to 254d sets number of lines

255d sets infinite calibration

DDAC Scaling

00 Linear - 1 LSB adjust

01 Scaling = 1/2

10 Scaling = 1/4

11 Scaling = 1/8

[3:2]

[1:0]

ADAC Scaling

00 Reserved (No scaling)

01 Scaling = 1/2

10 Scaling = 1/4

11 Scaling = 1/8

Black Cal

Config

Number of Black Pixels

Number of pixels averaged by Black Loop

00 4 pixels

01 8 pixels

10 16 pixels

11 32 pixels

2

3

0100 0000

[7:0]

Black Target Target level for Black calibration.

Range is 0 to 255 at 11 bit level or 0 to 8160 at 16 bit level

(default = 64 or 2048 at 16 bit level)

110

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

2

4

0100 0011

[6:3]

White Loop Tolerance

White Cal success if |White Peak - White Target| < White Loop

Tolerance

0 to 15 at 10 bit level - Default = 8

Number of White Pixels

[2:0]

Number of White Pixels processed in moving window average to find

White Peak in line between White Pixels Start and White Pixels End

White Cal

Config

000 4 pixels

001 8 pixels

010 16 pixels

011 32 pixels - Default

White Target

2

5

1000 0000

[7:0]

White Target = 768d + [7:0] at 10 bit level

White Target Range is 768d to 1023d at 10 bit level or 49152 to

65472 at 16 bit level

(Default = 896d or 57344 at 16 bit level)

2

6

7

8

6

7

8

0000 0100

0000 1100

0001 0000

[7:0]

AutoCLPIN

Start

# of pixels from SH interval End to Start of Black Pixel

Clamping (Default = 4d)

AutoCLPIN

End

# of pixels from SH interval End to End of Black Pixel

Clamping (Default = 12d)

Black Loop

Start

# of pixels from SH interval End to Start of Black Loop

Pixels (Default = 16d)

2

9

0000 0000

0001 0100

0001 0000

0000 0000

[7:0]

Active/White # of Pixels between SH Interval End and first Valid

Pixels Start -

Data Pixel (Default = 64d)

MSB

10

11

12

A

B

C

Active/White

Pixels Start -

LSB

Active/White # of Pixels between SH Interval End and last Valid Data

Pixels End -

Pixel (Default = 4096)

MSB

Active/White

Pixels End -

LSB

2

13

14

D

E

0001 0000

0100 0000

[7:0]

Line Length

MSB

# of Pixel Periods between beginning of consecutive SH Intervals

(Default = 4160)

Line Length

LSB

# of Pixel Periods between beginning of consecutive SH Intervals

2

15

F

0000 0000

[7:2]

[1:0]

Not Used

Multiplier factor for Active/White, LSPIX ON/OFF and

Line Length

Multiplier

Line Length Pixels Register Settings

00 1x

01 2x

10 4x

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

[7]

REGISTER DESCRIPTION

2

16

10

0000 0000

Not Used

CIS - 2 Color Coefficient Select

6:5

Select which color PGA/DAC coefficients are used in 2 color CIS

sequences

00 Red and Green Lamp/Coefficients Used

01 Green and Blue Lamp/Coefficients Used

10 Red and Blue Lamp/Coefficients Used

11 Reserved

4:3

CCD/CIS Mode Select

00 Normal CCD Timing

01 CISa (2, 3, or 4 color sequences)

10 CISb (2 or 3 color sequences)

11 Reserved

Line Mode

[1:0]

# SH Intervals. How many different SH intervals in a sequence of lines

00 1 SH Interval - Same SH timing every line

01 2 SH Intervals - 2 different SH interval timings

10 3 SH Intervals - 3 different SH interval timings

11 4 SH Intervals - 4 different SH interval timings

SH States are allocated as follows:

1 Interval 1 = 0 to 30

2 Interval 1 = 0 to 14, Interval 2 = 15 to 30

3 Int 1 = 0 to 9, Int 2 = 10 to 19, Int 3 = 20 to 30

4 Int 1 = 0 to 6, Int 2 = 7 to 14, Int 3 = 15 to 22, Int 4 =23 to 30

Not Used

2

17

11

0000 0000

[7:3]

[2:0]

SH State Length values are multiplied by this factor

000 SH Timings x1

SH State

Length

001 SH Timings x2

Multiplier

010 SH Timings x4

011 SH Timings x8

100 SH Timings x16

101 to 111 Reserved

112

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

[7:6]

[5]

REGISTER DESCRIPTION

2

18

12

0000 0000

Not Used

PHIA On Delay

0 Normal

1 PHIA begins 1 pixel period late

[4]

[3]

PHIA Off Delay

0 Normal

1 PHIA stops 1 pixel period late

PHIB On Delay

0 Normal

1 PHIB begins 1 pixel period late

PHIA/B/C

Delays

[2]

[1]

[0]

PHIB Off Delay

0 Normal

1 PHIB stops 1 pixel period late

PHIC On Delay

0 Normal

1 PHIC begins 1 pixel period late

PHIC Off Delay

0 Normal

1 PHIC stops 1 pixel period late

Not Used

2

19

13

0000 0000

[7:4]

[3]

RS On Delay

0 Normal

1 RS begins 1 pixel period late

[2]

[1]

[0]

RS Off Delay

0 Normal

RS/CP Delays 1 RS stops 1 pixel period late

CP On Delay

0 Normal

1 CP begins 1 pixel period late

CP Off Delay

0 Normal

1 CP stops 1 pixel period late

Reserved

2

20 to

23

14 to

17

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

2

24

18

1111 1000

[7:5]

Master PLL Range Setting for PLL1 and PLL2 when

Autorange is off. Set to 111.

[4:3]

[2:0]

[7:5]

[4:3]

PLL1 Charge Pump Current Control

PLL Control 1 Default = 11

PLL1 Filter Bandwidth Control

Default = 000

2

25

19

0001 1000

Reserved

Default = 000

PLL2 Charge Pump Current Control

Default = 11

PLL Control 2 Set to 00 when using SSCG.

[2:0]

[7:6]

PLL2 Filter Bandwidth Control

Default = 000

Set to 111 when using SSCG.

Spread Rate Multiplier

2

26

1A

0000 0000

(Increases modulation frequency in low pixel frequency applications)

00 1x - Default

01 2x

10 4x (Page 2, Register D,E max = 32,768)

11 Reserved

[5]

SSCG Spread Boost

0 Normal, PLL divide step is 1/28

1 Boost, PLL divide step is 1/56. Narrower and cleaner spread for 1ch

and 2ch modes, but limits max pixel freq to 25 MHz.

[4]

SSCG Spread Gain

0 Spread widths as specified in [3:2]

1 Spread widths are 2x [3:2] settings

[3:2]

SSCG Spread Width (Fmod = Fcenter+/- Width/2)

SSCG Control 00 5%

1

01 2.5%

10 1.25%

11 0.625%

[1]

[0]

SSCG SH Sync Enable

0 Spread unsynched, once SSCG Enable is set, SSCG wil begin

immediately.

1 Spread synched to SH interval, once SSCG Enable

is set, the SSCG will begin at the first SH Interval.

SSCG Enable

0 Spread Disabled

1 Spread Enabled

114

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

2

27

1B

0000 0010

[7]

Load SSCG state machine

(SSCG Enable 0->1 also performs this function)

0 Normal

1 Load state machine (self clearing)

[6]

FIFO Reset at SH_R

0 FIFO is only reset when SSCG started

1 FIFO is reset at SH_R. Only useful in Slave Mode with Spread LVDS

Only set. Ensures that FIFO counters are centered if SH_R period is

consistenly shorter or longer than Line Length settings.

[5]

[4]

Spread Waveform Reset at SH_R

0 Spread waveform not reset by SH_R

1 Spread waveform reset by SH_R

Override PLL2 Lock Detector

0 PLL2 Lock Detector Normal

1 Force PLL2 Lock Detect = 1. Set to 1 when using

SSCG.

[3]

SSCG Control Override PLL1 Lock Detector

2

0 PLL1 Lock Detector Normal

1 Force PLL1 Lock Detect = 1. Useful only if using a large multiplication

factor and a lot of jitter is present in the source clock.

[2]

Spread MaxRate

0 Spread Normal

1 Force Spreading to highest modulation frequency instead of tied to

Line Length Setting.

[1:0]

PLL Mode Select

11 Spread All System Clocks, No Multiplication

10 PLLs and SSCG Disabled - Default

01 Spread All System Clocks, Multiplication Enabled

00 Spread Output Clocks Only, Mutiplication Enabled

Clock Mult M Multiplying PLL. Fout = Fin x M/N M = mmmmmmmm + 1 (1 to 256)

2

28

29

30

1C

1D

1E

0000 0000

Clock Mult N Multiplying PLL. Fout = Fin x M/N N = nnnnnnnn + 1 (1 to 256)

[7]

FIFO Reset

0 FIFO normal operating

1 Force reset of FIFO (self clearing)

[6:0]

SSCG Control FIFO and Spread Waveform SH_R Reset Holdoff

3

Delay reset of FIFO and Spread Waveform from 0 to

127 ADC clock cycles after the internal synchronized SH_R. To allow

this event to occur during SH Interval after all valid pixels in the pipeline

have been processed.

2

31

1F

[3:0]

Page Register

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

PAGE 3

3

0

0000 0000

[7:0]

SH State 0

Length

Sets length of this SH interval state

1

SH State 1

Length

2

SH State 2

Length

3

SH State 3

Length

4

SH State 4

Length

5

SH State 5

Length

6

SH State 6

Length

7

SH State 7

Length

8

SH State 8

Length

9

SH State 9

Length

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

A

SH State 10

Length

B

SH State 11

Length

C

SH State 12

Length

D

SH State 13

Length

E

SH State 14

Length

F

SH State 15

Length

10

11

12

13

14

15

16

17

18

19

1A

SH State 16

Length

SH State 17

Length

SH State 18

Length

SH State 19

Length

SH State 20

Length

SH State 21

Length

SH State 22

Length

SH State 23

Length

SH State 24

Length

SH State 25

Length

SH State 26

Length

116

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

Sets length of this SH interval state

3

27

28

29

30

31

1B

1C

1D

1E

1F

0000 0000

[7:0]

SH State 27

Length

[7:0]

[3:0]

SH State 28

Length

Sets length of this SH interval state

SH State 29

Length

SH State 30

Length

Page Register

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

PAGE 4

4

0

0000 0000

Controls whether these outputs are 1 or 0 during this

SH interval state

[7]

[6]

RS 0 = Low, 1 = High 1 0 = Low, 1 = High

CP 0 = Low, 1 = High

[5]

SH State 0

PHIA2 0 = Low, 1 = High

[4]

PHI, RS, CP

PHIA1 0 = Low, 1 = High

[3]

PHIB2 0 = Low, 1 = High

[2]

PHIB1 0 = Low, 1 = High

[1]

PHIC2 0 = Low, 1 = High

[0]

PHIC1 0 = Low, 1 = High

4

1

0000 0000

[7:0]

SH State 1

PHI, RS, CP

Controls whether these outputs are 1 or 0 during this SH interval state

2

[7:0]

SH State 2

PHI, RS, CP

3

SH State 3

PHI, RS, CP

4

SH State 4

PHI, RS, CP

5

SH State 5

PHI, RS, CP

6

SH State 6

PHI, RS, CP

7

SH State 7

PHI, RS, CP

8

SH State 8

PHI, RS, CP

9

SH State 9

PHI, RS, CP

10

11

12

13

14

15

16

17

18

19

20

21

A

SH State 10

PHI, RS, CP

B

SH State 11

PHI, RS, CP

C

D

E

SH State 12

PHI, RS, CP

SH State 13

PHI, RS, CP

SH State 14

PHI, RS, CP

F

SH State 15

PHI, RS, CP

10

11

12

13

14

15

SH State 16

PHI, RS, CP

SH State 17

PHI, RS, CP

SH State 18

PHI, RS, CP

SH State 19

PHI, RS, CP

SH State 20

PHI, RS, CP

SH State 21

PHI, RS, CP

118

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

4

22

23

24

25

26

27

28

29

30

31

16

17

18

19

1A

1B

1C

1D

1E

1F

0000 0000

[7:0]

SH State 22

PHI, RS, CP

Controls whether these outputs are 1 or 0 during this SH interval state

[7:0]

[3:0]

SH State 23

PHI, RS, CP

Controls whether these outputs are 1 or 0 during this SH interval state

SH State 24

PHI, RS, CP

SH State 25

PHI, RS, CP

SH State 26

PHI, RS, CP

SH State 27

PHI, RS, CP

SH State 28

PHI, RS, CP

SH State 29

PHI, RS, CP

SH State 30

PHI, RS, CP

Page Register

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

PAGE 5

5

0

0000 0000

[7:5]

Not Used

Controls whether these outputs are 1 or 0 during this

SH interval state

[4]

[3]

SH State 0

SH1-SH5

SH5 0 = Low, 1 = High

SH4 0 = Low, 1 = High

[2]

SH3 0 = Low, 1 = High

[1]

SH2 0 = Low, 1 = High

[0]

SH1 0 = Low, 1 = High

5

1

0000 0000

[4:0]

SH State 1

SH1-SH5

Controls whether these outputs are 1 or 0 during this SH interval state

2

[4:0]

SH State 2

SH1-SH5

3

SH State 3

SH1-SH5

4

SH State 4

SH1-SH5

5

SH State 5

SH1-SH5

6

SH State 6

SH1-SH5

7

SH State 7

SH1-SH5

8

SH State 8

SH1-SH5

9

SH State 9

SH1-SH5

10

11

12

13

14

15

16

17

18

19

20

21

22

A

SH State 10

SH1-SH5

B

SH State 11

SH1-SH5

C

D

E

SH State 12

SH1-SH5

SH State 13

SH1-SH5

SH State 14

SH1-SH5

F

SH State 15

SH1-SH5

10

11

12

13

14

15

16

SH State 16

SH1-SH5

SH State 17

SH1-SH5

SH State 18

SH1-SH5

SH State 19

SH1-SH5

SH State 20

SH1-SH5

SH State 21

SH1-SH5

SH State 22

SH1-SH5

120

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

5

23

24

25

26

27

28

29

30

31

17

18

19

1A

1B

1C

1D

1E

1F

0000 0000

[4:0]

SH State 23

SH1-SH5

Controls whether these outputs are 1 or 0 during this SH interval state

[4:0]

[3:0]

SH State 24

SH1-SH5

Controls whether these outputs are 1 or 0 during this SH interval state

SH State 25

SH1-SH5

SH State 26

SH1-SH5

SH State 27

SH1-SH5

SH State 28

SH1-SH5

SH State 29

SH1-SH5

SH State 30

SH1-SH5

Page Register

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

PAGE 6

6

0

0000 0000

[1:0]

[7:0]

[1:0]

[7:0]

[1:0]

[7:0]

[1:0]

[7:0]

[1:0]

[7:0]

[7:5]

PHIA0

PHIA1

PHIA2

PHIA3

PHIA4

PHIA5

PHIB0

PHIB1

PHIB2

PHIB3

PHIB4

PHIB5

PHIC0

PHIC1

PHIC2

PHIC3

PHIC4

PHIC5

RS0

Upper 2 MSb (first shifted out of HSTG)

1

Next 8

2

Next 8

3

Next 8

4

Next 8

5

Lower 8 LSb (last shifted out of HSTG)

6

Upper 2 MSb (first shifted out of HSTG)

7

Next 8

8

Next 8

9

Next 8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

A

Next 8

B

Lower 8 LSb (last shifted out of HSTG)

C

Upper 2 MSb (first shifted out of HSTG)

D

Next 8

E

Next 8

F

Next 8

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

Next 8

Lower 8 LSb (last shifted out of HSTG)

Upper 2 MSb (first shifted out of HSTG)

RS1

Next 8

RS2

Next 8

RS3

Next 8

RS4

Next 8

RS5

Lower 8 LSb (last shifted out of HSTG)

CP0

Upper 2 MSb (first shifted out of HSTG)

CP1

Next 8

CP2

Next 8

CP3

Next 8

CP4

Next 8

CP5

Lower 8 LSb (last shifted out of HSTG)

Not Used

Allows high speed generators to operate at 1/2 normal rate. So the full

sequence will be clocked out over 2 pixels instead of 1 pixel

[4]

[3]

PHIA 0 = Normal Rate, 1 = 1/2

HSPIX Rate

Select

Rate PHIB 0 = Normal Rate, 1 = 1/2

Rate PHIC 0 = Normal Rate, 1 = 1/2

Rate RS 0 = Normal Rate, 1 = 1/2

Rate CP 0 = Normal Rate, 1 = 1/2 Rate

[2]

[1]

[0]

6

31

1F

[3:0]

Page Register

122

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

PAGE 7

SH1

PIXEL ON

MSB

MSB of Pixel count where this signal goes low to high

Range is 0 to 65535

7

0

0000 0000

[7:0]

SH1

PIXEL ON

LSB

LSB of Pixel count where this signal goes low to high

1

SH1

PIXEL OFF

MSB

MSB of Pixel count where this signal goes high to low

Range is 0 to 65535

2

SH1

PIXEL OFF

LSB

LSB of Pixel count where this signal goes high to low

3

SH2

PIXEL ON

MSB

MSB of Pixel count where this signal goes low to high

Range is 0 to 65535

4

SH2

PIXEL ON

LSB

LSB of Pixel count where this signal goes low to high

5

SH2

PIXEL OFF

MSB

MSB of Pixel count where this signal goes high to low

Range is 0 to 65535

6

SH2

PIXEL OFF

LSB

LSB of Pixel count where this signal goes high to low

7

SH3

PIXEL ON

MSB

MSB of Pixel count where this signal goes low to high

Range is 0 to 65535

8

SH3

PIXEL ON

LSB

LSB of Pixel count where this signal goes low to high

9

SH3

PIXEL OFF

MSB

MSB of Pixel count where this signal goes high to low

Range is 0 to 65535

10

11

12

13

14

15

16

17

18

A

B

C

D

E

F

SH3

PIXEL OFF

LSB

LSB of Pixel count where this signal goes high to low

SH4

PIXEL ON

MSB

MSB of Pixel count where this signal goes low to high

Range is 0 to 65535

SH4

PIXEL ON

LSB

LSB of Pixel count where this signal goes low to high

SH4

PIXEL OFF

MSB

MSB of Pixel count where this signal goes high to low

Range is 0 to 65535

SH4

PIXEL OFF

LSB

LSB of Pixel count where this signal goes high to low

SH5

PIXEL ON

MSB

MSB of Pixel count where this signal goes low to high

Range is 0 to 65535

10

11

12

SH5

PIXEL ON

LSB

LSB of Pixel count where this signal goes low to high

SH5

PIXEL OFF

MSB

MSB of Pixel count where this signal goes high to low

Range is 0 to 65535

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

SH5

PIXEL OFF

LSB

LSB of Pixel count where this signal goes high to low

7

19

20

13

14

0000 0000

[7:0]

[7:4]

[3]

Not Used

Polarity Override Line 3

0 Signal Not Inverted

PHIA Polarity 1 Signal Inverted

Override Polarity Override Line 2

[2]

[1]

Polarity Override Line 1

[0]

Polarity Override Line 0

Not Used

7

21

22

23

24

15

16

17

18

0000 0000

[7:4]

[3]

Polarity Override Line 3

0 Signal Not Inverted

PHIB Polarity 1 Signal Inverted

Override Polarity Override Line 2

[2]

[1]

Polarity Override Line 1

[0]

Polarity Override Line 0

Not Used

[7:4]

[3]

Polarity Override Line 3

0 Signal Not Inverted

PHIC Polarity 1 Signal Inverted

[2]

[1]

Override

Polarity Override Line 2

Polarity Override Line 1

[0]

Polarity Override Line 0

Not Used

[7:4]

[3]

Polarity Override Line 3

0 Signal Not Inverted

1 Signal Inverted

RS Polarity

Override

[2]

[1]

Polarity Override Line 2

Polarity Override Line 1

[0]

Polarity Override Line 0

Not Used

[7:4]

[3]

Polarity Override Line 3

0 Signal Not Inverted

1 Signal Inverted

CP Polarity

Override

[2]

[1]

[0]

Polarity Override Line 2

Polarity Override Line 1

Polarity Override Line 0

124

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

[7:4]

[3]

REGISTER DESCRIPTION

7

25

26

27

28

29

19

1A

1B

1C

1D

0000 0000

Not Used

Polarity Override Line 3

0 Signal Not Inverted

1 Signal Inverted

SH1 Polarity

Override

[2]

[1]

Polarity Override Line 2

Polarity Override Line 1

[0]

Polarity Override Line 0

Not Used

[7:4]

[3]

Polarity Override Line 3

0 Signal Not Inverted

1 Signal Inverted

SH2 Polarity

Override

[2]

[1]

Polarity Override Line 2

Polarity Override Line 1

[0]

Polarity Override Line 0

Not Used

[7:4]

[3]

Polarity Override Line 3

0 Signal Not Inverted

1 Signal Inverted

SH3 Polarity

Override

[2]

[1]

Polarity Override Line 2

Polarity Override Line 1

[0]

Polarity Override Line 0

Not Used

[7:4]

[3]

Polarity Override Line 3

0 Signal Not Inverted

1 Signal Inverted

SH4 Polarity

Override

[2]

[1]

Polarity Override Line 2

Polarity Override Line 1

[0]

Polarity Override Line 0

Not Used

[7:4]

[3]

Polarity Override Line 3

0 Signal Not Inverted

1 Signal Inverted

SH5 Polarity

Override

[2]

[1]

[0]

Polarity Override Line 2

Polarity Override Line 1

Polarity Override Line 0

7

30

31

1E

1F

Reserved

[3:0]

Page Register

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

PAGE 8

8

0

1

2

0

1

2

0000 0000

[7]

[6]

[5]

[4]

Not Used

PHIA1 Active (0 = Tristate, 1* = Active)

PHIA1 Source (0* = Timing, 1 = DC logic 1)

PHIA1 Polarity (0* = Not Inverted, 1 = Inverted)

PHIA1,

PHIA2,

Polarity /

State

[3]

Not Used

[2]

[1]

PHIA2 Active (0 = Tristate, 1* = Active)

PHIA2 Source (0* = Timing, 1 = DC logic 1)

[0]

[7]

PHIA2 Polarity (0* = Not Inverted, 1 = Inverted)

Not Used

[6]

[5]

[4]

PHIB1 Active (0 = Tristate, 1* = Active) PHIB1

Source (0* = Timing, 1 = DC logic 1) PHIB1

Polarity (0* = Not Inverted, 1 = Inverted)

PHIB1,

PHIB2,

Polarity /

State

[3]

Not Used

[2]

[1]

PHIB2 Active (0 = Tristate, 1* = Active)

PHIB2 Source (0* = Timing, 1 = DC logic 1)

[0]

[7]

PHIB2 Polarity (0* = Not Inverted, 1 = Inverted)

Not Used

[6]

[5]

[4]

PHIC1 Active (0 = Tristate, 1* = Active)

PHIC1 Source (0* = Timing, 1 = DC logic 1)

PHIC1 Polarity (0* = Not Inverted, 1 = Inverted)

PHIC1

PHIC2

[3]

Polarity /

State

Not Used

[2]

[1]

[0]

PHIC2 Active (0 = Tristate, 1* = Active)

PHIC2 Source (0* = Timing, 1 = DC logic 1)

PHIC2 Polarity (0* = Not Inverted, 1 = Inverted)

126

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

[7]

REGISTER DESCRIPTION

8

3

0000 0000

Not Used

[6]

RS Active (0 = Tristate, 1* = Active)

[5]

RS Source (0* = Timing, 1 = DC logic 1)

RS Polarity (0* = Not Inverted, 1 = Inverted)

[4]

RS, CP

Polarity /

State

[3]

Not Used

[2]

[1]

CP Active (0 = Tristate, 1* = Active)

CP Source (0* = Timing, 1 = DC logic 1)

[0]

[7]

CP Polarity (0* = Not Inverted, 1 = Inverted)

Not Used

8

4

0000 0000

[6]

[5]

[4]

SH1 Active (0 = Tristate, 1* = Active)

SH1 Source (0* = Timing, 1 = DC logic 1)

SH1 Polarity (0* = Not Inverted, 1 = Inverted)

SH1, SH2

Polarity /

State

[3]

[2]

[1]

Not Used

SH2 Active (0 = Tristate, 1* = Active)

SH2 Source (0* = Timing, 1 = DC logic 1)

[0]

[7]

SH2 Polarity (0* = Not Inverted, 1 = Inverted)

Not Used

8

5

0000 0000

[6]

[5]

[4]

SH3 Active (0 = Tristate, 1* = Active)

SH3 Source (0* = Timing, 1 = DC logic 1)

SH3 Polarity (0* = Not Inverted, 1 = Inverted)

SH3, SH4

Polarity /

State

[3]

[2]

[1]

Not Used

SH4 Active (0 = Tristate, 1* = Active)

SH4 Source (0* = Timing, 1 = DC logic 1)

[0]

[7]

SH4 Polarity (0* = Not Inverted, 1 = Inverted)

Not Used

8

6

0000 0000

[6]

[5]

[4]

SH5 Active (0 = Tristate, 1* = Active)

SH5

Polarity /

State

SH5 Source (0* = Timing, 1 = DC logic 1)

SH5 Polarity (0* = Not Inverted, 1 = Inverted)

Not Used

[3:0]

[7:0]

8

7

0000 0000

Reserved

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

8

0010 0000

[7]

LVDS TXCLK Disable

0 LVDS TXCLK Enabled - Default

1 LVDS TXCLK Disabled

[6]

CMOS CLKOUT Disable

0 CMOS CLKOUT Enabled - Default

1 CMOS CLKOUT Disabled

[5:4]

LVDS Drive Adjust

00 Reduce 100mV

01 Reduce 50 mV

10 Default

11 Increase 50 mV

[3]

[2]

[1]

[0]

LVDS

LVDS TXCLK Delay

Configuration 0 TXCLK timing normal

1 TXCLK delayed

BOL CB Bit Latency

0 Normal Compensation

1 No latency compensation

LVDS Disable TXOUT0

0 TXOUT0 LVDS Pair Enabled

1 TXOUT0 LVDS Pair Disabled

LVDS Mode Select

0 LM98714

1 Flexible CB Mapping

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

8

9

0000 0000

Selects CB Bit Mapping

CB1 Mapping

[7:4]

0000 CBO1 from LM98714 definition

0001 CBO0 from LM98714 definition

0010 CBO1 from LM98714 definition

0011 CBO2 from LM98714 definition

0100 CBO3 from LM98714 definition

0101 CBO4 from LM98714 definition

0110 R - High for a red channel pixel

0111 G - High for a green channel pixel

1000 B - High for a blue channel pixel

1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if TXOUT0 disabled

1010 Ping - High for pixels processed by the Ping section of a channel,

low for Pong

1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in multiline sequences

1100 Line#msb

1101 Black Loop Pixels - High for pixels processed by the Black Loop

1110 ActiveWhite Loop Pixels - High for pixels processed by the White

Loop

1111 CLP Pixels - High for pixels where the input CLP switch is closed

CB1/CB0 CB

Mapping

[3:0]

CB0 Mapping

0000 CBO0 from LM98714 definition

0001 CBO0 from LM98714 definition

0010 CBO1 from LM98714 definition

0011 CBO2 from LM98714 definition

0100 CBO3 from LM98714 definition

0101 CBO4 from LM98714 definition

0110 R - High for a red channel pixel

0111 G - High for a green channel pixel

1000 B - High for a blue channel pixel

1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if TXOUT0 disabled

1010 Ping - High for pixels processed by the Ping section of a channel,

low for Pong

1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in multiline sequences

1100 Line#msb

1101 Black Loop Pixels - High for pixels processed by the Black Loop

1110 ActiveWhite Loop Pixels - High for pixels processed by the White

Loop

1111 CLP Pixels - High for pixels where the input CLP switch is closed

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

8

10

A

0000 0000

Selects CB Bit Mapping

CB3 Mapping

[7:4]

0000 CBO30 from LM98714 definition

0001 CBO0 from LM98714 definition

0010 CBO1 from LM98714 definition

0011 CBO2 from LM98714 definition

0100 CBO3 from LM98714 definition

0101 CBO4 from LM98714 definition

0110 R - High for a red channel pixel

0111 G - High for a green channel pixel

1000 B - High for a blue channel pixel

1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if TXOUT0 disabled

1010 Ping - High for pixels processed by the Ping section of a channel,

low for Pong

1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in multiline sequences

1100 Line#msb

1101 Black Loop Pixels - High for pixels processed by the Black Loop

CB3/CB2 CB 1110 ActiveWhite Loop Pixels - High for pixels processed by the White

Loop

Mapping

1111 CLP Pixels - High for pixels where the input CLP switch is closed

[3:0]

CB2 Mapping

0000 CBO2 from LM98714 definition

0001 CBO0 from LM98714 definition

0010 CBO1 from LM98714 definition

0011 CBO2 from LM98714 definition

0100 CBO3 from LM98714 definition

0101 CBO4 from LM98714 definition

0110 R - High for a red channel pixel

0111 G - High for a green channel pixel

1000 B - High for a blue channel pixel

1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if

TXOUT0 disabled

1010 Ping - High for pixels processed by the Ping section of a channel,

low for Pong

1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in multiline sequences

1100 Line#msb

1101 Black Loop Pixels - High for pixels processed by the Black Loop

1110 ActiveWhite Loop Pixels - High for pixels processed by the White

Loop

1111 CLP Pixels - High for pixels where the input CLP switch is closed

130

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

8

11

B

0000 0000

Selects CB Bit Mapping

D2 Mapping

[7:4]

0000 D2 (Normal output for particular bit position)

0001 CBO0 from LM98714 definition

0010 CBO1 from LM98714 definition

0011 CBO2 from LM98714 definition

0100 CBO3 from LM98714 definition

0101 CBO4 from LM98714 definition

0110 R - High for a red channel pixel

0111 G - High for a green channel pixel

1000 B - High for a blue channel pixel

1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if TXOUT0 disabled

1010 Ping - High for pixels processed by the Ping section of a channel,

low for Pong

1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in multiline sequences

1100 Line#msb

1101 Black Loop Pixels - High for pixels processed by the Black Loop

D2/CB4 CB

Mapping

1110 Active White Loop Pixels - High for pixels processed by the White

Loop

1111 CLP Pixels - High for pixels where the input CLP switch is closed

[3:0]

CB4 Mapping

0000 CBO4 from LM98714 definition

0001 CBO0 from LM98714 definition

0010 CBO1 from LM98714 definition

0011 CBO2 from LM98714 definition

0100 CBO3 from LM98714 definition

0101 CBO4 from LM98714 definition

0110 R - High for a red channel pixel

0111 G - High for a green channel pixel

1000 B - High for a blue channel pixel

1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if TXOUT0 disabled

1010 Ping - High for pixels processed by the Ping section of a channel,

low for Pong

1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in multiline sequences

1100 Line#msb

1101 Black Loop Pixels - High for pixels processed by the Black Loop

1110 ActiveWhite Loop Pixels - High for pixels processed by the White

Loop

1111 CLP Pixels - High for pixels where the input CLP switch is closed

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

8

12

C

0000 0000

Selects CB Bit Mapping

D4 Mapping

[7:4]

0000 D4 (Normal output for particular bit position)

0001 CBO0 from LM98714 definition

0010 CBO1 from LM98714 definition

0011 CBO2 from LM98714 definition

0100 CBO3 from LM98714 definition

0101 CBO4 from LM98714 definition

0110 R - High for a red channel pixel

0111 G - High for a green channel pixel

1000 B - High for a blue channel pixel

1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if TXOUT0 disabled

1010 Ping - High for pixels processed by the Ping section of a channel,

low for Pong

1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in multiline sequences

1100 Line#msb

1101 Black Loop Pixels - High for pixels processed by the Black Loop

1110 ActiveWhite Loop Pixels - High for pixels processed by the White

Loop

D4/D3 CB

Mapping

1111 CLP Pixels - High for pixels where the input CLP switch is closed

[3:0]

D3 Mapping

0000 D4 (Normal output for particular bit position)

0001 CBO0 from LM98714 definition

0010 CBO1 from LM98714 definition

0011 CBO2 from LM98714 definition

0100 CBO3 from LM98714 definition

0101 CBO4 from LM98714 definition

0110 R - High for a red channel pixel

0111 G - High for a green channel pixel

1000 B - High for a blue channel pixel

1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if TXOUT0 disabled

1010 Ping - High for pixels processed by the Ping section of a channel,

low for Pong

1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in multiline sequences

1100 Line#msb

1101 Black Loop Pixels - High for pixels processed by the Black Loop

1110 ActiveWhite Loop Pixels - High for pixels processed by the White

Loop

1111 CLP Pixels - High for pixels where the input CLP switch is closed

132

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

[7:4]

[3:0]

REGISTER DESCRIPTION

8

13

D

0000 0000

Not Used

Selects CB Bit Mapping

D5 Mapping

0000 D5 (Normal output for particular bit position)

0001 CBO0 from LM98714 definition

0010 CBO1 from LM98714 definition

0011 CBO2 from LM98714 definition

0100 CBO3 from LM98714 definition

0101 CBO4 from LM98714 definition

0110 R - High for a red channel pixel

0111 G - High for a green channel pixel

1000 B - High for a blue channel pixel

1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if TXOUT0 disabled

D5 CB

Mapping

1010 Ping - High for pixels processed by the Ping section of a channel,

low for Pong

1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in multiline sequences

1100 Line#msb

1101 Black Loop Pixels - High for pixels processed by the Black Loop

1110 ActiveWhite Loop Pixels - High for pixels processed by the White

Loop

1111 CLP Pixels - High for pixels where the input CLP switch is closed

Select level of CLK outputs during register updating (UNLOCK state)

8

14

E

0000 0000

These can be modified during LOCK state to allow user to set up chip for

what happens during the next UNLOCK state

[7]

[6]

[5]

PHIA1 Unlock State

0 = Low, 1 = High

PHIA2 Unlock State

0 = Low, 1 = High

Unlock State PHIB1 Unlock State

Output Values 0 = Low, 1 = High

PHIA, PHIB,

[4]

[3]

[2]

[1]

[0]

PHIC, RS, CP PHIB2 Unlock State

0 = Low, 1 = High

PHIC1 Unlock State

0 = Low, 1 = High

PHIC2 Unlock State

0 = Low, 1 = High

RS Unlock State

0 = Low, 1 = High

CP Unlock State

0 = Low, 1 = High

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

8

15

F

0000 0000

[7:5]

Not Used

Select level of CLK outputs during register updating (UNLOCK state)

These can be modified during LOCK state to allow user to set up chip for

what happens during the next UNLOCK state

[4]

SH1 Unlock State

Unlock State 0 = Low, 1 = High

Output Values

[3]

[2]

[1]

[0]

SH1, SH2,

SH2 Unlock State

SH3, SH4, SH5 0 = Low, 1 = High

SH3 Unlock State

0 = Low, 1 = High

SH4 Unlock State

0 = Low, 1 = High

SH5 Unlock State

0 = Low, 1 = High

8

16 to

17

10 to

11

0000 0000

Reserved

18

19

20

12

13

14

[7]

Reserved

Inhibit Scrambling Individual LVDS Bits if 1.

[6]

[5]

[4]

[3]

[2]

[1]

[0]

[7]

Do Not Scramble LVDS[6]

Do Not Scramble LVDS[5]

Do Not Scramble LVDS[4]

Do Not Scramble LVDS[3]

Do Not Scramble LVDS[2]

Do Not Scramble LVDS[1]

Do Not Scramble LVDS[0]

Reserved

Scrambler

Inhibit 0

8

0000 0000

Inhibit Scrambling Individual LVDS Bits if 1.

Do Not Scramble LVDS[13]

Do Not Scramble LVDS[12]

Do Not Scramble LVDS[11]

Do Not Scramble LVDS[10]

Do Not Scramble LVDS[9]

Do Not Scramble LVDS[8]

Do Not Scramble LVDS[7]

Reserved

[6]

[5]

[4]

[3]

[2]

[1]

[0]

[7]

Scrambler

Inhibit 1

8

0000 0000

Inhibit Scrambling Individual LVDS Bits if 1.

Do Not Scramble LVDS[20]

Do Not Scramble LVDS[19]

Do Not Scramble LVDS[18]

Do Not Scramble LVDS[17]

Do Not Scramble LVDS[16]

Do Not Scramble LVDS[15]

Do Not Scramble LVDS[14]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Scrambler

Inhibit 2

134

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Table 18. Register Definitions (continued)

PAGE ADDR ADDR DEFAULT

(DEC) (DEC) (HEX) (BINARY)

REGISTER

TITLE

BITS

REGISTER DESCRIPTION

8

21 to

30

15 to

1E

0000 0000

Reserved

8

31

1F

[3:0]

Page Register

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SNAS474H –APRIL 2009–REVISED MARCH 2015

9 Device and Documentation Support

9.1 Trademarks

All trademarks are the property of their respective owners.

9.2 Device Support

For additional information, see Texas Instruments' E2E community resources: http://e2e.ti.com.

9.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

9.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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137

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PACKAGE OUTLINE

DGG0056A

TSSOP - 1.2 mm max height

S

C

A

L

E

1

.

2

0

SMALL OUTLINE PACKAGE

C

8.3

7.9

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

54X 0.5

56

1

14.1

13.9

NOTE 3

2X

13.5

28

B

29

0.27

0.17

6.2

6.0

56X

1.2 MAX

0.08

C A

B

(0.15) TYP

0.25

GAGE PLANE

0 - 8

SEE DETAIL A

0.15

0.05

0.75

0.50

DETAIL A

TYPICAL

4222167/A 07/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

DGG0056A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

56X (1.5)

SYMM

1

56

56X (0.3)

54X (0.5)

(R0.05)

TYP

SYMM

28

29

(7.5)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

METAL

SOLDER MASK

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222167/A 07/2015

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DGG0056A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

56X (1.5)

SYMM

1

56

56X (0.3)

54X (0.5)

(R0.05) TYP

SYMM

28

29

(7.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:6X

4222167/A 07/2015

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LM98725CCMT/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	具有 LVDS/CMOS 输出和集成 CCD/CIS 传感器定时发送器的 3 通道 16 位 81MSPS AFE \| DGG \| 56 \| 0 to 70 CD 光电二极管传感器
文件：	总146页 (文件大小：5508K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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