LMH6550MA [NSC]
Differential, High Speed Op Amp; 差，高速运算放大器
| 型号： | LMH6550MA |
| 厂家： | 
National Semiconductor |
| 描述： | Differential, High Speed Op Amp |
| 文件： | 总17页 (文件大小：851K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2004
LMH6550
Differential, High Speed Op Amp
General Description
Features
n 400 MHz −3 dB bandwidth (VOUT = 0.5 VPP
)
™
The LMH 6550 is a high performance voltage feedback
differential amplifier. The LMH6550 has the high speed and
low distortion necessary for driving high performance ADCs
as well as the current handling capability to drive signals
over balanced transmission lines like CAT 5 data cables. The
LMH6550 can handle a wide range of video and data for-
mats.
n 90 MHz 0.1 dB bandwidth
n 3000 V/µs slew Rate
n 8 ns settling time to 0.1%
@
n −92/−103 dB HD2/HD3 5 MHz
n 10 ns shutdown/enable
With external gain set resistors, the LMH6550 can be used
at any desired gain. Gain flexibility coupled with high speed
makes the LMH6550 suitable for use as an IF amplifier in
high performance communications equipment.
Applications
n Differential AD driver
n Video over twisted pair
n Differential line driver
n Single end to differential converter
n High speed differential signaling
n IF/RF amplifier
The LMH6550 is available in the space saving SOIC pack-
age.
n SAW filter buffer/driver
Typical Application
20130110
Single Ended Input Differential Output.
Gain = A =0.5 * R /R
G
V
F
™
LMH is a trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation
DS201301
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Connection Diagram
8-Pin SOIC
20130108
Top View
Ordering Information
Package
Part Number
LMH6550MA
LMH6550MAX
Package Marking
LMH6550MA
Transport Media
95/Rails
NSC Drawing
8-Pin SOIC
M08A
2.5k Units Tape and Reel
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Soldering Information
Infrared or Convection (20 sec)
Wave Soldering (10 sec)
235˚C
260˚C
ESD Tolerance (Note 5)
Operating Ratings (Note 1)
Operating Temperature Range
Storage Temperature Range
Total Supply Voltage
Human Body Model
Machine Model
2000V
200V
13.2V
Vs
−40˚C to +85˚C
−65˚C to +150˚C
4.5V to 12V
Supply Voltage
Common Mode Input Voltage
Maximum Input Current (pins 1, 2,
7, 8)
Package Thermal Resistance (θJA) (Note 4)
8-Pin SOIC
150˚C/W
30mA
Maximum Output Current (pins 4, 5)
(Note 3)
5V Electrical Characteristics (Note 2)
Single ended in differential out, TA= 25˚C, AV= +1, VS
=
5V, VCM = 0V, RF = RG = 365Ω, RL = 500Ω;; Unless specified Bold-
face limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
AC Performance (Differential)
SSBW
LSBW
Small Signal −3 dB Bandwidth
VOUT = 0.5 VPP
VOUT = 2 VPP
VOUT = 4 VPP
VOUT = 0.5 VPP
4V Step(Note 6)
2V Step
400
380
320
90
MHz
MHz
MHz
MHz
V/µs
ns
Large Signal −3 dB Bandwidth
Large Signal −3 dB Bandwidth
0.1 dB Bandwidth
Slew Rate
2000
3000
Rise/Fall Time
1
8
Settling Time
2V Step, 0.1%
ns
VCM Pin AC Performance (Common Mode Feedback Amplifier)
Common Mode Small Signal
Bandwidth
V
CMbypass capacitor removed
210
200
MHz
V/µs
Slew Rate
VCMbypass capacitor removed
Distortion and Noise Response
HD2
HD2
HD2
HD3
HD3
HD3
en
2nd Harmonic Distortion
3rd Harmonic Distortion
VO = 2 VPP, f = 5 MHz, RL=800Ω
VO = 2 VPP, f = 20 MHz, RL=800Ω
VO = 2 VPP, f = 70 MHz, RL=800Ω
VO = 2 VPP, f = 5 MHz, RL=800Ω
VO = 2 VPP, f = 20 MHz, RL=800Ω
VO = 2 VPP, f = 70 MHz, RL=800Ω
Freq ≥ 1 MHz
−92
−78
−59
−103
−88
−50
6.0
dBc
dBc
dBc
dBc
dBc
dBc
Input Referred Voltage Noise
Input Referred Noise Current
nV/
pA/
in
Freq ≥ 1 MHz
1.5
Input Characteristics (Differential)
VOSD
Input Offset Voltage
Differential Mode, VID = 0, VCM = 0
(Note 10)
1
4
mV
6
Input Offset Voltage Average
Temperature Drift
1.6
µV/˚C
IBI
Input Bias Current
(Note 9)
0
-8
−16
µA
Input Bias Current Average
Temperature Drift
(Note 10)
9.6
nA/˚C
Input Bias Difference
Difference in Bias currents between
the two inputs
0.3
µA
CMRR
RIN
Common Mode Rejection Ratio
Input Resistance
DC, VCM = 0V, VID = 0V
Differential
72
82
5
dBc
MΩ
pF
CIN
Input Capacitance
Differential
1
3
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5V Electrical Characteristics (Note 2) (Continued)
Single ended in differential out, TA= 25˚C, AV= +1, VS
face limits apply at the temperature extremes.
=
5V, VCM = 0V, RF = RG = 365Ω, RL = 500Ω;; Unless specified Bold-
Symbol
Parameter
Conditions
CMRR 53dB
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
>
CMVR
Input Common Mode Voltage
Range
+3.1
−4.6
+3.2
−4.7
V
VCMPin Input Characteristics (Common Mode Feedback Amplifier)
VOSC
Input Offset Voltage
Common Mode, VID = 0
1
5
mV
8
Input Offset Voltage Average
Temperature Drift
Input Bias Current
VCM CMRR
(Note 10)
25
µV/˚C
(Note 9)
−2
75
µA
dB
VID = 0V, 1V step on VCM pin,
measure VOD
70
Input Resistance
25
kΩ
▲
▲
VCM
Common Mode Gain
VO,CM
/
0.995
0.997
1.005
V/V
Output Performance
Output Voltage Swing
Single Ended, Peak to Peak,
VID = 0 V,
7.38
7.18
3.69
7.8
3.8
V
V
Output Common Mode Voltage
Range
IOUT
ISC
Linear Output Current
Short Circuit Current
VOUT = 0V
63
75
mA
mA
Output Shorted to Ground
VIN = 3V Single Ended(Note 3)l
∆VOUTCommon Mode
200
Output Balance Error
−68
dB
/∆VOUTDIfferential , VOUT = 1Vpp
Differential, f = 10 MHz
Miscellaneous Performance
Enable/Disable Time
10
70
90
20
ns
dB
dB
mA
AVOL
Open Loop Gain
Differential
PSRR
Power Supply Rejection Ratio
Supply Current
DC, ∆VS
=
1V
74
18
∞
RL
=
24
27
Disabled Supply Current
1
1.2
mA
5V Electrical Characteristics (Note 2)
Single ended in differential out, TA= 25˚C, AV= +1, VS = 5V, VCM = 2.5V, RF = RG = 365Ω, RL = 500Ω; ; Unless specifiedBold-
face limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
SSBW
LSBW
Small Signal −3 dB Bandwidth
Large Signal −3 dB Bandwidth
0.1 dB Bandwidth
RL = 500Ω, VOUT = 0.5 VPP
RL = 500Ω, VOUT = 2 VPP
350
330
60
MHz
MHz
MHz
V/µs
ns
Slew Rate
2V Step(Note 6)
1V Step
1500
1
Rise/Fall Time, 10% to 90%
Settling Time
1V Step, 0.05%
12
ns
VCM Pin AC Performance (Common Mode Feedback Amplifier)
Common Mode Small Signal
Bandwidth
185
180
−89
MHz
V/µs
dBc
Slew Rate
Distortion and Noise Response
HD2
2nd Harmonic Distortion
VO = 2 VPP, f = 5 MHz, RL=800Ω
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4
5V Electrical Characteristics (Note 2) (Continued)
Single ended in differential out, TA= 25˚C, AV= +1, VS = 5V, VCM = 2.5V, RF = RG = 365Ω, RL = 500Ω; ; Unless specifiedBold-
face limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
HD2
HD3
HD3
en
VO = 2 VPP, f = 20 MHz, RL=800Ω
VO = 2 VPP, f = 5 MHz, RL=800Ω
VO = 2 VPP, f = 20 MHz, RL=800Ω
Freq ≥ 1 MHz
−88
−85
−70
6.0
dBc
dBc
dBc
3rd Harmonic Distortion
Input Referred Noise Voltage
Input Referred Noise Current
nV/
pA/
in
Freq ≥ 1 MHz
1.5
Input Characteristics (Differential)
VOSD
Input Offset Voltage
Differential Mode, VID = 0, VCM = 0
(Note 10)
1
4
mV
6
Input Offset Voltage Average
Temperature Drift
1.6
µV/˚C
IBIAS
Input Bias Current
(Note 9)
0
−8
−16
µA
Input Bias Current Average
Temperature Drift
(Note 10)
9.5
nA/˚C
Input Bias Current Difference
Difference in Bias currents between
the two inputs
0.3
µA
CMRR
VICM
Common-Mode Rejection Ratio
Input Resistance
DC, VID = 0V
70
80
5
dBc
MΩ
pF
Differential
Input Capacitance
Differential
1
>
Input Common Mode Range
CMRR 53 dB
+3.1
+0.4
+3.2
+0.3
VCMPin Input Characteristics (Common Mode Feedback Amplifier)
Input Offset Voltage
Common Mode, VID = 0
1
5
mV
8
Input Offset Voltage Average
Temperature Drift
Input Bias Current
VCM CMRR
18.6
µV/˚C
3
µA
dB
VID = 0,
70
75
1V step on VCM pin, measure VOD
VCM pin to ground
Input Resistance
25
kΩ
▲
▲
VCM
Common Mode Gain
VO,CM
/
0.991
V/V
Output Performance
VOUT
Output Voltage Swing
Single Ended, Peak to Peak, VS=
2.5V, VCM= 0V
2.4
54
2.8
V
IOUT
ISC
Linear Output Current
VOUT = 0V Differential
70
mA
mA
Output Short Circuit Current
Output Shorted to Ground
VIN = 3V Single Ended(Note 3)
VID = 0, VCMpin = 1.2V and 3.8V
250
CMVR
Common Mode Voltage Range
Output Balance Error
3.72
1.23
3.8
1.2
V
∆VOUTCommon Mode
−65
dB
/∆VOUTDIfferential , VOUT = 1Vpp
Differential, f = 10 MHz
Miscellaneous Performance
Enable/Disable Time
Open Loop Gain
10
70
77
19
ns
dB
dB
mA
DC, Differential
PSRR
IS
Power Supply Rejection Ratio
DC, ∆VS
=
0.5V
72
∞
Supply Current
RL
=
16.5
23.5
26.5
1.2
ISD
Disabled Supply Current
1
mA
5
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5V Electrical Characteristics (Note 2) (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables.
Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of
>
the device such that T = T . No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where T
T .
J
A
J
A
Note 3: The maximum output current (I
) is determined by device power dissipation limitations.
OUT
Note 4: The maximum power dissipation is a function of T
, θ and T . The maximum allowable power dissipation at any ambient temperature is
JA A
J(MAX)
P
= (T — T )/ θ . All numbers apply for package soldered directly into a 2 layer PC board with zero air flow.
J(MAX) A JA
D
Note 5: Human body model: 1.5 kΩ in series with 100 pF. Machine model: 0Ω in series with 200pF.
Note 6: Slew Rate is the average of the rising and falling edges.
Note 7: Typical numbers are the most likely parametric norm.
Note 8: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control
(SQC) methods.
Note 9: Negative input current implies current flowing out of the device.
Note 10: Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
Note 11: Parameter is guaranteed by design.
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6
Typical Performance Characteristics (TA = 25˚C, VS
=
5V, RL = 500Ω, RF = 365Ω, AV=+1; Unless
Specified).
Frequency Response vs. Supply Voltage
Frequency Response
20130114
20130115
Frequency Response vs. VOUT
Frequency Response vs. Capacitive Load
20130121
20130116
Suggested ROUT vs. Cap Load
Suggested ROUT vs. Cap Load
20130122
20130123
7
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Typical Performance Characteristics (TA = 25˚C, VS
=
5V, RL = 500Ω, RF = 365Ω, AV=+1; Unless
Specified). (Continued)
1 VPP Pulse Response Single Ended Input
2 VPP Pulse Response Single Ended Input
20130127
20130126
Large Signal Pulse Response
Output Common Mode Pulse Response
20130125
20130124
Distortion vs. Frequency Single Ended Input
Distortion vs. Frequency Single Ended Input
20130128
20130129
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Typical Performance Characteristics (TA = 25˚C, VS
=
5V, RL = 500Ω, RF = 365Ω, AV=+1; Unless
Specified). (Continued)
Maximum VOUT vs. IOUT
Minimum VOUT vs. IOUT
20130130
20130131
Closed Loop Output Impedance
Closed Loop Output Impedance
20130117
20130118
PSRR
PSRR
20130119
20130120
9
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Typical Performance Characteristics (TA = 25˚C, VS
=
5V, RL = 500Ω, RF = 365Ω, AV=+1; Unless
Specified). (Continued)
CMRR
Balance Error
20130113
20130133
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Application Section
The LMH6550 is a fully differential amplifier designed to
provide low distortion amplification to wide bandwidth differ-
ential signals. The LMH6550, though fully integrated for
ultimate balance and distortion performance, functionally
provides three channels. Two of these channels are the V+
and V− signal path channels, which function similarly to
inverting mode operational amplifiers and are the primary
signal paths. The third channel is the common mode feed-
back circuit. This is the circuit that sets the output common
mode as well as driving the V+ and V− outputs to be equal
magnitude and opposite phase, even when only one of the
two input channels is driven. The common mode feedback
circuit allows single ended to differential operation.
The resistors RO help keep the amplifier stable when pre-
sented with a load CL as is typical in an analog to digital
converter (ADC). When fed with a differential signal, the
LMH6550 provides excellent distortion, balance and com-
mon mode rejection provided the resistors RF, RG and RO
are well matched and strict symmetry is observed in board
layout. With a DC CMRR of over 80dB, the DC and low
frequency CMRR of most circuits will be dominated by the
external resistors and board trace resistance. At higher fre-
quencies board layout symmetry becomes a factor as well.
Precision resistors of at least 0.1% accuracy are recom-
mended and careful board layout will also be required.
The LMH6550 is a voltage feedback amplifier with gain set
by external resistors. Output common mode voltage is set by
the VCM pin. This pin should be driven by a low impedance
reference and should be bypassed to ground with a 0.1 µF
ceramic capacitor. Any signal coupling into the VCM will be
passed along to the output and will reduce the dynamic
range of the amplifier.
The LMH6550 is equipped with a ENABLE pin to reduce
power consumption when not in use. The ENABLE pin floats
to logic high. If this pin is not used it can be left floating. The
amplifier output stage goes into a high impedance state
when the amplifier is disabled. The feedback and gain set
resistors will then set the impedance of the circuit. For this
reason input to output isolation will be poor in the disabled
state.
FULLY DIFFERENTIAL OPERATION
20130102
The LMH6550 will perform best when used with split sup-
plies and in a fully differential configuration. See Figure 1
and Figure 3 for recommend circuits.
FIGURE 2. Fully Differential Cable Driver
With up to 15 VPP differential output voltage swing and 80
mA of linear drive current the LMH6550 makes an excellent
cable driver as shown in Figure 2. The LMH6550 is also
suitable for driving differential cables from a single ended
source.
20130104
FIGURE 1. Typical Application
The circuit shown in Figure 1 is a typical fully differential
application as might be used to drive an ADC. In this circuit
closed loop gain, (AV) = VOUT/ VIN = RF/RG. For all the
applications in this data sheet VINis presumed to be the
voltage presented to the circuit by the signal source. For
differential signals this will be the difference of the signals on
each input (which will be double the magnitude of each
individual signal), while in single ended inputs it will just be
the driven input signal.
20130110
FIGURE 3. Single Ended in Differential Out
11
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Application Section (Continued)
The LMH6550 requires supply bypassing capacitors as
shown in Figure 4 and Figure 5. The 0.01 µF and 0.1 µF
capacitors should be leadless SMT ceramic capacitors and
should be no more than 3 mm from the supply pins. The
SMT capacitors should be connected directly to a ground
plane. Thin traces or small vias will reduce the effectiveness
of bypass capacitors. Also shown in both figures is a capaci-
tor from the VCM pin to ground. The VCM pin is a high
impedance input to a buffer which sets the output common
mode voltage. Any noise on this input is transferred directly
to the output. Output common mode noise will result in loss
of dynamic range, degraded CMRR, degraded Balance and
higher distortion. The VCM pin should be bypassed even if
the pin in not used. There is an internal resistive divider on
chip to set the output common mode voltage to the mid point
of the supply pins. The impedance looking into this pin is
approximately 25kΩ. If a different output common mode
voltage is desired drive this pin with a clean, accurate volt-
age reference.
20130101
FIGURE 4. Split Supply Bypassing Capacitors
20130112
FIGURE 5. Single Supply Bypassing Capacitors
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12
Application Section (Continued)
SINGLE ENDED INPUT TO DIFFERENTIAL OUTPUT
The LMH6550 provides excellent performance as an active
balun transformer. Figure 3 shows a typical application
where an LMH6550 is used to produce a differential signal
from a single ended source. It should be noted that com-
pared to differential input, using a single ended input will
reduce gain by 1/2. So that the closed loop gain will be; Gain
= Av = 0.5 * RF/RG.
In single ended input operation the output common mode
voltage is set by the VCMpin as in fully differential mode.
Also, In this mode the common mode feedback circuit must
recreate the signal that is not present on the unused differ-
ential input pin. The performance chart titled “Balance Error”
is the measurement of the effectiveness of this process. The
common mode feedback circuit is responsible for ensuring
balanced output with a single ended input. Balance error is
defined as the amount of input signal that couples into the
output common mode. It is measured as a the undesired
output common mode swing divided by the signal on the
input. Balance error can be caused by either a channel to
channel gain error, or phase error. Either condition will pro-
duce a common mode shift. The chart titled “Balance Error”
measures the balance error with a single ended input as that
is the most demanding mode of operation for the amplifier.
20130109
FIGURE 7. AC Coupled for Single Supply Operation
DRIVING ANALOG TO DIGITAL CONVERTERS
Analog to digital converters (ADC) present challenging load
conditions. They typically have high impedance inputs with
large and often variable capacitive components. As well,
there are usually current spikes associated with switched
capacitor or sample and hold circuits. Figure 8 shows a
typical circuit for driving an ADC. The two 56Ω resistors
serve to isolate the capacitive loading of the ADC from the
amplifier and ensure stability. In addition, the resistors form
part of a low pass filter which helps to provide anti alias and
noise reduction functions. The two 39 pF capacitors help to
smooth the current spikes associated with the internal
switching circuits of the ADC and also are a key component
in the low pass filtering of the ADC input. In the circuit of
Figure 8the cutoff frequency of the filter is 1/ (2*π*56Ω *(39
pF + 14pF)) = 53MHz (which is slightly less than the sam-
pling frequency). Note that the ADC input capacitance must
be factored into the frequency response of the input filter,
and that being a differential input the effective input capaci-
tance is double. Also as shown in Figure 8 the input capaci-
tance to many ADCs is variable based on the clock cycle.
See the data sheet for your particular ADC for details.
Supply and VCMpin bypassing are also critical in this mode of
operation. See the above section on FULLY DIFFERENTIAL
OPERATION for bypassing recommendations also see Fig-
ure 4 and Figure 5 for recommended supply bypassing
configurations.
SINGLE SUPPLY OPERATION
The input stage of the LMH6550 has a built in offset of 0.7V
towards the lower supply to accommodate single supply
operation with single ended inputs. As shown in Figure 6, the
input common mode voltage is less than the output common
voltage. It is set by current flowing through the feedback
network from the device output. The input common mode
range of 0.4V to 3.2V places constraints on gain settings.
Possible solutions to this limitation include AC coupling the
input signal, using split power supplies and limiting stage
gain. AC coupling with single supply is shown in Figure 7.
In Figure 6 below closed loop gain = AV= RF/RG. Please note
that in single ended to differential operation VIN is measured
single ended while VOUT is measured differentially. This
means that gain is really 1/2 or 6 dB less when measured on
either of the output pins separately.
VICM= Input common mode voltage = (V+IN+V−IN)/2.
20130111
FIGURE 6. Relating AVto Input/Output Common Mode
Voltages
13
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USING TRANSFORMERS
Application Section (Continued)
Transformers are useful for impedance transformation as
well as for single to differential, and differential to single
ended conversion. A transformer can be used to step up the
output voltage of the amplifier to drive very high impedance
loads as shown in Figure 9. Figure 11 shows the opposite
case where the output voltage is stepped down to drive a low
impedance load.
Transformers have limitations that must be considered be-
fore choosing to use one. Compared to a differential ampli-
fier, the most serious limitations of a transformer are the
inability to pass DC and balance error (which causes distor-
tion and gain errors). For most applications the LMH6550 will
have adequate output swing and drive current and a trans-
former will not be desirable. Transformers are used primarily
to interface differential circuits to 50Ω single ended test
equipment to simplify diagnostic testing.
20130105
FIGURE 8. Driving an ADC
The amplifier and ADC should be located as closely together
as possible. Both devices require that the filter components
be in close proximity to them. The amplifier needs to have
minimal parasitic loading on the output traces and the ADC is
sensitive to high frequency noise that may couple in on its
input lines. Some high performance ADCs have an input
stage that has a bandwidth of several times its sample rate.
The sampling process results in all input signals presented
to the input stage mixing down into the Nyquist range (DC to
Fs/2). See AN-236 for more details on the subsampling
process and the requirements this imposes on the filtering
necessary in your system.
20130107
FIGURE 9. Transformer Out High Impedance Load
20130132
FIGURE 10. Calculating Transformer Circuit Net Gain
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14
shutdown is not provided. Therefore, it is of utmost impor-
tance to make sure that the TJMAX is never exceeded due to
the overall power dissipation.
Application Section (Continued)
Follow these steps to determine the Maximum power dissi-
pation for the LMH6550:
1. Calculate the quiescent (no-load) power: PAMP = ICC
*
(VS), where VS = V+ - V−. (Be sure to include any current
through the feedback network if VOCM is not mid rail.)
2. Calculate the RMS power dissipated in each of the
output stages: PD (rms) = rms ((VS - V+OUT) * I+OUT) +
rms ((VS − V−OUT) * I−OUT) , where VOUT and IOUT are
the voltage and the current measured at the output pins
of the differential amplifier as if they were single ended
amplifiers and VS is the total supply voltage.
3. Calculate the total RMS power: PT = PAMP + PD.
The maximum power that the LMH6550 package can dissi-
pate at a given temperature can be derived with the following
equation:
20130106
PMAX = (150˚ – TAMB)/ θJA, where TAMB = Ambient tempera-
ture (˚C) and θJA = Thermal resistance, from junction to
ambient, for a given package (˚C/W). For the SOIC package
θJA is 150˚C/W.
FIGURE 11. Transformer Out Low Impedance Load
NOTE: If VCM is not 0V then there will be quiescent current
flowing in the feedback network. This current should be
included in the thermal calculations and added into the qui-
escent power dissipation of the amplifier.
ESD PROTECTION
The LMH6550 is protected against electrostatic discharge
(ESD) on all pins. The LMH6550 will survive 2000V Human
Body model and 200V Machine model events. Under normal
operation the ESD diodes have no effect on circuit perfor-
mance. There are occasions, however, when the ESD di-
odes will be evident. If the LMH6550 is driven by a large
signal while the device is powered down the ESD diodes will
conduct . The current that flows through the ESD diodes will
either exit the chip through the supply pins or will flow
through the device, hence it is possible to power up a chip
with a large signal applied to the input pins. Using the
shutdown mode is one way to conserve power and still
prevent unexpected operation.
20130103
BOARD LAYOUT
FIGURE 12. Driving 50Ω Test Equipment
The LMH6550 is a very high performance amplifier. In order
to get maximum benefit from the differential circuit architec-
ture board layout and component selection is very critical.
The circuit board should have low a inductance ground plane
and well bypassed broad supply lines. External components
should be leadless surface mount types. The feedback net-
work and output matching resistors should be composed of
short traces and precision resistors (0.1%). The output
matching resistors should be placed within 3-4 mm of the
amplifier as should the supply bypass capacitors. The
LMH730154 evaluation board is an example of good layout
techniques. Evaluation boards are available free of charge
through the product folder on National’s web site.
CAPACITIVE DRIVE
As noted in the Driving ADC section, capacitive loads should
be isolated from the amplifier output with small valued resis-
tors. This is particularly the case when the load has a resis-
tive component that is 500Ω or higher. A typical ADC has
capacitive components of around 10 pF and the resistive
component could be 1000Ω or higher. If driving a transmis-
sion line, such as 50Ω coaxial or 100Ω twisted pair, using
matching resistors will be sufficient to isolate any subse-
quent capacitance. For other applications see the “Sug-
gested Rout vs. Cap Load” charts in the Typical Perfor-
mance Characteristics section.
The LMH6550 is sensitive to parasitic capacitances on the
amplifier inputs and to a lesser extent on the outputs as well.
Ground and power plane metal should be removed from
beneath the amplifier and from beneath RF and RG.
POWER DISSIPATION
The LMH6550 is optimized for maximum speed and perfor-
mance in the small form factor of the standard SOIC pack-
age, and is essentially a dual channel amplifier. To ensure
maximum output drive and highest performance, thermal
With any differential signal path symmetry is very important.
Even small amounts of assymetery will contribute to distor-
tion and balance errors.
15
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evaluation boards as a guide for high frequency layout and
as an aid in device testing and characterization:
Application Section (Continued)
EVALUATION BOARD
Device
Package
Evaluation Board
Part Number
LMH730154
Generally, a good high frequency layout will keep power
supply and ground traces away from the inverting input and
output pins. Parasitic capacitances on these nodes to
ground will cause frequency response peaking and possible
circuit oscillations (see Application Note OA-15 for more
information). National Semiconductor suggests the following
LMH6550MA
SOIC
These evaluation boards can be shipped when a device
sample request is placed with National Semiconductor.
www.national.com
16
Physical Dimensions inches (millimeters)
unless otherwise noted
8-Pin SOIC
NS Package Number M08A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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