LMH6550MA/NOPB [TI]
400MHz 差分高速运算放大器 | D | 8 | -40 to 85;
| 型号： | LMH6550MA/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 400MHz 差分高速运算放大器 | D | 8 | -40 to 85 放大器 PC 光电二极管 运算放大器 |
| 文件： | 总36页 (文件大小：2605K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMH6550
SNOSAK0I –DECEMBER 2004–REVISED JANUARY 2015
LMH6550 Differential, High-Speed Operational Amplifier
1 Features
3 Description
The LMH6550 device is a high-performance voltage
1
•
•
•
•
•
•
400 MHz −3-dB Bandwidth (VOUT = 0.5 VPP
)
feedback differential amplifier. The LMH6550 has the
high speed and low distortion necessary for driving
high-performance ADCs as well as the current
handling capability to drive signals over balanced
transmission lines like CAT 5 data cables. The
LMH6550 can handle a wide range of video and data
formats.
90 MHz 0.1-dB Bandwidth
3000 V/µs Slew Rate
8 ns Settling Time to 0.1%
−92/−103 dB HD2/HD3 at 5 MHz
10 ns Shutdown/Enable
With external gain set resistors, the LMH6550 can be
used at any desired gain. Gain flexibility coupled with
high speed makes the LMH6550 suitable for use as
an IF amplifier in high-performance communications
equipment.
2 Applications
•
•
•
•
•
•
•
Differential AD Driver
Video Over Twisted-Pair
Differential Line Driver
The LMH6550 is available in the space-saving SOIC
and VSSOP packages.
Single End to Differential Converter
High-Speed Differential Signaling
IF/RF Amplifier
Device Information(1)
SAW Filter Buffer/Driver
PART NUMBER
PACKAGE
SOIC (8)
VSSOP (8)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
LMH6550
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Typical Application Schematic
R
F
A , R
V
IN
+
V
R
R
R
G
S
O
G
V
I
+
IN-
-
V
+
VSa
V
CM
R
ADC
IN+
O
R
T
-
O
R
-
R
M
V
R
F
DesignTarget :
For RM ꢂꢂ RG :
VO RF
1
1)SetRT
Av
#
1
1
V RG
ꢀ
I
RS RIN
2RG(1ꢁ Av )
2 ꢁ Av
RIN #
2)Set RM RT ||RS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6550
SNOSAK0I –DECEMBER 2004–REVISED JANUARY 2015
www.ti.com
Table of Contents
8.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Applications ................................................ 14
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Typical Application Schematic............................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
7.1 Absolute Maximum Ratings ...................................... 3
7.2 ESD Ratings.............................................................. 3
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics: ±5 V ................................. 4
7.6 Electrical Characteristics: 5 V ................................... 6
7.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
9
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 22
11.3 Power Dissipation ................................................. 24
11.4 ESD Protection...................................................... 24
12 Device and Documentation Support ................. 25
12.1 Device Support...................................................... 25
12.2 Documentation Support ........................................ 25
12.3 Trademarks........................................................... 25
12.4 Electrostatic Discharge Caution............................ 25
12.5 Glossary................................................................ 25
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (March 2013) to Revision I
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision G (March 2013) to Revision H
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 22
2
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SNOSAK0I –DECEMBER 2004–REVISED JANUARY 2015
6 Pin Configuration and Functions
D Package / DGK Package
8 Pins
Top View
1
2
3
4
8
-IN
+IN
-
+
7
6
V
EN
CM
V-
V+
5
-OUT
+OUT
Pin Functions
PIN
I/O
DESCRIPTION
NAME
EN
NO.
7
I
I
Enable
-IN
1
Negative Input
Positive Input
+IN
8
I
-OUT
+OUT
V-
5
O
O
P
P
I
Negative Output
4
Positive Output
6
Negative Supply
V+
3
Positive Supply
VCM
2
Output Common-Mode Input
7 Specifications
7.1 Absolute Maximum Ratings(1)(2)(3)
MIN
MAX
13.2
±VS
30
UNIT
V
Supply Voltage
Common-Mode Input Voltage
Maximum Input Current (pins 1, 2, 7, 8)
Maximum Output Current (pins 4, 5)
Maximum Junction Temperature
Storage Temperature, Tstg
V
mA
(4)
150
150
°C
°C
−65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) For Soldering Information, see Product Folder at www.ti.com and SNOA549.
(4) The maximum output current (IOUT) is determined by device power dissipation limitations.
7.2 ESD Ratings
VALUE
±2000
±200
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2)
Machine model (MM)
V(ESD)
Electrostatic discharge(1)
V
(1) Human body model: 1.5 kΩ in series with 100 pF. Machine model: 0 Ω in series with 200 pF.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
MIN
−40
4.5
NOM
MAX
85
UNIT
°C
Operating Temperature
Total Supply Voltage
12
V
7.4 Thermal Information
LMH6550
THERMAL METRIC(1)
D
DGK
UNIT
8 PINS
150
8 PINS
(2)
RθJA
Junction-to-ambient thermal resistance
235
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is P D= (TJ(MAX) — TA)/ θJA. All numbers apply for package soldered directly into a 2 layer PC board with zero air flow.
7.5 Electrical Characteristics: ±5 V(1)
Single-ended in differential out, TA = 25°C, VS = ±5 V, VCM = 0 V, RF = RG = 365 Ω, RL = 500 Ω; unless specified.
(2)
(3)
(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE (DIFFERENTIAL)
SSBW
LSBW
Small Signal −3 dB Bandwidth
Large Signal −3 dB Bandwidth
Large Signal −3 dB Bandwidth
0.1 dB Bandwidth
VOUT = 0.5 VPP
400
380
320
90
MHz
MHz
MHz
MHz
V/μs
ns
VOUT = 2 VPP
VOUT = 4 VPP
VOUT = 0.5 VPP
(4)
Slew Rate
4-V Step
2000
3000
1
Rise/Fall Time
2-V Step
Settling Time
2-V Step, 0.1%
8
ns
VCM PIN AC PERFORMANCE (COMMON-MODE FEEDBACK AMPLIFIER)
Common-Mode Small Signal
Bandwidth
VCM Bypass Capacitor Removed
210
200
MHz
V/µs
Slew Rate
VCM Bypass Capacitor Removed
DISTORTION AND NOISE RESPONSE
HD2
2nd Harmonic Distortion
3rd Harmonic Distortion
VO = 2 VPP, f = 5 MHz, RL = 800 Ω
VO = 2 VPP, f = 20 MHz, RL = 800 Ω
VO = 2 VPP, f = 70 MHz, RL = 800 Ω
VO = 2 VPP, f = 5 MHz, RL = 800 Ω
VO = 2 VPP, f = 20 MHz, RL = 800 Ω
VO = 2 VPP, f = 70 MHz, RL = 800 Ω
f ≥ 1 MHz
−92
−78
−59
−103
−88
−50
6.0
dBc
dBc
HD3
en
in
Input Referred Voltage Noise
Input Referred Noise Current
nV/√Hz
pA/√Hz
f ≥ 1 MHz
1.5
INPUT CHARACTERISTICS (DIFFERENTIAL)
VOSD
Input Offset Voltage
Differential Mode, VID
0, VCM = 0
=
1
±4
±6
mV
At extreme
temperatures
(5)
(6)
Input Offset Voltage Average
Temperature Drift
1.6
-8
µV/°C
µA
IBI
Input Bias Current
0
−16
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using
Statistical Quality Control (SQC) methods.
(3) Typical numbers are the most likely parametric norm.
(4) Slew Rate is the average of the rising and falling edges.
(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(6) Negative input current implies current flowing out of the device.
4
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Electrical Characteristics: ±5 V(1) (continued)
Single-ended in differential out, TA = 25°C, VS = ±5 V, VCM = 0 V, RF = RG = 365 Ω, RL = 500 Ω; unless specified.
(2)
(3)
(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(5)
Input Bias Current Average
Temperature Drift
9.6
0.3
nA/°C
Input Bias Difference
Difference in Bias Currents Between the
Two Inputs
µA
CMRR
RIN
Common-Mode Rejection Ratio
Input Resistance
DC, VCM = 0 V, VID = 0 V
Differential
72
82
5
dBc
MΩ
pF
CIN
Input Capacitance
Differential
1
CMVR
Input Common-Mode Voltage Range CMRR > 53 dB
+3.1
−4.6
+3.2
−4.7
V
VCM PIN INPUT CHARACTERISTICS (COMMON-MODE FEEDBACK AMPLIFIER)
VOSC
Input Offset Voltage
Common Mode, VID = 0
1
±5
±8
mV
At extreme
temperatures
(5)
(6)
Input Offset Voltage Average
Temperature Drift
25
µV/°C
Input Bias Current
VCM CMRR
−2
μA
VID = 0 V, 1-V Step on VCM Pin, Measure
VOD
70
75
dB
Input Resistance
25
kΩ
Common-Mode Gain
ΔVO,CM/ΔVCM
0.995
0.997
1.005
V/V
OUTPUT PERFORMANCE
Output Voltage Swing
Peak to Peak,
Differential
7.38
7.18
7.8
V
V
At extreme
temperatures
Output Common-Mode Voltage
Range
VID = 0 V,
±3.69
±63
±3.8
IOUT
ISC
Linear Output Current
Short Circuit Current
VOUT = 0 V
±75
mA
mA
Output Shorted to Ground
VIN = 3 V Single-Ended
±200
(7)
Output Balance Error
ΔVOUT Common Mode /ΔVOUT
Differential, VOUT = 1 VPP Differential, f =
10 MHz
−68
dB
MISCELLANEOUS PERFORMANCE
Enable Voltage Threshold
Disable Voltage Threshold
Enable Pin Current
Pin 7
Pin 7
2.0
V
V
1.5
(6)
VEN =0 V
-250
55
µA
(6)
VEN =4 V
Enable/Disable Time
10
ns
dB
dB
mA
AVOL
Open Loop Gain
Differential
DC, ΔVS = ±1 V
RL = ∞
70
PSRR
Power Supply Rejection Ratio
Supply Current
74
18
90
20
24
27
At extreme
temperatures
Disabled Supply Current
1
1.2
mA
(7) The maximum output current (IOUT) is determined by device power dissipation limitations.
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7.6 Electrical Characteristics: 5 V(1)
Single-ended in differential out, TA = 25°C, AV = +1, VS = 5 V, VCM = 2.5 V, RF = RG = 365 Ω, RL = 500 Ω; unless specified.
(2)
(3)
(2)
PARAMETER
Small Signal −3 dB Bandwidth
Large Signal −3 dB Bandwidth
0.1 dB Bandwidth
TEST CONDITIONS
RL = 500 Ω, VOUT = 0.5 VPP
RL = 500 Ω, VOUT = 2 VPP
MIN
TYP
MAX
UNIT
MHz
MHz
MHz
V/μs
ns
SSBW
LSBW
350
330
60
(4)
Slew Rate
2-V Step
1500
1
Rise/Fall Time, 10% to 90%
Settling Time
1-V Step
1-V Step, 0.05%
12
ns
VCM PIN AC PERFORMANCE (COMMON-MODE FEEDBACK AMPLIFIER)
Common-Mode Small Signal
Bandwidth
185
180
MHz
Slew Rate
V/μs
DISTORTION AND NOISE RESPONSE
HD2
2nd Harmonic Distortion
VO = 2 VPP, f = 5 MHz, RL = 800 Ω
VO = 2 VPP, f = 20 MHz, RL = 800 Ω
VO = 2 VPP, f = 5 MHz, RL = 800 Ω
VO = 2 VPP, f = 20 MHz, RL = 800 Ω
f ≥ 1 MHz
−89
−88
−85
−70
6.0
dBc
dBc
HD3
3rd Harmonic Distortion
en
in
Input Referred Noise Voltage
Input Referred Noise Current
nV/√Hz
pA/√Hz
f ≥ 1 MHz
1.5
INPUT CHARACTERISTICS (DIFFERENTIAL)
VOSD
Input Offset Voltage
Differential Mode, VID
0, VCM = 0
=
1
±4
±6
mV
At extreme
temperatures
(5)
Input Offset Voltage Average
Temperature Drift
1.6
µV/°C
(6)
(5)
IBIAS
Input Bias Current
0
−8
−16
μA
Input Bias Current Average
Temperature Drift
9.5
nA/°C
Input Bias Current Difference
Difference in Bias Currents Between the
Two Inputs
0.3
µA
CMRR
VICM
Common-Mode Rejection Ratio
Input Resistance
DC, VID = 0 V
Differential
70
80
5
dBc
MΩ
pF
Input Capacitance
Differential
1
Input Common-Mode Range
CMRR > 53 dB
+3.1
+0.4
+3.2
+0.3
VCM PIN INPUT CHARACTERISTICS (COMMON-MODE FEEDBACK AMPLIFIER)
Input Offset Voltage
Common-Mode, VID = 0
1
±5
±8
mV
At extreme
temperatures
Input Offset Voltage Average
Temperature Drift
18.6
µV/°C
Input Bias Current
VCM CMRR
3
μA
VID = 0,
70
75
dB
1-V Step on VCM Pin, Measure VOD
Input Resistance
VCM Pin to Ground
25
kΩ
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using
Statistical Quality Control (SQC) methods.
(3) Typical numbers are the most likely parametric norm.
(4) Slew Rate is the average of the rising and falling edges.
(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(6) Negative input current implies current flowing out of the device.
6
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Electrical Characteristics: 5 V(1) (continued)
Single-ended in differential out, TA = 25°C, AV = +1, VS = 5 V, VCM = 2.5 V, RF = RG = 365 Ω, RL = 500 Ω; unless specified.
(2)
(3)
(2)
PARAMETER
Common-Mode Gain
TEST CONDITIONS
ΔVO,CM/ΔVCM
MIN
TYP
MAX
UNIT
0.991
2.8
V/V
OUTPUT PERFORMANCE
VOUT
Output Voltage Swing
Peak to Peak, Differential,
VS = ±2.5 V, VCM = 0 V
2.4
V
IOUT
ISC
Linear Output Current
VOUT = 0-V Differential
±54
±70
250
mA
mA
Output Short Circuit Current
Output Shorted to Ground
VIN = 3 V Single-Ended
(7)
CMVR
Common-Mode Voltage Range
Output Balance Error
VID = 0, VCM Pin = 1.2 V and 3.8 V
3.72
1.23
3.8
1.2
V
ΔVOUT Common Mode /ΔVOUT
DIfferential, VOUT = 1 VPP Differential, f =
10 MHz
−65
dB
MISCELLANEOUS PERFORMANCE
Enable Voltage Threshold
Disable Voltage Threshold
Enable Pin Current
Pin 7
Pin 7
2.0
V
V
1.5
(6)
VEN =0 V
-250
55
µA
(6)
VEN =4 V
Enable/Disable Time
Open Loop Gain
10
ns
dB
dB
mA
DC, Differential
DC, ΔVS = ±0.5 V
RL = ∞
70
PSRR
IS
Power Supply Rejection Ratio
Supply Current
72
77
16.5
19
23.5
26.5
At extreme
temperatures
ISD
Disabled Supply Current
1
1.2
mA
(7) The maximum output current (IOUT) is determined by device power dissipation limitations.
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7.7 Typical Characteristics
(TA = 25°C, VS = ±5 V, RL = 500 Ω, RF = RG = 365 Ω; unless specified).
1
0
1
0
V
= 5V
V = 5V
S
S
-1
-2
-3
-4
-5
-6
-7
-8
-9
-1
-2
-3
-4
-5
-6
-7
-8
-9
V
= ±5V
V = ±5V
S
S
V
A
= 0.5V
PP
V
A
= 1V
PP
OD
OD
= 1
= 1
V
V
DIFFERENTIAL INPUT
SINGLE ENDED INPUT
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 1. Frequency Response vs Supply Voltage
Figure 2. Frequency Response
1
0
1
0
GAIN = 2
-1
-2
-3
-4
-5
-6
-7
-8
-9
-1
V
= 4.0V
PP
OD
-2
-3
-4
-5
-6
-7
-8
-9
GAIN = 4
GAIN = 6
V
= 0.5V
PP
OD
V
= 2.0V
PP
OD
V
A
= ±5V
= 1
s
V
V
= 0.5 V
PP
SINGLE ENDED INPUT
OUT
SINGLE ENDED INPUT
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4. Frequency Response vs Gain
Figure 3. Frequency Response vs VOUT
2
70
60
50
40
V
S
= ±5V
C
= 5.7 pF, R
= 40:
L
OUT
1
0
C
= 10 pF, R
= 30:
= 22:
= 13:
L
OUT
-1
-2
-3
-4
-5
-6
-7
-8
C
= 22 pF, R
= 47 pF, R
L
OUT
C
L
OUT
30
20
V
OD
= 210 mV
PP
A
V
= 1
LOAD = 1 k: || CAP LOAD
10
LOAD = (CL || 1 k:) IN
SERIES WITH 2 ROUTS
V
= ±5V
S
0
1
10
100
1000
10
CAPACITIVE LOAD (pF)
100
1
FREQUENCY (MHz)
Figure 5. Frequency Response vs Capacitive Load
Figure 6. Suggested ROUT vs Cap Load
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Typical Characteristics (continued)
(TA = 25°C, VS = ±5 V, RL = 500 Ω, RF = RG = 365 Ω; unless specified).
1.5
2.5
2
1
1.5
1
0.5
0.5
0
0
-0.5
-0.5
R
R
= 500:
= 360:
-1
-1.5
-2
L
F
V
= ±5
S
-1
R
= 500:
= 360:
L
F
SINGLE ENDED
INPUT
R
-1.5
-2.5
0
10 20 30 40 50 60 70 80 90 100
TIME (ns)
0
10 20 30 40 50 60 70 80 90 100
TIME (ns)
Figure 7. 2 VPP Pulse Response Single-Ended Input
Figure 8. Large Signal Pulse Response
-30
40
30
20
10
0
-40
HD3
-50
-60
-70
-10
-20
-30
V
S
= 5V
-80
-90
R
R
V
= 500:
= 360:
= 4 V
R
V
= 800:
= 2 V
L
F
L
HD2
-40
-50
-60
OD
PP
V
OCM
= 2.5V
OD
PP
-100
0
10 20 30 40 50 60 70 80 90 100
TIME (ns)
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
Figure 10. Distortion vs Frequency Single-Ended Input
Figure 9. Output Common-Mode Pulse Response
-40
4
3.9
3.8
3.7
3.6
3.5
3.4
-50
HD3
-60
-70
-80
HD2
V
= ±5V
= 800:
= 2 V
V
A
= ±5V
S
S
3.3
3.2
3.1
3
-90
-100
-110
R
= 2
L
V
V
OD
R
= 730:
PP
F
V
OCM
= 0V
V
IN
= 3.88V SINGLE ENDED
-50
-60 -70 -80 -90 -100
0
-10 -20 -30 -40
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
OUTPUT CURRENT (mA)
Figure 11. Distortion vs Frequency Single-Ended Input
Figure 12. Maximum VOUT vs IOUT
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Typical Characteristics (continued)
(TA = 25°C, VS = ±5 V, RL = 500 Ω, RF = RG = 365 Ω; unless specified).
100
-3
V
V
A
= ±5V
= 0V
= 1
V
A
= ±5V
S
S
V
-3.1
-3.2
-3.3
-3.4
-3.5
-3.6
= 2
IN
V
R
= 730:
F
10
1
V
= 3.88V SINGLE ENDED
IN
-3.7
-3.8
0.1
-3.9
-4
0.01
0
50
0.01
1
10
100
1000
10 20 30 40
60 70 80 90 100
0.1
FREQUENCY (MHz)
OUTPUT CURRENT (mA)
Figure 14. Closed-Loop Output Impedance
Figure 13. Minimum VOUT vs IOUT
100
100
V
V
A
= 5V
= 0V
= 1
S
90
PSRR -
IN
V
80
10
1
70
PSRR +
60
50
40
V
= ±5V
= 500:
= 1
30
20
S
0.1
R
L
A
V
V
10
0
= 0V
IN
0.01
10
FREQUENCY (MHz)
0.01
0.1
1
100
1000
0.01
1
10
100
1000
0.1
FREQUENCY (MHz)
Figure 15. Closed-Loop Output Impedance
Figure 16. PSRR
100
90
85
80
75
70
65
60
55
50
45
40
PSRR -
80
70
PSRR +
60
50
40
V
= 5V
= 500:
= 1
30
20
S
R
L
A
V
V
10
0
= 2.5V
IN
10
FREQUENCY (MHz)
0.01
0.1
1
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 17. PSRR
Figure 18. CMRR
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Typical Characteristics (continued)
(TA = 25°C, VS = ±5 V, RL = 500 Ω, RF = RG = 365 Ω; unless specified).
-40
-25
V
A
= ±5V
S
V
R
R
= 500:
= 360:
= 1
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
L
F
V
-45
-50
-55
-60
-65
-70
= 2 V/V
= 200:
f = 40 MHz
f = 20 MHz
V
S
= 5V
R
L
A
V
= ±5V
S
f = 5 MHz
-75
-80
-85
0
5
6
7
1
2
3
4
1
10
100
1000
FREQUENCY (MHz)
DIFFERENTIAL V )
(V
OUT PP
Figure 19. Balance Error
Figure 20. Third-Order Intermodulation Products vs VOUT
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8 Detailed Description
8.1 Overview
The LMH6550 is a fully differential amplifier designed to provide low distortion amplification to wide bandwidth
differential signals. The LMH6550, though fully integrated for ultimate balance and distortion performance,
functionally provides three channels. Two of these channels are the V+ and V− signal path channels, which
function similarly to inverting mode operational amplifiers and are the primary signal paths. The third channel is
the common-mode feedback circuit. This is the circuit that sets the output common mode as well as driving the
V+ and V− outputs to be equal magnitude and opposite phase, even when only one of the two input channels is
driven. The common-mode feedback circuit allows single-ended to differential operation.
8.2 Functional Block Diagram
V+
+OUT
±
-IN
2.5 kꢀ
2.5 kꢀ
High-Aol
Differential I/O
Amplifier
+
±
+IN
+
-OUT
V+
50 kꢀ
±
Vcm
Error
Amplifier
+
Vcm
EN
Buffer
50 kꢀ
V±
8.3 Feature Description
The LMH6550 combines a core differential I/O, high-gain block with an output common-mode sense that is
compared to a reference voltage and then fed back into the main amplifier block to control the average output to
that reference. The differential I/O block is a classic, high open-loop gain stage. The high-speed differential
outputs include an internal averaging resistor network to sense the output common-mode voltage. This voltage is
compared by a separate Vcm error amplifier to the voltage on the Vocm pin. If floated, this reference is at half
the total supply voltage across the device using two 50-kΩ resistors. This Vcm error amplifier transmits a
correction signal into the main amplifier to force the output average voltage to meet the target voltage on the
Vocm pin.
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8.4 Device Functional Modes
This wideband FDA requires external resistors for correct signal-path operation. When configured for the desired
input impedance and gain setting with these external resistors, the amplifier can be either on with the PD pin
asserted to a voltage greater than Vs– + 1.7 V, or turned off by asserting PD low. Disabling the amplifier shuts
off the quiescent current and stops correct amplifier operation. The signal path is still present for the source
signal through the external resistors. The Vocm control pin sets the output average voltage. Left open, Vocm
defaults to an internal midsupply value. Driving this high-impedance input with a voltage reference within its valid
range sets a target for the internal Vcm error amplifier.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMH6550 is a fully differential amplifier designed to provide low distortion amplification to wide bandwidth
differential signals. The LMH6550, though fully integrated for ultimate balance and distortion performance,
functionally provides three channels. Two of these channels are the V+ and V− signal path channels, which
function similarly to inverting mode operational amplifiers and are the primary signal paths. The third channel is
the common-mode feedback circuit. This is the circuit that sets the output common mode as well as driving the
V+ and V− outputs to be equal magnitude and opposite phase, even when only one of the two input channels is
driven. The common-mode feedback circuit allows single-ended to differential operation.
The LMH6550 is a voltage feedback amplifier with gain set by external resistors. Output common-mode voltage
is set by the VCM pin. This pin should be driven by a low impedance reference and should be bypassed to ground
with a 0.1-µF ceramic capacitor. Any signal coupling into the VCM will be passed along to the output and will
reduce the dynamic range of the amplifier.
The LMH6550 is equipped with a ENABLE pin to reduce power consumption when not in use. The ENABLE pin
floats to logic high. If this pin is not used it can be left floating. The amplifier output stage goes into a high
impedance state when the amplifier is disabled. The feedback and gain set resistors will then set the impedance
of the circuit. For this reason input to output isolation will be poor in the disabled state.
9.2 Typical Applications
9.2.1 Typical Fully Differential Application
The LMH6550 performs best when used with split supplies and in a fully differential configuration. See Figure 21
and Figure 22 for recommend circuits.
R
F1
R
O
R
G1
+
-
C
L
R
L
V
O
V
CM
V
I
a
R
G2
R
O
R
F2
ENABLE
Figure 21. Typical Fully Differential Application Schematic
9.2.1.1 Design Requirements
Applications using fully differential amplifiers have several requirements. The main requirements are high linearity
and good signal amplitude. Linearity is accomplished by using well matched feedback and gain set resistors as
well as an appropriate supply voltage. The signal amplitude can be tailored by using an appropriate gain. In this
design the gain is set for a gain of 2 (RF=500/ RG=250) and the distortion criteria is better than -90 dBc at a
frequency of 5 Mhz. The supply voltages are set to +5 V and -5 V and the output common mode is 0 V. The
LMH6550 can be placed into shutdown to reduce power dissipation to 10 mW.
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Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
The power supplies for this design are symmetrical ±5-V supplies (not shown for simplicity). The ADC input
common mode is 1 V which is within the optimum operating range for the LMH6550 when used on ±5-V split
supplies. The gain of this circuit is equal to RF/RG and due to the split supplies can be set to gains of 15 V/V or
less. Higher gains will result in values of RF that are too large for high speed operation.
9.2.1.2.1 Fully Differential Operation
The circuit shown in is a typical fully differential application as might be used to drive an ADC. In this circuit
closed loop gain, (AV) = VOUT/ VIN = RF/RG. For all the applications in this data sheet VIN is presumed to be the
voltage presented to the circuit by the signal source. For differential signals this will be the difference of the
signals on each input (which will be double the magnitude of each individual signal), while in single-ended inputs
it will just be the driven input signal.
The resistors RO help keep the amplifier stable when presented with a load CL as is typical in an analog to digital
converter (ADC). When fed with a differential signal, the LMH6550 provides excellent distortion, balance and
common-mode rejection provided the resistors RF, RG and RO are well matched and strict symmetry is observed
in board layout. With a DC CMRR of over 80 dB, the DC and low frequency CMRR of most circuits will be
dominated by the external resistors and board trace resistance. At higher frequencies board layout symmetry
becomes a factor as well. Precision resistors of at least 0.1% accuracy are recommended and careful board
layout will also be required.
500
100:
50:
TWISTED PAIR
250
+
V
2 V
PP
CM
a
-
250
2 V
PP
50:
500
GAIN = 2
ENABLE
Figure 22. Fully Differential Cable Driver
With up to 15 VPP differential output voltage swing and 80 mA of linear drive current the LMH6550 makes an
excellent cable driver as shown in Figure 22. The LMH6550 is also suitable for driving differential cables from a
single-ended source.
The LMH6550 requires supply bypassing capacitors as shown in Figure 23 and Figure 24. The 0.01 µF and 0.1
µF capacitors should be leadless SMT ceramic capacitors and should be no more than 3 mm from the supply
pins. The SMT capacitors should be connected directly to a ground plane. Thin traces or small vias will reduce
the effectiveness of bypass capacitors. Also shown in both figures is a capacitor from the VCM pin to ground. The
VCM pin is a high impedance input to a buffer which sets the output common-mode voltage. Any noise on this
input is transferred directly to the output. Output common-mode noise will result in loss of dynamic range,
degraded CMRR, degraded Balance and higher distortion. The VCM pin should be bypassed even if the pin in not
used. There is an internal resistive divider on chip to set the output common-mode voltage to the mid point of the
supply pins. The impedance looking into this pin is approximately 25 kΩ. If a different output common-mode
voltage is desired drive this pin with a clean, accurate voltage reference.
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Typical Applications (continued)
+
+
V
V
0.01 PF
0.01 PF
10 PF
10 PF
0.01 PF
+
-
+
V
CM
0.1 PF
V
CM
0.1 PF
-
0.1 PF
0.01 PF
10 PF
-
V
Figure 23. Split Supply Bypassing Capacitors
Figure 24. Single Supply Bypassing Capacitors
9.2.1.2.2 Capacitive Drive
As noted in Driving Analog-to-Digital Converters, capacitive loads should be isolated from the amplifier output
with small valued resistors. This is particularly the case when the load has a resistive component that is 500 Ω or
higher. A typical ADC has capacitive components of around 10 pF and the resistive component could be 1000 Ω
or higher. If driving a transmission line, such as 50-Ω coaxial or 100-Ω twisted pair, using matching resistors will
be sufficient to isolate any subsequent capacitance. For other applications see Figure 6 and Figure 25 in Typical
Characteristics.
9.2.1.2.3 Application Curves
Many application circuits have capacitive loading. As shown in Figure 25, amplifier bandwidth is reduced with
increasing capacitive load, so parasitic capacitance should be strictly limited.
To ensure stability, resistance should be added between the capacitive load and the amplifier output pins. The
value of the resistor is dependent on the amount of capacitive load as shown in Figure 26. This resistive value is
a suggestion. System testing will be required to determine the optimal value. Using a smaller resistor will retain
more system bandwidth at the expense of overshoot and ringing, while larger values of resistance will reduce
overshoot but will also reduce system bandwidth.
70
60
50
40
0.8
0.6
0.4
0.2
0
30
20
10
-0.2
-0.4
-0.6
-0.8
V
= 5V
S
LOAD = 1 k: || CAP LOAD
= 5V
R
= 500:
= 360:
L
F
V
R
S
0
1
10
100
0
10 20 30 40 50 60 70 80 90 100
TIME (ns)
CAPACITIVE LOAD (pF)
Figure 25. Suggested ROUT vs Cap Load
Figure 26. 1 VPP Pulse Response Single-Ended Input
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Typical Applications (continued)
9.2.2 Driving Analog-to-Digital Converters
Analog-to-digital converters (ADC) present challenging load conditions. They typically have high-impedance
inputs with large and often variable capacitive components. As well, there are usually current spikes associated
with switched capacitor or sample and hold circuits. Figure 27 shows a typical circuit for driving an ADC. The two
56-Ω resistors serve to isolate the capacitive loading of the ADC from the amplifier and ensure stability. In
addition, the resistors form part of a low pass filter which helps to provide anti alias and noise reduction
functions. The two 39-pF capacitors help to smooth the current spikes associated with the internal switching
circuits of the ADC and also are a key component in the low pass filtering of the ADC input. In the circuit of
Figure 27 the cutoff frequency of the filter is 1/ (2*π*56 Ω *(39 pF + 14 pF)) = 53 MHz (which is slightly less than
the sampling frequency). Note that the ADC input capacitance must be factored into the frequency response of
the input filter, and that being a differential input the effective input capacitance is double. Also as shown in
Figure 27 the input capacitance to many ADCs is variable based on the clock cycle. See the data sheet for your
particular ADC for details.
The amplifier and ADC should be located as closely together as possible. Both devices require that the filter
components be in close proximity to them. The amplifier needs to have minimal parasitic loading on the output
traces and the ADC is sensitive to high frequency noise that may couple in on its input lines. Some high
performance ADCs have an input stage that has a bandwidth of several times its sample rate. The sampling
process results in all input signals presented to the input stage mixing down into the Nyquist range (DC to Fs/2).
See AN-236 for more details on the subsampling process and the requirements this imposes on the filtering
necessary in your system.
R
F1
56
ADC12LO66
R
G1
39 pF
+
V
-
V
I
a
CM
7 - 8 pF
39 pF
56
R
G2
V
REF
R
F2
ENABLE
1V LOW IMPEDANCE
VOLTAGE REFERENCE
Figure 27. Driving an ADC
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Typical Applications (continued)
9.2.3 Single-Ended Input to Differential Output
The LMH6550 provides excellent performance as an active balun transformer. Figure 28 shows a typical
application where an LMH6550 is used to produce a differential signal from a single-ended source.
In single-ended input operation the output common-mode voltage is set by the VCM pin as in fully differential
mode. Also, in this mode the common-mode feedback circuit must recreate the signal that is not present on the
unused differential input pin. Figure 19 is the measurement of the effectiveness of this process. The common-
mode feedback circuit is responsible for ensuring balanced output with a single-ended input. Balance error is
defined as the amount of input signal that couples into the output common mode. It is measured as a the
undesired output common-mode swing divided by the signal on the input. Balance error can be caused by either
a channel to channel gain error, or phase error. Either condition will produce a common-mode shift. Figure 19
measures the balance error with a single-ended input as that is the most demanding mode of operation for the
amplifier.
Supply and VCM pin bypassing are also critical in this mode of operation. See the above section on for bypassing
recommendations and also see Figure 23 and Figure 24 for recommended supply bypassing configurations.
R
F
A , R
V
IN
+
V
R
R
R
S
O
G
V
I
V
V
I1
O1
+
IN-
-
V
+
VSa
V
CM
R
ADC
IN+
O
R
T
-
V
O2
V
I2
O
R
G
-
R
M
V
+
-
R
F
Definitions :
Conditions :
RS RT ||RIN
RM RT ||RS
RG
ꢀ1
RG ꢁ RF
RG ꢁ RM
ꢀ2
RG ꢁ RM ꢁ RF
VO 2(1ꢂ ꢀ1) RF
Av
#
for RM ꢀꢀ RG
V
ꢀ1 ꢁ ꢀ2
RG
I
ꢀ2
RG(1ꢁ
)
2RG ꢁRM(1ꢂꢀ2)
1ꢁꢀ2
ꢀ1
2RG(1ꢁ Av )
2ꢁ Av
RIN
#
for RM ꢀꢀ RG
1ꢁꢀ2
VO1 ꢁ VO2
VOCM VCM
(by design)
2
V ꢁ V
VOCM
I1
I2
V
VOCM.ꢀ2 #
for RM ꢀꢀRG
ICM
2
1ꢁ Av
Figure 28. Single-Ended Input to Differential Output Schematic
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Typical Applications (continued)
9.2.4 Single Supply Operation
The input stage of the LMH6550 has a built in offset of 0.7 V towards the lower supply to accommodate single
supply operation with single-ended inputs. As shown in Figure 28, the input common-mode voltage is less than
the output common voltage. It is set by current flowing through the feedback network from the device output. The
input common-mode range of 0.4 V to 3.2 V places constraints on gain settings. Possible solutions to this
limitation include AC coupling the input signal, using split power supplies and limiting stage gain. AC coupling
with single supply is shown in Figure 29.
In Figure 28 closed loop gain = VO / VI ≊ RF / RG, where VI =VS / 2, as long as RM << RG. Note that in single-
ended to differential operation VI is measured single-ended while VO is measured differentially. This means that
gain is really 1/2 or 6 dB less when measured on either of the output pins separately. Additionally, note that the
input signal at RT (labeled as VI) is 1/2 of VS when RT is chosen to match RS to RIN.
VICM = Input common-mode voltage = (VI1+VI2) / 2.
R
F
R
O
V
O
1
V 1
I
R
R
G
S
+
C
L
R
L
V
O
V
CM
R
V
T
I
a
-
R
G
V 2
I
V
O
2
R
M
R
O
R
F
ENABLE
VICM = VOCM
VO1 + VO2
*VCM
=
VI1 + VI2
2
VICM
=
*BY DESIGN
2
Figure 29. AC-Coupled for Single Supply Operation
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Typical Applications (continued)
9.2.5 Using Transformers
Transformers are useful for impedance transformation as well as for single to differential, and differential to
single-ended conversion. A transformer can be used to step up the output voltage of the amplifier to drive very
high impedance loads as shown in Figure 30. Figure 32 shows the opposite case where the output voltage is
stepped down to drive a low-impedance load.
Transformers have limitations that must be considered before choosing to use one. Compared to a differential
amplifier, the most serious limitations of a transformer are the inability to pass DC and balance error (which
causes distortion and gain errors). For most applications the LMH6550 will have adequate output swing and drive
current and a transformer will not be desirable. Transformers are used primarily to interface differential circuits to
50-Ω single-ended test equipment to simplify diagnostic testing.
300: TWISTED PAIR
500
1:2 (TURNS)
37.5:
250
+
-
V
CM
4 V
PP a
V
CM
250
8 V
PP
R
L
= 300:
37.5:
500
ENABLE
A
= 2
V
Figure 30. Transformer Out High-Impedance Load
VIN * AV * N
VL =
©
¨
¨
§
2 ROUT * N2
RL
§
¨
¨
©
+ 1
WHERE VIN = DIFFERENTIAL INPUT VOLTAGE
N = TRANSFORMER TURNS RATIO =
©
¨
¨
§
§
¨
¨
©
SECONDARY
PRIMARY
AV = CLOSED LOOP AMPLIFIER GAIN
ROUT = SERIES OUTPUT MATCHING RESISTOR
RL = LOAD RESISTOR
VL = VOLTAGE ACROSS LOAD RESISTOR
Figure 31. Calculating Transformer Circuit Net Gain
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Typical Applications (continued)
100: TWISTED PAIR
375
2:1 (TURNS)
200:
375
+
V
CM
4 V
PP a
V
CM
-
375
1 V
PP
R
L
= 100:
200:
375
ENABLE
A
= 1
V
Figure 32. Transformer Out Low-Impedance Load
50: COAX
375
2:1 (TURNS)
100:
375
+
-
V
CM
4 V
PP a
C
1
375
1 V
PP
100:
375
ENABLE
GAIN = 1
IS NOT REQUIRED IF V
C
1
= GROUND
CM
Figure 33. Driving 50-Ω Test Equipment
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10 Power Supply Recommendations
The LMH6550 can be used with any combination of positive and negative power supplies as long as the
combined supply voltage is between 4.5 V and 12 V. The LMH6550 will provide best performance when the
output voltage is set at the mid supply voltage, and when the total supply voltage is between 9 V and 12 V.
When selecting a supply voltage that is less than 9 V it is important to consider both the input common-mode
voltage range as well as the output voltage range.
Power supply bypassing as shown in Figure 23 and Figure 24 is important and power supply regulation should
be within 5% or better when using a supply voltage near the edges of the operating range.
11 Layout
11.1 Layout Guidelines
The LMH6550 is a very high performance amplifier. To get maximum benefit from the differential circuit
architecture, board layout and component selection is very critical. The circuit board should have low a
inductance ground plane and well bypassed broad supply lines. External components should be leadless surface
mount types. The feedback network and output matching resistors should be composed of short traces and
precision resistors (0.1%). The output matching resistors should be placed within 3-4 mm of the amplifier as
should the supply bypass capacitors. The LMH730154 evaluation board is an example of good layout
techniques.
The LMH6550 is sensitive to parasitic capacitances on the amplifier inputs and to a lesser extent on the outputs
as well. Ground and power plane metal should be removed from beneath the amplifier and from beneath RF and
RG.
With any differential signal path, symmetry is very important. Even small amounts of asymmetry will contribute to
distortion and balance errors.
TI offers evaluation boards to aid in device testing and characterization and as a guide for proper layout.
Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations (see OA-15 Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers,
SNOA367, for more information).
11.2 Layout Example
Figure 34. EVM Layout (Top)
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Layout Example (continued)
Figure 35. EVM Layout (Bottom)
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11.3 Power Dissipation
The LMH6550 is optimized for maximum speed and performance in the small form factor of the standard SOIC
package, and is essentially a dual channel amplifier. To ensure maximum output drive and highest performance,
thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAX of 150°C is
never exceeded due to the overall power dissipation.
Follow these steps to determine the Maximum power dissipation for the LMH6550:
1. Calculate the quiescent (no-load) power: PAMP = ICC* (VS), where VS = V+ - V−. (Be sure to include any
current through the feedback network if VOCM is not mid rail.)
2. Calculate the RMS power dissipated in each of the output stages: PD (rms) = rms ((VS - V+OUT) * I+OUT) + rms
((VS − V−OUT) * I−OUT), where VOUT and IOUT are the voltage and the current measured at the output pins of
the differential amplifier as if they were single-ended amplifiers and VS is the total supply voltage.
3. Calculate the total RMS power: PT = PAMP + PD.
The maximum power that the LMH6550 package can dissipate at a given temperature can be derived with the
following equation:
PMAX = (150° – TAMB)/ θJA
where
•
•
•
•
TAMB = Ambient temperature (°C)
θJA = Thermal resistance, from junction to ambient, for a given package (°C/W)
For the SOIC package θJA is 150°C/W
For the VSSOP package θJA is 235°C/W
(1)
NOTE
If VCM is not 0V then there will be quiescent current flowing in the feedback network. This
current should be included in the thermal calculations and added into the quiescent power
dissipation of the amplifier.
11.4 ESD Protection
The LMH6550 is protected against electrostatic discharge (ESD) on all pins. The LMH6550 will survive 2000 V
Human Body model and 200 V Machine model events. Under normal operation the ESD diodes have no effect
on circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6550 is
driven by a large signal while the device is powered down the ESD diodes will conduct. The current that flows
through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is
possible to power up a chip with a large signal applied to the input pins. Using the shutdown mode is one way to
conserve power and still prevent unexpected operation.
24
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Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: LMH6550
LMH6550
www.ti.com
SNOSAK0I –DECEMBER 2004–REVISED JANUARY 2015
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
OA-15 Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, SNOA367
12.3 Trademarks
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2004–2015, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: LMH6550
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6550MA
NRND
SOIC
SOIC
SOIC
D
D
D
8
8
8
95
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
LMH65
50MA
LMH6550MA/NOPB
LMH6550MAX/NOPB
ACTIVE
ACTIVE
95
RoHS & Green
SN
SN
LMH65
50MA
2500 RoHS & Green
LMH65
50MA
LMH6550MM/NOPB
LMH6550MMX/NOPB
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
1000 RoHS & Green
3500 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
AL1A
AL1A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6550MAX/NOPB
LMH6550MM/NOPB
LMH6550MMX/NOPB
SOIC
D
8
8
8
2500
1000
3500
330.0
178.0
330.0
12.4
12.4
12.4
6.5
5.3
5.3
5.4
3.4
3.4
2.0
1.4
1.4
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
VSSOP
VSSOP
DGK
DGK
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6550MAX/NOPB
LMH6550MM/NOPB
LMH6550MMX/NOPB
SOIC
D
8
8
8
2500
1000
3500
367.0
208.0
367.0
367.0
191.0
367.0
35.0
35.0
35.0
VSSOP
VSSOP
DGK
DGK
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6550MA
LMH6550MA
D
D
D
SOIC
SOIC
SOIC
8
8
8
95
95
95
495
495
495
8
8
8
4064
4064
4064
3.05
3.05
3.05
LMH6550MA/NOPB
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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