LMK02000ISQX [NSC]
Precision Clock Conditioner with Integrated PLL; 精密时钟调节器，集成PLL
| 型号： | LMK02000ISQX |
| 厂家： | 
National Semiconductor |
| 描述： | Precision Clock Conditioner with Integrated PLL |
| 文件： | 总20页 (文件大小：445K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2007
LMK02000
Precision Clock Conditioner with Integrated PLL
General Description
Features
The LMK02000 precision clock conditioner combines the
functions of jitter cleaning/reconditioning, multiplication, and
distribution of a reference clock. The device integrates a high
performance Integer-N Phase Locked Loop (PLL), three
LVDS, and five LVPECL clock output distribution blocks.
20 fs additive jitter
■
■
Integrated Integer-N PLL with outstanding normalized
phase noise contribution of -224 dBc/Hz
Clock output frequency range of 1 to 800 MHz
3 LVDS and 5 LVPECL clock outputs
■
■
■
■
■
■
Each clock distribution block includes a programmable di-
vider, a phase synchronization circuit, a programmable delay,
a clock output mux, and an LVDS or LVPECL output buffer.
This allows multiple integer-related and phase-adjusted
copies of the reference to be distributed to eight system com-
ponents.
Dedicated divider and delay blocks on each clock output
Pin compatible family of clocking devices
3.15 to 3.45 V operation
Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
The clock conditioner comes in a 48-pin LLP package and is
footprint compatible with other clocking devices in the same
family.
Target Applications
Data Converter Clocking
■
■
■
■
■
■
Networking, SONET/SDH, DSLAM
Wireless Infrastructure
Medical
Test and Measurement
Military / Aerospace
Functional Block Diagram
20216501
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation
202165
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Connection Diagram
48-Pin LLP Package
20216502
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2
Pin Descriptions
Pin #
1, 25
2, 7
Pin Name
GND
I/O
Description
-
-
Ground
NC
No Connection to these pins
3, 8, 13, 16, 19, 22, 26,
30, 31, 33, 37, 40, 43, 46 Vcc8, Vcc9, Vcc10, Vcc11, Vcc12, Vcc13, Vcc14
Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7,
-
Power Supply
4
CLKuWire
DATAuWire
I
I
MICROWIRE Clock Input
MICROWIRE Data Input
MICROWIRE Latch Enable Input
LDO Bypass
5
6
LEuWire
I
9, 10
11
LDObyp1, LDObyp2
GOE
-
I
Global Output Enable
12
LD
O
O
O
O
O
I
Lock Detect and Test Output
LVDS Clock Output 0
14, 15
17, 18
20, 21
23, 24
27
CLKout0, CLKout0*
CLKout1, CLKout1*
CLKout2, CLKout2*
CLKout3, CLKout3*
SYNC*
LVDS Clock Output 1
LVDS Clock Output 2
LVPECL Clock Output 3
Global Clock Output Synchronization
Oscillator Clock Input; Must be AC coupled
Charge Pump Output
28, 29
32
OSCin, OSCin*
CPout
I
O
I
34, 35
36
Fin, Fin*
Frequency Input; Must be AC coupled
Bias Bypass
Bias
I
38, 39
41, 42
44, 45
47, 48
DAP
CLKout4, CLKout4*
CLKout5, CLKout5*
CLKout6, CLKout6*
CLKout7, CLKout7*
DAP
O
O
O
O
-
LVPECL Clock Output 4
LVPECL Clock Output 5
LVPECL Clock Output 6
LVPECL Clock Output 7
Die Attach Pad is Ground
3
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors
for availability and specifications.
Parameter
Power Supply Voltage
Symbol
VCC
VIN
Ratings
-0.3 to 3.6
-0.3 to (VCC + 0.3)
-65 to 150
+260
Units
V
Input Voltage
V
TSTG
TL
Storage Temperature Range
Lead Temperature (solder 4 s)
Junction Temperature
°C
°C
°C
TJ
125
Recommended Operating Conditions
Parameter
Ambient Temperature
Power Supply Voltage
Symbol
TA
Min
-40
Typ
25
Max
85
Units
°C
V
VCC
3.15
3.3
3.45
Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work
stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV.
Package Thermal Resistance
Package
θJA
θJ-PAD (Thermal Pad)
48-Lead LLP (Note 3)
27.4° C/W
5.8° C/W
Note 3: Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key
role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout.
Electrical Characteristics (Note 4)
(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most likely
parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization
and are not guaranteed).
Symbol
Parameter
Conditions
Current Consumption
Min
Typ
Max
Units
Entire device; CLKout0 & CLKout4
enabled in Bypass Mode
145.8
Power Supply Current
(Note 5)
ICC
mA
mA
Entire device; All Outputs Off (no
emitter resistors placed)
70
1
ICCPD
Power Down Current
POWERDOWN = 1
Reference Oscillator
Reference Oscillator Input Frequency
Range for Square Wave
fOSCin square
VOSCinsquare
1
200
1.6
MHz
Vpp
AC coupled; Differential (VOD
)
Square Wave Input Voltage for OSCin and
OSCin*
0.2
Frequency Input
(Notes 6, 10)
AC coupled
fFin
Frequency Input Frequency Range
Frequency Input Slew Rate
1
800
MHz
V/ns
%
SLEWFin
DUTYFin
PFin
0.5
40
Frequency Input Duty Cycle
60
8
Input Power Range for Fin or Fin*
-13
dBm
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4
Symbol
fCOMP
Parameter
Conditions
Min
Typ
Max
Units
PLL
Phase Detector Frequency
40
MHz
VCPout = Vcc/2, PLL_CP_GAIN = 1x
VCPout = Vcc/2, PLL_CP_GAIN = 4x
VCPout = Vcc/2, PLL_CP_GAIN = 16x
VCPout = Vcc/2, PLL_CP_GAIN = 32x
VCPout = Vcc/2, PLL_CP_GAIN = 1x
VCPout = Vcc/2, PLL_CP_GAIN = 4x
VCPout = Vcc/2, PLL_CP_GAIN = 16x
VCPout = Vcc/2, PLL_CP_GAIN = 32x
0.5 V < VCPout < Vcc - 0.5 V
100
400
ISRCECPout
Charge Pump Source Current
µA
1600
3200
-100
-400
-1600
-3200
2
ISINKCPout
Charge Pump Sink Current
μA
ICPoutTRI
Charge Pump TRI-STATE® Current
10
nA
%
VCPout = Vcc / 2
TA = 25°C
Magnitude of Charge Pump
Sink vs. Source Current Mismatch
ICPout%MIS
3
4
4
Magnitude of Charge Pump
Current vs. Charge Pump Voltage
Variation
0.5 V < VCPout < Vcc - 0.5 V
TA = 25°C
ICPoutVTUNE
%
Magnitude of Charge Pump Current vs.
Temperature Variation
ICPoutTEMP
PN10kHz
PN1Hz
%
PLL_CP_GAIN = 1x
PLL_CP_GAIN = 32x
PLL_CP_GAIN = 1x
PLL_CP_GAIN = 32x
-117
-122
-219
-224
PLL 1/f Noise at 10 kHz Offset (Note 7)
Normalized to 1 GHz Output Frequency
dBc/Hz
dBc/Hz
Normalized Phase Noise Contribution
(Note 8)
Clock Distribution Section (Note 9) - LVDS Clock Outputs (CLKout0 to CLKout2)
CLKoutX_MUX
= Bypass
20
75
RL = 100 Ω
Distribution Path =
800 MHz
Bandwidth =
12 kHz to 20 MHz
CLKoutX_MUX
= Divided
CLKoutX_DIV =
4
JitterADD
Additive RMS Jitter (Note 9)
fs
Equal loading and identical clock
configuration
tSKEW
CLKoutX to CLKoutY (Note 10)
Differential Output Voltage
-30
±4
30
ps
RL = 100 Ω
VOD
RL = 100 Ω
RL = 100 Ω
RL = 100 Ω
RL = 100 Ω
250
-50
350
450
50
mV
mV
V
Change in magnitude of VOD for
complementary output states
ΔVOD
VOS
Output Offset Voltage
1.070
-35
1.25
1.370
35
Change in magnitude of VOS for
complementary output states
ΔVOS
mV
ISA
ISB
Clock Output Short Circuit Current
single ended
Single ended outputs shorted to GND
Complementary outputs tied together
-24
-12
24
12
mA
mA
Clock Output Short Circuit Current
differential
ISAB
5
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
Clock Distribution Section (Note 9) - LVPECL Clock Outputs (CLKout3 to CLKout7)
CLKoutX_MUX
= Bypass
20
RL = 100 Ω
Distribution Path =
800 MHz
Bandwidth =
12 kHz to 20 MHz
CLKoutX_MUX
= Divided
CLKoutX_DIV =
4
JitterADD
Additive RMS Jitter (Note 9)
fs
75
Equal loading and identical clock
configuration
tSKEW
CLKoutX to CLKoutY (Note 10)
Output High Voltage
-30
±3
30
ps
V
Termination = 50 Ω to Vcc - 2 V
Vcc -
0.98
VOH
Vcc -
1.8
Termination = 50 Ω to Vcc - 2 V
VOL
VOD
Output Low Voltage
V
Differential Output Voltage
660
2.0
810
965
mV
Digital LVTTL Interfaces (Note 11)
VIH
VIL
IIH
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
Vcc
0.8
5.0
5.0
V
V
VIH = Vcc
VIL = 0
-5.0
µA
µA
IIL
-40.0
Vcc -
0.4
VOH
VOL
IOH = +500 µA
High-Level Output Voltage
Low-Level Output Voltage
V
V
IOL = -500 µA
0.4
Digital MICROWIRE Interfaces (Note 12)
VIH
VIL
IIH
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
1.6
Vcc
0.4
5.0
5.0
V
V
VIH = Vcc
-5.0
-5.0
µA
µA
IIL
VIL = 0
MICROWIRE Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
tCS
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
25
8
ns
ns
ns
ns
ns
ns
ns
tCH
tCWH
tCWL
tES
25
25
25
25
25
Clock to Enable Set Up Time
Enable to Clock Set Up Time
Enable Pulse Width High
tCES
tEWH
Note 4: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 5: See 3.4 for more current consumption / power dissipation calculation information.
Note 6: For all frequencies the slew rate, SLEWFin, is measured between 20% and 80%.
Note 7: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10
dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker
(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade
slope close to the carrier. A high phase detector frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker
(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of
LPLL_flicker(f) and LPLL_flat(f).
Note 8: A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, LPLL_flat(f), of the PLL and is defined as PN1Hz =
LPLL_flat(f) – 20log(N) – 10log(fCOMP). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth and fCOMP is the phase
detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). To measure LPLL_flat(f) the offset frequency, f, must be chosen sufficiently
smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference and flicker noise. LPLL_flat(f) can be
masked by the reference oscillator performance if a low power or noisy source is used.
Note 9: The Clock Distribution Section includes all parts of the device except the PLL section. Typical Additive Jitter specifications apply to the clock distribution
section only.
Note 10: Specification is guaranteed by characterization and is not tested in production.
Note 11: Applies to GOE, LD, and SYNC*.
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Note 12: Applies to CLKuWire, DATAuWire, and LEuWire.
Serial Data Timing Diagram
20216503
Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the CLKuWire signal. On
the rising edge of the LEuWire signal, the data is sent from the shift register to the addressed register determined by the LSB bits.
After the programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state.
7
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Charge Pump Current Specification Definitions
20216531
I1 = Charge Pump Sink Current at VCPout = Vcc - ΔV
I2 = Charge Pump Sink Current at VCPout = Vcc/2
I3 = Charge Pump Sink Current at VCPout = ΔV
I4 = Charge Pump Source Current at VCPout = Vcc - ΔV
I5 = Charge Pump Source Current at VCPout = Vcc/2
I6 = Charge Pump Source Current at VCPout = ΔV
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.
Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage
20216532
Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch
20216533
Charge Pump Output Current Magnitude Variation vs. Temperature
20216534
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grammed as CLKout0_MUX = Bypassed, CLKout1_MUX =
Divided, CLKout1_DIV = 2, CLKout2_MUX = Divided, and
CLKout2_DIV = 4.
1.0 Functional Description
The LMK02000 precision clock conditioner combines the
functions of jitter cleaning/reconditioning, multiplication, and
distribution of a reference clock. The device integrates a high
performance Integer-N Phase Locked Loop (PLL), three
LVDS, and five LVPECL clock output distribution blocks.
SYNC* Timing Diagram
Each clock distribution block includes a programmable di-
vider, a phase synchronization circuit, a programmable delay,
a clock output mux, and an LVDS or LVPECL output buffer.
This allows multiple integer-related and phase-adjusted
copies of the reference to be distributed to eight system com-
ponents.
The clock conditioner comes in a 48-pin LLP package and is
footprint compatible with other clocking devices in the same
family.
1.1 BIAS PIN
20216504
The SYNC* pin provides an internal pull-up resistor as shown
on the functional block diagram. If the SYNC* pin is not ter-
minated externally the clock outputs will operate normally. If
the SYNC* function is not used, clock output synchronization
is not guaranteed.
To properly use the device, bypass Bias (pin 36) with a low
leakage 1 µF capacitor connected to Vcc. This is important
for low noise performance.
1.2 LDO BYPASS
To properly use the device, bypass LDObyp1 (pin 9) with a
10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF capacitor.
1.8 CLKout OUTPUT STATES
Each clock output may be individually enabled with the
CLKoutX_EN bits. Each individual output enable control bit is
gated with the Global Output Enable input pin (GOE) and the
Global Output Enable bit (EN_CLKout_Global).
1.3 OSCILLATOR INPUT PORT (OSCin, OSCin*)
The purpose of OSCin is to provide the PLL with a reference
signal. The OSCin port must be AC coupled, refer to the Sys-
tem Level Diagram in the Application Information section. The
OSCin port may be driven single endedly by AC grounding
OSCin* with a 0.1 µF capacitor.
All clock outputs can be disabled simultaneously if the GOE
pin is pulled low by an external signal or EN_CLKout_Global
is set to 0.
1.4 FREQUENCY INPUT PORT (Fin, Fin*)
CLKoutX
_EN bit
EN_CLKout
_Global bit
GOE pin
Clock X
Output State
The purpose of Fin is to provide the PLL with a feedback sig-
nal from an external oscillator. The Fin port may be driven
single endedly by AC grounding Fin*.
1
Don't care
0
1
0
Low
Low
Off
Don't care
Don't care
1.5 CLKout DELAYS
Don't care
Off
Each individual clock output includes a delay adjustment.
Clock output delay registers (CLKoutX_DLY) support a 150
ps step size and range from 0 to 2250 ps of total delay.
High / No
Connect
1
1
Enabled
When an LVDS output is in the Off state, the outputs are at a
voltage of approximately 1.5 volts. When an LVPECL output
is in the Off state, the outputs are at a voltage of approximately
1 volt.
1.6 LVDS/LVPECL OUTPUTS
Each LVDS or LVPECL output may be disabled individually
by programming the CLKoutX_EN bits. All the outputs may
be disabled simultaneously by pulling the GOE pin low or
programming EN_CLKout_Global to 0.
1.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT
The GOE pin provides an internal pull-up resistor. If it is not
terminated externally, the clock output states are determined
by the Clock Output Enable bits (CLKoutX_EN) and the
EN_CLKout_Global bit.
1.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION
The SYNC* pin synchronizes the clock outputs. When the
SYNC* pin is held in a logic low state, the divided outputs are
also held in a logic low state. When the SYNC* pin goes high,
the divided clock outputs are activated and will transition to a
high state simultaneously. Clocks in the bypassed state are
not affected by SYNC* and are always synchronized with the
divided outputs.
By programming the PLL_MUX register to Digital Lock Detect
Active High (See 2.5.2), the Lock Detect (LD) pin can be con-
nected to the GOE pin in which case all outputs are set low
automatically if the synthesizer is not locked.
The SYNC* pin must be held low for greater than one clock
cycle of the Frequency Input port, also known as the distribu-
tion path. Once this low event has been registered, the out-
puts will not reflect the low state for four more cycles. Similarly
once the SYNC* pin becomes high, the outputs will not si-
multaneously transition high until four more distribution path
clock cycles have passed. See the timing diagram below for
further detail. In the timing diagram below the clocks are pro-
1.10 POWER ON RESET
When supply voltage to the device increases monotonically
from ground to Vcc, the power on reset circuit sets all registers
to their default values, see 2.3.1 for more information on de-
fault register values. Voltage should be applied to all Vcc pins
simultaneously.
9
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2.0 General Programming
Information
The LMK02000 device is programmed using several 32-bit
registers which control the device's operation. The registers
consist of a data field and an address field. The last 4 register
bits, ADDR[3:0] form the address field. The remaining 28 bits
form the data field DATA[27:0].
During programming, LEuWire is low and serial data is
clocked in on the rising edge of clock (MSB first). When
LEuWire goes high, data is transferred to the register bank
selected by the address field. Only registers R0 to R7, R11,
R14, and R15 need to be programmed for proper device op-
eration.
It is required to program register R14.
2.1 RECOMMENDED PROGRAMMING SEQUENCE
The recommended programming sequence involves pro-
gramming R0 with the reset bit set (RESET = 1) to ensure the
device is in a default state. It is not necessary to program R0
again, but if R0 is programmed again, the reset bit is pro-
grammed clear (RESET = 0). Registers are programmed in
order with R15 being the last register programmed. An ex-
ample programming sequence is shown below.
•
Program R0 with the reset bit set (RESET = 1). This
ensures the device is in a default state. When the reset bit
is set in R0, the other R0 bits are ignored.
If R0 is programmed again, the reset bit is programmed
clear (RESET = 0).
—
•
Program R0 to R7 as necessary with desired clocks with
appropriate enable, mux, divider, and delay settings.
•
•
Program R11 with DIV4 setting if necessary.
Program R14 with global clock output bit, power down
setting, PLL mux setting, and PLL R divider. It is required
to program register R14.
R14 must be programmed in accordance with the
register map as shown in the register map (see 2.2).
—
•
Program R15 with PLL charge pump gain, and PLL N
divider.
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C L K o u t 0 _ E N C L K o u t 1 _ E N C L K o u t 2 _ E N C L K o u t 3 _ E N C L K o u t 4 _ E N C L K o u t 5 _ E N C L K o u t 6 _ E N C L K o u t 7 _ E N
R E S E T
R e g i s t e r
11
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D I V 4
P L L _ C P _ P O L
T R I - S T A T E
P O W E R D O W N
E N _ C L K o u t _ G l o b a l
R e g i s t e r
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2.3 REGISTER R0 to R7
2.3.1 RESET Bit -- R0 only
Registers R0 through R7 control the eight clock outputs. Reg-
ister R0 controls CLKout0, Register R1 controls CLKout1, and
so on. There is one additional bit in register R0 called RESET.
Aside from this, the functions of these bits are identical. The
X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and
CLKoutX_EN denote the actual clock output which may be
from 0 to 7.
This bit is only in register R0. The use of this bit is optional
and it should be set to '0' if not used. Setting this bit to a '1'
forces all registers to their power on reset condition and there-
fore automatically clears this bit. If this bit is set, all other R0
bits are ignored and R0 needs to be programmed again if
used with its proper values and RESET = 0.
Default
Bit Value
Bit
Location
Bit Name
Bit State
Bit Description
Register
RESET
0
0
0
1
0
0
No reset, normal operation
Bypassed
Reset to power on defaults
CLKoutX mux mode
CLKoutX enable
R0
31
CLKoutX_MUX
CLKoutX_EN
CLKoutX_DIV
CLKoutX_DLY
DIV4
18:17
16
Disabled
R0 to R7
R11
Divide by 2
0 ps
CLKoutX clock divide
CLKoutX clock delay
Phase Detector Frequency
15:8
7:4
15
PDF ≤ 20 MHz
Normal - CLKouts normal
Normal - Device active
Normal - PLL active
Negative Polarity CP
Disabled
EN_CLKout_Global
POWERDOWN
PLL_CP_TRI
PLL_CP_POL
PLL_MUX
1
0
Global clock output enable
Device power down
27
26
0
TRI-STATE PLL charge pump
Polarity of charge pump
Multiplexer control for LD pin
PLL R divide value
25
R14
R15
0
24
0
23:20
19:8
31:30
25:8
PLL_R
10
0
R divider = 10
PLL_CP_GAIN
PLL_N
100 uA
Charge pump current
760
N divider = 760
PLL N divide value
2.3.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers
CLKoutX_MUX
[1:0]
Mode
Added Delay
Relative to
Bypass Mode
These bits control the Clock Output Multiplexer for each clock
output. Changing between the different modes changes the
blocks in the signal path and therefore incurs a delay relative
to the bypass mode. The different MUX modes and associ-
ated delays are listed below.
0
1
Bypassed (default)
Divided
0 ps
100 ps
400 ps
(In addition to the
programmed
delay)
2
3
Delayed
500 ps
(In addition to the
programmed
delay)
Divided and
Delayed
13
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2.3.3 CLKoutX_DIV[7:0] -- Clock Output Dividers
CLKoutX_DLY[3:0]
Delay (ps)
2100
These bits control the clock output divider value. In order for
these dividers to be active, the respective CLKoutX_MUX
(See 2.3.2) bit must be set to either "Divided" or "Divided and
Delayed" mode. After all the dividers are programed, the
SYNC* pin must be used to ensure that all edges of the clock
outputs are aligned (See 1.7). By adding the divider block to
the output path a fixed delay of approximately 100 ps is in-
curred.
14
15
2250
2.3.5 CLKoutX_EN bit -- Clock Output Enables
These bits control whether an individual clock output is en-
abled or not. If the EN_CLKout_Global bit (See 2.5.4) is set
to zero or if GOE pin is held low, all CLKoutX_EN bit states
will be ignored and all clock outputs will be disabled. See 1.8
for more information on CLKout states.
The actual Clock Output Divide value is twice the binary value
programmed as listed in the table below.
CLKoutX_EN bit
Conditions
CLKoutX State
CLKoutX_DIV[7:0]
Clock Output
Divider value
0
EN_CLKout_Global Disabled (default)
bit = 1
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
1
1
.
0
0
1
1
0
0
.
0
1
0
1
0
1
.
Invalid
GOE pin = High / No
Connect 1
1
Enabled
2 (default)
4
6
2.4 REGISTER R11
This register only has one bit and only needs to be pro-
grammed in the case that the phase detector frequency is
greater than 20 MHz and digital lock detect is used. Other-
wise, it is automatically defaulted to the correct values.
8
10
...
1
1
1
1
1
1
1
1
510
2.4.1 DIV4
This bit divides the frequency presented to the digital lock de-
tect circuitry by 4. It is necessary to get a reliable output from
the digital lock detect output in the case of a phase detector
frequency greater than 20 MHz.
2.3.4 CLKoutX_DLY[3:0] -- Clock Output Delays
These bits control the delay stages for each clock output. In
order for these delays to be active, the respective
CLKoutX_MUX (See 2.3.2) bit must be set to either "Delayed"
or "Divided and Delayed" mode. By adding the delay block to
the output path a fixed delay of approximately 400 ps is in-
curred in addition to the delay shown in the table below.
DIV4
Digital Lock Detect Circuitry Mode
Not divided; Phase detector
0
frequency ≤ 20 MHz (default)
Divided by 4; Phase detector
CLKoutX_DLY[3:0]
Delay (ps)
0 (default)
150
1
0
1
frequency > 20 MHz
2.5 REGISTER R14
2
300
The LMK02000 requires register R14 to be programmed as
shown in the register map (see 2.2).
3
450
4
600
2.5.1 PLL_R[11:0] -- R Divider Value
5
750
These bits program the PLL R Divider and are programmed
in binary fashion.
6
900
7
1050
1200
1350
1500
1650
1800
1950
PLL_R[11:0]
PLL R Divide
Value
8
9
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
Invalid
10
11
12
13
1
2
...
10 (default)
...
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
0
.
1
.
0
.
1
1
1
1
1
1
1
1
1
1
1
1
4095
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14
2.5.2 PLL_MUX[3:0] -- Multiplexer Control for LD Pin
2.5.5 PLL_CP_TRI Bit -- PLL Charge Pump TRI-STATE
These bits set the output mode of the LD pin. The table below
lists several different modes.
This bit sets the PLL charge pump TRI-STATE.
PLL_CP_TRI
PLL Charge Pump
Normal operation (default)
TRI-STATE
PLL_MUX[3:0]
Output Type
Hi-Z
LD Pin Function
Disabled (default)
Logic High
0
1
0
1
2
3
Push-Pull
Push-Pull
Push-Pull
2.5.6 PLL_CP_POLBbit -- PLL Charge Pump Polarity
Logic Low
This bit sets the polarity of the charge pump to either negative
or positive. A negative charge pump is used with a VCO or
VCXO which decreases frequency with increasing tuning volt-
age. A positive charge pump is used with a VCO or VCXO
which increases frequency with increasing tuning voltage.
Digital Lock Detect
(Active High)
4
5
6
7
Push-Pull
Push-Pull
Digital Lock Detect
(Active Low)
PLL_CP_POL
PLL Charge Pump Polarity
Negative (default)
Positive
Analog Lock
Detect
0
1
Open Drain NMOS
Open Drain PMOS
Analog Lock
Detect
2.6 Register R15
Analog Lock
Detect
2.6.1 PLL_N[17:0] -- PLL N Divider
These bits program the divide value for the PLL N Divider.
The PLL N Divider precedes the PLL phase detector. The
VCO or VCXO frequency is calculated as, fVCO = fOSCin × PLL
N Divider / PLL R Divider. Since the PLL N divider is a pure
binary counter, there are no illegal divide values for PLL_N
[17:0] except for 0.
8
9
Invalid
Push-Pull
Push-Pull
N Divider Output/2
(50% Duty Cycle)
10
11
Invalid
R Divider Output/2
(50% Duty Cycle)
PLL_N[17:0]
PLL N
Divider
Value
12 to 15
Invalid
2.5.3 POWERDOWN Bit -- Device Power Down
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Invalid
This bit can power down the device. Enabling this bit powers
down the entire device and all blocks, regardless of the state
of any of the other bits or pins.
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
...
0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0
760
POWERDOWN bit
Mode
(default)
0
1
Normal Operation (default)
Entire Device Powered Down
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
...
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
262143
2.5.4 EN_CLKout_Global Bit -- Global Clock Output
Enable
2.6.2 PLL_CP_GAIN[1:0] -- PLL Charge Pump Gain
These bits set the charge pump gain of the PLL.
This bit overrides the individual CLKoutX_EN bits (See 2.3.5).
When this bit is set to 0, all clock outputs are disabled, re-
gardless of the state of any of the other bits or pins. See 1.8
for more information on CLKout states.
PLL_CP_GAIN[1:0]
Charge Pump Gain
0
1
2
3
1x (default)
4x
EN_CLKout_Global
bit
Clock Outputs
16x
32x
0
1
All Off
Normal Operation (default)
15
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3.0 Application Information
3.1 SYSTEM LEVEL DIAGRAM
The following shows the LMK02000 in a typical application.
In this setup the clock may be multiplied, reconditioned, and
redistributed.
20216570
FIGURE 1. Typical Application
3.2 BIAS PIN
3.3 LDO BYPASS
To properly use the device, bypass Bias (pin 36) with a low
leakage 1 µF capacitor connected to Vcc. This is important
for low noise performance.
To properly use the device, bypass LDObyp1 (pin 9) with a
10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF capacitor.
www.national.com
16
3.4 CURRENT CONSUMPTION / POWER DISSIPATION
CALCULATIONS
calculate estimated current consumption of the LMK02000.
Unless otherwise noted Vcc = 3.3 V, TA = 25 °C.
Due to the myriad of possible configurations the following ta-
ble serves to provide enough information to allow the user to
Table 3.4 - Block Current Consumption
Current
Consumption at
3.3 V (mA)
Power
Dissipated in
device (mW)
Power Dissipated in
LVPECL emitter
resistors (mW)
Block
Condition
Entire device,
core current
All outputs off; No LVPECL emitter resistors
connected
70
9
231
-
-
Low clock buffer The low clock buffer is enabled anytime one of
(internal) CLKout0 through CLKout3 are enabled
High clock buffer The high clock buffer is enabled anytime one of
29.7
9
29.7
58.7
72
-
-
(internal)
the CLKout4 through CLKout7 are enabled
LVDS output, bypass mode
17.8
40
LVPECL output, bypass mode (includes 120 Ω
emitter resistors)
60
Output buffers
LVPECL output, disabled mode (includes 120
17.4
0
38.3
0
19.1
-
Ω emitter resistors)
LVPECL output, disabled mode. No emitter
resistors placed; open outputs
Divide enabled, divide = 2
5.3
8.5
17.5
28.0
19.1
32.7
421.1
-
-
Divide circuitry
per output
Divide enabled, divide > 2
Delay enabled, delay < 8
5.8
-
Delay circuitry
per output
Delay enabled, delay > 7
9.9
-
Entire device
CLKout0 & CLKout4 enabled in bypass mode
145.8
60
From Table 3.4 the current consumption can be calculated in
any configuration. For example, the current for the entire de-
vice with 1 LVDS (CLKout0) & 1 LVPECL (CLKout4) output
in bypass mode can be calculated by adding up the following
blocks: core current, low clock buffer, high clock buffer, one
LVDS output buffer current, and one LVPECL output buffer
current. There will also be one LVPECL output drawing emit-
ter current, but some of the power from the current draw is
dissipated in the external 120 Ω resistors which doesn't add
to the power dissipation budget for the device. If delays or
divides are switched in, then the additional current for these
stages needs to be added as well.
& Vol typical specification. Therefore the power dissipated in
each emitter resistor is approximately (1.9 V)2 / 120 Ω = 30
mW. When the LVPECL output is disabled, the emitter resis-
tor voltage is ~1.07 V. Therefore the power dissipated in each
emitter resistor is approximately (1.07 V)2 / 120 Ω = 9.5 mW.
3.5 THERMAL MANAGEMENT
Power consumption of the LMK02000 can be high enough to
require attention to thermal management. For reliability and
performance reasons the die temperature should be limited
to a maximum of 125 °C. That is, as an estimate, TA (ambient
temperature) plus device power consumption times θJA
should not exceed 125 °C.
For power dissipated by the device, the total current entering
the device is multiplied by the voltage at the device minus the
power dissipated in any emitter resistors connected to any of
the LVPECL outputs. If no emitter resistors are connected to
the LVPECL outputs, this power will be 0 watts. For example,
in the case of 1 LVDS (CLKout0) & 1 LVPECL (CLKout4) op-
erating at 3.3 volts, we calculate 3.3 V × (70 + 9 + 9 + 17.8 +
40) mA = 3.3 V × 145.8 mA = 481.1 mW. Because the
LVPECL output (CLKout4) has the emitter resistors hooked
up and the power dissipated by these resistors is 60 mW, the
total device power dissipation is 481.1 mW - 60 mW = 421.1
mW.
The package of the device has an exposed pad that provides
the primary heat removal path as well as excellent electrical
grounding to the printed circuit board. To maximize the re-
moval of heat from the package a thermal land pattern in-
cluding multiple vias to a ground plane must be incorporated
on the PCB within the footprint of the package. The exposed
pad must be soldered down to ensure adequate heat con-
duction out of the package. A recommended land and via
pattern is shown in Figure 2. More information on soldering
LLP packages can be obtained at www.national.com.
When the LVPECL output is active, ~1.9 V is the average
voltage on each output as calculated from the LVPECL Voh
17
www.national.com
20216573
FIGURE 2.
To minimize junction temperature it is recommended that a
simple heat sink be built into the PCB (if the ground plane
layer is not exposed). This is done by including a copper area
of about 2 square inches on the opposite side of the PCB from
the device. This copper area may be plated or solder coated
to prevent corrosion but should not have conformal coating (if
possible), which could provide thermal insulation. The vias
shown in Figure 2 should connect these top and bottom cop-
per layers and to the ground layer. These vias act as “heat
pipes” to carry the thermal energy away from the device side
of the board to where it can be more effectively dissipated.
www.national.com
18
Physical Dimensions inches (millimeters) unless otherwise noted
Leadless Leadframe Package (Bottom View)
48 Pin LLP (SQA48A) Package
Order Number
Package Marking
Packing
LVDS Outputs
LVPECL
Outputs
LMK02000ISQ
K02000 I
K02000 I
250 Unit Tape and Reel
2500 Unit Tape and Reel
3
3
5
5
LMK02000ISQX
19
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相关型号：
LMK02000ISQX/NOPB
IC 800 MHz, OTHER CLOCK GENERATOR, QCC48, 7 X 7 MM, 0.8MM HEIGHT, LEAD FREE, LLP-48, Clock Generator
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