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LMK02002ISQX/NOPB [TI]

具有集成 PLL 和 4 个 LVPECL 输出的 1 至 800MHz 精密时钟分配器 | RHS | 48 | -40 to 85;
LMK02002ISQX/NOPB
型号： LMK02002ISQX/NOPB
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

具有集成 PLL 和 4 个 LVPECL 输出的 1 至 800MHz 精密时钟分配器 | RHS | 48 | -40 to 85

时钟 外围集成电路 晶体
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LMK02002  
www.ti.com  
SNAS418 –AUGUST 2007  
LMK02002 Precision Clock Conditioner with Integrated PLL  
Check for Samples: LMK02002  
1
FEATURES  
DESCRIPTION  
The LMK02002 precision clock conditioner combines  
the functions of jitter cleaning/reconditioning,  
multiplication, and distribution of a reference clock.  
The device integrates a high performance Integer-N  
Phase Locked Loop (PLL), and four LVPECL clock  
output distribution blocks.  
2
•
•
20 fs Additive Jitter  
Integrated Integer-N PLL with Outstanding  
Normalized Phase Noise Contribution of -224  
dBc/Hz  
•
Clock Output Frequency Range of 1 to 800  
MHz  
Each  
clock  
distribution  
block  
includes  
a
•
•
4 LVPECL Clock Outputs  
programmable divider,  
a
phase synchronization  
circuit, a programmable delay, a clock output mux,  
and an LVPECL output buffer. This allows multiple  
integer-related and phase-adjusted copies of the  
reference to be distributed to eight system  
components.  
Dedicated Divider and Delay Blocks on Each  
Clock Output  
•
•
•
Pin Compatible Family of Clocking Devices  
3.15 to 3.45 V Operation  
Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)  
The clock conditioner comes in a 48-pin WQFN  
package and is footprint compatible with other  
clocking devices in the same family.  
TARGET APPLICATIONS  
•
•
•
•
•
•
Data Converter Clocking  
Networking, SONET/SDH, DSLAM  
Wireless Infrastructure  
Medical  
Test and Measurement  
Military / Aerospace  
Functional Block Diagram  
OSCin  
OSCin*  
R Divider  
N Divider  
Phase  
Detector  
Charge  
Pump  
CPout  
Fin  
Fin*  
Distribution Path  
CLKout0  
CLKout0*  
Divider  
Mux  
Mux  
Mux  
Mux  
Delay  
Delay  
Delay  
Delay  
CLK  
mWire  
Port  
Control  
Registers  
DATA  
LE  
CLKout1  
CLKout1*  
Divider  
Divider  
Divider  
CLKout2  
CLKout2*  
GOE  
LD  
Device  
Control  
SYNC*  
CLKout3  
CLKout3*  
Clock Buffers  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007, Texas Instruments Incorporated  
 
LMK02002  
SNAS418 –AUGUST 2007  
www.ti.com  
Connection Diagram  
Figure 1. 48-Pin WQFN Package  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
GND  
NC  
1
2
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Bias  
Fin*  
Vcc1  
3
Fin  
CLKuWire  
DATAuWire  
LEuWire  
NC  
4
Vcc10  
CPout  
Vcc9  
Vcc8  
OSCin*  
OSCin  
SYNC*  
Vcc7  
GND  
5
WQFN-48  
Top Down View  
6
7
Vcc2  
8
LDObyp1  
LDObyp2  
GOE  
9
10  
11  
12  
DAP  
LD  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Pin Descriptions  
Pin #  
Pin Name  
I/O  
Description  
1, 25  
GND  
-
Ground  
2, 7, 14, 15, 17, 18, 20,  
21, 23, 24  
NC  
-
-
No Connection to these pins  
Power Supply  
3, 8, 13, 16, 19, 22, 26,  
30, 31, 33, 37, 40, 43, 46  
Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8,  
Vcc9, Vcc10, Vcc11, Vcc12, Vcc13, Vcc14  
4
5
CLKuWire  
DATAuWire  
LEuWire  
I
I
MICROWIRE Clock Input  
MICROWIRE Data Input  
MICROWIRE Latch Enable Input  
LDO Bypass  
6
I
9, 10  
11  
LDObyp1, LDObyp2  
GOE  
-
I
Global Output Enable  
12  
LD  
O
I
Lock Detect and Test Output  
Global Clock Output Synchronization  
27  
SYNC*  
28, 29  
32  
OSCin, OSCin*  
CPout  
I
Oscillator Clock Input; Must be AC coupled  
Charge Pump Output  
O
I
34, 35  
36  
Fin, Fin*  
Frequency Input; Must be AC coupled  
Bias Bypass  
Bias  
I
38, 39  
41, 42  
CLKout0, CLKout0*  
CLKout1, CLKout1*  
O
O
LVPECL Clock Output 0  
LVPECL Clock Output 1  
2
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LMK02002  
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SNAS418 –AUGUST 2007  
Pin Descriptions (continued)  
Pin #  
Pin Name  
CLKout2, CLKout2*  
CLKout3, CLKout3*  
DAP  
I/O  
O
O
-
Description  
LVPECL Clock Output 2  
44, 45  
47, 48  
DAP  
LVPECL Clock Output 3  
Die Attach Pad is Ground  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
(1)(2)(3)  
Absolute Maximum Ratings  
Parameter  
Symbol  
VCC  
VIN  
Ratings  
-0.3 to 3.6  
-0.3 to (VCC + 0.3)  
-65 to 150  
+260  
Units  
V
Power Supply Voltage  
Input Voltage  
V
Storage Temperature Range  
Lead Temperature (solder 4 s)  
Junction Temperature  
TSTG  
TL  
°C  
°C  
°C  
TJ  
125  
(1) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of  
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or  
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating  
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.  
(2) This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD  
protected work stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV.  
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.  
Recommended Operating Conditions  
Parameter  
Symbol  
Min  
-40  
Typ  
25  
Max  
85  
Units  
°C  
Ambient Temperature  
TA  
Power Supply Voltage  
VCC  
3.15  
3.3  
3.45  
V
Package Thermal Resistance  
Package  
θJA  
27.4° C/W  
θJ-PAD (Thermal Pad)  
(1)  
48-Lead WQFN  
5.8° C/W  
(1) Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These  
vias play a key role in improving the thermal performance of the WQFN. It is recommended that the maximum number of vias be used in  
the board layout.  
Copyright © 2007, Texas Instruments Incorporated  
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SNAS418 –AUGUST 2007  
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(1)  
Electrical Characteristics  
(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most  
likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product  
characterization and are not specified).  
Symbol  
Parameter  
Conditions  
Current Consumption  
Min  
Typ  
Max  
Units  
Entire device; CLKout0 & CLKout3  
enabled in Bypass Mode  
159  
(2)  
ICC  
Power Supply Current  
mA  
mA  
Entire device; All Outputs Off (no  
emitter resistors placed)  
70  
1
ICCPD  
Power Down Current  
POWERDOWN = 1  
Reference Oscillator  
Reference Oscillator Input Frequency  
Range for Square Wave  
fOSCin square  
VOSCinsquare  
1
200  
1.6  
MHz  
Vpp  
AC coupled; Differential (VOD  
)
Square Wave Input Voltage for OSCin and  
OSCin*  
0.2  
Frequency Input  
fFin  
Frequency Input Frequency Range  
Frequency Input Slew Rate  
1
800  
MHz  
V/ns  
%
(3)(4)  
SLEWFin  
DUTYFin  
PFin  
See  
0.5  
40  
Frequency Input Duty Cycle  
60  
8
Input Power Range for Fin or Fin*  
AC coupled  
-13  
dBm  
PLL  
fCOMP  
Phase Detector Frequency  
40  
MHz  
µA  
VCPout = Vcc/2, PLL_CP_GAIN = 1x  
VCPout = Vcc/2, PLL_CP_GAIN = 4x  
VCPout = Vcc/2, PLL_CP_GAIN = 16x  
VCPout = Vcc/2, PLL_CP_GAIN = 32x  
VCPout = Vcc/2, PLL_CP_GAIN = 1x  
VCPout = Vcc/2, PLL_CP_GAIN = 4x  
VCPout = Vcc/2, PLL_CP_GAIN = 16x  
VCPout = Vcc/2, PLL_CP_GAIN = 32x  
0.5 V < VCPout < Vcc - 0.5 V  
100  
400  
ISRCECPout  
Charge Pump Source Current  
1600  
3200  
-100  
-400  
-1600  
-3200  
2
ISINKCPout  
Charge Pump Sink Current  
μA  
ICPoutTRI  
Charge Pump TRI-STATE Current  
10  
nA  
%
Magnitude of Charge Pump  
Sink vs. Source Current Mismatch  
VCPout = Vcc / 2  
TA = 25°C  
ICPout%MIS  
3
4
4
Magnitude of Charge Pump  
Current vs. Charge Pump Voltage Variation TA = 25°C  
0.5 V < VCPout < Vcc - 0.5 V  
ICPoutVTUNE  
ICPoutTEMP  
%
%
Magnitude of Charge Pump Current vs.  
Temperature Variation  
(5)  
PLL_CP_GAIN = 1x  
PLL_CP_GAIN = 32x  
-117  
-122  
PLL 1/f Noise at 10 kHz Offset  
PN10kHz  
dBc/Hz  
Normalized to 1 GHz Output Frequency  
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as  
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and  
are not ensured.  
(2) See CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS for more current consumption / power dissipation  
calculation information.  
(3) For all frequencies the slew rate, SLEWFin, is measured between 20% and 80%.  
(4) Specification is ensured by characterization and is not tested in production.  
(5) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker  
noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10  
kHz) - 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise,  
L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high phase detector frequency and a  
clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference  
oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of LPLL_flicker(f)  
and LPLL_flat(f).  
4
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LMK02002  
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SNAS418 –AUGUST 2007  
Electrical Characteristics (1) (continued)  
(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most  
likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product  
characterization and are not specified).  
Symbol  
Parameter  
Conditions  
PLL_CP_GAIN = 1x  
PLL_CP_GAIN = 32x  
Min  
Typ  
-219  
-224  
Max  
Units  
PN1Hz  
Normalized Phase Noise Contribution(6)  
dBc/Hz  
Clock Distribution Section (7) - LVPECL Clock Outputs (CLKout0 to CLKout3)  
CLKoutX_MUX =  
Bypass  
20  
75  
RL = 100 Ω  
Distribution Path =  
800 MHz  
Bandwidth =  
12 kHz to 20 MHz  
(7)  
CLKoutX_MUX =  
Divided  
CLKoutX_DIV =  
4
JitterADD  
Additive RMS Jitter  
fs  
Equal loading and identical clock  
configuration  
Termination = 50 Ω to Vcc - 2 V  
(4)  
tSKEW  
CLKoutX to CLKoutY  
-30  
±3  
30  
ps  
V
Vcc -  
0.98  
VOH  
Output High Voltage  
Output Low Voltage  
Termination = 50 Ω to Vcc - 2 V  
CLKoutX output frequency = 200 MHz  
Vcc -  
1.8  
VOL  
VOD  
V
Differential Output Voltage  
660  
2.0  
810  
965  
mV  
(8)  
Digital LVTTL Interfaces  
VIH  
VIL  
IIH  
High-Level Input Voltage  
Low-Level Input Voltage  
High-Level Input Current  
Low-Level Input Current  
Vcc  
0.8  
5.0  
5.0  
V
V
VIH = Vcc  
VIL = 0  
-5.0  
µA  
µA  
IIL  
-40.0  
Vcc -  
0.4  
VOH  
VOL  
High-Level Output Voltage  
Low-Level Output Voltage  
IOH = +500 µA  
V
V
IOL = -500 µA  
0.4  
(9)  
Digital MICROWIRE Interfaces  
VIH  
VIL  
IIH  
High-Level Input Voltage  
Low-Level Input Voltage  
High-Level Input Current  
Low-Level Input Current  
1.6  
Vcc  
0.4  
5.0  
5.0  
V
V
VIH = Vcc  
-5.0  
-5.0  
µA  
µA  
IIL  
VIL = 0  
MICROWIRE Timing  
See Data Input Timing  
See Data Input Timing  
See Data Input Timing  
See Data Input Timing  
See Data Input Timing  
See Data Input Timing  
See Data Input Timing  
tCS  
Data to Clock Set Up Time  
Data to Clock Hold Time  
Clock Pulse Width High  
Clock Pulse Width Low  
25  
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCH  
tCWH  
tCWL  
tES  
25  
25  
25  
25  
25  
Clock to Enable Set Up Time  
Enable to Clock Set Up Time  
Enable Pulse Width High  
tCES  
tEWH  
(6) A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, LPLL_flat(f), of the PLL and is defined  
as PN1Hz = LPLL_flat(f) – 20log(N) – 10log(fCOMP). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a  
1 Hz Bandwidth and fCOMP is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). To measure  
LPLL_flat(f) the offset frequency, f, must be chosen sufficiently smaller then the loop bandwidth of the PLL, and yet large enough to avoid  
a substantial noise contribution from the reference and flicker noise. LPLL_flat(f) can be masked by the reference oscillator performance if  
a low power or noisy source is used.  
(7) The Clock Distribution Section includes all parts of the device except the PLL section. Typical Additive Jitter specifications apply to the  
clock distribution section only.  
(8) Applies to GOE, LD, and SYNC*.  
(9) Applies to CLKuWire, DATAuWire, and LEuWire.  
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Serial Data Timing Diagram  
MSB  
D27  
LSB  
A0  
DATAuWire  
CLKuWire  
D26  
D25  
D24  
D23  
D0  
A3  
A2  
A1  
t
t
CWH  
CS  
t
ES  
t
t
CH  
CES  
t
CWL  
LEuWire  
t
EWH  
Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the  
CLKuWire signal. On the rising edge of the LEuWire signal, the data is sent from the shift register to the  
addressed register determined by the LSB bits. After the programming is complete the CLKuWire, DATAuWire,  
and LEuWire signals should be returned to a low state.  
Charge Pump Current Specification Definitions  
I1 = Charge Pump Sink Current at VCPout = Vcc - ΔV  
I2 = Charge Pump Sink Current at VCPout = Vcc/2  
I3 = Charge Pump Sink Current at VCPout = ΔV  
I4 = Charge Pump Source Current at VCPout = Vcc - ΔV  
I5 = Charge Pump Source Current at VCPout = Vcc/2  
I6 = Charge Pump Source Current at VCPout = ΔV  
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.  
Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage  
6
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Charge Pump Current Specification Definitions (continued)  
Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch  
Charge Pump Output Current Magnitude Variation vs. Temperature  
Functional Description  
The LMK02002 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication,  
and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop  
(PLL), and four LVPECL clock output distribution blocks.  
Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable  
delay, a clock output mux, and an LVPECL output buffer. This allows multiple integer-related and phase-adjusted  
copies of the reference to be distributed to eight system components.  
The clock conditioner comes in a 48-pin WQFN package and is footprint compatible with other clocking devices  
in the same family.  
BIAS PIN  
To properly use the device, bypass Bias (pin 36) with a low leakage 1 µF capacitor connected to Vcc. This is  
important for low noise performance.  
LDO BYPASS  
To properly use the device, bypass LDObyp1 (pin 9) with a 10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF  
capacitor.  
OSCILLATOR INPUT PORT (OSCin, OSCin*)  
The purpose of OSCin is to provide the PLL with a reference signal. The OSCin port must be AC coupled, refer  
to the System Level Diagram in the Application Information section. The OSCin port may be driven single  
endedly by AC grounding OSCin* with a 0.1 µF capacitor.  
FREQUENCY INPUT PORT (Fin, Fin*)  
The purpose of Fin is to provide the PLL with a feedback signal from an external oscillator. The Fin port may be  
driven single endedly by AC grounding Fin*.  
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CLKout DELAYS  
Each individual clock output includes a delay adjustment. Clock output delay registers (CLKoutX_DLY) support a  
150 ps step size and range from 0 to 2250 ps of total delay.  
LVPECL OUTPUTS  
Each LVPECL output may be disabled individually by programming the CLKoutX_EN bits. All the outputs may be  
disabled simultaneously by pulling the GOE pin low or programming EN_CLKout_Global to 0.  
GLOBAL CLOCK OUTPUT SYNCHRONIZATION  
The SYNC* pin synchronizes the clock outputs. When the SYNC* pin is held in a logic low state, the divided  
outputs are also held in a logic low state. When the SYNC* pin goes high, the divided clock outputs are activated  
and will transition to a high state simultaneously. Clocks in the bypassed state are not affected by SYNC* and  
are always synchronized with the divided outputs.  
The SYNC* pin must be held low for greater than one clock cycle of the Frequency Input port, also known as the  
distribution path. Once this low event has been registered, the outputs will not reflect the low state for four more  
cycles. Similarly once the SYNC* pin becomes high, the outputs will not simultaneously transition high until four  
more distribution path clock cycles have passed. See the timing diagram below for further detail. In the timing  
diagram below the clocks are programmed as CLKout0_MUX = Bypassed, CLKout1_MUX = Divided,  
CLKout1_DIV = 2, CLKout2_MUX = Divided, and CLKout2_DIV = 4.  
SYNC* Timing Diagram  
Distribution  
Path  
SYNC*  
CLKout0  
CLKout1  
CLKout2  
The SYNC* pin provides an internal pull-up resistor as shown on the functional block diagram. If the SYNC* pin  
is not terminated externally the clock outputs will operate normally. If the SYNC* function is not used, clock  
output synchronization is not specified.  
CLKout OUTPUT STATES  
Each clock output may be individually enabled with the CLKoutX_EN bits. Each individual output enable control  
bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit  
(EN_CLKout_Global).  
All clock outputs can be disabled simultaneously if the GOE pin is pulled low by an external signal or  
EN_CLKout_Global is set to 0.  
CLKoutX  
_EN bit  
EN_CLKout  
_Global bit  
GOE pin  
Clock X Output State  
1
1
Low  
Low  
Off  
Don't care  
0
Don't care  
1
Don't care  
0
1
Don't care  
Off  
High / No Connect  
Enabled  
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When an LVPECL output is in the Off state, the outputs are at a voltage of approximately 1 volt.  
GLOBAL OUTPUT ENABLE AND LOCK DETECT  
The GOE pin provides an internal pull-up resistor. If it is not terminated externally, the clock output states are  
determined by the Clock Output Enable bits (CLKoutX_EN) and the EN_CLKout_Global bit.  
By programming the PLL_MUX register to Digital Lock Detect Active High (See PLL_MUX[3:0] -- Multiplexer  
Control for LD Pin), the Lock Detect (LD) pin can be connected to the GOE pin in which case all outputs are set  
low automatically if the synthesizer is not locked.  
POWER ON RESET  
When supply voltage to the device increases monotonically from ground to Vcc, the power on reset circuit sets  
all registers to their default values, see RESET bit -- R0 only for more information on default register values.  
Voltage should be applied to all Vcc pins simultaneously.  
General Programming Information  
The LMK02002 device is programmed using several 32-bit registers which control the device's operation. The  
registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0] form the address field.  
The remaining 28 bits form the data field DATA[27:0].  
During programming, LEuWire is low and serial data is clocked in on the rising edge of clock (MSB first). When  
LEuWire goes high, data is transferred to the register bank selected by the address field. Only registers R0 to  
R7, R11, R14, and R15 need to be programmed for proper device operation.  
It is required to program register R14.  
RECOMMENDED PROGRAMMING SEQUENCE  
The recommended programming sequence involves programming R0 with the reset bit set (RESET = 1) to  
ensure the device is in a default state. It is not necessary to program R0 again. Registers are programmed in  
order with R15 being the last register programmed. An example programming sequence is shown below.  
•
•
•
•
Program R0 with the reset bit set (RESET = 1). This ensures the device is in a default state.  
Program R4 to R7 as necessary with desired clocks with appropriate enable, mux, divider, and delay settings.  
Program R11 with DIV4 setting if necessary.  
Program R14 with global clock output bit, power down setting, PLL mux setting, and PLL R divider. It is  
required to program register R14.  
–
R14 must be programmed in accordance with the register map as shown in the register map (see  
Table 1).  
•
Program R15 with PLL charge pump gain, and PLL N divider.  
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Table 1. LMK02002 REGISTER MAP  
Re  
gist 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  
er  
9
8
7
6
5
4
3
2
1
0
Data [27:0]  
A3 A2 A1 A0  
RE  
R0 SE  
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CL  
Kou  
t0_  
EN  
CLKout0  
_MUX  
[1:0]  
CLKout0_DIV  
[7:0]  
CLKout0_DLY  
[3:0]  
R4  
R5  
R6  
0
0
0
0
1
0
0
CL  
Kou  
t1_  
EN  
CLKout1  
_MUX  
[1:0]  
CLKout1_DIV  
[7:0]  
CLKout1_DLY  
[3:0]  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
CL  
Kou  
t2_  
EN  
CLKout2  
_MUX  
[1:0]  
CLKout2_DIV  
[7:0]  
CLKout2_DLY  
[3:0]  
CL  
Kou  
t3_  
EN  
CLKout3  
_MUX  
[1:0]  
CLKout3_DIV  
[7:0]  
CLKout3_DLY  
[3:0]  
R7  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
DIV  
4
R11  
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EN  
_CL  
Kou  
t_Gl  
oba  
l
PO TRI PLL  
WE _C  
RD ST P_  
OW AT PO  
-
PLL_MUX  
[3:0]  
PLL_R  
[11:0]  
R14  
R15  
0
0
1
0
0
1
1
1
1
1
1
0
1
N
E
L
PLL_  
CP_  
GAIN  
[1:0]  
PLL_N  
[17:0]  
0
0
0
0
0
0
0
10  
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REGISTER R4 to R7  
Registers R4 through R7 control the eight clock outputs. Register R4 controls CLKout0, Register R5 controls  
CLKout1, and so on. There is one additional bit in register R0 called RESET. Aside from this, the functions of  
these bits are identical. The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the  
actual clock output which may be from 0 to 3.  
RESET bit -- R0 only  
This bit is only in register R0. The use of this bit is optional and it should be set to '0' if not used. Setting this bit  
to a '1' forces all registers to their power on reset condition and therefore automatically clears this bit. If this bit is  
set, all other R0 bits are ignored and R0 needs to be programmed again if used with its proper values and  
RESET = 0.  
Default  
Bit Value  
Bit  
Location  
Bit Name  
Bit State  
Bit Description  
Register  
RESET  
0
0
No reset, normal operation  
Bypassed  
Reset to power on defaults  
CLKoutX mux mode  
R0  
31  
18:17  
16  
CLKoutX_MUX  
CLKoutX_EN  
CLKoutX_DIV  
CLKoutX_DLY  
DIV4  
0
Disabled  
CLKoutX enable  
R4 to R7  
R11  
1
Divide by 2  
CLKoutX clock divide  
CLKoutX clock delay  
Phase Detector Frequency  
Global clock output enable  
Device power down  
15:8  
7:4  
0
0 ps  
0
PDF ≤ 20 MHz  
Normal - CLKouts normal  
Normal - Device active  
Normal - PLL active  
Negative Polarity CP  
Disabled  
15  
EN_CLKout_Global  
POWERDOWN  
PLL_CP_TRI  
PLL_CP_POL  
PLL_MUX  
1
27  
0
26  
0
TRI-STATE PLL charge pump  
Polarity of charge pump  
Multiplexer control for LD pin  
PLL R divide value  
25  
R14  
R15  
0
24  
0
23:20  
19:8  
31:30  
25:8  
PLL_R  
10  
0
R divider = 10  
100 uA  
PLL_CP_GAIN  
PLL_N  
Charge pump current  
PLL N divide value  
760  
N divider = 760  
CLKoutX_MUX[1:0] -- Clock Output Multiplexers  
These bits control the Clock Output Multiplexer for each clock output. Changing between the different modes  
changes the blocks in the signal path and therefore incurs a delay relative to the bypass mode. The different  
MUX modes and associated delays are listed below.  
CLKoutX_MUX[1:0]  
Mode  
Bypassed (default)  
Divided  
Added Delay Relative to Bypass Mode  
0
1
0 ps  
100 ps  
400 ps  
2
3
Delayed  
(In addition to the programmed delay)  
500 ps  
Divided and Delayed  
(In addition to the programmed delay)  
CLKoutX_DIV[7:0] -- Clock Output Dividers  
These bits control the clock output divider value. In order for these dividers to be active, the respective  
CLKoutX_MUX (See CLKoutX_MUX[1:0] -- Clock Output Multiplexers) bit must be set to either "Divided" or  
"Divided and Delayed" mode. After all the dividers are programed, the SYNC* pin must be used to ensure that all  
edges of the clock outputs are aligned (See GLOBAL CLOCK OUTPUT SYNCHRONIZATION). The Clock  
Output Dividers follow the VCO Divider so the final clock divide for an output is VCO Divider × Clock Output  
Divider. By adding the divider block to the output path a fixed delay of approximately 100 ps is incurred.  
The actual Clock Output Divide value is twice the binary value programmed as listed in the table below.  
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CLKoutX_DIV[7:0]  
Clock Output Divider value  
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
1
1
.
0
0
1
1
0
0
.
0
1
0
1
0
1
.
Invalid  
2 (default)  
4
6
8
10  
...  
1
1
1
1
1
1
1
1
510  
CLKoutX_DLY[3:0] -- Clock Output Delays  
These bits control the delay stages for each clock output. In order for these delays to be active, the respective  
CLKoutX_MUX (See CLKoutX_MUX[1:0] -- Clock Output Multiplexers) bit must be set to either "Delayed" or  
"Divided and Delayed" mode. By adding the delay block to the output path a fixed delay of approximately 400 ps  
is incurred in addition to the delay shown in the table below.  
CLKoutX_DLY[3:0]  
Delay (ps)  
0 (default)  
150  
0
1
2
300  
3
450  
4
600  
5
750  
6
900  
7
1050  
1200  
1350  
1500  
1650  
1800  
1950  
2100  
2250  
8
9
10  
11  
12  
13  
14  
15  
CLKoutX_EN bit -- Clock Output Enables  
These bits control whether an individual clock output is enabled or not. If the EN_CLKout_Global bit (See  
EN_CLKout_Global bit -- Global Clock Output Enable) is set to zero or if GOE pin is held low, all CLKoutX_EN  
bit states will be ignored and all clock outputs will be disabled. See CLKout OUTPUT STATES for more  
information on CLKout states.  
CLKoutX_EN bit  
Conditions  
CLKoutX State  
Disabled (default)  
Enabled  
0
1
EN_CLKout_Global bit = 1  
GOE pin = High / No Connect 1  
REGISTER R11  
This register only has one bit and only needs to be programmed in the case that the phase detector frequency is  
greater than 20 MHz and digital lock detect is used. Otherwise, it is automatically defaulted to the correct values.  
DIV4  
This bit divides the frequency presented to the digital lock detect circuitry by 4. It is necessary to get a reliable  
output from the digital lock detect output in the case of a phase detector frequency greater than 20 MHz.  
12  
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DIV4  
Digital Lock Detect Circuitry Mode  
0
1
Not divided; Phase detector frequency ≤ 20 MHz (default)  
Divided by 4; Phase detector frequency > 20 MHz  
REGISTER R14  
The LMK02002 requires register R14 to be programmed as shown in the register map (see Table 1).  
PLL_R[11:0] -- R Divider Value  
These bits program the PLL R Divider and are programmed in binary fashion.  
PLL_R[11:0]  
PLL R Divide Value  
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
Invalid  
1
2
...  
10 (default)  
...  
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
0
.
1
.
0
.
1
1
1
1
1
1
1
1
1
1
1
1
4095  
PLL_MUX[3:0] -- Multiplexer Control for LD Pin  
These bits set the output mode of the LD pin. The table below lists several different modes.  
PLL_MUX[3:0]  
Output Type  
Hi-Z  
LD Pin Function  
Disabled (default)  
0
1
Push-Pull  
Logic High  
2
Push-Pull  
Logic Low  
3
Push-Pull  
Digital Lock Detect (Active High)  
Digital Lock Detect (Active Low)  
Analog Lock Detect  
Analog Lock Detect  
Analog Lock Detect  
4
Push-Pull  
5
Push-Pull  
6
Open Drain NMOS  
Open Drain PMOS  
7
8
9
Invalid  
Invalid  
Invalid  
Push-Pull  
Push-Pull  
N Divider Output/2 (50% Duty Cycle)  
R Divider Output/2 (50% Duty Cycle)  
10  
11  
12 to 15  
POWERDOWN bit -- Device Power Down  
This bit can power down the device. Enabling this bit powers down the entire device and all blocks, regardless of  
the state of any of the other bits or pins.  
POWERDOWN bit  
Mode  
0
1
Normal Operation (default)  
Entire Device Powered Down  
EN_CLKout_Global bit -- Global Clock Output Enable  
This bit overrides the individual CLKoutX_EN bits (See CLKoutX_EN bit -- Clock Output Enables). When this bit  
is set to 0, all clock outputs are disabled, regardless of the state of any of the other bits or pins. See CLKout  
OUTPUT STATES for more information on CLKout states.  
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EN_CLKout_Global bit  
Clock Outputs  
All Off  
0
1
Normal Operation (default)  
PLL_CP_TRI bit -- PLL Charge Pump TRI-STATE  
This bit sets the PLL charge pump TRI-STATE.  
PLL_CP_TRI  
PLL Charge Pump  
Normal operation (default)  
TRI-STATE  
0
1
PLL_CP_POL bit -- PLL Charge Pump Polarity  
This bit sets the polarity of the charge pump to either negative or positive. A negative charge pump is used with a  
VCO or VCXO which decreases frequency with increasing tuning voltage. A positive charge pump is used with a  
VCO or VCXO which increases frequency with increasing tuning voltage.  
PLL_CP_POL  
PLL Charge Pump Polarity  
Negative (default)  
Positive  
0
1
Register R15  
PLL_N[17:0] -- PLL N Divider  
These bits program the divide value for the PLL N Divider. The PLL N Divider follows the VCO Divider and  
precedes the PLL phase detector. Since the VCO Divider is also in the feedback path from the VCO to the PLL  
Phase Detector, the total N divide value, NTotal, is also influenced by the VCO Divider value. NTotal = PLL N  
Divider × VCO Divider. The VCO frequency is calculated as, fVCO = fOSCin × PLL N Divider × VCO Divider / PLL R  
Divider. Since the PLL N divider is a pure binary counter, there are no illegal divide values for PLL_N[17:0]  
except for 0.  
PLL_N[17:0]  
PLL N Divider Value  
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
Invalid  
1
...  
760 (default)  
...  
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
0
.
1
.
1
.
1
.
1
.
1
.
0
.
0
.
0
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
262143  
PLL_CP_GAIN[1:0] -- PLL Charge Pump Gain  
These bits set the charge pump gain of the PLL.  
PLL_CP_GAIN[1:0]  
Charge Pump Gain  
0
1
2
3
1x (default)  
4x  
16x  
32x  
14  
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APPLICATION INFORMATION  
SYSTEM LEVEL DIAGRAM  
The following shows the LMK02002 in a typical application. In this setup the clock may be multiplied,  
reconditioned, and redistributed.  
Vcc  
100Ö  
1 mF  
0.1 mF  
0.1 mF  
0.1 mF  
0.1 mF  
OSCin  
CLKout0  
CLKout0*  
100Ö  
OSCin*  
CLKout1  
CLKout1*  
CLKout2  
CLKout2*  
To System  
LEuWire  
CLKuWire  
CLKout3  
CLKout3*  
DATAuWire  
SYNC*  
To Host  
LMK02002  
LD  
(optional)  
GOE  
LDObyp1  
LDObyp2  
10 mF  
0.1 mF  
Figure 2. Typical Application  
BIAS PIN  
To properly use the device, bypass Bias (pin 36) with a low leakage 1 µF capacitor connected to Vcc. This is  
important for low noise performance.  
LDO BYPASS  
To properly use the device, bypass LDObyp1 (pin 9) with a 10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF  
capacitor.  
CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS  
Due to the myriad of possible configurations the following table serves to provide enough information to allow the  
user to calculate estimated current consumption of the LMK02002. Unless otherwise noted Vcc = 3.3 V, TA = 25  
°C.  
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Table 2. Block Current Consumption  
Power  
Current  
Consumption at  
Power  
Dissipated in  
device (mW)  
Dissipated in  
LVPECL emitter  
resistors (mW)  
Block  
Condition  
3.3 V (mA)  
Entire device,  
core current  
All outputs off; No LVPECL emitter resistors connected  
70  
9
231  
29.7  
72  
-
-
Clock buffers  
(internal)  
The low clock buffer is enabled anytime one of CLKout0  
through CLKout3 are enabled  
LVPECL output, bypass mode (includes 120 Ω emitter  
resistors)  
40  
17.4  
0
60  
19.1  
-
LVPECL output, disabled mode (includes 120 Ω emitter  
resistors)  
Output buffers  
38.3  
0
LVPECL output, disabled mode. No emitter resistors  
placed; open outputs  
Divide enabled, divide = 2  
5.3  
8.5  
5.8  
9.9  
159  
17.5  
28.0  
19.1  
32.7  
404.7  
-
Divide circuitry  
per output  
Divide enabled, divide > 2  
-
Delay enabled, delay < 8  
-
-
Delay circuitry per  
output  
Delay enabled, delay > 7  
Entire device  
CLKout0 & CLKout3 enabled in bypass mode  
120  
From Table 2 the current consumption can be calculated in any configuration. For example, the current for the  
entire device with two LVPECL (CLKout0 and CLKout3) outputs in bypass mode can be calculated by adding up  
the following blocks: core current, clock buffers, and two LVPECL output buffer currents. There will also be two  
LVPECL outputs drawing emitter current, but some of the power from the current draw is dissipated in the  
external 120 Ω resistors which doesn't add to the power dissipation budget for the device. If delays or divides are  
switched in, then the additional current for these stages needs to be added as well.  
For power dissipated by the device, the total current entering the device is multiplied by the voltage at the device  
minus the power dissipated in any emitter resistors connected to any of the LVPECL outputs. If no emitter  
resistors are connected to the LVPECL outputs, this power will be 0 watts. For example, in the case of two  
LVPECL (CLKout0 and CLKout3) operating at 3.3 volts, we calculate 3.3 V × (70 + 9 + 40 + 40) mA = 3.3 V ×  
159 mA = 524.7 mW. Because the LVPECL outputs have emitter resistors hooked up and the power dissipated  
by these resistors is 60 mW for each clock, the total device power dissipation is 524.7 mW - 120 mW = 404.7  
mW.  
When an LVPECL output is active, ~1.9 V is the average voltage on each output as calculated from the LVPECL  
VOH & VOL typical specification. Therefore the power dissipated in each emitter resistor is approximately (1.9 V)2 /  
120 Ω = 30 mW. When an LVPECL output is disabled, the emitter resistor voltage is ~1.07 V. Therefore the  
power dissipated in each emitter resistor is approximately (1.07 V)2 / 120 Ω = 9.5 mW.  
THERMAL MANAGEMENT  
Power consumption of the LMK02002 can be high enough to require attention to thermal management. For  
reliability and performance reasons the die temperature should be limited to a maximum of 125 °C. That is, as an  
estimate, TA (ambient temperature) plus device power consumption times θJA should not exceed 125 °C.  
The package of the device has an exposed pad that provides the primary heat removal path as well as excellent  
electrical grounding to the printed circuit board. To maximize the removal of heat from the package a thermal  
land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the  
package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A  
recommended land and via pattern is shown in Figure 3. More information on soldering WQFN packages can be  
obtained at www.ti.com.  
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5.0 mm, min  
0.33 mm, typ  
1.2 mm, typ  
Figure 3.  
To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground  
plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite  
side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but  
should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in  
Figure 3 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat  
pipes” to carry the thermal energy away from the device side of the board to where it can be more effectively  
dissipated.  
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PACKAGE OPTION ADDENDUM  
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10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
LMK02002ISQ/NOPB  
LMK02002ISQX/NOPB  
ACTIVE  
ACTIVE  
WQFN  
WQFN  
RHS  
RHS  
48  
48  
250  
RoHS & Green  
SN  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
-40 to 85  
-40 to 85  
K02002 I  
K02002 I  
2500 RoHS & Green  
SN  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Aug-2022  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
LMK02002ISQ/NOPB  
LMK02002ISQX/NOPB  
WQFN  
WQFN  
RHS  
RHS  
48  
48  
250  
178.0  
330.0  
16.4  
16.4  
7.3  
7.3  
7.3  
7.3  
1.3  
1.3  
12.0  
12.0  
16.0  
16.0  
Q1  
Q1  
2500  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Aug-2022  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
LMK02002ISQ/NOPB  
LMK02002ISQX/NOPB  
WQFN  
WQFN  
RHS  
RHS  
48  
48  
250  
208.0  
356.0  
191.0  
356.0  
35.0  
35.0  
2500  
Pack Materials-Page 2  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, regulatory or other requirements.  
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an  
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license  
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you  
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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with  
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2023, Texas Instruments Incorporated  

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