LMK03033CISQX [NSC]
Precision Clock Conditioner with Integrated VCO; 精密时钟调节器集成VCO
| 型号： | LMK03033CISQX |
| 厂家： | 
National Semiconductor |
| 描述： | Precision Clock Conditioner with Integrated VCO |
| 文件： | 总30页 (文件大小：654K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 23, 2009
LMK03000 Family
Precision Clock Conditioner with Integrated VCO
General Description
Features
The LMK03000 family of precision clock conditioners com-
bine the functions of jitter cleaning/reconditioning, multiplica-
tion, and distribution of a reference clock. The devices
integrate a Voltage Controlled Oscillator (VCO), a high per-
formance Integer-N Phase Locked Loop (PLL), a partially
integrated loop filter, and up to eight outputs in various LVDS
and LVPECL combinations.
Integrated VCO with very low phase noise floor
■
■
Integrated Integer-N PLL with outstanding normalized
phase noise contribution of -224 dBc/Hz
VCO divider values of 2 to 8 (all divides)
Channel divider values of 1, 2 to 510 (even divides)
LVDS and LVPECL clock outputs
■
■
■
■
■
■
■
■
■
The VCO output is optionally accessible on the Fout port. In-
ternally, the VCO output goes through a VCO Divider to feed
the various clock distribution blocks.
Partially integrated loop filter
Dedicated divider and delay blocks on each clock output
Pin compatible family of clocking devices
3.15 to 3.45 V operation
Each clock distribution block includes a programmable di-
vider, a phase synchronization circuit, a programmable delay,
a clock output mux, and an LVDS or LVPECL output buffer.
This allows multiple integer-related and phase-adjusted
copies of the reference to be distributed to eight system com-
ponents.
Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
200 fs RMS Clock generator performance (10 Hz to 20
MHz) with a clean input clock
The clock conditioners come in a 48-pin LLP package and are
footprint compatible with other clocking devices in the same
family.
VCO
Device
Outputs
Tuning Range RMS Jitter
(MHz)
(fs)
400
800
1200
400
800
1200
500
800
LMK03000C
LMK03000
LMK03000D
LMK03001C
LMK03001
LMK03001D
LMK03033C
LMK03033
Target Applications
1185 - 1296
Data Converter Clocking
■
■
■
■
■
■
3 LVDS
5 LVPECL
Networking, SONET/SDH, DSLAM
Wireless Infrastructure
1470 - 1570
1843 - 2160
Medical
Test and Measurement
Military / Aerospace
4 LVDS
4 LVPECL
System Diagram
20211440
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2009 National Semiconductor Corporation
202114
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Functional Block Diagram
20211401
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2
Connection Diagram
48-Pin LLP Package
20211402
3
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Pin Descriptions
Pin #
Pin Name
GND
I/O
-
Description
1, 25
Ground
2
Fout
O
Internal VCO Frequency Output
3, 8, 13, 16, 19, 22,
26, 30, 31, 33, 37,
40, 43, 46
Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8, Vcc9, Vcc10,
Vcc11, Vcc12, Vcc13, Vcc14
-
Power Supply
4
5
CLKuWire
DATAuWire
LEuWire
I
I
MICROWIRE Clock Input
MICROWIRE Data Input
MICROWIRE Latch Enable Input
No Connection to these pins
LDO Bypass
6
I
7, 34, 35
9, 10
11
NC
-
LDObyp1, LDObyp2
GOE
-
I
Global Output Enable
12
LD
O
O
O
O
Lock Detect and Test Output
LVDS Clock Output 0
14, 15
17, 18
20, 21
CLKout0, CLKout0*
CLKout1, CLKout1*
CLKout2, CLKout2*
LVDS Clock Output 1
LVDS Clock Output 2
Clock Output 3
23, 24
CLKout3, CLKout3*
O
(LVDS for LMK03033C/LMK03033
LVPECL for all other parts)
27
SYNC*
I
I
Global Clock Output Synchronization
Oscillator Clock Input; Should be AC
coupled
28, 29
OSCin, OSCin*
32
CPout
O
I
Charge Pump Output
Bias Bypass
36
Bias
38, 39
41, 42
44, 45
47, 48
DAP
CLKout4, CLKout4*
CLKout5, CLKout5*
CLKout6, CLKout6*
CLKout7, CLKout7*
DAP
O
O
O
O
-
LVPECL Clock Output 4
LVPECL Clock Output 5
LVPECL Clock Output 6
LVPECLClock Output 7
Die Attach Pad is Ground
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4
Absolute Maximum Ratings (Note 1, Note 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors
for availability and specifications.
Parameter
Power Supply Voltage
Symbol
VCC
VIN
Ratings
-0.3 to 3.6
-0.3 to (VCC + 0.3)
-65 to 150
+260
Units
V
Input Voltage
V
TSTG
TL
Storage Temperature Range
Lead Temperature (solder 4 s)
Junction Temperature
°C
°C
°C
TJ
125
Recommended Operating Conditions
Parameter
Ambient Temperature
Power Supply Voltage
Symbol
TA
Min
-40
Typ
25
Max
85
Units
°C
V
VCC
3.15
3.3
3.45
Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work
stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV.
Package Thermal Resistance
Package
θJA
θJ-PAD (Thermal Pad)
48-Lead LLP (Note 3)
27.4° C/W
5.8° C/W
Note 3: Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key
role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout.
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Electrical Characteristics (Note 4)
(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values represent
most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed).
Symbol
Parameter
Conditions
Current Consumption
Min
Typ
Max
Units
Entire device; one LVDS and one
LVPECL clock enabled; no divide; no
delay.
161.8
Power Supply Current
(Note 5)
ICC
mA
mA
Entire device; All Outputs Off (no
emitter resistors placed)
86
1
ICCPD
Power Down Current
POWERDOWN = 1
Reference Oscillator
Reference Oscillator Input Frequency
Range for Square Wave
fOSCinsquare
VOSCinsquare
1
200
1.6
MHz
Vpp
AC coupled; Differential (VOD
)
Square Wave Input Voltage for OSCin and
OSCin*
0.2
PLL
fPD
Phase Detector Frequency
40
MHz
µA
VCPout = Vcc/2, PLL_CP_GAIN = 1x
VCPout = Vcc/2, PLL_CP_GAIN = 4x
VCPout = Vcc/2, PLL_CP_GAIN = 16x
VCPout = Vcc/2, PLL_CP_GAIN = 32x
VCPout = Vcc/2, PLL_CP_GAIN = 1x
VCPout = Vcc/2, PLL_CP_GAIN = 4x
VCPout = Vcc/2, PLL_CP_GAIN = 16x
VCPout = Vcc/2, PLL_CP_GAIN = 32x
0.5 V < VCPout < Vcc - 0.5 V
100
400
ISRCECPout
Charge Pump Source Current
1600
3200
-100
-400
-1600
-3200
2
ISINKCPout
Charge Pump Sink Current
µA
ICPoutTRI
Charge Pump TRI-STATE® Current
10
nA
%
VCPout = Vcc / 2
TA = 25°C
Magnitude of Charge Pump
Sink vs. Source Current Mismatch
ICPout%MIS
3
4
4
Magnitude of Charge Pump
Current vs. Charge Pump Voltage
Variation
0.5 V < VCPout < Vcc - 0.5 V
TA = 25°C
ICPoutVTUNE
%
Magnitude of Charge Pump Current vs.
Temperature Variation
ICPoutTEMP
PN10kHz
PN1Hz
%
PLL_CP_GAIN = 1x
PLL_CP_GAIN = 32x
PLL_CP_GAIN = 1x
PLL_CP_GAIN = 32x
-117
-122
-219
-224
PLL 1/f Noise at 10 kHz Offset (Note 6)
Normalized to 1 GHz Output Frequency
dBc/Hz
dBc/Hz
Normalized Phase Noise Contribution
(Note 7)
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
VCO
LMK03000C/LMK03000/LMK03000D
LMK03001C/LMK03001/LMK03001D
LMK03033C/LMK03033
1185
1470
1843
1296
1570
2160
fFout
VCO Tuning Range
MHz
After programming R15 for lock, no
changes to output configuration are
permitted to guarantee continuous
lock. (Note 8)
Allowable Temperature Drift for
Continuous Lock
|ΔTCL
|
125
°C
LMK03000C/LMK03000/LMK03000D;
TA = 25 °C
3.3
2.7
Output Power to a 50 Ω load driven by Fout
(Note 10)
pFout
LMK03001C/LMK03001/LMK03001D;
TA = 25 °C
dBm
MHz/V
fs
LMK03033C/LMK03033;TA = 25 °C
LMK03000C/LMK03000/LMK03000D
LMK03001C/LMK03001/LMK03001D
LMK03033C/LMK03033
LMK03000C/LMK03001C
LMK03000/LMK03001
LMK03000D/LMK03001D
LMK03033C
-5 to 0
7 to 9
9 to 11
14 to 26
400
KVCO
Fine Tuning Sensitivity (Note 9)
800
Fout RMS Period Jitter
(12 kHz to 20 MHz bandwidth)
JRMSFout
1200
500
LMK03033
800
10 kHz Offset
-91.4
-116.8
-137.8
-156.9
-93.5
-118.5
-139.4
-158.4
-89.6
-115.2
-136.5
-156.0
-91.6
-116.0
-137.9
-156.2
-83
LMK03000C
100 kHz Offset
fFout = 1296 MHz
1 MHz Offset
(Note 11)
10 MHz Offset
10 kHz Offset
LMK03000C
100 kHz Offset
fFout = 1185 MHz
1 MHz Offset
(Note 11)
10 MHz Offset
10 kHz Offset
LMK03001C
100 kHz Offset
fFout = 1570 MHz
1 MHz Offset
(Note 11)
10 MHz Offset
10 kHz Offset
L(f)Fout
Fout Single Side Band Phase Noise
dBc/Hz
LMK03001C
100 kHz Offset
fFout = 1470 MHz
1 MHz Offset
(Note 11)
10 MHz Offset
10 kHz Offset
LMK03033C
100 kHz Offset
fFout = 2160 MHz
-109
1 MHz Offset
-131
(Note 11)
10 MHz Offset
10 kHz Offset
-152
-86
LMK03033C
100 kHz Offset
fFout = 1843 MHz
-111
1 MHz Offset
-134
(Note 11)
10 MHz Offset
-153
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
Clock Distribution Section (Note 12, Note 13) - LVDS Clock Outputs
CLKoutX_MUX
= Bypass (no
divide or delay)
20
RL = 100 Ω
Distribution Path =
765 MHz
Bandwidth =
12 kHz to 20 MHz
CLKoutX_MUX
= Divided (no
delay)
CLKoutX_DIV =
4
JitterADD
Additive RMS Jitter (Note 12)
fs
75
Equal loading and identical clock
configuration
tSKEW
CLKoutX to CLKoutY (Note 14)
-30
±4
30
ps
RL = 100 Ω
VOD
Differential Output Voltage
RL = 100 Ω
RL = 100 Ω
RL = 100 Ω
RL = 100 Ω
250
-50
350
450
50
mV
mV
V
Change in magnitude of VOD for
complementary output states
ΔVOD
VOS
Output Offset Voltage
1.070
-35
1.25
1.370
35
Change in magnitude of VOS for
complementary output states
ΔVOS
mV
ISA
ISB
Clock Output Short Circuit Current
single-ended
Single-ended outputs shorted to GND
Complementary outputs tied together
-24
-12
24
12
mA
mA
Clock Output Short Circuit Current
differential
ISAB
Clock Distribution Section (Note 12, Note 13) - LVPECL Clock Outputs
CLKoutX_MUX
= Bypass (no
divide or delay)
20
75
±3
RL = 100 Ω
Distribution Path =
765 MHz
Bandwidth =
12 kHz to 20 MHz
CLKoutX_MUX
= Divided (no
delay)
CLKoutX_DIV =
4
JitterADD
Additive RMS Jitter (Note 12)
fs
Equal loading and identical clock
configuration
tSKEW
CLKoutX to CLKoutY (Note 14)
-30
30
ps
V
Termination = 50 Ω to Vcc - 2 V
Vcc -
0.98
VOH
Output High Voltage
Termination = 50 Ω to Vcc - 2 V
Vcc -
1.8
VOL
VOD
Output Low Voltage
V
Differential Output Voltage
RL = 100 Ω
660
2.0
810
965
mV
Digital LVTTL Interfaces (Note 15)
VIH
VIL
IIH
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
Vcc
0.8
5.0
5.0
V
V
VIH = Vcc
VIL = 0
-5.0
µA
µA
IIL
-40.0
Vcc -
0.4
VOH
VOL
IOH = +500 µA
High-Level Output Voltage
Low-Level Output Voltage
V
V
IOL = -500 µA
0.4
Digital MICROWIRE Interfaces (Note 16)
VIH
VIL
IIH
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
1.6
Vcc
0.4
5.0
5.0
V
V
VIH = Vcc
VIL = 0
-5.0
-5.0
µA
µA
IIL
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Symbol
tCS
Parameter
Conditions
MICROWIRE Timing
Min
Typ
Max
Units
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
25
8
ns
ns
ns
ns
ns
ns
ns
tCH
tCWH
tCWL
tES
25
25
25
25
25
Clock to Enable Set Up Time
Enable to Clock Set Up Time
Enable Pulse Width High
tCES
tEWH
Note 4: The Electrical Characteristics table lists guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 5: See 3.5 for more current consumption / power dissipation calculation information.
Note 6: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10
dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker
(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade
slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f)
can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of
LPLL_flicker(f) and LPLL_flat(f).
Note 7: A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, LPLL_flat(f), of the PLL and is defined as PN1Hz =
LPLL_flat(f) – 20log(N) – 10log(fCOMP). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth and fCOMP is the phase
detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). To measure LPLL_flat(f) the offset frequency, f, must be chosen sufficiently
smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference and flicker noise. LPLL_flat(f) can be
masked by the reference oscillator performance if a low power or noisy source is used.
Note 8: Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction and stay in lock from the ambient temperature
and programmed state at which the device was when register R15 was programmed. The action of programming the R15 register, even to the same value,
activates a frequency calibration routine. This implies that the device will work over the entire frequency range, but if the temperature drifts more than the maximum
allowable drift for continuous lock, then it will be necessary to reprogram the R15 register to ensure that the device stays in lock. Regardless of what temperature
the device was initially programmed at, the ambient temperature can never drift outside the range of -40 °C ≤ TA ≤ 85 °C without violating specifications. For
this specification to be valid, the programmed state of the device must not change after R15 is programmed.
Note 9: The lower sensitivity indicates the typical sensitivity at the lower end of the tuning range, the higher sensitivity at the higher end of the tuning range
Note 10: Output power varies as a function of frequency. When a range is shown, the higher output power applies to the lower frequency and the lower output
power applies to the higher frequency.
Note 11: VCO phase noise is measured assuming the VCO is the dominant noise source due to a 75 Hz loop bandwidth. Over frequency, the phase noise typically
varies by 1 to 2 dB, with the worst case performance typically occurring at the highest frequency. Over temperature, the phase noise typically varies by 1 to 2 dB,
assuming the device is not reprogrammed. Reprogramming R15 will run the frequency calibration routine for optimum phase noise.
Note 12: The Clock Distribution Section includes all parts of the device except the PLL and VCO sections. Typical Additive Jitter specifications apply to the clock
distribution section only and this adds in an RMS fashion to the shaped jitter of the PLL and the VCO.
Note 13: For CLKout frequencies above 1 GHz, the delay should be limited to one half of a period. For 1 GHz and below, the maximum delay can be used.
Note 14: Specification is guaranteed by characterization and is not tested in production.
Note 15: Applies to GOE, LD, and SYNC*.
Note 16: Applies to CLKuWire, DATAuWire, and LEuWire.
Serial Data Timing Diagram
20211403
Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the CLKuWire signal. On
the rising edge of the LEuWire signal, the data is sent from the shift register to the addressed register determined by the LSB bits.
After the programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state. It is rec-
ommended that the slew rate of CLKuWire, DATAuWire, and LEuWire should be at least 30 V/µs.
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Charge Pump Current Specification Definitions
20211431
I1 = Charge Pump Sink Current at VCPout = Vcc - ΔV
I2 = Charge Pump Sink Current at VCPout = Vcc/2
I3 = Charge Pump Sink Current at VCPout = ΔV
I4 = Charge Pump Source Current at VCPout = Vcc - ΔV
I5 = Charge Pump Source Current at VCPout = Vcc/2
I6 = Charge Pump Source Current at VCPout = ΔV
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.
Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage
20211432
Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch
20211433
Charge Pump Output Current Magnitude Variation vs. Temperature
20211434
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Typical Performance Characteristics (Note 17)
LVDS Differential Output Voltage (VOD
)
LVPECL Differential Output Voltage (VOD)
20211407
20211408
LVDS Output Buffer Noise Floor (Note 18)
LVPECL Output Buffer Noise Floor (Note 18)
20211409
20211410
Delay Noise Floor (Adds to Output Noise Floor) (Note 18,
Note 19)
20211412
Note 17: These plots show performance at frequencies beyond what the part is guaranteed to operate at to give the user an idea of the capabilities of the part,
but they do not imply any sort of guarantee.
Note 18: To estimate this noise, only the output frequency is required. Divide value and input frequency are not integral.
Note 19: The noise of the delay block is independent of output type and only applies if the delay is enabled. The noise floor due to the distribution section
accounting for the delay nise can be calculated as: Total Output Noise = 10 × log(10Output Buffer Noise/10 + 10Delay Noise Floor/10).
11
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be disabled simultaneously by pulling the GOE pin low or
programming EN_CLKout_Global to 0.
1.0 Functional Description
The LMK03000 family of precision clock conditioners com-
bine the functions of jitter cleaning/reconditioning, multiplica-
tion, and distribution of a reference clock. The devices
integrate a Voltage Controlled Oscillator (VCO), a high per-
formance Integer-N Phase Locked Loop (PLL), a partially
integrated loop filter, three LVDS, and five LVPECL clock out-
put distribution blocks.
The duty cycle of the LVDS and LVPECL clock outputs are
shown in the table below.
Duty
VCO_DIV
CLKoutX_MUX
Cycle
50%
50%
33%
40%
43%
Any
Divided, or Divided and Delayed
Any
2, 4, 6, 8
The devices include internal 3rd and 4th order poles to sim-
plify loop filter design and improve spurious performance. The
1st and 2nd order poles are off-chip to provide flexibility for
the design of various loop filter bandwidths.
3
5
7
Bypassed, or Delayed
Bypassed, or Delayed
Bypassed, or Delayed
The LMK03000 family has multiple options for VCO frequen-
cies. The VCO output is optionally accessible on the Fout port.
Internally, the VCO output goes through an VCO Divider to
feed the various clock distribution blocks.
1.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION
The SYNC* pin synchronizes the clock outputs. When the
SYNC* pin is held in a logic low state, the divided outputs are
also held in a logic low state. The bypassed outputs will con-
tinue to operate normally. Shortly after the SYNC* pin goes
high, the divided clock outputs are activated and will all tran-
sition to a high state simultaneously. All the outputs, divided
and bypassed, will now be synchronized. Clocks in the by-
passed state are not affected by SYNC* and are always
synchronized with the divided outputs.
Each clock distribution block includes a programmable di-
vider, a phase synchronization circuit, a programmable delay,
a clock output mux, and an LVDS or LVPECL output buffer.
This allows multiple integer-related and phase-adjusted
copies of the reference to be distributed to eight system com-
ponents.
The clock conditioners come in a 48-pin LLP package and are
footprint compatible with other clocking devices in the same
family.
The SYNC* pin must be held low for greater than one clock
cycle of the output of the VCO Divider, also known as the
distribution path. Once this low event has been registered, the
outputs will not reflect the low state for four more cycles. This
means that the outputs will be low on the fifth rising edge of
the distribution path. Similarly once the SYNC* pin becomes
high, the outputs will not simultaneously transition high until
four more distribution path clock cycles have passed, which
is the fifth rising edge of the distribution path. See the timing
diagram in Figure 1 for further detail. The clocks are pro-
grammed as CLKout0_MUX = Bypassed, CLKout1_MUX =
Divided, CLKout1_DIV = 2, CLKout2_MUX = Divided, and
CLKout2_DIV = 4. To synchronize the outputs, after the low
SYNC* event has been registered, it is not required to wait for
the outputs to go low before SYNC* is set high.
1.1 BIAS PIN
To properly use the device, bypass Bias (pin 36) with a low
leakage 1 µF capacitor connected to Vcc. This is important
for low noise performance.
1.2 LDO BYPASS
To properly use the device, bypass LDObyp1 (pin 9) with a
10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF capacitor.
1.3 OSCILLATOR INPUT PORT (OSCin, OSCin*)
The purpose of OSCin is to provide the PLL with a reference
signal. Due to an internal DC bias the OSCin port should be
AC coupled, refer to the System Level Diagram in the Appli-
cation Information section. The OSCin port may be driven
single-endedly by AC grounding OSCin* with a 0.1 µF capac-
itor.
1.4 LOW NOISE, FULLY INTEGRATED VCO
The LMK03000 family of devices contain a fully integrated
VCO. In order for proper operation the VCO uses a frequency
calibration algorithm. The frequency calibration algorithm is
activated any time that the R15 register is programmed. Once
R15 is programmed the temperature may not drift more than
the maximum allowable drift for continuous lock, ΔTCL, or else
the VCO is not guaranteed to stay in lock.
For the frequency calibration algorithm to work properly OS-
Cin must be driven by a valid signal when R15 is programmed.
20211404
FIGURE 1. SYNC* Timing Diagram
1.5 CLKout DELAYS
Each individual clock output includes a delay adjustment.
Clock output delay registers (CLKoutX_DLY) support a 150
ps step size and range from 0 to 2250 ps of total delay.
The SYNC* pin provides an internal pull-up resistor as shown
on the functional block diagram. If the SYNC* pin is not ter-
minated externally the clock outputs will operate normally. If
the SYNC* function is not used, clock output synchronization
is not guaranteed.
1.6 LVDS/LVPECL OUTPUTS
By default all the clock outputs are disabled until pro-
grammed.
Each LVDS or LVPECL output may be disabled individually
by programming the CLKoutX_EN bits. All the outputs may
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12
1.8 CLKout OUTPUT STATES
The function of this word is to divide the comparison frequen-
cy presented to the lock detect circuit by 4.
Each clock output may be individually enabled with the
CLKoutX_EN bits. Each individual output enable control bit is
gated with the Global Output Enable input pin (GOE) and the
Global Output Enable bit (EN_CLKout_Global).
All clock outputs can be disabled simultaneously if the GOE
pin is pulled low by an external signal or EN_CLKout_Global
is set to 0.
CLKoutX
_EN bit
EN_CLKout
_Global bit
CLKoutX
Output State
GOE pin
1
Don't care
0
1
0
Low
Low
Off
Don't care
Don't care
Don't care
Off
High / No
Connect
1
1
Enabled
When an LVDS output is in the Off state, the outputs are at a
voltage of approximately 1.5 volts. When an LVPECL output
is in the Off state, the outputs are at a voltage of approximately
1 volt.
1.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT
The GOE pin provides an internal pull-up resistor as shown
on the functional block diagram. If it is not terminated exter-
nally, the clock output states are determined by the Clock
Output
Enable
bits
(CLKoutX_EN)
and
the
EN_CLKout_Global bit.
By programming the PLL_MUX register to Digital Lock Detect
Active High, the Lock Detect (LD) pin can be connected to the
GOE pin in which case all outputs are set low automatically if
the synthesizer is not locked.
1.10 POWER ON RESET
When supply voltage to the device increases monotonically
from ground to Vcc, the power on reset circuit sets all registers
to their default values, see the programming section for more
information on default register values. Voltage should be ap-
plied to all Vcc pins simultaneously.
1.11 DIGITAL LOCK DETECT
The PLL digital lock detect circuitry compares the difference
between the phase of the inputs of the phase detector to a
RC generated delay of ε. To indicate a locked state the phase
error must be less than the ε RC delay for 5 consecutive ref-
erence cycles. Once in lock, the RC delay is changed to
approximately δ. To indicate an out of lock state, the phase
error must become greater δ. The values of ε and δ are shown
in the table below:
ε
δ
10 ns
20 ns
To utilize the digital lock detect feature, PLL_MUX must be
programmed for "Digital Lock Detect (Active High)" or "Digital
Lock Detect (Active Low)." When one of these modes is pro-
grammed the state of the LD pin will be set high or low as
determined by the description above as shown in Figure 2.
20211405
FIGURE 2. Digital Lock Detect Flowchart
When the device is in power down mode and the LD pin is
programmed for a digital lock detect function, LD will show a
"no lock detected" condition which is low or high given active
high or active low circuitry respectively.
The accuracy of this circuit degrades at higher comparison
frequencies. To compensate for this, the DIV4 word should
be set to one if the comparison frequency exceeds 20 MHz.
13
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2.0 General Programming
Information
The LMK03000 family of devices are programmed using sev-
eral 32-bit registers which control the device's operation. The
registers consist of a data field and an address field. The last
4 register bits, ADDR[3:0] form the address field. The remain-
ing 28 bits form the data field DATA[27:0].
During programming, LEuWire is low and serial data is
clocked in on the rising edge of CLKuWire (MSB first). When
LE goes high, data is transferred to the register bank selected
by the address field. Only registers R0 to R7, R11, and R13
to R15 need to be programmed for proper device operation.
For the frequency calibration algorithm to work properly OS-
Cin must be driven by a valid signal when R15 is programmed.
Any changes to the PLL R divider or OSCin require R15 to be
programmed again to activate the frequency calibration rou-
tine.
2.1 RECOMMENDED PROGRAMMING SEQUENCE
The recommended programming sequence involves pro-
gramming R0 with the reset bit set (RESET = 1) to ensure the
device is in a default state. It is not necessary to program R0
again, but if R0 is programmed again, the reset bit is pro-
grammed clear (RESET = 0). Registers are programmed in
order with R15 being the last register programmed. An ex-
ample programming sequence is shown below.
•
Program R0 with the reset bit set (RESET = 1). This
ensures the device is in a default state. When the reset bit
is set in R0, the other R0 bits are ignored.
If R0 is programmed again, the reset bit is programmed
clear (RESET = 0).
—
•
Program R0 to R7 as necessary with desired clocks with
appropriate enable, mux, divider, and delay settings.
•
•
Program R8 for optimum phase noise performance.
Program R9 with Vboost setting if necessary. Optional,
only needed to set Vboost = 1.
•
•
Program R11 with DIV4 setting if necessary.
Program R13 with oscillator input frequency and internal
loop filter values
•
•
Program R14 with Fout enable bit, global clock output bit,
power down setting, PLL mux setting, and PLL R divider.
Program R15 with PLL charge pump gain, VCO divider,
and PLL N divider. Also starts frequency calibration
routine.
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14
CLKout0_EN CLKout1_EN CLKout2_EN CLKout3_EN CLKout4_EN CLKout5_EN CLKout6_EN CLKout7_EN
RESET
R e g i s t e r
15
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0
DIV4
Vboost
POWERDOWN
EN_CLKout_Global
EN_Fout
R e g i s t e r
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16
2.3 REGISTER R0 to R7
Aside from this, the functions of these bits are identical. The
X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and
CLKoutX_EN denote the actual clock output which may be
from 0 to 7.
Registers R0 through R7 control the eight clock outputs. Reg-
ister R0 controls CLKout0, Register R1 controls CLKout1, and
so on. There is one additional bit in register R0 called RESET.
Default Register Settings after Power on Reset
Default
Bit Value
Bit
Location
Bit Name
Bit State
Bit Description
Register
RESET
0
0
0
1
0
0
0
No reset, normal operation
Bypassed
Reset to power on defaults
CLKoutX mux mode
CLKoutX enable
R0
31
18:17
16
CLKoutX_MUX
CLKoutX_EN
CLKoutX_DIV
CLKoutX_DLY
Vboost
Disabled
R0 to R7
Divide by 2
CLKoutX clock divide
CLKoutX clock delay
Output Power Control
Phase Detector Frequency
15:8
7:4
0 ps
Normal Mode
R9
16
DIV4
R11
15
PDF ≤ 20 MHz
10 MHz OSCin
Low (~200 Ω)
OSCin_FREQ
VCO_R4_LF
VCO_R3_LF
VCO_C3_C4_LF
EN_Fout
10
0
OSCin Frequency in MHz
R4 internal loop filter values
R3 internal loop filter values
C3 and C4 internal loop filter values
Fout enable
21:14
13:11
10:8
7:4
R13
0
Low (~600 Ω)
C3 = 0 pF, C4 = 10 pF
Fout disabled
0
0
28
EN_CLKout_Global
POWERDOWN
PLL_MUX
1
Normal - CLKouts normal
Normal - Device active
Disabled
Global clock output enable
Device power down
27
0
R14
R15
26
0
Multiplexer control for LD pin
PLL R divide value
23:20
19:8
31:30
29:26
25:8
PLL_R
10
0
R divider = 10
100 µA
PLL_CP_GAIN
VCO_DIV
Charge pump current
VCO divide value
2
Divide by 2
PLL_N
760
N divider = 760
PLL N divide value
2.3.1 RESET bit -- R0 only
2.3.3 CLKoutX_DIV[7:0] -- Clock Output Dividers
This bit is only in register R0. The use of this bit is optional
and it should be set to '0' if not used. Setting this bit to a '1'
forces all registers to their power on reset condition and there-
fore automatically clears this bit. If this bit is set, all other R0
bits are ignored and R0 needs to be programmed again if
used with its proper values and RESET = 0.
These bits control the clock output divider value. In order for
these dividers to be active, the respective CLKoutX_MUX bit
must be set to either "Divided" or "Divided and Delayed"
mode. After all the dividers are programed, the SYNC* pin
must be used to ensure that all edges of the clock outputs are
aligned. The Clock Output Dividers follow the VCO Divider so
the final clock divide for an output is VCO Divider × Clock
Output Divider. By adding the divider block to the output path
a fixed delay of approximately 100 ps is incurred.
2.3.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers
These bits control the Clock Output Multiplexer for each clock
output. Changing between the different modes changes the
blocks in the signal path and therefore incurs a delay relative
to the bypass mode. The different MUX modes and associ-
ated delays are listed below.
The actual Clock Output Divide value is twice the binary value
programmed as listed in the table below.
Clock Output
CLKoutX_DIV[7:0]
Divider value
CLKoutX_MUX
[1:0]
Added Delay Relative
to Bypass Mode
Mode
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
0
0
.
0
0
0
0
1
1
.
0
0
1
1
0
0
.
0
1
0
1
0
1
.
Invalid
2 (default)
Bypassed
(default)
0
1
0 ps
4
6
Divided
100 ps
8
400 ps
10
...
2
3
Delayed
(In addition to the
programmed delay)
500 ps
(In addition to the
programmed delay)
1
1
1
1
1
1
1
1
510
Divided and
Delayed
17
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2.3.4 CLKoutX_DLY[3:0] -- Clock Output Delays
2.6 REGISTER R11
These bits control the delay stages for each clock output. In
order for these delays to be active, the respective
CLKoutX_MUX (See 2.3.2) bit must be set to either "Delayed"
or "Divided and Delayed" mode. By adding the delay block to
the output path a fixed delay of approximately 400 ps is in-
curred in addition to the delay shown in the table below.
This register only has one bit and only needs to be pro-
grammed in the case that the phase detector frequency is
greater than 20 MHz and digital lock detect is used. Other-
wise, it is automatically defaulted to the correct values.
2.6.1 DIV4 -- High Phase Detector Frequencies and Lock
Detect
CLKoutX_DLY[3:0]
Delay (ps)
0 (default)
150
This bit divides the frequency presented to the digital lock de-
tect circuitry by 4. It is necessary to get a reliable output from
the digital lock detect output in the case of a phase detector
frequency frequency greater than 20 MHz.
0
1
2
300
DIV4
Digital Lock Detect Circuitry Mode
Not divided
3
450
4
600
0
Phase Detector Frequency ≤ 20 MHz (default)
5
750
Divided by 4
Phase Detector Frequency > 20 MHz
6
900
1
7
1050
1200
1350
1500
1650
1800
1950
2100
2250
8
2.7 REGISTER R13
9
2.7.1 VCO_C3_C4_LF[3:0] -- Value for Internal Loop Filter
Capacitors C3 and C4
10
11
12
13
14
15
These bits control the capacitor values for C3 and C4 in the
internal loop filter.
Loop Filter Capacitors
VCO_C3_C4_LF[3:0]
C3 (pF)
C4 (pF)
10 (default)
60
0
0 (default)
1
0
2.3.5 CLKoutX_EN bit -- Clock Output Enables
These bits control whether an individual clock output is en-
abled or not. If the EN_CLKout_Global bit (See 2.8.4) is set
to zero or if GOE pin is held low, all CLKoutX_EN bit states
will be ignored and all clock outputs will be disabled.
2
50
10
3
0
110
4
50
110
5
100
0
110
CLKoutX_EN
bit
CLKoutX
State
Conditions
6
160
7
50
160
0
EN_CLKout_Global bit = 1
GOE pin = High / No
Connect
Disabled
(default)
8
9
100
100
150
150
10
60
1
Enabled
10
110
2.4 REGISTER R8
11
60
The programming of register R8 provides optimum phase
noise performance.
12 to 15
Invalid
2.7.2 VCO_R3_LF[2:0] -- Value for Internal Loop Filter
Resistor R3
2.5 REGISTER R9
The programming of register R9 is optional. If it is not pro-
grammed the bit Vboost will be defaulted to 0, which is the
test condition for all electrical characteristics.
These bits control the R3 resistor value in the internal loop
filter. The recommended setting for VCO_R3_LF[2:0] = 0 for
optimum phase noise and jitter.
2.5.1 Vboost -- Voltage Boost
VCO_R3_LF[2:0]
R3 Value (kΩ)
By enabling this bit, the voltage output levels for all clock out-
puts is increased. Also, the noise floor is improved
0
Low (~600 Ω) (default)
1
10
20
Typical LVDS
Voltage Output
(mV)
Typical LVPECL
Voltage Output
(mV)
2
3
Vboost
30
4
40
0
1
350
390
810
865
5 to 7
Invalid
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18
2.7.3 VCO_R4_LF[2:0] -- Value for Internal Loop Filter
Resistor R4
2.8.2 PLL_MUX[3:0] -- Multiplexer Control for LD Pin
These bits set the output mode of the LD pin. The table below
lists several different modes.
These bits control the R4 resistor value in the internal loop
filter. The recommended setting for VCO_R4_LF[2:0] = 0 for
optimum phase noise and jitter.
PLL_MUX[3:0]
Output Type
Hi-Z
LD Pin Function
Disabled (default)
Logic High
0
1
2
VCO_R4_LF[2:0]
R4 Value (kΩ)
Push-Pull
Push-Pull
0
Low (~200 Ω) (default)
Logic Low
1
10
20
Digital Lock Detect
(Active High)
3
Push-Pull
2
3
30
Digital Lock Detect
(Active Low)
4
5
6
Push-Pull
Push-Pull
4
40
5 to 7
Invalid
Analog Lock Detect
Open Drain
NMOS
2.7.4 OSCin_FREQ[7:0] -- Oscillator Input Calibration
Adjustment
Analog Lock Detect
Open Drain
PMOS
These bits are to be programmed to the OSCin frequency. If
the OSCin frequency is not an integral multiple of 1 MHz, then
round to the closest value.
7
Analog Lock Detect
8
9
Invalid
N Divider Output/2
(50% Duty Cycle)
OSCin_FREQ[7:0]
OSCin Frequency
Push-Pull
Push-Pull
1
1 MHz
2 MHz
10
Invalid
2
R Divider Output/2
(50% Duty Cycle)
...
10
...
11
10 MHz (default)
...
12 to 15
Invalid
...
"Logic High" and "Logic Low" allow the PLL_MUX pin to be
used as a general purpose output. These modes are also
useful when debugging to verify programming. The Digital
Lock Detect operation is covered in 1.11 DIGITAL LOCK DE-
TECT.
200
200 MHz
Invalid
201 to 255
2.8 REGISTER R14
2.8.1 PLL_R[11:0] -- R Divider Value
Analog Lock Detect outputs the state of the charge pump on
the LD pin. While the charge pump is on, the LD pin is low.
While the charge pump is off, the LD pin is high. By using two
resistors, a capacitor, diode, and comparator a lock detect
circuit may be constructed (Note 20). When in lock the charge
pump will only turn on momentarily once every period of the
phase detector frequency. "N Divider Output/2" and "R Di-
vider Output/2" output half the frequency of the phase detec-
tor on the LD pin. When the device is locked, these
frequencies should be the same. These options are useful for
debugging.
These bits program the PLL R Divider and are programmed
in binary fashion. Any changes to PLL_R require R15 to be
programmed again to active the frequency calibration routine.
PLL R Divide
PLL_R[11:0]
Value
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
Invalid
1
2
...
10 (default)
...
Note 20: For more information on lock detect circuits, see chapter 32 of PLL
Performance, Simulation and Design Handbook, Fourth Edition by Dean
Banerjee.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
0
.
1
.
0
.
1
1
1
1
1
1
1
1
1
1
1
1
4095
19
www.national.com
2.8.3 POWERDOWN bit -- Device Power Down
2.9.2 VCO_DIV[3:0] -- VCO Divider
This bit can power down the device. Enabling this bit powers
down the entire device and all blocks, regardless of the state
of any of the other bits or pins.
These bits program the divide value for the VCO Divider. The
VCO Divider follows the VCO output and precedes the clock
distribution blocks. Since the VCO Divider is in the feedback
path from the VCO to the PLL phase detector the VCO Divider
contributes to the total N divide value, NTotal. NTotal = PLL N
Divider × VCO Divider. The VCO Divider can not be by-
passed. See 2.9.1 (PLL N Divider) for more information on
setting the VCO frequency.
POWERDOWN bit
Mode
0
1
Normal Operation (default)
Entire Device Powered Down
2.8.4 EN_CLKout_Global bit -- Global Clock Output
Enable
VCO Divider
VCO_DIV[3:0]
Value
This bit overrides the individual CLKoutX_EN bits. When this
bit is set to 0, all clock outputs are disabled, regardless of the
state of any of the other bits or pins.
0
0
0
0
0
0
0
0
1
1
.
0
0
0
0
1
1
1
1
0
0
.
0
0
1
1
0
0
1
1
0
0
.
0
1
0
1
0
1
0
1
0
1
.
Invalid
Invalid
2 (default)
EN_CLKout_Global bit
Clock Outputs
All Off
3
0
1
4
Normal Operation (default)
5
2.8.5 EN_Fout bit -- Fout port enable
6
7
This bit enables the Fout pin.
EN_Fout bit
Fout Pin Status
8
0
1
Disabled (default)
Enabled
Invalid
...
1
1
1
1
Invalid
2.9 REGISTER R15
Programming R15 also activates the frequency calibration
routine.
2.9.3 PLL_CP_GAIN[1:0] -- PLL Charge Pump Gain
These bits set the charge pump gain of the PLL.
2.9.1 PLL_N[17:0] -- PLL N Divider
PLL_CP_GAIN[1:0]
Charge Pump Gain
These bits program the divide value for the PLL N Divider.
The PLL N Divider follows the VCO Divider and precedes the
PLL phase detector. Since the VCO Divider is also in the
feedback path from the VCO to the PLL Phase Detector, the
total N divide value, NTotal, is also influenced by the VCO Di-
vider value. NTotal = PLL N Divider × VCO Divider. The VCO
frequency is calculated as, fVCO = fOSCin × PLL N Divider ×
VCO Divider / PLL R Divider. Since the PLL N divider is a pure
binary counter there are no illegal divide values for PLL_N
[17:0] except for 0.
0
1
2
3
1x (default)
4x
16x
32x
PLL N
PLL_N[17:0]
Divider
Value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Invalid
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
...
0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0
760
(default)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
...
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
262143
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20
3.0 Application Information
3.1 SYSTEM LEVEL DIAGRAM
20211470
FIGURE 3. Typical Application
Figure 3 shows an LMK03000 family device used in a typical
application. In this setup the clock may be multiplied, recon-
ditioned, and redistributed. Both the OSCin/OSCin* and CLK-
outX/CLKoutX* pins can be used in a single-ended or a
differential fashion, which is discussed later in this datasheet.
The GOE pin needs to be high for the outputs to operate. One
technique sometimes used is to take the output of the LD
(Lock Detect) pin and use this as an input to the GOE pin. If
this is done, then the outputs will turn off if lock detect circuit
detects that the PLL is out of lock. The loop filter actually con-
sists of seven components, but four of these components that
for the third and fourth poles of the loop filter are integrated in
the chip. The first and second pole of the loop filter are exter-
nal.
3.2 BIAS PIN
See section 1.1 for bias pin information.
3.3 LDO BYPASS
See section 1.2 for LDO bypass information.
21
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3.4 LOOP FILTER
20211471
FIGURE 4. Loop Filter
The internal charge pump is directly connected to the inte-
grated loop filter components. The first and second pole of the
loop filter are externally attached as shown in Figure 4. When
the loop filter is designed, it must be stable over the entire
frequency band, meaning that the changes in KVtune from the
low to high band specification will not make the loop filter un-
stable. The design of the loop filter is application specific and
can be rather involved, but is discussed in depth in the Clock
Conditioner Owner's Manual provided by National Semicon-
ductor. When designing with the integrated loop filter of the
LMK03000 family, considerations for minimum resistor ther-
mal noise often lead one to the decision to design for the
minimum value for integrated resistors, R3 and R4. Both the
integrated loop filter resistors and capacitors (C3 and C4) also
restrict how wide the loop bandwidth the PLL can have. How-
ever, these integrated components do have the advantage
that they are closer to the VCO and can therefore filter out
some noise and spurs better than external components. For
this reason, a common strategy is to minimize the internal
loop filter resistors and then design for the largest internal ca-
pacitor values that permit a wide enough loop bandwidth. In
some situations where spurs requirements are very stringent
and there is margin on phase noise, it might make sense to
design for a loop filter with integrated resistor values that are
larger than their minimum value.
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22
3.5 CURRENT CONSUMPTION / POWER DISSIPATION
CALCULATIONS
calculate estimated current consumption of the device. Un-
less otherwise noted Vcc = 3.3 V, TA = 25 °C.
Due to the myriad of possible configurations the following ta-
ble serves to provide enough information to allow the user to
Table 3.5 - Block Current Consumption
Power
Current
Power
Dissipated in
LVPECL emitter
resistors (mW)
Block
Condition
Consumption at Dissipated in
3.3 V (mA)
device (mW)
283.8
Entire device,
core current
All outputs off; No LVPECL emitter resistors connected
86.0
9
-
-
-
Low clock buffer The low clock buffer is enabled anytime one of
(internal) CLKout0 through CLKout3 are enabled
High clock buffer The high clock buffer is enabled anytime one of the
29.7
9
29.7
(internal)
CLKout4 through CLKout7 are enabled
Fout buffer, EN_Fout = 1
14.5
17.8
47.8
58.7
-
-
LVDS output, Bypassed mode
LVPECL output, Bypassed mode (includes 120 Ω
emitter resistors)
40
17.4
0
72
38.3
0
60
19.1
-
Output buffers
LVPECL output, disabled mode (includes 120 Ω
emitter resistors)
LVPECL output, disabled mode. No emitter resistors
placed; open outputs
Divide enabled, divide = 2
5.3
8.5
17.5
28.0
19.1
32.7
474
-
-
Divide circuitry
per output
Divide enabled, divide > 2
Delay enabled, delay < 8
5.8
-
Delay circuitry
per output
Delay enabled, delay > 7
9.9
-
Entire device
CLKout0 & CLKout4 enabled in Bypassed mode
161.8
60
From Table 3.5 the current consumption can be calculated in
any configuration. For example, the current for the entire de-
vice with 1 LVDS (CLKout0) & 1 LVPECL (CLKout4) output
in Bypassed mode can be calculated by adding up the fol-
lowing blocks: core current, low clock buffer, high clock buffer,
one LVDS output buffer current, and one LVPECL output
buffer current. There will also be one LVPECL output drawing
emitter current, but some of the power from the current draw
is dissipated in the external 120 Ω resistors which doesn't add
to the power dissipation budget for the device. If delays or
divides are switched in, then the additional current for these
stages needs to be added as well.
the LVPECL outputs, this power will be 0 watts. For example,
in the case of 1 LVDS (CLKout0) & 1 LVPECL (CLKout4) op-
erating at 3.3 volts, we calculate 3.3 V × (86 + 9 + 9 + 17.8 +
40) mA = 3.3 V × 161.8 mA = 533.9 mW. Because the
LVPECL output (CLKout4) has the emitter resistors hooked
up and the power dissipated by these resistors is 60 mW, the
total device power dissipation is 533.9 mW - 60 mW = 473.9
mW.
When the LVPECL output is active, ~1.9 V is the average
voltage on each output as calculated from the LVPECL Voh
& Vol typical specification. Therefore the power dissipated in
each emitter resistor is approximately (1.9 V)2 / 120 Ω = 30
mW. When the LVPECL output is disabled, the emitter resis-
tor voltage is ~1.07 V. Therefore the power dissipated in each
emitter resistor is approximately (1.07 V)2 / 120 Ω = 9.5 mW.
For power dissipated by the device, the total current entering
the device is multiplied by the voltage at the device minus the
power dissipated in any emitter resistors connected to any of
the LVPECL outputs. If no emitter resistors are connected to
23
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3.6 THERMAL MANAGEMENT
3.7 TERMINATION AND USE OF CLOCK OUTPUTS
(DRIVERS)
Power consumption of the LMK03000 family of devices can
be high enough to require attention to thermal management.
For reliability and performance reasons the die temperature
should be limited to a maximum of 125 °C. That is, as an es-
timate, TA (ambient temperature) plus device power con-
sumption times θJA should not exceed 125 °C.
The package of the device has an exposed pad that provides
the primary heat removal path as well as excellent electrical
grounding to the printed circuit board. To maximize the re-
moval of heat from the package a thermal land pattern in-
cluding multiple vias to a ground plane must be incorporated
on the PCB within the footprint of the package. The exposed
pad must be soldered down to ensure adequate heat con-
duction out of the package. A recommended land and via
pattern is shown in Figure 5. More information on soldering
LLP packages can be obtained at www.national.com.
When terminating clock drivers keep in mind these guidelines
for optimum phase noise and jitter performance:
•
Transmission line theory should be followed for good
impedance matching to prevent reflections.
•
Clock drivers should be presented with the proper loads.
For example:
LVDS drivers are current drivers and require a closed
current loop.
—
LVPECL drivers are open emitter and require a DC
path to ground.
—
•
Receivers should be presented with a signal biased to
their specified DC bias level (common mode voltage) for
proper operation. Some receivers have self-biasing inputs
that automatically bias to the proper voltage level. In this
case, the signal should normally be AC coupled.
It is possible to drive a non-LVPECL or non-LVDS receiver
with a LVDS or LVPECL driver as long as the above guide-
lines are followed. Check the datasheet of the receiver or
input being driven to determine the best termination and cou-
pling method to be sure that the receiver is biased at its
optimum DC voltage (common mode voltage). For example,
when driving the OSCin/OSCin* input of the LMK03000 fam-
ily, OSCin/OSCin* should be AC coupled because OSCin/
OSCin* biases the signal to the proper DC level, see Figure
3. This is only slightly different from the AC coupled cases
described in 3.7.2 because the DC blocking capacitors are
placed between the termination and the OSCin/OSCin* pins,
but the concept remains the same, which is the receiver (OS-
Cin/OSCin*) set the input to the optimum DC bias voltage
(common mode voltage), not the driver.
20211473
3.7.1 Termination for DC Coupled Differential Operation
FIGURE 5. Recommended Land and Via Pattern
For DC coupled operation of an LVDS driver, terminate with
100 Ω as close as possible to the LVDS receiver as shown in
Figure 6. To ensure proper LVDS operation when DC cou-
pling it is recommend to use LVDS receivers without fail-safe
or internal input bias such as DS90LV110T. The LVDS driver
will provide the DC bias level for the LVDS receiver. For op-
eration with LMK03000 family LVDS drivers it is recommend
to use AC coupling with LVDS receivers that have an internal
DC bias voltage. Some fail-safe circuitry will present a DC
bias (common mode voltage) which will prevent the LVDS
driver from working correctly. This precaution does not apply
to the LVPECL drivers.
To minimize junction temperature it is recommended that a
simple heat sink be built into the PCB (if the ground plane
layer is not exposed). This is done by including a copper area
of about 2 square inches on the opposite side of the PCB from
the device. This copper area may be plated or solder coated
to prevent corrosion but should not have conformal coating (if
possible), which could provide thermal insulation. The vias
shown in Figure 5 should connect these top and bottom cop-
per layers and to the ground layer. These vias act as “heat
pipes” to carry the thermal energy away from the device side
of the board to where it can be more effectively dissipated.
20211420
FIGURE 6. Differential LVDS Operation, DC Coupling
For DC coupled operation of an LVPECL driver, terminate
with 50 Ω to Vcc - 2 V as shown in Figure 7. Alternatively
terminate with a Thevenin equivalent circuit (120 Ω resistor
connected to Vcc and an 82 Ω resistor connected to ground
with the driver connected to the junction of the 120 Ω and 82
Ω resistors) as shown in Figure 8 for Vcc = 3.3 V.
www.national.com
24
3.7.2 Termination for AC Coupled Differential Operation
AC coupling allows for shifting the DC bias level (common
mode voltage) when driving different receiver standards.
Since AC coupling prevents the driver from providing a DC
bias voltage at the receiver it is important to ensure the re-
ceiver is biased to its ideal DC level.
When driving LVDS receivers with an LVDS driver, the signal
may be AC coupled by adding DC blocking capacitors, how-
ever the proper DC bias point needs to be established at the
receiver. If the receiver does not automatically bias its input,
one way to do this is with the termination circuitry in Figure
9.
20211418
When using AC coupling with LVDS outputs, there may be a
startup delay observed in the clock output due to capacitor
charging. Figure 9 employs 0.1 µF capacitors. This value may
need to be adjusted to meet the startup requirements for a
particular application.
FIGURE 7. Differential LVPECL Operation, DC Coupling
20211419
20211421
FIGURE 9. Differential LVDS Operation, AC Coupling
FIGURE 8. Differential LVPECL Operation, DC Coupling,
Thevenin Equivalent
LVPECL drivers require a DC path to ground. When AC cou-
pling an LVPECL signal use 120 Ω emitter resistors close to
the LVPECL driver to provide a DC path to ground as shown
in Figure 10. For proper receiver operation, the signal should
be biased to the DC bias level (common mode voltage) spec-
ified by the receiver. The typical DC bias voltage (common
mode voltage) for LVPECL receivers is 2 V. A Thevenin
equivalent circuit (82 Ω resistor connected to Vcc and a 120
Ω resistor connected to ground with the driver connected to
the junction of the 82 Ω and 120 Ω resistors) is a valid termi-
nation as shown in Figure 10 for Vcc = 3.3 V. Note this
Thevenin circuit is different from the DC coupled example in
Figure 8.
20211417
FIGURE 10. Differential LVPECL Operation, AC Coupling,
Thevenin Equivalent
25
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3.7.3 Termination for Single-Ended Operation
When AC coupling an LVPECL driver use a 120 Ω emitter
resistor to provide a DC path to ground and ensure a 50 ohm
termination with the proper DC bias level for the receiver. The
typical DC bias voltage for LVPECL receivers is 2 V (See
3.7.2). If the other driver is not used it should be terminated
with either a proper AC or DC termination. This latter example
of AC coupling a single-ended LVPECL signal can be used to
measure single-ended LVPECL performance using a spec-
trum analyzer or phase noise analyzer. When using most RF
test equipment no DC bias (0 V DC) is expected for safe and
proper operation. The internal 50 ohm termination the test
equipment provides correctly terminates the LVPECL driver
being measured as shown Figure 13. When using only one
LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to prop-
erly terminate the unused driver.
A balun can be used with either LVDS or LVPECL drivers to
convert the balanced, differential signal into an unbalanced,
single-ended signal.
It is possible to use an LVPECL driver as one or two separate
800 mV p-p signals. When DC coupling one of the LMK03000
family clock LVPECL drivers, the termination should still be
50 ohms to Vcc - 2 V as shown in Figure 11. Again the
Thevenin equivalent circuit (120 Ω resistor connected to Vcc
and an 82 Ω resistor connected to ground with the driver con-
nected to the junction of the 120 Ω and 82 Ω resistors) is a
valid termination as shown in Figure 12 for Vcc = 3.3 V.
20211415
FIGURE 11. Single-Ended LVPECL Operation, DC
Coupling
20211414
FIGURE 13. Single-Ended LVPECL Operation, AC
Coupling
3.7.4 Conversion to LVCMOS Outputs
To drive an LVCMOS input with an LMK03000 family LVDS
or LVPECL output, an LVPECL/LVDS to LVCMOS converter
such
as
National
Semiconductor's
DS90LV018A,
DS90LV028A, DS90LV048A, etc. is required. For best noise
performance, LVPECL provides a higher voltage swing into
input of the converter.
20211416
FIGURE 12. Single-Ended LVPECL Operation, DC
Coupling, Thevenin Equivalent
www.national.com
26
3.8 OSCin INPUT
In addition to LVDS and LVPECL inputs, OSCin can also be
driven with a sine wave. The OSCin input can be driven sin-
gle-ended or differentially with sine waves. The configurations
for these are shown in Figure 14 and Figure 15. Figure 16
shows the recommended power level for sine wave operation
for both differential and single-ended sources over frequency.
The part will operate at power levels below the recommended
power level, but as power decreases the PLL noise perfor-
mance will degrade. The VCO noise performance will remain
constant. At the recommended power level the PLL phase
noise degradation from full power operation (8 dBm) is less
than 2 dB.
20211424
FIGURE 15. Differential Sine Wave Input
20211422
FIGURE 14. Single-Ended Sine Wave Input
20211413
FIGURE 16. Recommended OSCin Power for Operation with a Sine Wave Input
3.9 MORE THAN EIGHT OUTPUTS WITH AN LMK03000
FAMILY DEVICE
using an LMK03000 device with eight LMK01000 family de-
vices up to 64 clocks may be distributed in many different
LVDS / LVPECL combinations. It's possible to distribute more
than 64 clocks by adding more LMK01000 family devices.
Refer to AN-1864 for more details on how to do this.
The LMK03000 family devices include eight or less outputs.
When more than 8 outputs are required the footprint compat-
ible LMK01000 family may be used for clock distribution. By
27
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Physical Dimensions inches (millimeters) unless otherwise noted
Leadless Leadframe Package (Bottom View)
48 Pin LLP (SQA48A) Package
Ordering Information
Order Number
LMK03000CISQ
LMK03000CISQX
LMK03000ISQ
VCO Version
Performance Grade
Packing
Package Marking
K3000CI
K3000CI
K3000 I
250 Unit Tape and Reel
2500 Unit Tape and Reel
250 Unit Tape and Reel
2500 Unit Tape and Reel
250 Unit Tape and Reel
1000 Unit Tape and Reel
2500 Unit Tape and Reel
250 Unit Tape and Reel
2500 Unit Tape and Reel
250 Unit Tape and Reel
2500 Unit Tape and Reel
250 Unit Tape and Reel
1000 Unit Tape and Reel
2500 Unit Tape and Reel
250 Unit Tape and Reel
1000 Unit Tape and Reel
250 Unit Tape and Reel
1000 Unit Tape and Reel
400 fs
800 fs
LMK03000ISQX
LMK03000DISQE
LMK03000DISQ
LMK03000DISQX
LMK03001CISQ
LMK03001CISQX
LMK03001ISQ
1.24 GHz
K3000 I
K3000DI
K3000DI
K3000DI
K3001CI
K3001CI
K3001 I
1200 fs
400 fs
800 fs
LMK03001ISQX
LMK03001DISQE
LMK03001DISQ
LMK03001DISQX
LMK03033CISQ
LMK03033CISQX
LMK03033ISQ
1.52 GHz
K3001 I
K3001DI
K3001DI
K3001DI
1200 fs
500 fs
800 fs
2 GHz
LMK03033ISQX
www.national.com
28
Notes
29
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Notes
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