LMP90077 [NSC]
Sensor AFE System: Multi-Channel, Low-Power 16-Bit; 传感器模拟前端系统：多通道，低功耗16位
| 型号： | LMP90077 |
| 厂家： | 
National Semiconductor |
| 描述： | Sensor AFE System: Multi-Channel, Low-Power 16-Bit |
| 文件： | 总62页 (文件大小：1686K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 30, 2011
LMP90080/LMP90079/
LMP90078/LMP90077
Sensor AFE System: Multi-Channel, Low-Power 16-Bit
Sensor AFE with True Continuous Background Calibration
Low-Noise programmable gain (1x - 128x)
■
■
1.0 General Description
Continuous background open/short and out of range
The LMP90080/LMP90079/LMP90078/LMP90077 are highly
sensor diagnostics
integrated, multi-channel, low-power 16-bit Sensor AFEs.
The devices feature a precision, 16-bit Sigma Delta Analog-
8 output data rates (ODR) with single-cycle settling
■
■
2 matched excitation current sources from 100 µA to
1000 µA (LMP90080/LMP90078)
4-DIFF / 7-SE inputs (LMP90080/LMP90079)
2-DIFF / 4-SE inputs (LMP90078/LMP90077)
7 General Purpose Input/Output pins
to-Digital Converter (ADC) with a low-noise programmable
gain amplifier and a fully differential high impedance analog
input multiplexer. A true continuous background calibration
feature allows calibration at all gains and output data rates
without interrupting the signal path. The background calibra-
tion feature essentially eliminates gain and offset errors
across temperature and time, providing measurement accu-
racy without sacrificing speed and power consumption.
■
■
■
■
■
■
■
■
■
Chopper-stabilized buffer for low offset
SPI 4/3-wire with CRC data link error detection
50 Hz to 60 Hz line rejection at ODR ≤13.42 SPS
Independent gain and ODR selection per channel
Supported by Webench Sensor AFE Designer
Automatic Channel Sequencer
Another feature of the LMP90080/LMP90079/LMP90078/
LMP90077 is continuous background sensor diagnostics, al-
lowing the detection of open and short circuit conditions and
out-of-range signals, without requiring user intervention, re-
sulting in enhanced system reliability.
Two sets of independent external reference voltage pins allow
multiple ratiometric measurements. In addition, two matched
programmable current sources are available in the
LMP90080/LMP90078 to excite external sensors such as re-
sistive temperature detectors and bridge sensors. Further-
more, seven GPIO pins are provided for interfacing to external
LEDs and switches to simplify control across an isolation bar-
rier.
3.0 Key Specifications
■ꢀENOB/NFR
■ꢀOffset Error (typ)
■ꢀGain Error (typ)
■ꢀTotal Noise
■ꢀIntegral Non-Linearity (INL max)
Up to 16/16 bits
8.4 nV
7 ppm
< 10 µV-rms
±1LSB
Collectively, these features make the LMP90080/LMP90079/
LMP90078/LMP90077 complete analog front-ends for low-
power, precision sensor applications such as temperature,
pressure, strain gauge, and industrial process control. The
LMP90080/LMP90079/LMP90078/LMP90077 are guaran-
teed over the extended temperature range of -40°C to +125°
C and are available in a 28-pin TSSOP package.
■ꢀOutput Data Rates (ODR)
■ꢀAnalog Voltage, VA
■ꢀOperating Temp Range
■ꢀPackage
1.6775 SPS - 214.65 SPS
+2.85V to +5.5V
-40°C to 125°C
28-Pin TSSOP
2.0 Features
4.0 Applications
16-Bit Low-Power Sigma Delta ADC
■
■
■
Temperature and Pressure Transmitters
■
■
■
True Continuous Background Calibration at all gains
Strain Gauge Interface
In-Place System Calibration using Expected Value
Industrial Process Control
programming
5.0 Typical Application
30169774
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation
301697
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6.0 Block Diagram
30169775
FIGURE 1. Block Diagram
• True Continuous Background Calibration
bridge sensors. The LMP90080/LMP90079’s multiplexer sup-
ports 4 differential channels while the LMP90078/LMP90077
supports 2. Each effective input voltage that is digitized is VIN
= VINx – VINy, where x and y are any input. In addition, the
input multiplexer of the LMP90080/LMP90079 also supports
7 single-ended channels (LMP90078/LMP90077 supports 4),
where the common ground is any one of the inputs.
The LMP90080/LMP90079/LMP90078/LMP90077 feature a
16 bit ΣΔ core with continuous background calibration to com-
pensate for gain and offset errors in the ADC, virtually elimi-
nating any drift with time and temperature. The calibration is
performed in the background without user or ADC input in-
terruption, making it unique in the industry and eliminating
down time associated with field calibration required with other
solutions. Having this continuous calibration improves perfor-
mance over the entire life span of the end product.
• Programmable Gain Amplifiers (FGA & PGA)
The LMP90080/LMP90079/LMP90078/LMP90077 contain
an internal 16x fixed gain amplifier (FGA) and a 1x, 2x, 4x, or
8x programmable gain amplifier (PGA). This allows accurate
gain settings of 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x through
configuration of internal registers. Having an internal amplifier
eliminates the need for external amplifiers that are costly,
space consuming, and difficult to calibrate.
• Continuous Background Sensor Diagnostics
Sensor diagnostics are also performed in the background,
without interfering with signal path performance, allowing the
detection of sensor shorts, opens, and out-of-range signals,
which vastly improves system reliability. In addition, the fully
flexible input multiplexer described below allows any input pin
to be connected to any ADC input channel providing addi-
tional sensor path diagnostic capability.
• Excitation Current Sources (IB1 & IB2) - LMP90080/
LMP90078
Two matched internal excitation currents, IB1 and IB2, can be
used for sourcing currents to a variety of sensors. The current
range is from 100 µA to 1000 µA in steps of 100 µA.
• Flexible Input MUX Channels
The flexible input MUX allows interfacing to a wide range of
sensors such as thermocouples, RTDs, thermistors, and
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2
Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Features ........................................................................................................................................ 1
3.0 Key Specifications ........................................................................................................................... 1
4.0 Applications .................................................................................................................................... 1
5.0 Typical Application ........................................................................................................................... 1
6.0 Block Diagram ................................................................................................................................ 2
7.0 Ordering Information ........................................................................................................................ 5
8.0 Connection Diagram ........................................................................................................................ 5
9.0 Pin Descriptions .............................................................................................................................. 6
10.0 Absolute Maximum Ratings ............................................................................................................. 7
11.0 Operating Ratings .......................................................................................................................... 7
12.0 Electrical Characteristics ................................................................................................................ 7
13.0 Timing Diagrams ......................................................................................................................... 12
14.0 Specific Definitions ...................................................................................................................... 15
15.0 Typical Performance Characteristics .............................................................................................. 16
16.0 Functional Description .................................................................................................................. 21
16.1 SIGNAL PATH ..................................................................................................................... 21
16.1.1 Reference Input (VREF) .............................................................................................. 21
16.1.2 Flexible Input MUX (VIN) ............................................................................................. 21
16.1.3 Selectable Gains (FGA & PGA) .................................................................................... 22
16.1.4 Buffer (BUFF) ............................................................................................................ 22
16.1.5 Internal/External CLK Selection .................................................................................... 22
16.1.6 Programmable ODRs .................................................................................................. 22
16.1.7 Digital Filter ............................................................................................................... 24
16.1.8 GPIO (D0–D6) ........................................................................................................... 27
16.2 CALIBRATION ..................................................................................................................... 27
16.2.1 Background Calibration ............................................................................................... 27
16.2.2 System Calibration ...................................................................................................... 28
FIGURE 15. Post-calibration Scaling Data-Flow Diagram ................................................... 29
16.3 CHANNELS SCAN MODE ..................................................................................................... 29
16.4 SENSOR INTERFACE .......................................................................................................... 30
16.4.1 IB1 & IB2 - Excitation Currents (LMP90080/LMP90078) ................................................... 30
16.4.2 Burnout Currents ........................................................................................................ 30
16.4.3 Sensor Diagnostic Flags .............................................................................................. 30
16.5 SERIAL DIGITAL INTERFACE ............................................................................................... 32
16.5.1 Register Address (ADDR) ............................................................................................ 32
16.5.2 Register Read/Write Protocol ....................................................................................... 32
16.5.3 Streaming .................................................................................................................. 32
16.5.4 CSB - Chip Select Bar ................................................................................................. 33
16.5.5 SPI Reset .................................................................................................................. 33
16.5.6 DRDYB - Data Ready Bar ............................................................................................ 33
16.5.7 Data Only Read Transaction ........................................................................................ 36
16.5.8 Cyclic Redundancy Check (CRC) ................................................................................. 37
16.6 POWER MANAGEMENT ...................................................................................................... 38
16.7 RESET and RESTART .......................................................................................................... 38
17.0 Applications Information ............................................................................................................... 39
17.1 QUICK START ..................................................................................................................... 39
17.2 CONNECTING THE SUPPLIES ............................................................................................. 39
17.2.1 VA and VIO ............................................................................................................... 39
17.2.2 VREF ........................................................................................................................ 39
17.3 ADC_DOUT CALCULATION .................................................................................................. 39
17.4 REGISTER READ/WRITE EXAMPLES ................................................................................... 40
17.4.1 Writing to Register Examples ....................................................................................... 40
17.4.2 Reading from Register Example ................................................................................... 41
17.5 STREAMING EXAMPLES ..................................................................................................... 42
17.5.1 Normal Streaming Example ......................................................................................... 42
17.5.2 Controlled Streaming Example ..................................................................................... 43
17.6 EXAMPLE APPLICATIONS ................................................................................................... 45
17.6.1 3–Wire RTD ............................................................................................................... 45
17.6.2 Thermocouple and IC Analog Temperature .................................................................... 47
18.0 Registers .................................................................................................................................... 48
18.1 REGISTER MAP .................................................................................................................. 48
18.2 POWER AND RESET REGISTERS ........................................................................................ 49
18.3 ADC REGISTERS ................................................................................................................ 51
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18.4 CHANNEL CONFIGURATION REGISTERS ............................................................................ 52
18.5 CALIBRATION REGISTERS .................................................................................................. 56
18.6 SENSOR DIAGNOSTIC REGISTERS ..................................................................................... 57
18.7 SPI REGISTERS .................................................................................................................. 58
18.8 GPIO REGISTERS ............................................................................................................... 60
19.0 Physical Dimensions .................................................................................................................... 61
List of Figures
FIGURE 1. Block Diagram ......................................................................................................................... 2
FIGURE 2. Timing Diagram ...................................................................................................................... 12
FIGURE 3. Simplified VIN Circuitry .............................................................................................................. 21
FIGURE 4. CLK Register Settings ............................................................................................................... 22
FIGURE 5. Digital Filter Response, 1.6775 SPS and 3.355 SPS .......................................................................... 24
FIGURE 6. Digital Filter Response, 6.71 SPS and 13.42 SPS .............................................................................. 24
FIGURE 7. Digital Filter Response at 13.42 SPS ............................................................................................. 25
FIGURE 8. Digital Filter Response, 26.83125 SPS and 53.6625 SPS .................................................................... 25
FIGURE 9. Digital Filter Response 107.325 SPS and 214.65 SPS ........................................................................ 26
FIGURE 10. Digital Filter Response for a 3.5717MHz versus 3.6864 MHz XTAL ...................................................... 26
FIGURE 11. GPIO Register Settings ............................................................................................................ 27
FIGURE 12. Types of Calibration ................................................................................................................ 27
FIGURE 13. BgcalMode2 Register Settings ................................................................................................... 28
FIGURE 14. System Calibration Data-Flow Diagram ......................................................................................... 28
FIGURE 15. Post-calibration Scaling Data-Flow Diagram ................................................................................... 29
FIGURE 16. Burnout Currents .................................................................................................................... 30
FIGURE 17. Burnout Currents Injection for ScanMode3 ..................................................................................... 30
FIGURE 18. Sensor Diagnostic Flags Diagram ............................................................................................... 31
FIGURE 19. Register Read/Write Protocol ..................................................................................................... 32
FIGURE 20. DRDYB Behavior .................................................................................................................... 33
FIGURE 21. DRDYB Behavior for an Incomplete ADC_DOUT Reading .................................................................. 33
FIGURE 22. DrdybCase1 Connection Diagram ............................................................................................... 34
FIGURE 23. Timing Protocol for DrdybCase1 ................................................................................................. 34
FIGURE 24. Timing Protocol for DrdybCase2 ................................................................................................. 35
FIGURE 25. DrdybCase3 Connection Diagram ............................................................................................... 36
FIGURE 26. Timing Protocol for DrdybCase3 ................................................................................................. 36
FIGURE 27. Timing Protocol for Reading SPI_CRC_DAT .................................................................................. 37
FIGURE 28. Timing Protocol for Reading SPI_CRC_DAT beyond normal DRDYB deassertion at every 1/ODR seconds ...... 37
FIGURE 29. Active, Power-Down, Stand-by State Diagram ................................................................................ 38
FIGURE 30. ADC_DOUT vs. VIN of a 16-Bit Resolution (VREF = 5.5V, Gain = 1). .................................................... 39
FIGURE 31. Register-Write Example 1 ......................................................................................................... 40
FIGURE 32. Register-Write Example 2 ......................................................................................................... 40
FIGURE 33. Register-Read Example ........................................................................................................... 41
FIGURE 34. Normal Streaming Example ....................................................................................................... 42
FIGURE 35. Setting up SPI_STREAMCN ...................................................................................................... 43
FIGURE 36. Controlled Streaming Example ................................................................................................... 44
FIGURE 37. Topology #1: 3-wire RTD Using 2 Current Sources ........................................................................... 45
FIGURE 38. Topology #2: 3-wire RTD Using 1 Current Source ............................................................................ 46
FIGURE 39. Thermocouple with CJC ........................................................................................................... 47
List of Tables
TABLE 1. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V ................................. 11
TABLE 2. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V .................................................... 11
TABLE 3. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V .................................. 11
TABLE 4. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V .................................................... 11
TABLE 5. Data First Mode Transactions ........................................................................................................ 36
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7.0 Ordering Information
Product
LMP90080
LMP90079
LMP90078
LMP90077
Channel Configuration
4 Differential / 7 Single-Ended
4 Differential / 7 Single-Ended
2 Differential / 4 Single-Ended
2 Differential / 4 Single-Ended
Current Sources
Yes
No
Yes
No
Order Code
Temperature Range
Description
LMP90080MH/NOPB
LMP90080MHE/NOPB
LMP90080MHX/NOPB
LMP90079MH/NOPB
LMP90079MHE/NOPB
LMP90079MHX/NOPB
LMP90078MH/NOPB
LMP90078MHE/NOPB
LMP90078MHX/NOPB
LMP90077MH/NOPB
LMP90077MHE/NOPB
LMP90077MHX/NOPB
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
28-Lead TSSOP Package, Rail of 48
28-Lead TSSOP Package, Reel of 250
28-Lead TSSOP Package, Reel of 2500
28-Lead TSSOP Package, Rail of 48
28-Lead TSSOP Package, Reel of 250
28-Lead TSSOP Package, Reel of 2500
28-Lead TSSOP Package, Rail of 48
28-Lead TSSOP Package, Reel of 250
28-Lead TSSOP Package, Reel of 2500
28-Lead TSSOP Package, Rail of 48
28-Lead TSSOP Package, Reel of 250
28-Lead TSSOP Package, Reel of 2500
8.0 Connection Diagram
30169776
See Pin Descriptions for specific information regarding options LMP90079, LMP90078, and LMP90077.
5
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9.0 Pin Descriptions
Pin #
1
Pin Name
Type
Function
Analog power supply pin
VA
Analog Supply
Analog Input
2 - 4
VIN0 - VIN2
Analog input pins
5 - 7
(LMP90080,
LMP90079)
VIN3 - VIN5
VIN3 - VIN5
Analog Input
No Connect
Analog input pins
5 - 7
(LMP90078,
LMP90077)
No connect: must be left unconnected
8
9
VREFP1
VREFN1
Analog Input
Analog Input
Analog Input
Analog Input
Positive reference input
Negative reference input
10
11
VIN6 / VREFP2
VIN7 / VREFN2
Analog input pin or VREFP2 input
Analog input pin or VREFN2 input
12 - 13
(LMP90080,
LMP90078)
IB2 & IB1
IB2 & IB1
Analog output
No Connect
Excitation current sources for external RTDs
12 - 13
(LMP90080,
LMP90078)
No connect: must be left unconnected
External crystal oscillator connection
14
XOUT
Analog output
Analog input
External crystal oscillator connection or external
clock input
15
XIN / CLK
16
17
GND
CSB
Ground
Digital Input
Digital Input
Digital Input
Digital Output
Digital IO
Power supply ground
Chip select bar
18
SCLK
Serial clock
19
SDI
Serial data input
20
SDO / DRDYB
D0 - D5
D6 / DRDYB
VIO
Serial data output and data ready bar
General purpose input/output (GPIO) pins
General purpose input/output pin or data ready bar
Digtal input/output supply pin
21 - 26
27
Digital IO
28
Digital Supply
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6
Machine Models (MM)
Charged Device Model (CDM)
200V
1250V
10.0 Absolute Maximum Ratings (Note
1, Note 2)
Junction Temperature (TJMAX
Storage Temperature Range
For soldering specifications:
see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
)
+150°C
–65°C to +150°C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Analog Supply Voltage, VA
Digital I/O Supply Voltage, VIO
Reference Voltage, VREF
-0.3V to 6.0V
-0.3V to 6.0V
-0.3V to VA+0.3V
-0.3V to VA+0.3V
11.0 Operating Ratings
Voltage on Any Analog Input Pin to
Analog Supply Voltage, VA
Digital I/O Supply Voltage, VIO
Full Scale Input Range, VIN
Reference Voltage, VREF
+2.85V to 5.5V
GND (Note 3)
+2.7V to 5.5V
±VREF / PGA
+0.5V to VA
Voltage on Any Digital Input PIN to
-0.3V to VIO+0.3V
GND (Note 3)
Voltage on SDO (Note 3)
-0.3V to VIO + 0.3V
TMIN = –40°C
TMAX = +125°C
Temperature Range for Electrical
Characteristics
Input Current at Any Pin (Note 3)
Output Current Source or Sink by SDO
5mA
3mA
Operating Temperature Range
Total Package Input and Output
Current
ESD Susceptibility
–40°C ≤ TA ≤ +125°C
20mA
Junction to Ambient Thermal
Resistance (θJA) (Note 4)
41°C/W
Human Body Model (HBM)
2500V
12.0 Electrical Characteristics
Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . Boldface limits
apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C.
Symbol Parameter
Conditions
Min
Typ
16
Max
Units
Bits
n
Resolution
Effective Number 3V / all / ON / OFF / all. Shorted input.
of Bits and Noise
Table 1
Bits
ENOB /
NFR
5V / all / ON / OFF / all. Shorted input.
Free Resolution
Table 3
Bits
ODR
Output Data Rates
1.6675
Table 1
Table 1
± 0.5
214.6
128
+1
SPS
Gain
FGA × PGA
1
3V / 214.65 / ON / ON / 1
-1
LSB
LSB
µV
Integral Non-
Linearity
INL
3V & 5V / 214.65 / ON / ON / 16
3V / all / ON / ON / all. Shorted input.
5V / all / ON / OFF / all. Shorted input.
± 1
Table 2
Table 4
Total Noise
Offset Error
µV
Below Noise
Floor (rms)
3V & 5V / all / ON or OFF / ON / all
µV
3V / 214.65 / ON / ON / 1
3V / 214.65 / ON / ON / 128
5V / 214.65 / ON / ON / 1
5V / 214.65 / ON / ON / 128
1.22
0.00838
1.79
9.52
0.70
8.25
0.63
µV
µV
µV
µV
OE
0.0112
3V & 5V / 214.65 / ON or OFF / OFF /
1-8
100
nV/°C
3V & 5V / 214.65 / ON / ON / 1-8
3V & 5V / 214.65 / ON / OFF / 16
3V & 5V / 214.65 / ON / ON / 16
3V & 5V / 214.65 / ON / OFF / 128
3V & 5V / 214.65 / ON / ON / 128
3
25
nV/°C
nV/°C
nV/°C
nV/°C
nV/°C
Offset Drift Over
Temp (Note 5)
0.4
6
0.125
nV /
1000 hours
5V / 214.65 / ON / OFF / 1, TA = 150°C
5V / 214.65 / ON / ON / 1, TA = 150°C
2360
100
Offset Drift over
Time (Note 5)
nV /
1000 hours
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Symbol Parameter
Conditions
Min
-80
Typ
7
Max
80
Units
ppm
ppm
ppm
ppm
3V & 5V / 214.65 / ON / ON / 1
3V & 5V / 13.42 / ON / ON / 16
3V & 5V / 13.42 / ON / ON / 64
3V & 5V / 13.42 / ON / ON / 128
50
GE
Gain Error
50
100
Gain Drift over
Temp (Note 5)
3V & 5V / 214.65 / ON / ON / all
0.5
5.9
1.6
ppm/°C
ppm / 1000
hours
5V / 214.65 / ON / OFF / 1, TA = 150°C
5V / 214.65 / ON / ON / 1, TA = 150°C
Gain Drift over
Time (Note 5)
ppm / 1000
hours
CONVERTER'S CHARACTERISTIC
DC, 3V / 214.65 / ON / ON / 1
70
90
117
120
117
dB
dB
dB
Input Common
CMRR Mode Rejection
Ratio
DC, 5V / 214.65 / OFF / OFF / 1
50/60 Hz, 5V / 214.65 / OFF / OFF / 1
Reference
Common Mode
Rejection
VREF = 2.5V
101
dB
DC, 3V / 214.65 / ON / ON / 1
DC, 5V / 214.65 / ON / ON / 1
75
115
112
dB
dB
Power Supply
PSRR
Rejection Ratio
Normal Mode
NMRR Rejection Ratio
(Note 5)
47 Hz to 63 Hz, 5V / 13.42 / OFF / OFF /
1
78
dB
3V / 214.65 / OFF / OFF / 1
5V / 214.65 / OFF / OFF / 1
95
95
136
143
dB
dB
Cross-talk
POWER SUPPLY CHARACTERISTICS
Analog Supply
Voltage
VA
2.85
2.7
3.0
3.3
5.5
5.5
V
V
Digital Supply
Voltage
VIO
3V / 13.42 / OFF / OFF / 1, ext. CLK
400
464
600
690
1547
1760
826
941
3
500
555
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
5V / 13.42 / OFF / OFF / 1, ext. CLK
3V / 13.42 / ON / OFF / 64, ext. CLK
5V / 13.42 / ON / OFF / 64, ext. CLK
3V / 214.65 / ON / OFF / 64, int. CLK
5V / 214.65 / ON / OFF / 64, int. CLK
3V / 214.65 / OFF / OFF / 1, int. CLK
5V / 214.65 / OFF / OFF / 1, int. CLK
Standby, 3V , int. CLK
700
800
1700
2000
1000
1100
10
Analog Supply
Current
IVA
Standby, 3V , ext. CLK
257
5
Standby, 5V, int. CLK
15
Standby, 3V, ext. CLK
300
2.6
Power-down, 3V, int/ext CLK
Power-down, 5V, int/ext CLK
5
9
4.6
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8
Symbol Parameter
REFERENCE INPUT
Conditions
Min
Typ
Max
Units
VREFP Positive Reference
VREFN + 0.5
GND
VA
V
V
Negative
VREFN
VREFP - 0.5
Reference
Differential
VREF
VREF = VREFP - VREFN
3V / 13.42 / OFF / OFF / 1
0.5
VA
V
MOhm
µA
Reference
Reference
ZREF
10
±2
6
Impedance
3V / 13.42 / ON or OFF / ON or OFF /
all
IREF
Reference Input
Capacitance of the
Positive Reference
CREFP
(Note 5), gain = 1
pF
Capacitance of the
CREFN Negative
Reference
(Note 5), gain = 1
6
1
pF
nA
Reference
ILREF
Power-down
Leakage Current
ANALOG INPUT
Gain = 1-8, buffer ON
Gain = 16 - 128, buffer ON
Gain = 1-8, buffer OFF
Gain = 1-8, buffer ON
Gain = 16 - 128, buffer ON
Gain = 1-8, buffer OFF
VIN = VINP - VINN
GND + 0.1
GND + 0.4
GND
VA - 0.1
VA - 1.5
VA
V
V
V
V
V
V
VINP
VINN
Positive Input
GND + 0.1
GND + 0.4
GND
VA - 0.1
VA - 1.5
VA
Negative Input
VIN
ZIN
Differential Input
±VREF / PGA
15.4
Differential Input
Impedance
ODR = 13.42 SPS
MOhm
pF
Capacitance of the 5V / 214.65 / OFF / OFF / 1
Positive Input
CINP
CINN
IIN
4
4
Capacitance of the 5V / 214.65 / OFF / OFF / 1
Negative Input
pF
3V & 5V / 13.42 / ON / OFF / 1-8
500
100
pA
pA
Input Leakage
Current
3V & 5V / 13.42 / ON / OFF / 16 - 128
DIGITAL INPUT CHARACTERISTICS at VA = VIO = VREF = 3.0V
Logical "1" Input
Voltage
VIH
0.7 x VIO
V
V
Logical "0" Input
Voltage
VIL
0.3 x VIO
+10
Digital Input
IIL
-10
µA
V
Leakage Current
Digital Input
VHYST
0.1 x VIO
Hysteresis
DIGITAL OUTPUT CHARACTERISTICS at VA = VIO = VREF = 3.0V
Logical "1" Output Source 300 µA
Voltage
VOH
2.6
-10
V
V
Logical "0" Output Sink 300 µA
Voltage
VOL
0.4
10
TRI-
IOZH,
STATE®Leakage
IOZL
µA
pF
Current
TRI-STATE
Capacitance
COUT
(Note 5)
5
9
www.national.com
Symbol Parameter
Conditions
Min
Typ
Max
Units
EXCITATION CURRENT SOURCES CHARACTERISTICS (LMP90080/LMP90078 only)
0, 100, 200,
300, 400, 500,
600, 700, 800,
900, 1000
Excitation Current
Source Output
IB1, IB2
µA
VA = VREF = 3V
VA = VREF = 5V
VA = 3.0V & 5.0V,
-7
2.5
0.2
7
%
%
IB1/IB2 Tolerance
IB1/IB2 Output
-3.5
3.5
VA - 0.8
0.07
V
Compliance Range IB1/IB2 = 100 µA to 1000 µA
VA = 5.0V,
IB1/IB2 Regulation
% / V
IB1/IB2 = 100 µA to 1000 µA
VA = 3.0V
IB1/IB2 Drift
95
60
ppm/°C
ppm/°C
IBTC
VA = 5.0V
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 100 µA
0.34
0.22
0.2
1.53
1
%
%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 200 µA
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 300 µA
0.85
0.8
%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 400 µA
0.15
0.14
0.13
0.075
0.085
0.11
0.11
2
%
3V & 5V / 214.65 / OFF / OFF / 1,
0.7
%
IB1/IB2 = 500 µA
IB1/IB2 Matching
IBMT
3V & 5V / 214.65 / OFF / OFF / 1,
0.7
%
IB1/IB2 = 600 µA
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 700 µA
0.65
0.6
%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 800 µA
%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 900 µA
0.55
0.45
%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 1000 µA
%
IB1/IB2 Matching VA = 3.0V & 5.0V,
IBMTC
ppm/°C
Drfit
IB1/IB2 = 100 µA to 1000 µA
INTERNAL/EXTERNAL CLK
Internal Clock
CLKIN
893
kHz
Frequency
External Clock
CLKEXT
(Note 5)
1.8
1.8
3.5717
7.2
MHz
Frequency
Input Low Voltage
Input High Voltage
Frequency
0
V
V
1
3.5717
7
External Crystal
Frequency
7.2
10
MHz
ms
Start-up time
SCLK
Serial Clock
MHz
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10
TABLE 1. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V
Gain
ODR (SPS)
1
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
2
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
4
8
16 (16)
16 (16)
16 (15.5)
16 (15)
16 (16)
16 (16)
16 (15.5)
16 (15)
16
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
32
16 (16)
16 (16)
16 (16)
16 (15.5)
16 (16)
16 (16)
16 (15.5)
16 (15)
64
16 (16)
16 (16)
16 (15)
16 (15)
16 (15.5)
16 (15)
16 (14.5)
16 (14.5)
128
16 (15.5)
16 (14.5)
16 (14.5)
16 (14)
1.6775
3.355
16 (16)
16 (16)
16 (16)
16 (15.5)
16 (16)
16 (16)
16 (16)
16 (15.5)
6.71
13.42
26.83125
53.6625
107.325
214.65
16 (15)
16 (14.5)
16 (14)
16 (13.5)
TABLE 2. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V
Gain of the ADC
ODR (SPS)
1
2
4
8
16
32
64
128
0.14
0.26
0.35
0.49
0.25
0.36
0.49
0.70
1.6775
3.355
3.08
4.56
6.15
8.60
3.35
4.81
6.74
9.52
1.90
2.70
4.10
5.85
2.24
3.11
4.51
6.37
1.53
2.21
3.16
4.29
1.65
2.37
3.38
4.72
1.27
1.67
2.39
3.64
1.33
1.90
2.66
3.79
0.23
0.34
0.51
0.67
0.33
0.44
0.63
0.90
0.21
0.27
0.40
0.54
0.27
0.39
0.54
0.79
0.15
0.24
0.37
0.51
0.26
0.37
0.52
0.72
6.71
13.42
26.83125
53.6625
107.325
214.65
TABLE 3. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V
Gain of the ADC
SPS
1.6775
1
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
2
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
4
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
8
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
32
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
64
16 (16)
16 (16)
16 (16)
16 (15.5)
16 (16)
16 (16)
16 (15.5)
16 (15)
128
16 (16)
3.355
16 (15.5)
16 (15)
6.71
13.42
16 (15)
26.83125
53.6625
107.325
214.65
16 (15.5)
16 (15)
16 (14.5)
16 (14)
TABLE 4. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V
Gain of the ADC
SPS
1
2
4
8
16
32
64
128
0.16
0.22
0.32
0.43
0.23
0.31
0.44
0.63
1.6775
3.355
2.68
3.86
5.23
7.94
2.90
4.11
5.74
8.25
1.65
2.36
3.49
5.01
1.86
2.60
3.72
5.31
1.24
1.78
2.47
3.74
1.34
1.90
2.72
3.82
1.00
1.47
2.09
2.94
1.08
1.50
2.11
2.97
0.22
0.34
0.44
0.61
0.29
0.39
0.56
0.79
0.19
0.27
0.34
0.50
0.24
0.35
0.48
0.68
0.17
0.22
0.30
0.45
0.23
0.32
0.46
0.64
6.71
13.42
26.83125
53.6625
107.325
214.65
11
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13.0 Timing Diagrams
Unless otherwise noted, specified limits apply for VA = VIO = 3.0V. Boldface limits apply for TMIN ≤ TA ≤ TMAX; the typical values
apply for TA = +25°C.
30169701
FIGURE 2. Timing Diagram
Symbol
fSCLK
tCH
Parameter
Conditions
Min
Typical
Max
Units
MHz
ns
10
0.4 / fSCLK
0.4 / fSCLK
SCLK High time
SCLK Low time
tCL
ns
30169702
30169703
Symbol
Parameter
Conditions
Min
Typical
Max
Units
CSB Setup time prior to an SCLK
rising edge
tCSSU
5
ns
CSB Hold time after the last rising
edge of SCLK
tCSH
6
ns
www.national.com
12
30169704
30169705
Symbol
tCLKR
Parameter
SCLK Rise time
Conditions
Min
Typical
1.15
Max
Units
ns
ns
tCLKF
SCLK Fall time
1.15
SDI Setup time prior to an SCLK
rising edge
5
6
ns
ns
tDISU
tDIH
SDI Hold time after an SCLK rising
edge
30169706
30169707
Symbol
Parameter
Conditions
Min
Typical
Max
Units
SDO Access time after an SCLK
falling edge
tDOA
35
ns
SDO Hold time after an SCLK
falling edge
tDOH
5
ns
ns
SDO Disable time after the rising
edge of CSB
tDOD1
5
13
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30169708
30169709
Symbol
Parameter
Conditions
Min
Typical
Max
Units
SDO Disable time after either
edge of SCLK
tDOD2
27
ns
30169711
30169710
Symbol
Parameter
Conditions
Min
Typical
Max
Units
SDO Enable time from the falling
edge of the 8th SCLK
tDOE
35
ns
tDOR
tDOF
SDO Rise time
SDO Fall time
(Note 5)
(Note 5)
7
7
ns
ns
µs
µs
64
4
ODR ≤ 13.42 SPS
13.42 < ODR ≤ 214.65 SPS
Data Ready Bar pulse at every
1/ODR second
tDRDYB
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified
Note 3: When the input voltage (VIN) exceeds the power supply (VIN < GND or VIN > VA), the current at that pin must be limited to 5mA and VIN has to be within
the Absolute Maximum Rating for that pin. The 20 mA package input current rating limits the number of pins that can safely exceed the power supplies with current
flow to four pins.
Note 4: The maximum power dissipation is a function of TJ(MAX) AND θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ
(MAX) - TA) / θJA
.
Note 5: This parameter is guaranteed by design and/or characterization and is not tested in production.
www.national.com
14
NEGATIVE GAIN ERROR is the difference between the neg-
ative full-scale error and the offset error divided by (VREF /
Gain).
14.0 Specific Definitions
COMMON MODE REJECTION RATIO is a measure of how
well in-phase signals common to both input pins are rejected.
To calculate CMRR, the change in output offset is measured
while the common mode input voltage is changed.
NOISE FREE RESOLUTION is a method of specifying the
number of bits for a converter with noise.
CMRR = 20 LOG(ΔCommon Input / ΔOutput Offset)
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) – says that the converter is equivalent to a perfect ADC
of this (ENOB) number of bits. LMP90080’s ENOB is a DC
ENOB spec, not the dynamic ENOB that is measured using
FFT and SINAD. Its equation is as follows:
ODR Output Data Rate.
OFFSET ERROR is the difference between the differential
input voltage at which the output code transitions from code
0000h to 0001h and 1 LSB.
POSITIVE FULL-SCALE ERROR is the difference between
the differential input voltage at which the output code transi-
tions to positive full scale and (VREF – 1LSB).
GAIN ERROR is the deviation from the ideal slope of the
transfer function.
POSITIVE GAIN ERROR is the difference between the pos-
itive full-scale error and the offset error divided by (VREF /
Gain).
INTEGRAL NON-LINEARITY (INL) is a measure of the de-
viation of each individual code from a straight line through the
input to output transfer function. The deviation of any given
code from this straight line is measured from the center of that
code value. The end point fit method is used. INL for this
product is specified over a limited range, per the Electrical
Tables.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure
of how well a change in the analog supply voltage is rejected.
PSRR is calculated from the ratio of the change in offset error
for a given change in supply voltage, expressed in dB.
PSRR = 20 LOG (ΔVA / ΔOutput Offset)
NEGATIVE FULL-SCALE ERROR is the difference between
the differential input voltage at which the output code transi-
tions to negative full scale and (-VREF + 1LSB).
15
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15.0 Typical Performance Characteristics Unless otherwise noted, specified limits apply for VA =
VIO = VREF = 3.0V. The maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = +25°C.
Noise Measurement without Calibration at Gain = 1
Noise Measurement with Calibration at Gain = 1
250
50
230
210
190
170
30
10
-10
-30
VA = 3V
150
VA = 3V
-50
0
200
400
600
800
1000
0
200
400
600
800
1000
TIME (ms)
TIME (ms)
30169715
30169716
Histogram without Calibration at Gain = 1
Histogram with Calibration at Gain = 1
30169721
30169722
Noise Measurement without Calibration at Gain = 8
Noise Measurement with Calibration at Gain = 8
40
20
35
30
25
20
15
10
5
15
10
5
0
-5
-10
-15
VA = 3V
VA = 3V
-20
0
0
200
400
600
800
1000
0
200
400
600
800
1000
TIME (ms)
TIME (ms)
30169717
30169718
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16
Histogram without Calibration at Gain = 8
Histogram with Calibration at Gain = 8
30169723
30169724
Noise Measurement without Calibration at Gain = 128
Noise Measurement with Calibration at Gain = 128
4
4
3
2
3
2
1
1
0
0
-1
-2
-3
-1
-2
-3
VA = 3V
VA = 3V
-4
-4
0
200
400
600
800
1000
0
200
400
600
800
1000
TIME (ms)
TIME (ms)
30169719
30169720
Histogram without Calibration at Gain = 128
Histogram with Calibration at Gain = 128
30169725
30169726
17
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Noise vs. Gain without Calibration at ODR = 13.42 SPS
Noise vs. Gain with Calibration at ODR = 13.42 SPS
30169741
30169748
Noise vs. Gain without Calibration at ODR = 214.65 SPS
Noise vs. Gain with Calibration at ODR = 214.65 SPS
30169749
30169750
Offset Error vs. Temperature without Calibration at Gain = 1 Offset Error vs. Temperature with Calibration at Gain = 1
300
250
200
150
100
50
2.0
1.5
1.0
0.5
0.0
VA = 3V
VA = 5V
VA = 3V
VA = 5V
0
-40 -20
0
20 40 60 80 100 120
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
30169761
30169764
www.national.com
18
Offset Error vs. Temperature without Calibration at Gain = 8 Offset Error vs. Temperature with Calibration at Gain = 8
25
20
15
10
5
0.4
0.2
VA = 5V
VA = 3V
0.0
VA = 3V
VA = 5V
-0.2
-0.4
0
-40 -20
0
20 40 60 80 100 120
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
30169762
30169765
Gain Error vs. Temperature without Calibration at Gain = 1 Gain Error vs. Temperature with Calibration at Gain = 1
160
150
140
130
120
110
40
20
0
VA = 5V
VA = 5V
VA = 3V
-20
VA = 3V
-40
-40 -20
0
20 40 60 80 100 120
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
30169767
30169770
Gain Error vs. Temperature without Calibration at Gain = 8 Gain Error vs. Temperature with Calibration at Gain = 8
-100
-110
-120
-130
-140
-150
-160
-20
VA = 3V
-40
VA = 3V
-60
-80
VA = 5V
VA = 5V
-100
-120
-40 -20
0
20 40 60 80 100 120
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
30169768
30169771
19
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Digital Filter Frequency Response
Digital Filter Frequency Response
0
0
-20
-40
-60
-80
-20
-40
-60
-80
1.7 SPS
3.4 SPS
26.83 SPS
53.66 SPS
-100
-120
-100
6.7 SPS
107.33 SPS
13.4 SPS
214.65 SPS
-120
1
10
100
10
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
30169751
30169753
INL at Gain = 1
10
5
0
-5
-10
VA = 5V, 13.4 SPS
-5 -4 -3 -2 -1
0
1
2
3
4
5
VIN (V)
30169727
www.national.com
20
programming the VREF_SEL bit in the CHx_INPUTCN reg-
isters (CHx_INPUTCN: VREF_SEL). The default mode is
VREF1. If VREF2 is used, then VIN6 and VIN7 cannot be
used as inputs because they share the same pin.
16.0 Functional Description
Throughout this datasheet, the LMP90080/LMP90079/
LMP90078/LMP90077 will be referred to as the LMP900xx.
The LMP900xx is a low-power 16-Bit ΣΔ ADC with 4 fully dif-
ferential / 7 single-ended analog channels for the LMP90080/
LMP90079 and 2 full differential / 4 single-ended for the
LMP90078/LMP90077. Its serial data output is two’s comple-
ment format. The output data rate (ODR) ranges from 1.6775
SPS to 214.65 SPS.
Refer to Section 17.2.2 VREF for VREF applications infor-
mation.
16.1.2 Flexible Input MUX (VIN)
LMP900xx provides a flexible input MUX as shown in Figure
3. The input that is digitized is VIN = VINP – VINN; where
VINP and VINN can be any availablie input.
The serial communication for LMP900xx is SPI, a syn-
chronous serial interface that operates using 4 pins: chip
select bar (CSB), serial clock (SCLK), serial data in (SDI), and
serial data out / data ready bar (SDO/DRYDYB).
The digitized input is also known as a channel, where
CH = VIN = VINP – VINN. Thus, there are a maximum of 4
differential channels: CH0, CH1, CH2, and CH3 for the
LMP90080/LMP90079. The LMP90078/LMP90077 has 2 dif-
ferential channels: CH0 and CH1 because it does not have
the VIN3, VIN4, and VIN5 pins.
True continuous built-in offset and gain background calibra-
tion is also available to improve measurement accuracy. Un-
like other ADCs, the LMP900xx’s background calibration can
run without heavily impacting the input signal. This unique
technique allows for positive as well as negative gain calibra-
tion and is available at all gain settings.
LMP900xx can also be configured single-endedly, where the
common ground is any one of the inputs. There are a maxi-
mum of 7 single-ended channels: CH0, CH1, CH2, CH3, CH4,
CH5, and CH6 for the LMP90080/LMP90079 and 4: CH0,
CH1, CH2, CH3 for the LMP90078/LMP90077.
The registers can be found in Section 18.0 Registers, and a
detailed description of the LMP900xx are provided in the fol-
lowing sections.
The input MUX can be programmed in the CHx_INPUTCN
registers. For example on the LMP90080, to program CH0 =
VIN = VIN4 – VIN1, go to the CH0_INPUTCN register and set:
16.1 SIGNAL PATH
1. VINP = 0x4
2. VINN = 0x1
16.1.1 Reference Input (VREF)
The differential reference voltage VREF (VREFP – VREFN)
sets the range for VIN.
The muxed VREF allows the user to choose between VREF1
or VREF2 for each channel. This selection can be made by
30169777
FIGURE 3. Simplified VIN Circuitry
21
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16.1.3 Selectable Gains (FGA & PGA)
When gain ≥ 16, the buffer is automatically included in the
signal path. When gain < 16, including or excluding the buffer
from the signal path can be done by programming the
CHX_CONFIG: BUF_EN bit.
LMP900xx provides two types of gain amplifiers: a fixed gain
amplifier (FGA) and a programmable gain amplifier (PGA).
FGA has a fixed gain of 16x or it can be bypassed, while the
PGA has programmable gain settings of 1x, 2x, 4x, or 8x.
16.1.5 Internal/External CLK Selection
Total gain is defined as FGA x PGA. Thus, LMP900xx pro-
vides gain settings of 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x
with true continuous background calibration.
LMP900xx allows two clock options: internal CLK or external
CLK (crystal (XTAL) or clock source).
There is an “External Clock Detection” mode, which detects
the external XTAL if it is connected to XOUT and XIN. When
operating in this mode, the LMP900xx shuts off the internal
clock to reduce power consumption. Below is a flow chart to
help set the appropriate clock registers.
The gain is channel specific, which means that one channel
can have one gain, while another channel can have the same
or a different gain.
The gain can be selected by programming the CHx_CONFIG:
GAIN_SEL bits.
16.1.4 Buffer (BUFF)
There is an internal unity gain buffer that can be included or
excluded from the signal path. Including the buffer provides a
high input impedance but increases the power consumption.
30169778
FIGURE 4. CLK Register Settings
The recommended value for the external CLK is discussed in
the next sections.
case, use the equation below to calculate the new ODR val-
ues.
ODR_Base1 = (CLKEXT) / (266,240)
ODR_Base2 = (CLKEXT) / (16,640)
16.1.6 Programmable ODRs
If using the internal CLK or external CLK of 3.5717 MHz, then
the output date rates (ODR) can be selected (using the
ODR_SEL bit) as:
ODR1 = (ODR_Base1) / n, where n = 1,2,4,8
ODR2 = (ODR_Base2) / n, where n = 1,2,4,8
1. 13.42/8 = 1.6775 SPS
2. 13.42/4 = 3.355 SPS
3. 13.42/2 = 6.71SPS
4. 13.42 SPS
For example, a 3.6864 MHz XTAL or external clock has the
following ODR values:
ODR_Base1 = (3.6864 MHz) / (266,240) = 13.85 SPS
ODR_Base2 = (3.6864 MHz) / (16,640) = 221.54 SPS
ODR1 = (13.85 SPS) / n = 13.85, 6.92, 3.46, 1.73 SPS
ODR2 = (221.54 SPS) / n = 221.54, 110.77, 55.38, 27.69 SPS
5. 214.65/8 = 26.83125 SPS
6. 214.65/4 = 53.6625 SPS
7. 214.65/2 = 107.325 SPS
8. 214.65 SPS (default)
If the internal CLK is not being used and the external CLK is
not 3.5717 MHz, then the ODR will be different. If this is the
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22
The ODR is channel specific, which means that one channel
can have one ODR, while another channel can have the same
or a different ODR.
scanning. For example, if the ADC were running at 214.65
SPS and four channels are being scanned, then the ODR per
channel would be 214.65/4 = 53.6625 SPS.
Note that these ODRs are meant for a single channel con-
version; the ODR needs to be divided by n for n channels
23
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16.1.7 Digital Filter
The LMP900xx has a fourth order rotated sinc filter that is used to configure various ODRs and to reject power supply frequencies
of 50Hz and 60Hz. The 50/60 Hz rejection is only effective when the device is operating at ODR ≤ 13.42 SPS. If the internal CLK
or the external CLK of 3.5717 MHz is used, then the LMP900xx will have the frequency response shown in Figure 5 through Figure
9.
0
1.6775 SPS
3.355 SPS
-20
-40
-60
-80
-100
-120
0
12
24
36
48
60
72
84
96
108
120
FREQUENCY (Hz)
30169760
FIGURE 5. Digital Filter Response, 1.6775 SPS and 3.355 SPS
0
-20
6.71 SPS
13.42 SPS
-40
-60
-80
-100
-120
0
12
24
36
48
60
72
84
96
108
120
FREQUENCY (Hz)
30169773
FIGURE 6. Digital Filter Response, 6.71 SPS and 13.42 SPS
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-60
-70
13.42 SPS
-80
-90
-100
-110
-120
45
47
49
51
53
55
57
59
61
63
65
FREQUENCY (Hz)
30169744
FIGURE 7. Digital Filter Response at 13.42 SPS
0
26.83125 SPS
53.6625 SPS
-40
-80
-120
0
200
400
600
800
1000
1200
1400
1600
1800
2000
FREQUENCY (Hz)
30169786
FIGURE 8. Digital Filter Response, 26.83125 SPS and 53.6625 SPS
25
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0
107.325 SPS
214.65 SPS
-40
-80
-120
0
200
400
600
800
1000
1200
1400
1600
1800
2000
FREQUENCY (Hz)
30169787
FIGURE 9. Digital Filter Response 107.325 SPS and 214.65 SPS
If the internal CLK is not being used and the external CLK is not 3.5717 MHz, then the filter response would be the same as the
response shown above, but the frequency will change according to the equation:
fNEW = [(CLKEXT) / 256 ] x (fOLD / 13.952k)
Using the equation above, an example of the filter response for a 3.5717 MHz XTAL versus a 3.6864 MHz XTAL can be seen in
Figure 10.
0
Crystal = 3.5717 MHz
Crystal = 3.6864 MHz
-20
-40
-60
-80
-100
-120
-140
40
45
50
55
60
65
70
FREQUENCY (Hz)
30169756
FIGURE 10. Digital Filter Response for a 3.5717MHz
versus 3.6864 MHz XTAL
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26
16.1.8 GPIO (D0–D6)
Figure 11 shows a flowchart how these GPIOs can be pro-
grammed.
Pins D0-D6 are general purpose input/output (GPIO) pins that
can be used to control external LEDs or switches. Only a high
or low value can be sourced to or read from each pin.
30169733
FIGURE 11. GPIO Register Settings
16.2 CALIBRATION
As seen in Figure 12, there are two types of calibration: back-
ground calibration and system calibration. These calibrations
are further described in the next sections.
30169779
FIGURE 12. Types of Calibration
16.2.1 Background Calibration
Figure 12 also shows that there are two types of background
calibration:
Background calibration is the process of continuously deter-
mining and applying the offset and gain calibration coeffi-
cients to the output codes to minimize the LMP900xx’s offset
and gain errors. Background calibration is a feature built into
the LMP900xx and is automatically done by the hardware
without interrupting the input signal.
1. Type 1: Correction - the process of continuously
determining and applying the offset and gain calibration
coefficients to the output codes to minimize the
LMP900xx’s offset and gain errors.
This method keeps track of changes in the LMP900xx's
gain and offset errors due to changes in the operating
condition such as voltage, temperature, or time.
Four differential channels, CH0-CH3, each with its own gain
and ODRs, can be calibrated to improve the accuracy.
2. Type 2: Estimation - the process of determining and
continuously applying the last known offset and gain
Types of Background Calibration:
27
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calibration coefficients to the output codes to minimize
the LMP900xx’s offset and gain errors.
The System Calibration Offset Registers (CHx_SCAL_OFF-
SET) hold the System Calibration Offset Coefficients in 16-
bit, two's complement binary format. The System Calibration
Gain Registers (CHx_SCAL_GAIN) hold the System Calibra-
tion Gain Coefficient in 16-bit, 1.15, unsigned, fixed-point
binary format. For each channel, the System Calibration Off-
set coefficient is subtracted from the conversion result prior
to the division by the System Calibration Gain coefficient.
The last known offset or gain calibration coefficients can
come from two sources. The first source is the default
coefficient which is pre-determined and burnt in the
device’s non-volatile memory. The second source is from
a previous calibration run of Type 1: Correction.
The benefits of using type 2 calibration is a higher throughput,
lower power consumption, and slightly better noise. The exact
savings would depend on the number of channels being
scanned, and the ODR and gain of each channel.
A data-flow diagram of these coefficients can be seen in Fig-
ure 14.
Using Background Calibration:
There are four modes of background calibration, which can
be programmed using the BGCALCN bits. They are as fol-
lows:
1. BgcalMode0: Background Calibration OFF
2. BgcalMode1: Offset Correction / Gain Estimation
30169731
3. BgcalMode2: Offset Correction / Gain Correction
Follow Figure 13 to set other appropriate registers when
using this mode.
FIGURE 14. System Calibration Data-Flow Diagram
4. BgcalMode3: Offset Estimation / Gain Estimation
There are four distinct sets of System Calibration Offset and
System Calibration Gain Registers for use with CH0-CH3.
CH4-CH6 reuse the registers of CH0-CH2, respectively.
The LMP900xx provides two system calibration modes that
automatically fill the Offset and Gain coefficients for each
channel. These modes are the System Calibration Offset Co-
efficient Determination mode and the System Calibration
Gain Coefficient Determination mode. The System Calibra-
tion Offset Coefficient Determination mode must be entered
prior to the System Calibration Gain Coefficient Determina-
tion mode, for each channel.
The system zero-scale condition is a system input condition
(sensor loading) for which zero (0x0000) system-calibrated
output code is desired. It may not, however, cause a zero in-
put voltage at the input of the ADC.
The system reference-scale condition is usually the system
full-scale condition in which the system's input (or sensor's
loading) would be full-scale and the desired system-calibrat-
ed output code would be 0x8000 (unsigned 16-bit binary).
However, system full-scale condition need not cause full-
scale input voltage at the input of the ADC.
The system reference-scale condition is not restricted to just
the system full-scale condition. In fact, it can be any arbitrary
fraction of full-scale (up to 1.25 times) and the desired system-
calibrated output code can be any appropriate value (up to
0xA000). The CHx_SCAL_GAIN register must be written with
the desired system-calibrated output code (default:0x8000)
before entering the System Calibration Gain Coefficient De-
termination mode. This helps in in-place system calibration.
30169730
FIGURE 13. BgcalMode2 Register Settings
If operating in BgcalMode2, four channels (with the same
ODR) are being converted, and FGA_BGCAL = 0 (default),
then the ODR is reduced by:
Below are the detailed procedures for using the System Cal-
ibration Offset Coefficient Determination and System Cali-
bration Gain Coefficient Determination modes.
1. 0.19% of 1.6775 SPS
2. 0.39% of 3.355 SPS
3. 0.78% of 6.71 SPS
4. 1.54% of 13.42 SPS
5. 3.03% of 26.83125 SPS
6. 5.88% of 53.6625 SPS
7. 11.11% of 107.325 SPS
8. 20% of 214.65 SPS
System Calibration Offset Coefficient Determination
mode
1. Apply system zero-scale condition to the channel (CH0/
CH1/CH2/CH3).
2. Enter the System Calibration Offset Coefficient
Determination mode by programming 0x1 in the
SCALCN register.
16.2.2 System Calibration
The LMP900xx provides some unique features to support
easy system offset and system gain calibrations.
3. LMP900xx starts a fresh conversion at the selected
output data rate for the selected channel. At the end of
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28
the conversion, the CHx_SCAL_OFFSET register is
filled-in with the System Calibration Offset coefficient.
4. The System Calibration Offset Coefficient Determination
mode is automatically exited.
5. The computed calibration coefficient is accurate only to
the effective resolution of the device and will probably
contain some noise. The noise factor can be minimized
by computing over many times, averaging (externally)
and putting the resultant value back into the register.
Alternatively, select the output data rate to be 26.83 sps
or 1.67 sps.
30169742
FIGURE 15. Post-calibration Scaling Data-Flow Diagram
System Calibration Gain Coefficient Determination mode
16.3 CHANNELS SCAN MODE
1. Repeat the System Calibration Offset Coefficient
Determination to calibrate the System offset for the
channel.
There are four scan modes. These scan modes are selected
using the CH_SCAN: CH_SCAN_SEL bit. The first scanned
channel is FIRST_CH, and the last scanned channel is
LAST_CH; they are both located in the CH_SCAN register.
2. Apply the system reference-scale condition to the
channel CH0/CH1/CH2/CH3.
The CH_SCAN register is double buffered. That is, user in-
puts are stored in a slave buffer until the start of the next
conversion during which time they are transferred to the mas-
ter buffer. Once the slave buffer is written, subsequent up-
dates are disregarded until a transfer to the master buffer
happens. Hence, it may be appropriate to check the
CH_SCAN_NRDY bit before programming the CH_SCAN
register.
3. In the CHx_SCAL_GAIN register, program the expected
(desired) system-calibrated output code for this condition
in 16-bit unsigned format.
4. Enter the System Calibration Gain Coefficient
Determination mode by programming 0x3 in the
SCALCN register.
5. LMP900xx starts a fresh conversion at the selected
output data rate for the channel. At the end of the
conversion, the CHx_SCAL_GAIN is filled-in (or
overwritten) with the System Calibration Gain coefficient.
ScanMode0: Single-Channel Continuous Conversion
LMP900xx continuously converts the selected FIRST_CH.
6. The System Calibration Gain Coefficient Determination
mode is automatically exited.
Do not operate in this scan mode if gain ≥ 16 and the LM-
P900xx is running in background calibration modes Bg-
calMode1 or BgcalMode2. If this is the case, then it is more
suitable to operate the device in ScanMode2 instead.
7. The computed calibration coefficient is accurate only to
the effective resolution of the device and will probably
contain some noise. The noise factor can be minimized
by computing over many times, averaging (externally)
and putting the resultant value back into the register.
Alternatively, select the output data rate to be 26.83 sps
or 1.67 sps.
ScanMode1: Multiple-Channels Single Scan
LMP900xx converts one or more channels starting from
FIRST_CH to LAST_CH, and then enters the stand-by state.
Post-calibration Scaling
ScanMode2: Multiple-Channels Continuous Scan
LMP900xx allows scaling (multiplication and shifting) for the
System Calibrated result. This eases downstream process-
ing, if any. Multiplication is done using the System Calibration
Scaling Coefficient in the CHx_SCAL_SCALING register and
shifting is done using the System Calibration Bits Selector in
the CHx_SCAL_BITS_SELECTOR register.
LMP900xx continuously converts one or more channels start-
ing from FIRST_CH to LAST_CH, and then it repeats this
process.
ScanMode3: Multiple-Channels Continuous Scan with
Burnout Currents
This mode is the same as ScanMode2 except that the burnout
current is provided in a serially scanned fashion (injected in a
channel after it has undergone a conversion). Thus it avoids
burnout current injection from interfering with the conversion
result for the channel.
The System Calibration Bits Selector value should ideally be
the logarithm (to the base 2) of the System Calibration Scaling
Coefficient value.
There are four distinct sets of System Calibration Scaling and
System Calibration Bits Selector Registers for use with CH0-
CH3. CH4-CH6 reuse the registers of CH0-CH2, respectively.
The sensor diagnostic burnout currents are available for all
four scan modes. The burnout current is further gated by the
BURNOUT_EN bit for each channel. ScanMode3 is the only
mode that scans multiple channels while injecting burnout
currents without interfering with the signal. This is described
in details in Section 16.4.2 Burnout Currents.
A data-flow diagram of these coefficients can be seen in Fig-
ure 15
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16.4 SENSOR INTERFACE
Burnout Current Injection:
The LMP90080/LMP90078 contains two excitation currents
(IB1 & IB2) for sourcing external sensors, and the LMP900xx
contain two burnout currents for sensor diagnostics. They are
described in the next sections.
Burnout currents are injected differently depending on the
channel scan mode selected.
When BURNOUT_EN = 1 and the device is operating in
ScanMode0, 1, or 2, the burnout currents are injected into all
the channels for which the BURNOUT_EN bit is selected.
This will cause problems and hence in this mode, more than
one channel should not have its BURNOUT_EN bit selected.
Also, the burnout current will interfere with the signal and in-
troduce a fixed error depending on the particular external
sensor.
16.4.1 IB1 & IB2 - Excitation Currents (LMP90080/
LMP90078)
IB1 and IB2 can be used for providing currents to external
sensors, such as RTDs or bridge sensors. 100µA to 1000µA,
in steps of 100µA, can be sourced by programming the
ADC_AUXCN: RTD_CUR_SEL bits.
When BURNOUT_EN = 1 and the device is operating in
ScanMode3, burnout currents are injected into the last sam-
pled channel on a cyclical basis (Figure 17). In this mode,
burnout currents injection is truly done in the background
without affecting the accuracy of the on-going conversion.
Operating in this mode is recommended.
Refer to Section 17.6.1 3–Wire RTD to see how IB1 and IB2
can be used to source a 3-wire RTD.
16.4.2 Burnout Currents
As shown in Figure 16, the LMP900xx contains two internal
10 µA burnout current sources, one sourcing current from VA
to VINP, and the other sinking current from VINN to ground.
These currents are used for sensor diagnostics and can be
enabled for each channel using the CHx_INPUTCN:
BURNOUT_EN bit.
30169781
FIGURE 17. Burnout Currents Injection for ScanMode3
16.4.3 Sensor Diagnostic Flags
Burnout currents can be used to verify that an external sensor
is still operational before attempting to make measurements
on that channel. A non-operational sensor means that there
is a possibility the connection between the sensor and the
LMP900xx is open circuited, short circuited, shorted to VA or
GND, overloaded, or the reference may be absent. The sen-
sor diagnostic flags diagram can be seen in Figure 18.
30169780
FIGURE 16. Burnout Currents
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30169782
FIGURE 18. Sensor Diagnostic Flags Diagram
The sensor diagnostic flags are located in the
POR_AFT_LST_RD:
SENDIAG_FLAGS register and are described in further de-
tails below.
If POR_AFT_LST_READ = 1, then there was a power-on re-
set since the last time the SENDIAG_FLAGS register was
read. This flag's status is cleared when this bit is read, unless
this bit is set again on account of another power-on-reset
event in the intervening period.
SHORT_THLD_FLAG:
The short circuit threshold flag is used to report a short-circuit
condition. It is set when the output voltage (VOUT) is within
the absolute Vthreshold. Vthreshold can be programmed us-
ing the 8-bit SENDIAG_THLDH register.
OFLO_FLAGS:
OFLO_FLAGS is used to indicate whether the modulator is
over-ranged or under-ranged. The following conditions are
possible:
For example, assume VREF = 5V, gain = 1, SENDIAG_THLD
= 0xDA (218d). In this case, Vthreshold can be calculated as:
1. OFLO_FLAGS = 0x0: Normal Operation
Vthreshold = [(SENDIAG_THLD)(2)(VREF)] / [(Gain)(216)]
Vthreshold = [(218)(2)(5V)] / [(1)(216)]
Vthreshold = 33.3 mV
2. OFLO_FLAGS = 0x1: The modulator was not
overranged, but ADC_DOUT got clamped to 0x7FFF
(positive fullscale) or 0x8000 (negative full scale). For
example, if VREF = 5V, VIN = 2V, and gain = 128, then
OFLO_FLAGS would be 01b.
When
(-33.3mV)
≤
VOUT
≤
(33.3mV),
then
SHORT_THLD_FLAG = 1; otherwise, SHORT_THLD_FLAG
= 0.
3. OFLO_FLAGS = 0x2: The modulator was over-ranged
towards +VREF.
4. OFLO_FLAGS = 0x3: The modulator was over-ranged
towards −VREF.
RAILS_FLAG:
The rails flag is used to detect if one of the sampled channels
is within 50mV of the rails potential (VA or VSS). This can be
further investigated to detect an open-circuit or short-circuit
condition. If the sampled channel is near a rail, then
RAILS_FLAG = 1; otherwise, RAILS_FLAG = 0.
The condition of OFLO_FLAGS = 10b or 11b can be used in
conjunction with the RAILS_FLAG to determine the fault con-
dition.
SAMPLED_CH:
These three bits show the channel number for which the
ADC_DOUT and SENDIAG_FLAGS are available. This does
not necessarily indicate the current channel under conversion
because the conversion frame and computation of results
from the channels are pipelined. That is, while the conversion
is going on for a particular channel, the results for the previous
conversion (of the same or a different channel) are available.
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16.5 SERIAL DIGITAL INTERFACE
16.5.2 Register Read/Write Protocol
A synchronous 4-wire serial peripheral interface (SPI) pro-
vides access to the internal registers of LMP900xx via CSB,
SCLK, SDI, SDO/DRDYB.
Figure 19 shows the protocol how to write to or read from a
register.
Transaction 1 sets up the upper register address (URA)
where the user wants to start the register-write or register-
read.
16.5.1 Register Address (ADDR)
All registers are memory-mapped. A register address (ADDR)
is composed of an upper register address (URA) and lower
register address (LRA) as shown in ADDR Map. For example,
ADDR 0x3A has URA=0x3 and LRA=0xA.
Transaction 2 sets the lower register address (LRA) and in-
cludes the Data Byte(s), which contains the incoming data
from the master or outgoing data from the LMP900xx.
Examples of register-reads or register-writes can be found in
ADDR Map
Section 17.4 REGISTER READ/WRITE EXAMPLES.
Bit
[6:4]
[3:0]
Name
URA
LRA
30169736
FIGURE 19. Register Read/Write Protocol
16.5.3 Streaming
0x1F, 0x20, 0x21. Once the data reaches ADDR 0x21, LM-
P900xx will wrap back to ADDR 0x1C and repeat this process
until CSB deasserts. See Section 17.5.2 Controlled Stream-
ing Example for an example of the Controlled Streaming
mode.
When writing/reading 3+ bytes, the user must operate the de-
vice in Normal Streaming mode or Controlled Streaming
mode. In the Normal Streaming mode, which is the default
mode, data runs continuously starting from ADDR until CSB
deasserts. This mode is especially useful when programming
all the configuration registers in a single transaction. See
Section 17.5.1 Normal Streaming Example for an example of
the Normal Streaming mode.
If streaming reaches ADDR 0x7F, then it will wrap back to
ADDR 0x00. Furthermore, reading back the Upper Register
Address after streaming will report the Upper Register Ad-
dress at the start of streaming, not the Upper Register Ad-
dress at the end of streaming.
In the Controlled Streaming mode, data runs continuously
starting from ADDR until the data has run through all
(STRM_RANGE + 1) registers. For example, if the starting
ADDR is 0x1C, STRM_RANGE = 5, then data will be written
to or read from the following ADDRs: 0x1C, 0x1D, 0x1E,
To stream, write 0x3 to INST2’s SZ bits as seen in Figure
19. To select the stream type, program the SPI_STREAMCN:
STRM_TYPE bit. The STRM_RANGE can also be pro-
grammed in the same register.
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16.5.4 CSB - Chip Select Bar
rising edge. After an SPI Reset, SDI is monitored for a pos-
sible Write Instruction at each SCLK rising edge.
An SPI transaction begins when the master asserts (active
low) CSB and ends when the master deasserts (active high)
CSB. Each transaction might be separated by a subsequent
one with a CSB deassertion, but this is optional. Once CSB
is asserted, it must not pulse (deassert and assert again) dur-
ing a (desired) transaction.
SPI Reset will reset the Upper Address Register (URA) to 0,
but the register contents are not reset.
By default, SPI reset is disabled, but it can be enabled by
writing 0x01 to SPI Reset Register (ADDR 0x02).
16.5.6 DRDYB - Data Ready Bar
CSB can be grounded in systems where LMP900xx is the only
SPI slave. This frees the software from handling the CSB.
Care has to be taken to avoid any false edge on SCLK, and
while operating in this mode, the streaming transaction should
not be used because exiting from this mode can only be done
through a CSB deassertion.
DRDYB is a signal generated by the LMP900xx that indicates
a fresh conversion data is available in the ADC_DOUT reg-
isters.
DRDYB is automatically asserted every (1/ODR) second as
seen in Figure 20. Before the next assertion, DRDYB will
pulse for tDRDYB second. The value for tDRDYB can be found in
Section 13.0 Timing Diagrams.
16.5.5 SPI Reset
SPI Reset resets the SPI-Protocol State Machine by moni-
toring the SDI for at least 73 consecutive 1's at each SCLK
30169785
FIGURE 20. DRDYB Behavior
If ADC_DOUT is being read while a new ADC_DOUT be-
comes available, then the ADC_DOUT that is being read is
still valid (Figure 21). DRDYB will still be deasserted every 1/
ODR second, but a consecutive read on the ADC_DOUT reg-
ister will fetch the newly converted data available.
30169712
FIGURE 21. DRDYB Behavior for an Incomplete ADC_DOUT Reading
DRDYB can also be accessed via registers using the
DT_AVAIL_B bit. This bit indicates when fresh conversion
data is available in the ADC_DOUT registers. If new conver-
sion data is available, then DT_AVAIL_B = 0; otherwise,
DT_AVAIL_B = 1.
DrdybCase1:
SDO_DRDYB_DRIVER = 0x00
Combining
SDO/DRDYB
with
A complete reading for DT_AVAIL_B occurs when the MSB
of ADC_DOUTH is read out. This bit cannot be reset even if
REG_AND_CNV_RST = 0xC3.
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30169732
FIGURE 22. DrdybCase1 Connection Diagram
As shown in Figure 22, the drdyb signal and SDO can be
Note that INST1 and UAB are omitted from the figure below
because this transaction is only required if a new UAB needs
to be implemented.
multiplexed on the same pin as their functions are mostly
complementary. In fact, this is the default mode for the
SDO/DRDYB pin.
While the CSB is asserted, DRDYB is driving the
SDO/DRDYB pin unless the device is reading data, in which
case, SDO will be driving the pin. If CSB is deasserted, then
the SDO/DRDYB pin is High-Z.
Figure 23 shows a timing protocol for DrdybCase1. In this
case, start by asserting CSB first to monitor a drdyb assertion.
When the drdyb signal asserts, begin writing the Instruction
Bytes (INST1, UAB, INST2) to read from or write to registers.
30169701
FIGURE 23. Timing Protocol for DrdybCase1
DrdybCase2:
SDO_DRDYB_DRIVER = 0x03
Combining
SDO/DRDYB
with
can only be used when the LMP900xx is the only device con-
nected to the master's SPI bus because the SDO/DRDYB pin
will be DRDYB even when CSB is deasserted.
SDO/DRDYB can be made independent of CSB by setting
SDO_DRDYB_DRIVER = 0x03 in the SPI Handshake Control
register. In this case, DRDYB will drive the pin unless the de-
vice is reading data, independent of the state of CSB. SDO
will drive the pin when CSB is asserted and the device is
reading data.
The timing protocol for this case can be seen in Figure 24.
When drdyb asserts, assert CSB to start the SPI transaction
and begin writing the Instruction Bytes (INST1, UAB, INST2)
to read from or write to registers.
With this scheme, one can use SDO/DRDYB as a true inter-
rupt source, independent of the state of CSB. But this scheme
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30169729
FIGURE 24. Timing Protocol for DrdybCase2
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DrdybCase3: Routing DRDYB to D6
30169791
FIGURE 25. DrdybCase3 Connection Diagram
The drdyb signal can be routed to pin D6 by setting
SPI_DRDYB_D6 high and SDO_DRDYB_DRIVER to 0x4.
This is the behavior for DrdybCase3 as shown in Figure 25.
using the interrupt or polling method. If polled, the drdyb signal
needs to be polled faster than tDRDYB to detect a drdyb as-
sertion. When drdyb asserts, assert CSB to start the SPI
transaction and begin writing the Instruction Bytes (INST1,
UAB, INST2) to read from or write to registers.
The timing protocol for this case can be seen in Figure 26.
Since DRDYB is separated from SDO, it can be monitored
30169789
FIGURE 26. Timing Protocol for DrdybCase3
16.5.7 Data Only Read Transaction
In order to use the data only transaction, the device must be
placed in the data first mode. The following table lists trans-
action formats for placing the device in and out of the data first
mode and reading the mode status.
In a data only read transaction, one can directly access the
data byte(s) as soon as the CSB is asserted without having
to send any instruction byte. This is useful as it brings down
the latency as well as the overhead associated with the in-
struction byte (as well as the Upper Address Byte, if any).
TABLE 5. Data First Mode Transactions
Bit[7]
Bits[6:5]
Bit[4]
Bits[3:0]
1010
Data Bytes
None
Enable Data First Mode Instruction
Disable Data First Mode Instruction
Read Mode Status Transaction
1
1
1
11
11
00
1
1
1
1011
None
1111
One
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36
Note that while being in the data first mode, once the data
bytes in the data only read transaction are sent out, the device
is ready to start on any normal (non-data-only) transaction
including the Disable Data First Mode Instruction. The current
status of the data first mode (enabled/disabled status) can be
read back using the Read Mode Status Transaction. This
transaction consists of the Read Mode Status Instruction fol-
lowed by a single data byte (driven by the device). The data
first mode status is available on bit [1] of this data byte.
Transaction; this transaction should be completed before the
next scheduled DRDYB deassertion.
16.5.8 Cyclic Redundancy Check (CRC)
CRC can be used to ensure integrity of data read from LM-
P900xx. To enable CRC, set EN_CRC high. Once CRC is
enabled, the CRC value is calculated and stored in
SPI_CRC_DAT so that the master device can periodically
read for data comparison. The CRC is automatically reset
when CSB or DRDYB is deasserted.
The CRC polynomial is x8 + x5 + x4 + 1. The reset value of the
SPI_CRC_DAT register is zero, and the final value is ones-
complemented before it is sent out. Note that CRC computa-
tion only includes the bits sent out on SDO and does not
include the bits of the SPI_CRC_DAT itself; thus it is okay to
read SPI_CRC_DAT repeatedly.
The data only read transaction allows reading up to eight
consecutive registers, starting from any start address. Usu-
ally, the start address will be the address of the most signifi-
cant byte of conversion data, but it could just as well be any
other address. The start address and number of bytes to be
read during the data only read transaction can be pro-
grammed using the DATA_ONLY_1 AND DATA_ONLY_2
registers respectively.
The drdyb signal normally deasserts (active high) every 1/
ODR second. However, this behavior can be changed so that
drdyb deassertion can occur after SPI_CRC_DAT is read, but
not later than normal DRDYB deassertion which occurs at
every 1/ODR seconds. This is done by setting bit
DRDYB_AFT_CRC high.
The upper register address is unaffected by a data only read
transaction. That is, it retains its setting even after encoun-
tering a data only transaction. The data only transaction uses
its own address (including the upper address) from the
DATA_ONLY_1 register. When in the data first mode, the
SCLK must stop high before entering the Data Only Read
The timing protocol for CRC can be found in Figure 27.
30169759
FIGURE 27. Timing Protocol for Reading SPI_CRC_DAT
If SPI_CRC_DAT read extends beyond the normal DRDYB
deassertion at every 1/ODR seconds, then CRC_RST has to
be set in the SPI Data Ready Bar Control Register. This is
done to avoid a CRC reset at the DRDYB deassertion.Timing
protocol for reading CRC with CRC_RST set is shown in Fig-
ure 28
30169738
FIGURE 28. Timing Protocol for Reading SPI_CRC_DAT beyond normal DRDYB deassertion at every 1/ODR seconds
37
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16.7 RESET and RESTART
16.6 POWER MANAGEMENT
Writing 0xC3 to the REG_AND_CNV_RST field will reset the
conversion and most of the programmable registers to their
default values. The only registers that will not be reset are the
System Calibration Registers (CHx_SCAL_OFFSET,
CHx_SCAL_GAIN) and the DT_AVAIL_B bit.
The device can be placed in Active, Power-Down, or Stand-
By state.
In Power-Down, the ADC is not converting data, contents of
the registers are unaffected, and there is a drastic power re-
duction. In Stand-By, the ADC is not converting data, but the
power is only slightly reduced so that the device can quickly
transition into the active state if desired.
If it is desirable to reset the System Calibration Coefficient
Registers, then set RESET_SYSCAL = 1 before writing 0xC3
to REG_AND_CNV_RST. If the device is operating in the
“System Calibration Offset/Gain Coefficient Determination”
mode (SCALCN register), then write REG_AND_CNV_RST
= 0xC3 twice to get out of this mode.
These states can be selected using the PWRCN register.
When written, PWRCN brings the device into the Active, Pow-
er-Down, or Stand-By state. When read, PWRCN indicates
the state of the device.
After a register reset, any on-going conversions will be abort-
ed and restarted. If the device is in the power-down state, then
a register reset will bring it out of the power-down state.
The read value would confirm the write value after a small
latency (approximately 15 µs with the internal CLK). It may be
appropriate to wait for this latency to confirm the state change.
Requests not adhering to this latency requirement may be
rejected.
To restart a conversion, write 1 to the RESTART bit. This bit
can be used to synchronize the conversion to an external
event.
It is not possible to make a direct transition from the power-
down state to the stand-by state. This state diagram is shown
below.
30169788
FIGURE 29. Active, Power-Down, Stand-by State Diagram
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38
be the same as VA and sourced with a clean source that is
bypassed with a ceramic capacitor value of 0.1 µF and a tan-
talum capacitor of 10 µF.
17.0 Applications Information
17.1 QUICK START
LMP900xx also allows ratiometric connection for noise im-
munity reasons. A ratiometric connection is when the ADC’s
VREFP and VREFN are used to excite the input device’s (i.e.
a bridge sensor) voltage references. This type of connection
severely attenuates any VREF ripple seen the ADC output,
and is thus strongly recommended.
This section shows step-by-step instructions to configure the
LMP900xx to perform a simple DC reading from CH0.
1. Apply VA = VIO = VREFP1 = 5V, and ground VREFN1
2. Apply VINP = ¾VREF and VINN = ¼VREF for CH0.
Thus, set CH0 = VIN = VINP - VINN = ½VREF
(CH0_INPUTCN register)
17.3 ADC_DOUT CALCULATION
3. Set gain = 1 (CH0_CONFIG: GAIN_SEL = 0x0)
The output code of the LMP900xx can be calculated as:
4. Exclude the buffer from the signal path (CH0_CONFIG:
BUF_EN = 1)
5. Set the background to BgcalMode2 (BGCALCN = 0x2)
6. Select VREF1 (CH0_INPUTCN: VREF_SEL = 0)
7. To use the internal CLK, set CLK_EXT_DET = 1 and
CLK_SEL = 0.
Equation 1 — Output Code
8. Follow the register read/write protocol (Figure 19) to
capture ADC_DOUT from CH0.
ADC_DOUT is in 16−bit two's complement binary format. The
largest positive value is 0x7FFF (or 32767 in decimal), while
the largest negative value is 0x8000 (or 32768 in decimal). In
case of an over range the value is automatically clamped to
one of these two values.
17.2 CONNECTING THE SUPPLIES
17.2.1 VA and VIO
Any ADC architecture is sensitive to spikes on the analog
voltage, VA, digital input/output voltage, VIO, and ground
pins. These spikes may originate from switching power sup-
plies, digital logic, high power devices, and other sources. To
diminish these spikes, the LMP900xx’s VA and VIO pins
should be clean and well bypassed. A 0.1 µF ceramic bypass
capacitor and a 1 µF tantalum capacitor should be used to
bypass the LMP900xx supplies, with the 0.1 µF capacitor
placed as close to the LMP900xx as possible.
Figure 30 shows the theoretical output code, ADC_DOUT, vs.
analog input voltage, VIN, using the equation above.
Since the LMP900xx has both external VA and VIO pins, the
user has two options on how to connect these pins. The first
option is to tie VA and VIO together and power them with the
same power supply. This is the most cost effective way of
powering the LMP900xx but is also the least ideal because
noise from VIO can couple into VA and negatively affect per-
formance. The second option involves powering VA and VIO
with separate power supplies. These supply voltages can
have the same amplitude or they can be different.
17.2.2 VREF
Operation with VREF below VA is also possible with slightly
diminished performance. As VREF is reduced, the range of
acceptable analog input voltages is also reduced. Reducing
the value of VREF also reduces the size of the LSB. When
the LSB size goes below the noise floor of the LMP900xx, the
noise will span an increasing number of codes and perfor-
mance will degrade. For optimal performance, VREF should
30169747
FIGURE 30. ADC_DOUT vs. VIN of a 16-Bit Resolution
(VREF = 5.5V, Gain = 1).
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17.4 REGISTER READ/WRITE EXAMPLES
17.4.1 Writing to Register Examples
Using the register read/write protocol shown in Figure 19, the following example shows how to write three data bytes starting at
register address (ADDR) 0x1F. After the last byte has been written to ADDR 0x21, deassert CSB to end the register-write.
30169737
FIGURE 31. Register-Write Example 1
The next example shows how to write one data byte to ADDR 0x12. Since the URA for this example is the same as the last example,
transaction 1 can be omitted.
30169790
FIGURE 32. Register-Write Example 2
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17.4.2 Reading from Register Example
The following example shows how to read two bytes. The first byte will be read from starting ADDR 0x24, and the second byte will
be read from ADDR 0x25.
30169739
FIGURE 33. Register-Read Example
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17.5 STREAMING EXAMPLES
17.5.1 Normal Streaming Example
This example shows how to write six data bytes starting at ADDR 0x28 using the Normal Streaming mode. Because the default
STRM_TYPE is the Normal Streaming mode, setting up the SPI_STREAMCN register can be omitted.
30169792
FIGURE 34. Normal Streaming Example
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17.5.2 Controlled Streaming Example
This example shows how to read the 16-bit conversion data (ADC_DOUT) four times using the Controlled Streaming mode. The
ADC_DOUT registers consist of ADC_DOUTH at ADDR 0x1A and ADC_DOUTL at ADDR 0x1B.
The first step (Figure 35) sets up the SPI_STREAMCN register. This step enters the Controlled Streaming mode by setting
STRM_TYPE high in ADDR 0x03. Since two registers (ADDR 0x1A - 0x1B) need to be read, the STRM_RANGE is 1.
30169793
FIGURE 35. Setting up SPI_STREAMCN
The next step shows how to perform the Controlled Streaming mode so that the master device will read ADC_DOUT from ADDR
0x1A and 0x1B, then wrap back to ADDR 0x1A, and repeat this process for four times. After this process, deassert CSB to end
the Controlled Streaming mode.
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30169794
FIGURE 36. Controlled Streaming Example
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17.6 EXAMPLE APPLICATIONS
17.6.1 3–Wire RTD
30169752
FIGURE 37. Topology #1: 3-wire RTD Using 2 Current Sources
Figure 37 shows the first topology for a 3-wire resistive tem-
perature detector (RTD) application. Topology #1 uses two
excitation current sources, IB1 and IB2, to create a differential
voltage across VIN0 and VIN1. As a result of using both IB1
and IB2, only one channel (VIN0-VIN1) needs to be mea-
sured. As shown in Equation 2, the equation for this channel
is IB1 x (RTD – RCOMP) assuming that RLINE1 = RLINE2.
The advantage of this circuit is its ratiometric configuration,
where VREF = (IB1 + IB2) x (RREF). Equation 3 shows that
a ratiometric configuration eliminates IB1 and IB2 from the
output equation, thus increasing the overall performance.
Equation 2 — VIN Equation for Topology #1
The PT-100 changes linearly from 100 Ohm at 0°C to
146.07 Ohm at 120°C. If desired, choose a suitable compen-
sating resistor (RCOMP) so that VIN can be virtually 0V at any
desirable temperature. For example, if RCOMP = 100 Ohm,
then at 0°C, VIN = 0V and thus a higher gain can be used.
Equation 3 — ADC_DOUT Showing IB1 & IB2 Elimination
45
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30169796
FIGURE 38. Topology #2: 3-wire RTD Using 1 Current Source
Figure 38 shows the second topology for a 3-wire RTD appli-
cation. Topology #2 shows the same connection as topology
#1, but without IB2. Although this topology eliminates a cur-
rent source, it requires two channel measurements as shown
in Equation 4.
Equation 4 — VIN Equation for Topology #2
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46
17.6.2 Thermocouple and IC Analog Temperature
30169799
FIGURE 39. Thermocouple with CJC
The LMP900xx is also ideal for thermocouple temperature
applications. Thermocouples have several advantages that
make them popular in many industrial and medical applica-
tions. Compare to RTDs, thermistors, and IC sensors, ther-
mocouples are the most rugged, least expensive, and can
operate over the largest temperature range.
In a CJC technique, the “cold” junction temperature, Tcold, is
sensed by using an IC temperature sensor, such as the
LM94022. The temperature sensor should be placed within
close proximity of the reference junction and should have an
isothermal connection to the board to minimize any potential
temperature gradients.
A thermocouple is a sensor whose junction generates a dif-
ferential voltage, VIN, that is relative to the temperature dif-
ference (Thot – Tcold). Thot is also known as the measuring
junction or “hot” junction, which is placed at the measured
environment. Tcold is also known as the reference or “cold”
junction, which is placed at the measuring system environ-
ment.
Once Tcold is obtained, use a standard thermocouple look-
up-table to find its equivalent voltage. Next, measure the
differential thermocouple voltage and add the equivalent cold
junction voltage. Lastly, convert the resulting voltage to tem-
perature using a standard thermocouple look-up-table.
For example, assume Tcold = 20°C. The equivalent voltage
from a type K thermocouple look-up-table is 0.798 mV. Next,
add the measured differential thermocouple voltage to the
Tcold equivalent voltage. For example, if the thermocouple
voltage is 4.096 mV, the total would be 0.798 mV + 4.096 mV
= 4.894 mV. Referring to the type K thermocouple table gives
a temperature of 119.37°C for 4.894 mV.
Because a thermocouple can only measure a temperature
difference, it does not have the ability to measure absolute
temperature. To determine the absolute temperature of the
measured environment (Thot), a technique known as cold
junction compensation (CJC) must be used.
47
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4. If written to, registers indicated as Reserved must have
the indicated default value as shown below. Any other
value can cause unexpected results.
18.0 Registers
1. If written to, RESERVED bits must be written to only 0
unless otherwise indicated.
18.1 REGISTER MAP
2. Read back value of RESERVED bits and registers is
unspecified and should be discarded.
3. Recommended values must be programmed and
forbidden values must not be programmed where they
are indicated in order to avoid unexpected results.
ADDR
(URA & LRA)
Register Name
Type
Default
RESETCN
Reset Control
SPI Handshake Control
SPI Reset Control
SPI Stream Control
-
0x00
WO
R/W
R/W
R/W
-
-
SPI_HANDSHAKECN
SPI_RESET
0x01
0x00
0x00
0x00
0x00
0x02
SPI_STREAMCN
Reserved
0x03
0x04 - 0x07
RO &
WO
PWRCN
Power Mode Control and Status
Data Only Read Control 1
Data Only Read Control 2
ADC Restart Conversion
-
0x08
0x09
0x00
0x1A
0x02
-
DATA_ONLY_1
DATA_ONLY_2
ADC_RESTART
Reserved
R/W
R/W
WO
-
0x0A
0x0B
0x0C - 0x0D
0x0E
0x00
0x00
GPIO_DIRCN
GPIO Direction Control
R/W
RO &
WO
GPIO_DAT
GPIO Data
0x0F
0x10
-
0x00
0x03
0x00
0x02
0x00
0x0000
0x00
-
BGCALCN
Background Calibration Control
SPI Data Ready Bar Control
ADC Auxiliary Control
CRC Control
R/W
R/W
R/W
R/W
R/W
-
SPI_DRDYBCN
ADC_AUXCN
SPI_CRC_CN
SENDIAG_THLD
Reserved
0x11
0x12
0x13
Sensor Diagnostic Threshold
-
0x14
0x15-0x16
0x17
SCALCN
System Calibration Control
ADC Data Available
Sensor Diagnostic Flags
Conversion Data 1 and 0
-
R/W
RO
RO
RO
-
ADC_DONE
SENDIAG_FLAGS
ADC_DOUT
Reserved
0x18
0x19
-
0x1A - 0x1B
0x1C
-
-
RO &
WO
SPI_CRC_DAT
CRC Data
0x1D
-
CHANNEL CONFIGURATION REGISTERS (CH4 to CH6 for LMP90080/LMP90079 only)
CH_STS
Channel Status
0x1E
0x1F
0x20
0x21
0X22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
RO
0x00
0x30
0x01
0x70
0x13
0x70
0x25
0x70
0x37
0x70
0x01
0x70
0x13
0x70
CH_SCAN
Channel Scan Mode
CH0 Input Control
CH0 Configuration
CH1 Input Control
CH1 Configuration
CH2 Input Control
CH2 Configuration
CH3 Input Control
CH3 Configuration
CH4 Input Control
CH4 Configuration
CH5 Input Control
CH5 Configuration
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CH0_INPUTCN
CH0_CONFIG
CH1_INPUTCN
CH1_CONFIG
CH2_INPUTCN
CH2_CONFIG
CH3_INPUTCN
CH3_CONFIG
CH4_INPUTCN
CH4_CONFIG
CH5_INPUTCN
CH5_CONFIG
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48
ADDR
(URA & LRA)
Register Name
Type
Default
CH6_INPUTCN
CH6_CONFIG
Reserved
CH6 Input Control
0x2C
0x2D
R/W
R/W
-
0x25
0x70
0x00
CH6 Configuration
-
0x2E - 0x2F
SYSTEM CALIBRATION REGISTERS
CH0_SCAL_OFFSET
Reserved
CH0 System Calibration Offset Coefficients
0x30 - 0x31
0x32
R/W
-
0x0000
0x00
-
CH0_SCAL_GAIN
Reserved
CH0 System Calibration Gain Coefficients
-
0x33 - 0x34
0x35
R/W
-
0x8000
0x00
CH0_SCAL_SCALING CH0 System Calibration Scaling Coefficients
0x36
R/W
0x01
CH0_SCAL_BITS_SEL
CH0 System Calibration Bit Selector
ECTOR
0x37
0x38 - 0x39
0x3A
R/W
R/W
-
0x00
0x0000
0x00
CH1_SCAL_OFFSET
Reserved
CH1 System Calibration Offset Coefficients
-
CH1_SCAL_GAIN
Reserved
CH1 System Calibration Gain Coefficient
-
0x3B - 0x3C
0x3D
R/W
-
0x8000
0x00
CH1_SCAL_SCALING CH1 System Calibration Scaling Coefficients
0x3E
R/W
0x01
CH1_SCAL_BITS_SEL
CH1 System Calibration Bit Selector
ECTOR
0x3F
0x40 - 0x41
0x42
R/W
R/W
-
0x00
0x0000
0x00
CH2_SCAL_OFFSET
Reserved
CH2 System Calibration Offset Coefficients
-
CH2_SCAL_GAIN
Reserved
CH2 System Calibration Gain Coefficient
-
0x43 - 0x44
0x45
R/W
-
0x8000
0x00
CH2_SCAL_SCALING CH2 System Calibration Scaling Coefficients
0x46
R/W
0x01
CH2_SCAL_BITS_SEL
CH2 System Calibration Bit Selector
ECTOR
0x47
0x48 - 0x49
0x4A
R/W
R/W
-
0x00
0x0000
0x00
CH3_SCAL_OFFSET
Reserved
CH3 System Calibration Offset Coefficients
-
CH3_SCAL_GAIN
Reserved
CH3 System Calibration Gain Coefficient
-
0x4B - 0x4C
0x4D
R/W
-
0x8000
0x00
CH3_SCAL_SCALING CH3 System Calibration Scaling Coefficients
0x4E
R/W
0x01
CH3_SCAL_BITS_SEL
CH3 System Calibration Bit Selector
ECTOR
0x4F
R/W
-
0x00
0x00
Reserved
-
0x50 - 0x7F
18.2 POWER AND RESET REGISTERS
ꢁ
RESETCN: Reset Control (Address 0x00)
Bit Bit Symbol
Bit Description
Register and Conversion Reset
[7:0] REG_AND_CNV_ RST
0xC3: Register and conversion reset
Others: Neglected
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ꢁ
SPI_RESET: SPI Reset Control (Address 0x02)
Bit Bit Symbol
Bit Description
SPI Reset Enable
0x0 (default): SPI Reset Disabled
0x1: SPI Reset Enabled
[0] SPI_ RST
Note:Once Written, The contents of this register are sticky. That is, the content of this reg-
ister cannot be changed with subsequent write.However, a Register reset clears the register
as well as the sticky status.
ꢁ
PWRCN: Power Mode Control and Status (Address 0x08)
Bit Bit Symbol
Bit Description
[7:2] Reserved
-
Power Control
Write Only – power down mode control
0x0: Active Mode
0x1: Power-down Mode
0x3: Stand-by Mode
[1:0] PWRCN
Read Only – the present mode is:
0x0 (default): Active Mode
0x1: Power-down Mode
0x3: Stand-by Mode
ꢁ
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50
18.3 ADC REGISTERS
ꢁ
ADC_RESTART: ADC Restart Conversion (Address 0x0B)
Bit Bit Symbol
Bit Description
[7:1] Reserved
-
Restart conversion
0
RESTART
1: Restart conversion.
ꢁ
14.2.1. ADC_AUXCN: ADC Auxiliary Control (Address 0x12)
Bit Bit Symbol
Bit Description
7
Reserved
-
The System Calibration registers (CHx_SCAL_OFFSET and CHx_SCAL_GAIN) are:
0 (default): preserved even when "REG_AND_CNV_ RST" = 0xC3.
1: reset by setting "REG_AND_CNV_ RST" = 0xC3.
6
RESET_SYSCAL
External clock detection
5
4
CLK_EXT_DET
CLK_SEL
0 (default): "External Clock Detection" is operational
1: "External-Clock Detection" is bypassed
Clock select – only valid if CLK_EXT_DET = 1
0 (default): Selects internal clock
1: Selects external clock
Selects RTD Current as follows:
0x0 (default): 0 µA
0x1: 100 µA
0x2: 200 µA
0x3: 300 µA
0x4: 400 µA
0x5: 500 µA
0x6: 600 µA
RTD_CUR_SEL
[3:0] (LMP90080 and LMP90078
only)
0x7: 700 µA
0x8: 800 µA
0x9: 900 µA
0xA: 1000 µA
ꢁ
ADC_DONE: ADC Data Available (Address 0x18)
Bit Bit Symbol
Bit Description
Data Available – indicates if new conversion data is available
0x00 − 0xFE: Available
[7:0] DT_AVAIL_B
0xFF: Not available
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ꢁ
ADC_DOUT: 16-bit Conversion Data (two’s complement) (Address 0x1A - 0x1B)
Address Name
Register Description
ADC Conversion Data [15:8]
ADC Conversion Data [7:0]
Reserved
0x1A
0x1B
0x1C
ADC_DOUTH
ADC_DOUTL
Reserved
Note: Repeat reads of these registers are allowed as long as such reads are spaced apart by at least 72 µs.
ꢁ
18.4 CHANNEL CONFIGURATION REGISTERS
ꢁ
CH_STS: Channel Status (Address 0x1E)
Bit Bit Symbol
Bit Description
[7:2] Reserved
-
Channel Scan Not Ready – indicates if it is okay to program CH_SCAN
0: Update not pending, CH_SCAN register is okay to program
1: Update pending, CH_SCAN register is not ready to be programmed
1
0
CH_SCAN_NRDY
Invalid or Repeated Read Status
INV_OR_RPT_RD_STS
0: ADC_DOUT just read was valid and hitherto unread
1: ADC_DOUT just read was either invalid (not ready) or there was a repeated read.
ꢁ
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CH_SCAN: Channel Scan Mode (Address 0x1F)
Bit Bit Symbol
Bit Description
Channel Scan Select
0x0 (default): ScanMode0: Single-Channel Continuous Conversion
0x1: ScanMode1: One or more channels Single Scan
0x2: ScanMode2: One or more channels Continuous Scan
0x3: ScanMode3: One or more channels Continuous Scan with Burnout Currents
[7:6] CH_SCAN_SEL
Last channel for conversion
0x0: CH0
0x1: CH1
0x2: CH2
0x3: CH3
0x4: CH4
0x5: CH5
LAST_CH
[5:3] (CH4 to CH6 for LMP90080
and LMP90079 only)
0x6 (default): CH6
Note: LAST_CH cannot be smaller than FIRST_CH. For example, if LAST_CH = CH5, then
FIRST_CH cannot be CH6. If 0x7 is written it is ignored.
ꢁ
Starting channel for conversion
0x0 (default): CH0
0x1: CH1
0x2: CH2
0x3: CH3
0x4: CH4
0x5: CH5
FIRST_CH
[2:0] (CH4 to CH6 for LMP90080
and LMP90079 only)
0x6: CH6
Note: FIRST_CH cannot be greater than LAST_CH. For example, if FIRST_CH = CH1,
then LAST_CH cannot be CH0. If 0x7 is written it is ignored.
ꢁ
Note: While writing to the CH_SCAN register, if 0x7 is written
to FIRST_CH or LAST_CH the write to the entire CH_SCAN
register is ignored.
ꢁ
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CHx_INPUTCN: Channel Input Control (CH4 to CH6 for LMP90080/LMP90079 only)
Register Address (hex):
a. CH0: 0x20
b. CH1: 0X22
c. CH2: 0x24
d. CH3: 0x26
e. CH4: 0x28
f. CH5: 0x2A
g. CH6: 0x2C
ꢁ
Bit Bit Symbol
Bit Description
Enable sensor diagnostic
7
6
BURNOUT_EN
VREF_SEL
0 (default): Disable Sensor Diagnostics current injection for this Channel
1: Enable Sensor Diagnostics current injection for this Channel
Select the reference
0 (Default): Select VREFP1 and VREFN1
1: Select VREFP2 and VREFN2
Positive input select
0x0: VIN0
0x1: VIN1
0x2: VIN2
0x3: VIN3 (LMP90080/LMP90079 only)
0x4: VIN4 (LMP90080/LMP90079 only)
0x5: VIN5 (LMP90080/LMP90079 only)
0x6: VIN6
[5:3] VINP
0x7: VIN7
Note: to see the default values for each channel, refer to the table below.
Negative input select
0x0: VIN0
0x1: VIN1
0x2: VIN2
0x3: VIN3 (LMP90080/LMP90079 only)
0x4: VIN4 (LMP90080/LMP90079 only)
0x5: VIN5 (LMP90080/LMP90079 only)
0x6: VIN6
[2:0] VINN
0x7: VIN7
Note: to see the default values for each channel, refer to the table below.
Default VINx for CH0-CH6
CH4 (LMP90080/ VIN0
LMP90079 only)
VIN1
VIN3
VIN5
VINP
VIN0
VIN2
VINN
CH5 (LMP90080/ VIN2
LMP90079 only)
CH0
CH1
VIN1
VIN3 (LMP90080/
LMP90079 only)
CH6 (LMP90080/ VIN4
LMP90079 only)
CH2
CH3
VIN4 (LMP90080/ VIN5 (LMP90080/
LMP90079 only)
VIN6
LMP90079 only)
VIN7
ꢁ
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54
CHx_CONFIG: Channel Configuration (CH4 to CH6 LMP90080/LMP90079 only)
Register Address (hex):
a. CH0: 0x21
b. CH1: 0x23
c. CH2: 0x25
d. CH3: 0x27
e. CH4: 0x29
f. CH5: 0x2B
g. CH6: 0x2D
ꢁ
Bit Bit Symbol
Reserved
Bit Description
7
-
ODR Select
0x0: 13.42 / 8 = 1.6775 SPS
0x1: 13.42 / 4 = 3.355 SPS
0x2: 13.42 / 2 = 6.71 SPS
0x3: 13.42 SPS
[6:4] ODR_SEL
0x4: 214.65 / 8 = 26.83125 SPS
0x5: 214.65 / 4 = 53.6625 SPS
0x6: 214.65 / 2 = 107.325 SPS
0x7 (default): 214.65 SPS
Gain Select
0x0 (default): 1 (FGA OFF)
0x1: 2 (FGA OFF)
0x2: 4 (FGA OFF)
0x3: 8 (FGA OFF)
0x4: 16 (FGA ON)
0x5: 32 (FGA ON)
0x6: 64 (FGA ON)
0x7: 128 (FGA ON)
[3:1] GAIN_SEL
Enable/Disable the buffer
0 (default): Include the buffer in the signal path
1: Exclude the buffer from the signal path
0
BUF_EN
Note: When gain ≥ 16, the buffer is automatically included in the signal path irrespective
of this bit.
55
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18.5 CALIBRATION REGISTERS
ꢁ
BGCALCN: Background Calibration Control (Address 0x10)
Bit Bit Symbol
Bit Description
[7:2] Reserved
-
ꢁ
Background calibration control – selects scheme for continuous background calibration.
0x0 (default): BgcalMode0: Background Calibration OFF
0x1: BgcalMode1: Offset Correction / Gain Estimation
0x2: BgcalMode2: Offset Correction / Gain Correction
0x3: BgcalMode3: Offset Estimation / Gain Estimation
[1:0] BGCALN
ꢁ
SCALCN: System Calibration Control (Address 0x17)
Bit Bit Symbol
Bit Description
[7:2] Reserved
-
ꢁ
System Calibration Control
When written, set SCALCN to:
0x0 (default): Normal Mode
0x1: “System Calibration Offset Coefficient Determination” mode
0x2: “System Calibration Gain Coefficient Determination” mode
0x3: Reserved
[1:0] SCALCN
When read, this bit indicates the system calibration mode is in:
0x0: Normal Mode
0x1: "System Calibration Offset Coefficient Determination" mode
0x2: "System Calibration Gain Coefficient Determination" mode
0x3: Reserved
Note: when read, this bit will indicate the current System Calibration status. Since this co-
efficient determination mode will only take 1 conversion cycle, reading this register will only
return 0x00, unless this register is read within 1 conversion window.
ꢁ
ꢁ
CHx_SCAL_OFFSET: CH0-CH3 System Calibration Offset Registers (Two's-Complement)
ADDR
Name
Description
CH0 CH1 CH2 CH3
0x30 0x38 0x40 0x48 CHx_SCAL_OFFSETH
0x31 0x39 0x41 0x49 CHx_SCAL_OFFSETM
0x32 0x3A 0x42 0x4A Reserved
System Calibration Offset Coefficient Data [15:8]
System Calibration Offset Coefficient Data [7:0]
-
ꢁ
CHx_SCAL_GAIN: CH0-CH3 System Calibration Gain Registers (Fixed Point 1.23 Format)
ADDR
Name
Description
CH0 CH1 CH2 CH3
0x33 0x3B 0x43 0x4B CHx_SCAL_GAINH
0x34 0x3C 0x44 0x4C CHx_SCAL_GAINL
0x35 0x3D 0x45 0x4D Reserved
System Calibration Gain Coefficient Data [15:8]
System Calibration Gain Coefficient Data [7:0]
-
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56
CHx_SCAL_SCALING: CH0-CH3 System Calibration Scaling Coefficient Registers
ADDR
Name
Description
CH0 CH1 CH2 CH3
0x36 0x3E 0x46 0x4E CHx_SCAL_SCALING
System Calibration Scaling Coefficient Data [5:0]
CHx_SCAL_BITS_SELECTOR: CH0-CH3 System Calibration Bit Selector Registers
ADDR
Name
Description
CH0 CH1 CH2 CH3
0x37 0x3F 0x47 0x4F CHx_SCAL_BITS_SELECTOR
System Calibration Bit Selection Data [2:0]
ꢁ
18.6 SENSOR DIAGNOSTIC REGISTERS
ꢁ
SENDIAG_THLD: Sensor Diagnostic Threshold (Address 0x14)
Address Name
0x14 SENDIAG_THLD
Register Description
Sensor Diagnostic threshold
ꢁ
SENDIAG_FLAGS: Sensor Diagnostic Flags (Address 0x19 )
Bit Bit Symbol
Bit Description
ꢁ
Short Circuit Threshold Flag = 1 when the absolute value of VOUT is within the absolute
threshold voltage set by the SENDIAG_THLD register.
7
6
5
SHORT_THLD_ FLAG
ꢁ
ꢁ
RAILS_FLAG
Rails Flag = 1 when at least one of the inputs is near rail (VA or GND).
ꢁ
ꢁ
Power-on-reset after last read = 1 when there was a power-on-reset event since the last
time the SENDIAG_FLAGS register was read.
POR_AFT_LST_RD
ꢁ
ꢁ
Overflow flags
0x0: Normal operation
[4:3] OFLO_FLAGS
[2:0] SAMPLED_CH
0x1: The modulator was not overranged, but ADC_DOUT got clamped to 0x7f_ffff (positive
fullscale) or 0x80_0000 (negative full scale)
0x2: The modulator was over-ranged (VIN > 1.2*VREF/GAIN)
0x3: The modulator was over-ranged (VIN < -1.2*VREF/GAIN)
ꢁ
Channel Number – the sampled channel for ADC_DOUT and SENDIAG_FLAGS.
ꢁ
ꢁ
57
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18.7 SPI REGISTERS
ꢁ
SPI_HANDSHAKECN: SPI Handshake Control (Address 0x01)
Bit Bit Symbol
Bit Description
[7:4] Reserved
-
ꢁ
SDO/DRDYB Driver – sets who is driving the SDO/DRYB pin
ꢁ
Whenever CSB is
Whenever CSB is
Asserted and the Device CSB is
Asserted and the Device
is Reading ADC_DOUT
is Not Reading
ADC_DOUT
Deasserted
[3:1] SDO_DRDYB_ DRIVER
0x0 (default)
0x3
SDO is driving
SDO is driving
SDO is driving
Forbidden
DRDYB is driving
DRDYB is driving
High-Z
High-Z
DRDYB is driving
High-Z
0x4
Others
ꢁ
Switch-off trigger - refers to the switching of the output drive from the slave to the master.
0 (default): SDO will be high-Z after the last (16th, 24th, 32nd, etc) rising edge of SCLK.
This option allows time for the slave to transfer control back to the master at the end of the
frame.
0
SW_OFF_TRG
ꢁ
1: SDO’s high-Z is postponed to the subsequent falling edge following the last (16th, 24th,
32nd, etc) rising edge of SCLK. This option provides additional hold time for the last bit, DB0,
in non-streaming read transfers.
ꢁ
ꢁ
SPI_STREAMCN: SPI Streaming Control (Address 0x03)
Bit Bit Symbol
Bit Description
ꢁ
Stream type
7
STRM_TYPE
0 (default): Normal Streaming mode
1: Controlled Streaming mode
ꢁ
ꢁ
Stream range – selects Range for Controlled Streaming mode
[6:0] STRM_ RANGE
Default: 0x00
ꢁ
ꢁ
DATA_ONLY_1: Data Only Read Control 1 (Address 0x09)
Bit Bit Symbol
Bit Description
7
Reserved
-
Start address for the Data Only Read Transaction
Default: 0x1A
[6:0] DATA_ONLY_ADR
Please refer to the description of DT_ONLY_SZ in DATA_ONLY_2 register.
www.national.com
58
DATA_ONLY_2: Data Only Read Control 2 (Address 0x0A)
Bit Bit Symbol
[7:3] Reserved
[2:0]
Bit Description
-
Number of bytes to be read out in Data Only mode. A value of 0x0 means read one byte
and 0x7 means read 8 bytes.
DATA_ONLY_SZ
Default: 0x2
SPI_DRDYBCN: SPI Data Ready Bar Control (Address 0x11 )
Bit Bit Symbol
Bit Description
ꢁ
Enable DRDYB on D6
7
SPI_DRDYB_D6
0 (default): D6 is a GPIO
1: D6 = drdyb signal
ꢁ
6
5
4
Reserved
CRC_RST
Reserved
-
CRC Reset
0 (default): Enable CRC reset on DRDYB deassertion
1: Disbale CRC reset on DRDYB deassertion
-
ꢁ
Gain background calibration
0 (default): Correct FGA gain error. This is useful only if the device is operating in Bg-
calMode2 and ScanMode2 or ScanMode3.
3
FGA_BGCAL
1: Correct FGA gain error using the last known coefficients.
ꢁ
[2:0] Reserved
Default - 0x3 (do not change this value)
ꢁ
SPI_CRC_CN: CRC Control (Address 0x13 )
Bit Bit Symbol
Bit Description
[7:5] Reserved
-
ꢁ
Enable CRC
4
3
2
EN_CRC
0 (default): Disable CRC
1: Enable CRC
ꢁ
Reserved
Default - 0x1 (do not change this value)
ꢁ
DRDYB After CRC
DRDYB_AFT_CRC
0 (default): DRDYB is deasserted (active high) after ADC_DOUTL is read.
1: DRDYB is deasserted after SPI_CRC_DAT (which follows ADC_DOUTL), is read.
ꢁ
[1:0] Reserved
-
ꢁ
59
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SPI_CRC_DAT: CRC Data (Address 0x1D )
Bit Bit Symbol
Bit Description
ꢁ
ꢁ
CRC Data
[7:0] CRC_DAT
When written, this register reset CRC:
Any Value: Reset CRC
When read, this register indicates the CRC data.
ꢁ
18.8 GPIO REGISTERS
ꢁ
GPIO_DIRCN: GPIO Direction (Address 0x0E )
Bit Bit Symbol Bit Description
7
x
Reserved
-
ꢁ
GPIO direction control – these bits are used to control the direction of each General Purpose
Input/Outputs (GPIO) pins D0 - D6.
0 (default): Dx is an Input
1: Dx is an Output
GPIO_DIRCNx
where 0 ≤ x ≤ 6.
ꢁ
For example, writing a 1 to bit 6 means D6 is an Output.
Note: If D6 is used for DRDYB, then it cannot be used for GPIO.
ꢁ
GPIO_DAT: GPIO Data (Address 0x0F)
Bit Bit Symbol Bit Description
7 Reserved
-
ꢁ
Write Only - when GPIO_DIRCNx = 0
0: Dx is LO
1: Dx is HI
ꢁ
Read Only - when GPIO_DIRCNx = 1
0: Dx driven LO
1: Dx driven HI
x
Dx
ꢁ
where 0 ≤ x ≤ 6.
ꢁ
For example, writing a 0 to bit 4 means D4 is LO.
It is okay to Read the GPIOs that are configured as outputs and write to GPIOs that are
configured as inputs. Reading the GPIOs that are outputs would return the current value
on those GPIOs, and writing to the GPIOs that are inputs are neglected.
ꢁ
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60
19.0 Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Molded Plastic TSSOP
Order Number LMP90080MH/NOPB, LMP90079MH/NOPB, LMP90078MH/NOPB, LMP90077MH/NOPB
NS Package Number MO-153
61
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Notes
For more National Semiconductor product information and proven design tools, visit the following Web sites at:
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Products
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Design Support
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App Notes
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