LMX1600_技术文档

PRELIMINARY

March 1998

LMX1600/LMX1601/LMX1602

™

PLLatinum Low Cost Dual Frequency Synthesizer

LMX1600

LMX1601

LMX1602

2.0 GHz/500 MHz

1.1 GHz/500 MHz

1.1 GHz/1.1 GHz

General Description

The LMX1600/01/02 is part of a family of monolithic inte-

grated dual frequency synthesizers designed to be used in a

local oscillator subsystem for a radio transceiver. It is fabri-

cated using National’s 0.5u ABiC V silicon BiCMOS process.

Features

n V_CC= 2.7V to 3.6V operation

n Low current consumption:

@

4 mA 3V (typ) for LMX1601

The LMX1600/01/02 contains two dual modulus prescalers,

four programmable counters, two phase detectors and two

selectable gain charge pumps necessary to provide the con-

trol voltage for two external loop filters and VCO loops. Digi-

tal filtered lock detects for both PLLs are included. Data is

@

5 mA 3V (typ) for LMX1600 or LMX1602

n PLL Powerdown mode: I_CC= 1 µA typical

n Dual modulus prescaler:

— 2 GHz/500 MHz option:

— 1.1 GHz/500 MHz option: (Main) 16/17 (Aux) 8/9

— 1.1 GHz/1.1 GHz option:

n Digital Filtered Lock Detects

(Main) 32/33 (Aux) 8/9

™

transferred into the LMX1600/01/02 via a MICROWIRE

serial interface (Data, Clock, LE).

(Main) 16/17 (Aux) 16/17

V_CCsupply voltage can range from 2.7V to 3.6V. The

LMX1600/01/02 features very low current consumption -

typically 4.0 mA at 3V for LMX1601, 5.0 mA at 3V for

LMX1600 or LMX1602. Powerdown for the PLL is hardware

controlled.

Applications

n Cordless / Cellular / PCS phones

n Other digital mobile phones

The LMX1600/01/02 is available in a 16 pin TSSOP surface

mount plastic package.

Functional Block Diagram

DS100129-1

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

™

MICROWIRE and PLLatinum are trademarks of National Semiconductor Corporation.

DS100129

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Connection Diagram

DS100129-2

Order Number LMX1600TM, LMX1601TM, or LMX1602TM

NS Package Number MTC16

Pin Description

No.

1

Pin Name

I/O

Description

FoLD

O

Multiplexed output of the Main/Aux programmable or reference dividers and Main/Aux lock

detect. CMOS output. (See Programming Description 2.5)

2

OSC_IN

I

PLL reference input which drives both the Main and Aux R counter inputs. Has about 1.2V

input threshold and can be driven from an external CMOS or TTL logic gate. Typically

connected to a TCXO output. Can be used with an external resonator (See Programming

Description 2.5.4).

3

4

5

6

OSC_OUT

GND

O

—

I

Oscillator output. Used with an external resonator.

Aux PLL ground.

fin_AUX

Aux prescaler input. Small signal input from the VCO.

V_CC

—

Aux PLL power supply voltage input. Must be equal to V_CC_MAIN. May range from 2.7V to

3.6V. Bypass capacitors should be placed as close as possible to this pin and be

connected directly to the ground plane.

AUX

7

8

CPo_AUX

EN_AUX

O

I

Aux PLL Charge Pump output. Connected to a loop filter for driving the control input of an

external VCO.

Powers down the Aux PLL when LOW (N and R counters, prescaler, and tristates charge

pump output). Bringing EN_AUXHIGH powers up the Aux PLL.

9

EN_MAIN

CPo_MAIN

I

Powers down the Main PLL when LOW (N and R counters, prescaler, and tristates charge

pump output). Bringing EN_MAINHIGH powers up the Main PLL.

10

11

O

—

Main PLL Charge Pump output. Connected to a loop filter for driving the control input of an

external VCO.

V_CC

Main PLL power supply voltage input. Must be equal to V_CC_AUX. May range from 2.7V to

3.6V. Bypass capacitors should be placed as close as possible to this pin and be

connected directly to the ground plane.

MAIN

12

13

14

fin_MAIN

GND

LE

I

—

I

Main prescaler input. Small signal input from the VCO.

Main PLL ground.

Load enable high impedance CMOS input. Data stored in the shift registers is loaded into

one of the 4 internal latches when LE goes HIGH (control bit dependent).

15

16

Data

I

High impedance CMOS input. Binary serial data input. Data entered MSB first. The last two

bits are the control bits.

Clock

High impedance CMOS Clock input. Data for the various counters is clocked in on the

rising edge, into the 18-bit shift register.

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2

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Value

Parameter

Symbol

Min

−0.3

−65

Typical

Max

6.5

Unit

V

V_CC

MAIN

Power Supply Voltage

V_CC

6.5

V

AUX

Voltage on any pin with GND=0V

Storage Temperature Range

Lead Temp. (solder 4 sec)

V_I

T_S

T_L

V_CC+ 0.3

+150

V

˚C

eV

+260

ESD-Human Body Model (Note 2)

2000

Recommended Operating Conditions

Value

Parameter

Symbol

Min

Typical

Max

Unit

V

V_CC

2.7

3.6

MAIN

Power Supply Voltage

Operating Temperature

V_CC

V

AUX

MAIN

T_A

−40

+85

˚C

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for

which the device is intended to be functional, but do not guarantee specific performance limits. Electrical Characteristics document specific minimum and/or maxi-

mum performance values at specified test conditions and are guaranteed. Typical values are for informational purposes only - based on design parameters or device

characterization and are not guaranteed.

Note 2: This device is a high performance RF integrated circuit and is ESD sensitive. Handling and assembly of this device should only be done on ESD-free work-

stations.

Electrical Characteristics

(V_CC

= V_CC

= 3.0V; T_A= 25˚C except as specified)

MAIN

AUX

Symbol

Parameter

Conditions

Min

Typ

Max

Units

GENERAL

I_CC

Power

Supply

Current

2 GHz + 500 MHz

1.1 GHz + 500 MHz

1.1 GHz + 1.1 GHz

2 GHz Only

Crystal Mode (Note 3)

EN_MAIN= LOW, EN_AUX= LOW

fin Main 2 GHz Option

fin Main and Aux 1.1 GHz Option

fin Aux 500 MHz Option

Logic Mode (Note 3)

5.0

4.0

5.0

3.5

2.5

1.5

1

mA

1.1 GHz Only

mA

500 MHz Only

mA

I_CC-PWDN

fin

Power Down Current

µA

fin Operating Frequency

200

100

40

1

2000

1100

500

40

MHz

V_PP

MHz

dBm

OSC_IN

Oscillator Operating Frequency

Crystal Mode (Note 3)

1

20

V_OSC

fφ

Oscillator Input Sensitivity

0.5

V_CC

Maximum Phase Detector Frequency

Main and Aux RF Input Sensitivity

10

Pfin

−15

0

CHARGE PUMP

ICP_o-source

ICP_o-sink

ICP_o-source

ICP_o-sink

ICP_o-Tri

RF Charge Pump Output Current

(See Programming Description 2.4)

VCPo = V_CC/2, High Gain Mode

VCPo = V_CC/2, Low Gain Mode

0.5 ≤ VCP_o≤ V_CC−0.5

−1600

1600

−160

160

µA

nA

Charge Pump TRI-STATE^®Current

1

DIGITAL INTERFACE (DATA, CLK, LE, EN, FoLD)

V_IH

V_IL

High-Level Input Voltage

Low-Level Input Voltage

0.8V_CC

V

0.2V_CC

3

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Electrical Characteristics (Continued)

(V_CC

= V_CC

= 3.0V; T_A= 25˚C except as specified)

MAIN

AUX

Symbol

Parameter

Conditions

Min

Typ

Max

Units

DIGITAL INTERFACE (DATA, CLK, LE, EN, FoLD)

I_IH

I_IL

I_IH

I_IL

I_O

High-Level Input Current

Low-Level Input Current

OSC_INInput Current

V_IH= V_CC= 3.6V, (Note 4)

V_IL= 0V; V_CC= 3.6V, (Note 4)

V_IH= V_CC= 3.6V

−1.0

1.0

100

µA

V_IL= 0V; V_CC= 3.6V

−100

OSC_OUTOutput Current Magnitude

(sink/source) (Note 5)

Logic Mode

V_CC= 3.6V

(Note 3)

|200|

V_OUT= V_CC/2

Crystal Mode

V_CC= 2.7V

(Note 3)

|300|

µA

V_OH

V_OL

High-Level Output Voltage

Low-Level Output Voltage

I_OH= −500 µA

I_OL= 500 µA

V_CC−0.4

V

0.4

MICROWIRE TIMING

t_CS

Data to Clock Set Up Time

See Data Input Timing

50

10

50

ns

t_CH

Data to Clock Hold Time

Clock Pulse Width High

t_CWH

t_CWL

t_ES

Clock Pulse Width Low

Clock to Load Enable Set Up Time

Load Enable Pulse Width

t_EW

CLOSED LOOP SYNTHESIZER PERFORMANCE (NSC evaluation board only)

RFφ_nMain PLL Phase Noise Floor (Note 6)

−160

dBc/Hz

Note 3: Refer to Programming Description 2.5.3.

Note 4: Except fin.

Note 5: The OSCout Output Current Magnitude is lass than or equal to 200µA when the Logic Mode is selected. The OSCout Output Current Magnitude is greater

than or equal to 300µA when the Crystal Mode is selected.

>

OSC

Note 6: Offset frequency = 1 kHz, fin = 900 MHz, fφ = 25 kHz, N = 3600, f

= 10 MHz, V

1.2 V . Refer to the Application Note, AN-1052, for description

PP

OSC

of phase noise floor measurement.

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4

1.0 Functional Description

The basic phase-lock-loop (PLL) configuration consists of a

high-stability crystal reference oscillator, a frequency synthe-

sizer such as the National Semiconductor LMX1600/01/02, a

voltage controlled oscillator (VCO), and a passive loop filter.

The frequency synthesizer includes a phase detector, cur-

rent mode charge pump, as well as programmable reference

[R], and feedback [N] frequency dividers. The VCO fre-

quency is established by dividing the crystal reference signal

down via the R counter to obtain the comparison frequency.

This reference signal, fr, is then presented to the input of a

phase/frequency detector and compared with another signal,

fp, the feedback signal, which was obtained by dividing the

VCO frequency down using the N counter. The phase/

frequency detector’s current source outputs pump charge

into the loop filter, which then converts the charge into the

VCO’s control voltage. The phase/frequency comparator’s

function is to adjust the voltage presented to the VCO until

the feedback signal’s frequency (and phase) match that of

the reference signal. When this “phase-locked” condition ex-

ists, the VCO’s frequency will be N times that of the compari-

son frequency, where N is the divider ratio.

ured as a 4-bit A Counter and a 12-bit B Counter. These in-

puts should be AC coupled through external capacitors. (See

Programming Description 2.3)

1.3.1 Prescalers

The RF input to the prescalers consists of the fin pins which

are one of two complimentary inputs to a differential pair am-

plifier. The complimentary inputs are internally coupled to

ground with a 10 pF capacitor and not brought out to a pin.

The input buffer drives the A counter’s ECL D-type flip flops

in a dual modulus configuration. A 32/33 for 2.0 GHz option,

16/17 for 1.1 GHz option, or 8/9 for 500 MHz option prescale

ratio is provided for the LMX1600/01/02. The prescaler

clocks the subsequent CMOS flip-flop chain comprising the

fully programmable A and B counters.

1.4 PHASE/FREQUENCY DETECTOR

The Main and Aux phase(/frequency) detectors are driven

from their respective N and R counter outputs. The maxi-

mum frequency at the phase detector inputs is 10 MHz (un-

less limited by the minimum continuous divide ratio of the

multi modulus prescalers). The phase detector outputs con-

trol the charge pumps. The polarity of the pump-up or pump-

down control is programmed using Main_PD_Pol or

Aux_PD_Pol depending on whether Main or Aux VCO char-

acteristics are positive or negative. (See Programming De-

scription 2.4) The phase detector also receives a feedback

signal from the charge pump in order to eliminate dead zone.

1.1 REFERENCE OSCILLATOR INPUTS

The reference oscillator frequency for the Main and Aux

PLL’s is provided by either an external reference through the

OSC_INpin with the OSC_OUTpin not connected or connected

to a 30 pF capacitor to ground in Logic Mode, or an external

crystal resonator across the OSC_INand OSC_OUTpins in

Crystal Mode (See Programming Description 2.5.3). The

OSC_INinput can operate to 40 MHz in Logic Mode or to 20

MHz in Crystal Mode with an input sensitivity of 0.5 V_PP. The

OSC_INpin drives the Main and Aux R counters. The inputs

1.5 CHARGE PUMP

The phase detector’s current source outputs pump charge

into an external loop filter, which then converts the charge

into the VCO’s control voltage. The charge pumps steer the

charge pump output, CPo, to V_CC(pump-up) or ground

z

have a 1.2V input threshold and can be driven from an ex-

ternal CMOS or TTL logic gate. The OSC_INpin is typically

connected to the output of a Temperature Compensated

Crystal Oscillator (TCXO).

(pump-down). When locked, CPo is primarily in

a

TRI-STATE mode with small corrections. The charge pump

output current magnitude can be selected as 160 µA or 1600

µA using bits AUX_CP_GAIN and MAIN_CP_GAIN as

shown in Programming Description 2.4.

1.2 REFERENCE DIVIDERS (R COUNTERS)

The Main and Aux R Counters are clocked through the oscil-

lator block in common. The maximum frequency is 40 MHz

in Logic Mode or 20 MHz in crystal Mode. Both R Counters

are 12-bit CMOS counters with a divide range from 2 to

4,095. (See Programming Description 2.2)

1.7 MICROWIRE SERIAL INTERFACE

The programmable functions are accessed through the MI-

CROWIRE serial interface. The interface is made of 3 func-

tions: clock, data, and latch enable (LE). Serial data for the

various counters is clocked in from data on the rising edge of

clock, into the 18-bit shift register. Data is entered MSB first.

The last two bits decode the internal register address. On the

rising edge of LE, data stored in the shift register is loaded

into one of the 4 appropriate latches (selected by address

bits). Data is loaded from the latch to the counter when

counter reaches to zero. A complete programming descrip-

tion is included in the following sections.

1.3 FEEDBACK DIVIDERS (N COUNTERS)

The Main and Aux N Counters are clocked by the small sig-

nal fin Main and fin Aux input pins respectively. These inputs

should be AC coupled through external capacitors. The Main

N counter has an 16-bit equivalent integer divisor configured

as a 5-bit A Counter and an 11-bit B Counter offering a con-

tinuous divide range from 992 to 65,535 (2 GHz option) or a

4-bit A Counter and a 12-bit B Counter offering a continuous

divide range from 240 to 65,535 (1.1 GHz option). The Main

N divider incorporates a 32/33 dual modulus prescaler ca-

pable of operation from 200 MHz to 2.0 GHz or a 16/17 dual

modulus prescaler capable of operation from 100 MHz to

1.1 GHz.

1.8 FoLD MULTIFUNCTION OUTPUT

The LMX1600/01/02 programmable output pin (FoLD) can

deliver the internal counter outputs, digital lock detects, or

CMOS high/low levels.

The Aux N divider operates from 100 MHz to 1.1 GHz with a

16/17 prescaler or from 40 MHz to 500 MHz with a 8/9 pres-

caler. The Aux N counter is a 16-bit integer divider fully pro-

grammable from 240 to 65,535 over the frequency range of

100 MHz to 1.1 GHz or from 56 to 32,767 over the frequency

range of 40 MHz to 550 MHz. The Aux N counter is config-

1.8.1 Lock Detect

A digital filtered lock detect function is included with each

phase detector through an internal digital filter to produce a

logic level output available on the Fo/LD output pin, if se-

lected. The lock detect output is high when the error between

5

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1.9 POWER CONTROL

1.0 Functional Description (Continued)

Each PLL is individually power controlled by the device EN

pin. The EN_MAINcontrols the Main PLL, and the EN_AUXcon-

trols the Aux PLL. Activation of EN = LOW (power down)

condition results in the disabling of the respective N and R

counters and de-biasing of their respective fin inputs (to a

high impedance state). The reference oscillator input block

powers down and the OSC_INpin reverts to a high impedance

state only when both EN pins are LOW. Power down forces

the respective charge pump and phase comparator logic to a

TRI-STATE condition as well as disabling the bandgap refer-

ence block. Power up occurs immediately when the EN pin is

brought high. Power up sequence: Bandgap and Oscillator

blocks come up first, with the remaining PLL functions be-

coming active approx. 1 µs later. All programming informa-

tion is retained internally in the chip when in power down

mode. The MICROWIRE control register remains active and

capable of loading and latching in data during power down

mode.

the phase detector inputs is less than 15 ns for 4 consecutive

comparison cycles. The lock detect output is low when the

error between the phase detector outputs is more than 30 ns

for one comparison cycle. The lock detect output is always

low when the PLL is in power down mode. For further de-

scription see Programming Description 2.5.

2.0 Programming Description

2.1 MICROWIRE INTERFACE

The descriptions below detail the 18-bit data register loaded through the MICROWIRE Interface. The 18-bit shift register is used

to program the 12-bit Main and Aux R counter registers and the 16-bit Main and Aux N counter registers. The shift register con-

sists of a 16-bit DATA field and a 2-bit control (CTL [1:0]) field as shown below. The control bits decode the internal register ad-

dress. On the rising edge of LE, data stored in the shift register is loaded into one of the 4 appropriate latches (selected by ad-

dress bits). Data is shifted in MSB first.

MSB

LSB

CTL [1:0]

DATA [15:0]

18

2

1

0

2.1.1 Register Location Truth Table

When LE transitions high, data is transferred from the 18-bit shift register into one of the 4 appropriate internal latches depending

upon the state of the control (CTL) bits. The control bits decode the internal register address

CTL [1:0]

DATA Location

AUX_R Register

0

1

0

1

0

1

AUX_N Register

MAIN_R Register

MAIN_N Register

2.1.2 Register Content Truth Table

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

AUX_R

AUX_N

MAIN_R

MAIN_N

FoLD

AUX_R_CNTR

AUX_B_CNTR

CP_WORD

AUX_A_CNTR

MAIN_R_CNTR

MAIN_B_CNTR and MAIN_A_CNTR

2.2 PROGRAMMABLE REFERENCE DIVIDERS

2.2.1 AUX_R Register

If the Control Bits (CTL [1:0]) are 0 0 when LE transitions high, data is transferred from the 18-bit shift register into a latch which

sets the Aux PLL 12-bit R counter divide ratio. The divide ratio is programmed using the bits AUX_R_CNTR as shown in table

2.2.3. The divider ratio must be ≥ 2. The FoLD word bits controls the multifunction FoLD output as described in section in 2.5.

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17 16 15 14 13 12 11 10

FoLD[3:0]

9

8

7

6

5

4

3

2

1

0

AUX_R

AUX_R_CNTR[11:0]

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2.0 Programming Description (Continued)

2.2.2 MAIN_R REGISTER

If the Control Bits (CTL [1:0]) are 1 0 when LE transitions high, data is transferred from the 18-bit shift register into a latch which

sets the Main PLL 12-bit R counter divide ratio and various control functions. The divide ratio is programmed using the bits

MAIN_R_CNTR as shown in table 2.2.3. The divider ratio must be ≥ 2. The charge pump control word (CP_WORD[3:0] ) sets the

charge pump gain and the phase detector polarity as detailed in 2.4.

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17 16 15 14 13 12 11 10

CP_WORD[3:0]

9

8

7

6

5

4

3

2

1

0

MAIN_R

MAIN_R_CNTR[11:0]

2.2.3 12-Bit Programmable Main and Auxiliary Reference Divider Ratio

(MAIN/AUX R Counter)

MAIN_R_CNTR/AUX_R_CNTR

Divide Ratio 11 10

9

0

•

8

0

•

7

0

•

6

0

•

5

0

•

4

0

•

3

0

•

2

0

•

1

•

0

1

•

2

0

•

0

•

3

•

4,095

1

Note 7: Legal divide ratio: 2 to 4,095.

2.3 PROGRAMMABLE FEEDBACK (N) DIVIDERS

2.3.1 AUX_N Register

If the Control Bits ( CTL[1:0]) are 0 1 when LE transitions high, data is transferred from the 18-bit shift register into the AUX_N

register latch which sets the Aux PLL 16-bit programmable N counter value. The AUX_N counter is a 16-bit counter which is fully

programmable from 240 to 65,535 for 1.1 GHz option or from 56 to 32,767 for 500 MHz option. The AUX_N register consists of

the 4-bit swallow counter (AUX_A_CNTR), the 12-bit programmable counter (AUX_B_CNTR). Serial data format is shown below.

The divide ratio (AUX_N_CNTR [13:0]) must be ≥ 240 (1.1 GHz option) or ≥ 56 (500 MHz option) for a continuous divide range.

The Aux PLL N divide ratio is programmed using the bits AUX_A_CNTR, AUX_B_CNTR as shown in tables 2.3.2.

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17 16 15 14 13 12 11 10

AUX_B_CNTR[11:0]

9

8

7

6

5

4

3

2

1

0

1

AUX_N

AUX_A_CNTR[3:0]

2.3.2 4-BIT Swallow Counter Divide Ratio (Aux A COUNTER)

1.1 GHz option

500 MHz option

Swallow

AUX_A_CNTR

Count

AUX_A_CNTR

Count

(A)

0

3

0

•

2

0

•

1

0

•

0

1

•

(A)

0

3

X

•

2

0

•

1

0

•

0

1

•

1

•

15

1

7

X

1

Note 8: Swallow Counter Value: 0 to 15

Note 9: Swallow Counter Value: 0 to 7

X = Don’t Care condition

2.3.3 12-BIT Programmable Counter Divide Ratio (Aux B COUNTER)

AUX_B_CNTR

Divide Ratio 11 10

9

0

•

8

0

•

7

0

•

6

0

•

5

0

•

4

0

•

3

0

•

2

0

1

•

1

0

•

0

1

0

•

3

0

•

0

•

4

•

4,095

1

Note 10: Divide ratio: 3 to 4,095 (Divide ratios less than 3 are prohibited)

AUX_B_CNTR ≥ AUX_A_CNTR.

See section 2.3.7 for calculation of VCO output frequency.

7

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2.0 Programming Description (Continued)

2.3.4 MAIN_N Register

If the Control Bits (CTL[1:0]) are 1 1 when LE transitions high, data is transferred from the 18-bit shift register into the MAIN_N

register latch which sets 16-bit programmable N divider value. The Main N divider is a 16-bit counter which is fully programmable

from 992 to 65,535 for 2 GHz option and from 240 to 65,535 for 1.1 GHz option. The MAIN_N register consists of the 5-bit (2 GHz

option) or 4-bit (1.1 GHz option) swallow counter (MAIN_A_CNTR) and the 11-bit (2 GHz option) or 12-bit (1.1 GHz option) pro-

grammable counter (MAIN_B_CNTR). Serial data format for the MAIN_N register latch shown below. The divide ratio must be ≥

992 (2 GHz option) or 240 (1.1 GHz option) for a continuous divide range. The divide ratio is programmed using the bits

MAIN _A_CNTR and MAIN_B_CNTR as shown in tables 2.3.5 and 2.3.6 The pulse swallow function which determines the divide

ratio is described in Section 2.3.7.

2 GHz option

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17 16 15 14 13 12 11 10

AUX_B_CNTR[10:0]

9

8

7

6

5

4

3

2

1

0

1

MAIN_N

AUX_A_CNTR[4:0]

1.1 GHz option

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17 16 15 14 13 12 11 10

AUX_B_CNTR[11:0]

9

8

7

6

5

4

3

2

1

0

1

MAIN_N

AUX_A_CNTR[3:0]

2.3.5 Swallow Counter Divide Ratio (Main A COUNTER)

2 GHz option (5 bit)

1.1 GHz option (4 bit)

Swallow

MAIN_A_CNTR

Count

MAIN_A_CNTR

Count

(A)

0

4

0

•

3

0

•

2

0

•

1

0

•

0

1

•

(A)

0

3

0

•

2

0

•

1

0

•

0

1

•

1

•

31

1

15

1

Note 11: Swallow Counter Value: 0 to 31

Note 12: Swallow Counter Value: 0 to 15

2.3.6 Programmable Counter Divide Ratio (Main B COUNTER)

2 GHz option (11 bit)

MAIN_B_CNTR

Divide Ratio 10

9

0

•

8

0

•

7

0

•

6

0

•

5

0

•

4

0

•

3

0

•

2

0

1

•

1

0

•

0

1

0

•

3

0

•

4

•

2,047

1

Note 13: Divide ratio: 3 to 2,047 (Divide ratios less than 3 are prohibited)

MAIN_B_CNTR ≥ MAIN_A_CNTR.

See section 2.3.7 for calculation of VCO output frequency.

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2.0 Programming Description (Continued)

1.1 GHz option (12 bit)

MAIN_B_CNTR

Divide Ratio 11 10

9

0

•

8

0

•

7

0

•

6

0

•

5

0

•

4

0

•

3

0

•

2

0

1

•

1

0

•

0

1

0

•

3

0

•

0

•

4

•

4,095

1

Note 14: Divide ratio: 3 to 4,095 (Divide ratios less than 3 are prohibited)

MAIN_B_CNTR ≥ MAIN_A_CNTR.

See section 2.3.7 for calculation of VCO output frequency.

2.3.7 Pulse Swallow Function

The N divider counts such that it divides the VCO RF frequency by (P+1) for A times, and then divides by P for (B – A ) times.

The B value (B_CNTR) must be ≥ 3. The continuous divider range for the Main PLL N divider is from 992 to 65,535 for 2 GHz

option, from 240 to 65,535 for 1.1 GHz option, and from 56 to 32,767 for 500 MHz option. Divider ratios less than the minimum

value are achievable as long as the binary counter value is greater than or equal to the swallow counter value (B_CNTR ≥

A_CNTR).

f_VCO= N x ( f_OSC/ R )

N = (P x B) + A

f_VCO

f_OSC

R:

:

Output frequency of external voltage controlled oscillator (VCO)

Output frequency of the external reference frequency oscillator (input to OSC_IN).

Preset divide ratio of binary programmable reference counter (R_CNTR)

Preset divide ratio of main programmable integer N counter (N_CNTR)

Preset divide ratio of binary programmable B counter (B_CNTR)

Preset value of binary 4-bit swallow A counter (A _CNTR)

:

N:

B:

A:

P:

Preset modulus of dual modulus prescaler (P = 32 for 2 GHz option, P=16 for 1.1 GHz option, and P=8 for 500 MHz

option)

2.4 CHARGE PUMP CONTROL WORD (CP_WORD)

MSB

LSB

MAIN_PD_POL

AUX_CP_GAIN

MAIN_CP_GAIN

AUX_PD_POL

BIT

LOCATION

MAIN_R[17]

MAIN_R[16]

MAIN_R[15]

MAIN_R[14]

FUNCTION

0

1

AUX_CP_GAIN

MAIN_CP_GAIN

AUX_PD_POL

MAIN_PD_POL

Aux Charge Pump Current Gain

Main Charge Pump Current Gain

Aux Phase Detector Polarity

Main Phase Detector Polarity

LOW

HIGH

LOW

HIGH

Negative

Positive

AUX_CP_GAIN (MAIN_R[17]) and MAIN_CP_GAIN (MAIN_R[16]) are used to select charge pump current magnitude either low

gain mode (160 µA typ) or high gain mode (1600 µA typ)

AUX_ PD_POL (MAIN_R[15]) and MAIN_ PD_POL (MAIN_R[14]) are respectively set to one when Aux or Main VCO character-

istics are positive as in (1) below. When VCO frequency decreases with increasing control voltage (2) PD_POL should set to zero.

9

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2.0 Programming Description (Continued)

2.4.1 VCO Characteristics

DS100129-14

2.4.2 Phase Comparator and Internal Charge Pump Characteristics

(AUX_PD_POL/MAIN_PD_POL = 1)

DS100129-15

Note 15: fr is phase detector input from reference counter. fp is phase detector input from programmable N counter.

Phase difference detection range: - 2π to + 2pπ.

The minimum width pump up and pump down current pulses occur at the CPo pin when the loop is locked.

2.5 F_OUT/LOCK DETECT PROGRAMMING TRUTH TABLE (FoLD)

FoLD

Fo/LD OUTPUT STATE

3

2

1

0

AUX_R[17]

AUX_R[16] AUX_R[15]

AUX_R[14]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

“0”

“1”

X

x

Main Lock Detect

Aux Lock Detect

X

Main “and” Aux Lock Detect

Main Reference Counter Output

Aux Reference Counter Output

Main Programmable Counter Output

Aux Programmable Counter Output

Note 16: See section 2.5.3 for AUX_R[14] description.

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10

2.0 Programming Description (Continued)

2.5.1 Lock Detect Digital Filter

The Lock Detect Digital Filter compares the difference between the phase of the inputs of the phase detector to a RC generated

delay of approximately 15 ns. To enter the locked state (Lock = HIGH) the phase error must be less than the 15 ns RC delay for

4 consecutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to approximately 30 ns. To exit the locked

state (Lock = LOW), the phase error must become greater than the 30 ns RC delay. When the PLL is in the powerdown mode,

Lock is forced LOW. A flow chart of the digital filter is shown below.

DS100129-16

2.5.2 Typical Lock Detect Timing (AUX_PD_POL/MAIN_PD_POL = 1)

DS100129-17

11

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2.0 Programming Description (Continued)

2.5.3 OSC Mode Programming

The OSC_outpin can be optimized for operating with an external crystal resonator or an external reference frequency source (i.e.

TCXO). If the application uses an external reference frequency source, the current dissipation of the LMX1600/01/02 can be re-

duced with the Logic Mode (0.5 mA typ.). Crystal Mode should be used when an external crystal resonator is used. Logic Mode

is used when an external reference frequency source is used. In Logic Mode, OSC_OUTshould be connected to a 30 pF capacitor

to ground for optimum performance.

When the FoLD output state is selected to CMOS high/low levels, the OSC Mode is forced to Crystal Mode.

FoLD

OSC_OUT

3

2

1

0

AUX_R[17]

AUX_R[16]

AUX_R[15]

AUX_R[14]

0

1

0

1

Crystal Mode

Logic Mode

0

All Other States

Crystal Mode

2.5.4 Typical Crystal Oscillator Circuit

A typical implementation of a 10 MHz crystal oscillator with the OSC_OUTpin in Crystal Mode is shown below.

DS100129-18

2.6 SERIAL DATA INPUT TIMING

DS100129-19

Note 17: Data shifted into register on clock rising edge.

Data is shifted in MSB first.

TEST CONDITIONS: The Serial Data Input Timing is tested using a symmetrical waveform around V_CC/2. The test waveform has

@

an edge rate of 0.6 V/ns with amplitudes of 2.2V V_CC= 2.7V.

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12

2.0 Programming Description (Continued)

2.7 TYPICAL APPLICATION EXAMPLE

DS100129-20

OPERATIONAL NOTES:

*

VCO is assumed AC coupled.

**

R_INincreases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10Ω to

200Ω depending on the VCO power level. The fin RF impedance ranges from 40Ω to 100Ω. The fin IF impedances are

higher.

*** 50Ω termination is often used on test boards to allow use of external reference oscillator. For most typical products, a CMOS

clock is used and no terminating resistor is required. OSC_INmay be AC or DC coupled. AC coupling is recommended be-

cause the input circuit provides its own bias. (See Figure below)

DS100129-21

**** Adding RC filter to the V_CCline is recommended to reduce loop-to-loop noise coupling.

—

Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins

can be reduced by careful board layout.

—

This is a static sensitive device. It should be handled only at static free work stations.

13

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Physical Dimensions inches (millimeters) unless otherwise noted

Dimensions are in millimeters.

LMX1600/01/02 Frequency Synthesizer IC (16-Pin TSSOP Package)

NS Package Number MTC16

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VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-

CONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or sys-

tems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, and whose fail-

ure to perform when properly used in accordance

with instructions for use provided in the labeling, can

be reasonably expected to result in a significant injury

to the user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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Tel: 1-800-272-9959

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.


型号：	LMX1600
厂家：	National Semiconductor
描述：	PLLatinum⑩ Low Cost Dual Frequency Synthesizer 半导体PLLatinum ™低成本双频合成器半导体
文件：	总14页 (文件大小：200K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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