LMX2310U [NSC]
PLLatinum⑩ Ultra Low Power Frequency Synthesizer for RF Personal Communications; PLLatinum⑩超低功耗频率合成射频个人通信
| 型号： | LMX2310U |
| 厂家： | 
National Semiconductor |
| 描述： | PLLatinum⑩ Ultra Low Power Frequency Synthesizer for RF Personal Communications |
| 文件： | 总29页 (文件大小：657K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2003
LMX2310U/LMX2311U/LMX2312U/LMX2313U
™
PLLatinum Ultra Low Power Frequency Synthesizer for
RF Personal Communications
LMX2310U 2.5 GHz
LMX2312U 1.2 GHz
General Description
The LMX2310/1/2/3U are high performance frequency syn-
thesizers. The LMX2310/1/2U use a selectable, dual modu-
lus 32/33 and 16/17 prescaler. The LMX2313U uses a se-
lectable, dual modulus 16/17 and 8/9 prescaler. The device,
when combined with a high quality reference oscillator and a
voltage controlled oscillator, generates very stable, low noise
local oscillator signals for up and down conversion in wire-
less communication devices.
LMX2311U 2.0 GHz
LMX2313U 600 MHz
Features
n RF operation up to 2.5 GHz
n 2.7V to 5.5V operation
n Ultra Low Current Consumption
n Low prescaler values
LMX2310/1/2U 32/33 or 16/17
LMX2313U 16/17 or 8/9
n Excellent Phase Noise
n Internal balanced, low leakage charge pump
n Selectable Charge Pump Current Levels
n Selectable Fastlock mode with Time-Out Counter
n Low Voltage MICROWIRE interface (1.72V to VCC
n Digital and Analog Lock Detect
n Small 20-pad Thin Chip Scale Package
Serial data is transferred into LMX2310/1/2/3U via a three-
wire interface (Data, Enable, Clock) that can be directly
interfaced with low voltage baseband processors. Supply
voltage can range from 2.7V to 5.5V. LMX2310U features
very low current consumption, typically 2.3 mA at 3.0V.
)
The LMX2310/1/2/3U are manufactured using National’s
0.5µ ABiC V silicon BiCMOS process and is available in
20-pin CSP packages.
Applications
n Cellular DCS, PCS, WCDMA telephone systems
n Wireless Local Area Networks (WLAN)
n Global Positioning Systems (GPS)
n Other wireless communications systems
Functional Block Diagram
20043822
™
PLLatinum is a trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation
DS200438
www.national.com
Connection Diagram
20043823
20-Pin Thin Chip Scale Package
NS Package Number SLD20A
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2
Pin Descriptions
Pin Number
Pin Name
NC
I/O
Description
I/O Circuit Configuration
1
2
— No Connect.
CPo
O
Charge Pump output. For connection to a
loop filter for driving the voltage control
input of an external VCO.
3
4
GND
FIN
— Analog ground.
I
RF prescaler input. Small signal input
from the VCO.
5
FINB
I
RF prescaler complementary input. For
single ended operation, this pin should be
AC grounded. The LMX2310/1/2/3U can
be driven differentially when a bypass
capacitor is omitted.
6
OSCIN
I
Oscillator input. An input to a CMOS low
noise inverting buffer. The input can be
driven from an external CMOS or TTL
logic gate.
7
8
NC
— No Connect.
OSCOUT
O
O
I
Oscillator output. The OSCIN low noise
buffer drives an independent oscillator
buffer. Its output is connected to the
OSCOUT pin. It can be used as a buffer to
provide the reference oscillator frequency
to other circuitry or as a crystal oscillator.
9
FoLD
Clock
Multi-function CMOS output pin that
provides multiplexed access to digital lock
detect, open drain analog lock detect, as
well as the outputs of the R and N
counters. The FoLD pin is internally
referenced to VµC
.
10
High impedance CMOS Clock input. Data
for the counters is clocked in on the rising
edge, into the 22-bit shift register. The
Clock is internally referenced to VµC
.
3
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Pin Descriptions (Continued)
Pin Number
Pin Name
NC
I/O
Description
I/O Circuit Configuration
11
12
— No Connect.
Data
I
High impedance CMOS Data input. Serial
Data is entered MSB first. The last two
bits are the address for the target
registers. The Data is internally referenced
to VµC
.
13
LE
I
High impedance CMOS LE input. When
Latch Enable goes HIGH, data stored in
the 22-bit shift register is loaded into one
the 3 control registers, based on the
address field. The Latch Enable is
internally referenced to VµC
.
14
15
GND
CE
— Digital ground.
I
High impedance CMOS Chip Enable
input. Provides logical power-down control
of the device. Pull-up to VµC if unused.
The Chip Enable is internally referenced
to VµC
.
™
16
VµC
— Power supply for MICROWIRE circuitry.
Must be ≤ VCC. Typically connected to
same supply level as microprocessor or
baseband controller to enable
programming at low voltages.
17
18
NC
— No Connect.
VCC
— Power supply voltage input. Input may
range from 2.7V to 5.5V. Bypass
capacitors should be placed as close as
possible to this pin and be connected
directly to the ground plane.
19
20
FL
O
Fastlock mode output. In Fastlock mode
this pin is at logic low. When not in
Fastlock mode, this pin is in TRI-STATE
mode. This pin can also be forced to
TRI-STATE, forced low or forced high by
the programming of the first two-bits of the
Timeout Counter.
VP
— Power supply for charge pump. Must be ≥
VCC
.
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4
Absolute Maximum Ratings (Notes 1,
2)
Lead Temp. (solder 4 sec.), (TL)
+260˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions (Note 1)
Min Max Unit
Power Supply Voltage,
Power Supply Voltage
(VCC, VP, VµC
Voltage on any pin with GND=0V
CPo, FL, FIN, OSCIN, OSCOUT (Vi) −0.3V to VCC + 0.3V
)
−0.3V to +6.5V
(VCC
(VP)
)
2.7 5.5
VCC 5.5
1.72 VCC
V
V
V
(VµC
)
Data, Clock, LE, CE, FoLD (Vi)
Storage Temperature Range, (TS)
−0.3V to VµC + 0.3V
−65˚C to +150˚C
Operating Temperature, (TA)
−40 +85 ˚C
Electrical Characteristics
<
<
VCC = VP = VµC = 3.0V, −40˚C TA +85˚C unless specified otherwise.
Symbol Parameter Conditions (Note 3)
Min
Typ
2.3
2.0
1.4
1.0
Max
Units
ICC
(Note 4)
3.0
3.4
2.7
3.2
2.0
2.4
1.3
1.6
mA
mA
mA
mA
mA
mA
mA
mA
LMX2310U
VCC = 5.5V (Note 4)
(Note 4)
LMX2311U
LMX2312U
LMX2313U
VCC = 5.5V (Note 4)
(Note 4)
Power Supply
Current
lCC
VCC = 5.5V (Note 4)
(Note 4)
VCC = 5.5V (Note 4)
Clock, Data and LE = GND
CE = GND
ICC-PWDN
Power-Down Current
1
10
µA
RF PRESCALER
LMX2310U
LMX2311U
LMX2312U
LMX2313U
0.5
0.5
0.2
45
2.5
2.0
1.2
600
0
GHz
GHz
GHz
MHz
dBm
dBm
Operating
Frequency
FIN
2.7 ≤ VCC ≤3.0V (Note 5)
−15
−10
Input Sensitivity, RF
Prescaler
PFIN
<
3.0V VCC ≤ 5.5V (Note 5)
0
PHASE DETECTOR
Fφ
Phase Detector Frequency
10
50
MHz
REFERENCE OSCILLATOR
Operating Frequency,
FOSC
VOSC
2
MHz
VP−P
Reference Oscillator Input
Input Sensitivity,
(Note 6)
0.5
VCC
100
IN
Reference Oscillator Input
OSCIN Input Current
OSCIN Input Current
OSCOUT Bias Level
IIH
VIH = VCC = 5.5V
VIL = 0, VCC = 5.5V
OSCIN Open
µA
µA
V
IIL
−100
VOSC
1.5
50
OUT
OSCIN = 20 MHz, 0.5 VP-P
OSCIN Duty Cycle = 50%
OSCIN = 20 MHz, 0.5 VP-P
,
DOSC
OSCOUT Duty Cycle
%
OUT
,
VOSC
OSCOUT Level
OSCOUT Load = 10 pF || 10 k
Ohm
2.6
VP-P
OUT
VOH
VOL
IOH
IOL
OSCOUT Output Voltage
OSCOUT Output Voltage
OSCOUT Output Current
OSCOUT Output Current
IOH = -500 µA
IOL = 500 µA
2.6
2.8
0.2
-1.1
1.1
V
V
0.4
VOH = 2.25 V
VOL = 0.75 V
mA
mA
5
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Electrical Characteristics (Continued)
<
<
VCC = VP = VµC = 3.0V, −40˚C TA +85˚C unless specified otherwise.
Symbol
CHARGE PUMP
ICPo-source
ICPo-sink
Parameter
Conditions (Note 3)
Min
Typ
Max
Units
VCPo = Vp/2, ICPo_4X = 0
VCPo = Vp/2, ICPo_4X = 0
VCPo = Vp/2, ICPo_4X = 1
VCPo = Vp/2, ICPo_4X = 1
0.8
−0.8
3.2
1.0
−1.0
4.0
1.2
−1.2
4.8
mA
mA
mA
mA
Charge Pump Output
Current (Note 7)
ICPo-source
ICPo-sink
−3.2
−4.0
−4.8
ICPo-tri
Charge Pump TRI-STATE 0.5V ≤ VCPo ≤ VP − 0.5V
Current
−2.5
2.5
10
15
nA
ICPo-sink vs.
ICPo-source
CP Sink vs. Source
Mismatch
VCPo = Vp/2
TA = 25˚C
3
%
(Note 8)
ICPo vs VCPo CP Current vs. Voltage
0.5V ≤ VCPo ≤ VP − 0.5V
TA = 25˚C (Note 8)
VCPo = Vp/2V (Note 7)
8
8
%
%
ICPo vs TA
CP Current vs.
Temperature
DIGITAL INTERFACE (Data, Clock, LE, CE)
VIH
VIL
IIH
High-level Input Voltage
Low-level Input Voltage
High-level Input Current
Low-level Input Current
VµC = 1.72V to 5.5V
VµC = 1.72V to 5.5V
VIH = VµC= 5.5V
0.8 VµC
V
V
0.2 VµC
1.0
−1.0
−1.0
µA
µA
IIL
VIL = 0V, VµC = 5.5V
1.0
VOH
High-level Output Voltage IOH = 500 µA
(Pin 7–FoLD)
VµC − 0.4
VCC − 0.4
V
High-level Output Voltage IOH = −500 µA
(Pin 15–FL)
V
V
VOL
Low-level Output Voltage
IOL = 1.0 mA (Note 9)
0.1
0.4
MICROWIRE TIMING (Data, Clock, LE, CE)
tCS
Data to Clock Set Up Time (Note 10)
50
20
50
50
ns
ns
ns
ns
tCH
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
(Note 10)
(Note 10)
(Note 10)
tCWH
tCWL
tES
Clock to Load Enable Set (Note 10)
Up Time
50
50
ns
ns
tEW
Load Enable Pulse Width (Note 10)
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6
Electrical Characteristics (Continued)
<
<
VCC = VP = VµC = 3.0V, −40˚C TA +85˚C unless specified otherwise.
Symbol Parameter Conditions (Note 3)
Min
Typ
Max
Units
PHASE NOISE CHARACTERISTICS
Fφ = 200 kHz
FOSC = 10 MHz
VOSC = 1.0 VPP
ICPO = 4 mA
TA = 25˚C
Normalized Single
LN(f)
−159
dBc/Hz
Side-Band Phase Noise
(Note 11)
LMX2310U
FIN = 2450 MHz
Fφ = 200 kHz
FOSC = 10 MHz
VOSC = 1.0 VPP
ICPO = 4 mA
TA = 25˚C
−78
−80
−85
−85
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
(Note 12)
LMX2311U
FIN = 1960 MHz
Fφ = 200 kHz
FOSC = 10 MHz
VOSC = 1.0 VPP
ICPO = 4 mA
TA = 25˚C
(Note 12)
Single Side-Band Phase
L(f)
Noise
LMX2312U
FIN = 902 MHz
Fφ = 200 kHz
FOSC = 10 MHz
VOSC = 1.0 VPP
ICPO = 4 mA
TA = 25˚C
(Note 12)
LMX2313U
FIN = 450 MHz
Fφ = 50 kHz
FOSC = 10 MHz
VOSC = 1.0 VPP
ICPO = 4 mA
TA = 25˚C
(Note 12)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the conditions listed.
<
Note 2: This device is a high performance RF integrated circuit with an ESD rating 2 kV. Handling and assembly of this device should only be done at ESD free
workstations.
Note 3: Typical Conditions are at a T of 25˚C.
A
Note 4: Icc current is measured with Clock, Data and LE pins connected to GND. OSCin and Fin pins are connected to Vcc. PWDN bit is program to 0. Icc current
is the current into Vcc pin.
Note 5: See F Sensitivity Test Setup.
IN
Note 6: See OSC Sensitivity Test Setup.
IN
Note 7: Charge Pump Magnitude is controlled by CPo_4X bit [R18].
Note 8: See Charge Pump Measurement Definition for detail on how these measurements are made.
Note 9: Analog Lock Detect open drain output pin only can be pulled up to V that will not exceed 6.5V.
ext
Note 10: See Serial Input Data Timing.
Note 11: Normalized Single-Side Band Phase Noise is defined as: L (f) = L(f) − 20 log (F / F ), where L(f) is defined as the Single Side-Band Phase Noise.
N
IN
φ
7
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Note 12: Phase Noise is measured using a reference evaluation board with a loop bandwidth of approximately 12 kHz. The phase noise specification is the
composite average of 3 measurements made at frequency offsets of 2.0 kHz, 2.5 kHz and 3.0 kHz.
Typical Performance Characteristics
Icc vs Vcc LMX2310U
Icc vs Vcc LMX2311U
20043838
20043839
Icc vs Vcc LMX2312U
Icc vs Vcc LMX2313U
20043840
20043841
CPOTRI-STATE vs CPO Voltage
20043843
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8
Typical Performance Characteristics (Continued)
LMX231xU Charge Pump Sweeps
20043842
9
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Typical Performance Characteristics (Continued)
Charge Pump Current Variation (See formula under
Charge Pump Current Specification Definitions)
Sink Vs Source Mismatch (See formula under Charge
Pump Current Specification Definitions)
20043866
20043867
LMX2310U Fin Sensitivity vs Frequency at 3.0V
20043846
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10
Typical Performance Characteristics (Continued)
LMX2310U Fin Sensitivity vs Frequency at 5.5V
20043847
LMX2311U Fin Sensitivity vs Frequency at 3.0V
20043848
11
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Typical Performance Characteristics (Continued)
LMX2311U Fin Sensitivity vs Frequency at 5.5V
20043849
LMX2312U Fin Sensitivity vs Frequency at 3.0V
20043850
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12
Typical Performance Characteristics (Continued)
LMX2312U Fin Sensitivity vs Frequency at 5.5V
20043851
LMX2313U Fin Sensitivity vs Frequency at 3.0V
20043852
13
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Typical Performance Characteristics (Continued)
LMX2313U Fin Sensitivity vs Frequency at 5.5V
20043853
LMX231XU OSCin Sensitivity vs Frequency at 3.0V
20043854
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14
Typical Performance Characteristics (Continued)
LMX231XU OSCin Sensitivity vs Frequency at 5.5V
20043855
LMX231xU OSCin Input Impedance vs Frequency
20043858
15
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Typical Performance Characteristics (Continued)
LMX231xUSLD OSCIN IMPEDANCE
VCC = 3.0V (TA = 25˚C)
VCC = 5.5V (TA = 25˚C)
OSCIN BUFFER
OSCI N BUFFER
OSCIN BUFFER
OSCIN BUFFER
NORMAL OPERATION
POWERED-DOWN MODE
NORMAL OPERATION
POWERED-DOWN MODE
Imag-
Real
Imag-
Real
Imag-
Real
Imag-
Real
FOSC
(MHz)
inary |ZOSCIN
ZOSCIN
|
inary |ZOSCIN
ZOSCIN
|
inary |ZOSCIN
|
inary |ZOSCIN
ZOSCIN
|
ZOSCIN
ZOSCIN
(Ω)
(Ω)
ZOSCIN
(Ω)
(Ω)
ZOSCIN
(Ω)
(Ω)
ZOSCIN
(Ω)
(Ω)
(Ω)
(Ω)
(Ω)
(Ω)
2
12900
5200
2400
1350
920
820
630
570
420
440
390
360
340
330
300
290
280
280
−1500
−10900
−7500
−5400
−4300
−3600
−3100
−2600
−2100
−2000
−1900
−1800
−1700
−1500
−1400
−1400
−1300
−1300
13000
12100
7900
5600
4400
3700
3200
2700
2100
2000
1900
1800
1700
1500
1400
1400
1300
1300
9000
2000
1100
410
350
450
220
200
150
140
140
80
−33000
−20000
−13000
−9500
−7000
−5900
−5000
−4300
−3800
−3400
−3000
−2700
−2500
−2400
−2200
−2100
−1900
−1900
34200
20100
13000
9500
7000
5900
5000
4300
3800
3400
3000
2700
2500
2400
2200
2100
1900
1900
10000
5500
2700
1600
1000
800
−7400
−7800
−5700
−4500
−3500
−3900
−2500
−2100
−1900
−1700
−1500
−1400
−1300
−1200
−1100
−1000
−1000
−990
12400
9500
6300
4800
3600
4000
2600
2200
2000
1700
1500
1440
1340
1240
1140
1040
1030
1020
12000 −35000
12200 −21000
37000
24300
13100
9100
7800
6000
5100
4400
3900
3500
3100
2900
2600
2400
2300
2100
2000
2000
4
7
1300
800
300
400
310
280
180
140
120
110
100
120
100
90
−13000
−9100
−7800
−6000
−5100
−4400
−3900
−3500
−3100
−2900
−2600
−2400
−2300
−2100
−2000
−2000
10
13
16
19
22
25
28
31
34
37
40
43
46
49
50
630
540
450
400
350
330
100
100
95
310
300
280
80
270
70
260
80
70
260
100
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16
Typical Performance Characteristics (Continued)
LMX231xU Fin Input Impedance vs Frequency
VCC =3.0V, TA = 25˚C
20043856
LMX231xU Fin Input Impedance vs Frequency
VCC =5.5V, TA = 25˚C
20043857
17
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Typical Performance Characteristics (Continued)
LMX231xUSLD FIN IMPEDANCE
VCC = 3.0V (TA = 25˚C)
VCC = 5.5V (TA = 25˚C)
FIN
FIN
FIN
FIN
POWERED-UP
POWERED-DOWN
Real Imaginary
POWERED-UP
POWERED-DOWN
Real Imaginary
Real Imaginary
Real Imaginary
FIN
(MHz)
|ZFIN
(Ω)
|
|ZFIN
|
|ZFIN
(Ω)
|
|ZFIN|
ZFIN
(Ω)
452
305
225
180
147
120
102
88
ZFIN
(Ω)
ZFIN
(Ω)
440
300
225
179
145
118
100
86
ZFIN
(Ω)
ZFIN
(Ω)
460
313
235
190
155
127
108
94
ZFIN
(Ω)
ZFIN
(Ω)
444
312
237
189
155
126
107
91
ZFIN
(Ω)
(Ω)
(Ω)
100
200
−325
−278
−243
−219
−197
−175
−158
−141
−126
−117
−109
−98
557
413
331
283
246
212
188
166
148
138
126
113
104
96
−337
−276
−242
−217
−195
−173
−156
−139
−123
−113
−106
−95
554
408
330
281
243
209
185
163
144
134
123
110
100
95
−325
−277
−244
−221
−200
−179
−162
−146
−131
−118
−112
−102
−95
563
418
339
291
253
219
195
174
155
141
132
119
110
101
90
−333
−275
−244
−221
−200
−179
−161
−143
−129
−116
−111
−100
−91
555
416
340
291
253
219
193
169
152
138
130
116
106
100
89
300
400
500
600
700
800
900
78
75
83
81
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
73
72
78
75
64
63
69
68
57
55
61
59
52
−90
52
−86
55
55
46
−84
46
−83
49
−88
50
−87
41
−75
85
40
−73
83
44
−79
42
−78
39
−69
79
37
−66
76
41
−73
84
40
−70
81
35
−61
70
34
−59
68
37
−65
75
36
−63
73
34
−55
65
33
−52
62
35
−58
68
34
−56
66
35
−50
61
35
−47
59
35
−52
63
35
−50
61
37
−50
62
37
−48
61
38
−50
63
38
−48
61
34
−52
62
33
−51
61
36
−52
63
34
−51
61
29
−50
58
27
−48
55
32
−51
60
30
−50
58
25
−48
54
23
−45
51
27
−50
57
25
−48
54
20
−44
48
19
−42
46
23
−47
52
21
−44
49
18
−41
45
16
−38
41
20
−43
47
18
−41
45
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18
Charge Pump Measurement Definitions
20043837
I1 = CP sink current at VCP = V − ∆V
o
o
P
I2 = CP sink current at VCP = V /2
o
o
P
I3 = CP sink current at VCP = ∆V
o
o
I4 = CP source current at VCP = V − ∆V
o
o
P
I5 = CP source current at VCP = V /2
o
o
P
I6 = CP source current at VCP = ∆V
o
o
∆V = 0.5V
Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage
20043863
Charge Pump Output Current Sink Vs Charge Pump Output Current Source Mismatch
20043864
Charge Pump Output Current Magnitude Variation Vs Temperature
20043865
19
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Serial Data Input Timing
20043810
Notes:
1. Data shifted into register on Clock rising edge.
2. Data is shifted in MSB first.
FIN Sensitivity Test Setup
20043830
Notes:
1. LMX2310/1/2U Test Conditions: NA_CNTR = 16, NB_CNTR = 312, P = 1, FoLD2 = 1, FoLD1 = 1, FoLD0 = 0, PWDN = 0.
2. LMX2313U Test Conditions: NA_CNTR = 0, NB_CNTR = 625, P = 1, FoLD2 = 1, FoLD1 = 1, FoLD0 = 0, PWDN = 0.
3. Sensitivity limit is reached when the frequency error of the divided RF input is greater than or equal to 1 Hz.
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20
OSCIN Sensitivity Test Setup
20043831
Notes:
1. Test Conditions: R_CNTR = 1000, FoLD2 = 1, FoLD1 = 0, FoLD0 = 1, PWDN = 0.
2. Sensitivity limit is reached when the frequency error of the divided RF input is greater than or equal to 1 Hz.
21
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dividing the VCO frequency down by way of the feedback
counter. The phase/frequency detector measures the phase
error between the fr and fp signals and outputs control sig-
nals that are directly proportional to the phase error. The
charge pump then pumps charge into or out of the loop filter
based on the magnitude and direction of the phase error.
The loop filter converts the charge into a stable control
voltage for the VCO. The phase/frequency detector’s func-
tion is to adjust the voltage presented to the VCO until the
feedback signal’s frequency and phase match that of the
reference signal. When this “phase-locked” condition exists,
the RF VCO frequency will be N times that of the comparison
frequency, where N is the feedback divider ratio.
1.0 Functional Description
The basic phase-lock-loop (PLL) configuration consists of a
high-stability crystal reference oscillator, a frequency synthe-
sizer such as the National Semiconductor LMX2310/1/2/3U,
a voltage controlled oscillator (VCO), and a passive loop
filter. The frequency synthesizer includes a phase detector, a
current mode charge pump, as well as a programmable
reference divider and feedback frequency divider. The VCO
frequency is established by dividing the crystal reference
signal down via the reference divider to obtain a frequency
that sets the comparison frequency. This reference signal, fr,
is then presented to the input of a phase/frequency detector
and compared with another signal, fp, which was obtained by
20043829
1.1 REFERENCE OSCILLATOR
PLL
Input
Frequency
FIN ≤ 1.2 GHz
PLL
Part
Numbers
LMX2310/1/2U
Allowable
Prescaler
Values
16/17 or
32/33
The reference oscillator frequency for the RF PLL is provided
from the external source via the OSCin pin. The low noise
reference buffer circuit supports frequencies from 2 MHz to
50 MHz with a minimum input sensitivity of 0.5 Vpp. The input
can be driven from an external CMOS or TTL logic gate. The
output of this buffer drives the R COUNTER. The output of
the buffer also connects to an oscillator/buffer circuit. Its
output connects to the OSCout pin. The oscillator/buffer cir-
cuit can be used as a buffer to provide the reference fre-
quency to other circuitry. It can also be used as an oscillator
with a crystal/resonator with proper components connected
between OSCin and OSCout pins to generate a reference
frequency.
FIN ≤ 600
LMX2313U
8/9 or
MHz
16/17
The complimentary FIN and FINB input pins drive the input of
a bipolar, differential-pair amplifier. The output of the bipolar,
differential-pair amplifier drives a chain of ECL D-type flip-
flops in a dual modulus configuration. The output of the
prescaler is used to clock the subsequent programmable
feedback divider. Refer to Section 3.3.2 for details on pro-
gramming the Prescaler Value.
1.2 REFERENCE DIVIDER (R COUNTER)
The reference divider is comprised of a 15-bit CMOS binary
counter that supports a continuous integer divide range from
2 to 32,767. The divide ratio should be chosen such that the
maximum phase comparison frequency of 10 MHz is not
exceeded. The reference divider circuit is clocked by the
output of the reference buffer circuit. The output of the
reference divider circuit feeds the reference input of the
phase detector circuit. The frequency of the reference input
to the phase detector (also referred to as the comparison
frequency) is equal to reference oscillator frequency divided
by the reference divider ratio. Refer to Section 3.2.1 for
details on programming the R COUNTER.
1.4 FEEDBACK DIVIDER (N COUNTER)
The N COUNTER is clocked by the output of the prescaler.
The N COUNTER is composed of a 13-bit programmable
integer divider. The 5-bit swallow counter is part of the
prescaler. Selecting a 32/33 prescaler provides a minimum
continuous divider range from 992 to 262,143 while selecting
a 16/17 prescaler value allows for continuous divider values
from 240 to 131,071. In the LMX2313U, selecting a 8/9
prescaler provides a minimum continuous divider range from
56 to 65535.
N = (P x NB_CNTR) + NA_CNTR
FIN = N x Fφ
1.3 PRESCALERS
The LMX2310/1/2U contains a selectable, dual modulus
32/33 and 16/17 prescaler. The LMX2313U contains a se-
lectable, dual modulus 16/17 and 8/9 prescaler.
Definitions
Fφ
FIN
P
Phase Detector Comparison Frequency
RF Input Frequency
PLL
Input
Frequency
PLL
Part
Numbers
LMX2310/1U
Allowable
Prescaler
Values
Prescaler Value
NA_CNTR A Counter Value
NB_CNTR B Counter Value
>
FIN 1.2 GHz
32/33
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22
trol the charge pump. The polarity of the pump-up or pump-
down control signals are programmed using the PD_POL
control bit, depending on whether the RF VCO tuning char-
acteristics are positive or negative (see programming de-
scription in Section 3.2.2). The phase/frequency detector
has a detection range of −2π to +2π.
1.0 Functional Description (Continued)
1.5 PHASE/FREQUENCY DETECTORS
The phase/frequency detector is driven from the N and R
COUNTER outputs. The maximum frequency at the phase
detector inputs is 10 MHz. The phase detector outputs con-
Phase Comparator and Internal Charge Pump Characteristics
20043804
Note 13: The minimum width of the pump up and pump down current pulses occur at the CP pin when the loop is phase-locked.
o
Note 14: The diagram assumes that PD_POL = 1
Note 15: f is the phase comparator input from the R Divider
r
Note 16: f is the phase comparator input from the N Divider
p
Note 17: CP is charge pump output
o
1.6 CHARGE PUMP
ence divider and the feedback divider circuits. The FoLD
output pin is referenced to the VµC supply. The FoLD0,
FoLD1 and FoLD2 bits are used to select the desired output
function. A complete programming description of the FoLD
output pin is in Section 3.2.5.
The charge pumps directs charge into or out of an external
loop filter. The loop filter converts the charge into a stable
control voltage which is applied to the tuning input of a VCO.
The charge pump steers the VCO control voltage towards VP
during pump-up events and towards GND during pump-
down events. When locked, CPo is primarily in a TRI-STATE
condition with small corrections occurring at the phase com-
parison rate. The charge pump output current magnitude can
be selected as 1.0 mA or 4.0 mA by programming the
ICPo_4X bits. When TO_CNTR[11:0] = 1, the charge pump
output current magnitude is set to 4.0 mA. Refer to Section
3.2.3 and 3.4.2 for details on programming the charge pump
output current magnitude.
1.8.1 Analog Lock Detect
When programmed for analog lock detect, the analog lock
detect status is available on the FoLD output pin. When the
charge pump is inactive, the lock detect output goes to a
high impedance in the open drain configuration and to a VµC
source in a push-pull configuration. It goes low when the
charge pump is active during a comparison cycle. The ana-
log lock detect status can be programmed in either an open
drain or push-pull configuration. The push-pull output is ref-
1.7 MICROWIRE SERIAL INTERFACE
erenced to VµC.
The programmable register set is accessed through the
MICROWIRE serial interface. The interface is comprised of
three signal pins: CLOCK, DATA and LE (Latch Enable). The
MICROWIRE circuitry is referenced to VµC, which allows the
circuitry to operate down to a 1.72V source. Serial data is
clocked into a 22-bit shift register from DATA on the rising
edge of CLOCK. The serial data is clocked in MSB first. The
last two bits decode the internal register address. On the
rising edge of LE, the data stored in the shift register is
loaded into one of the three latches based on the address
bits. The synthesizer can be programmed even in the power-
down state. A complete programming description is in Sec-
tion 3.0.
1.8.2 Digital Lock Detect
When programmed for digital lock detect, the digital lock
detect status is available on the FoLD pin. The digital lock
detect filter compares the phase difference of the inputs from
the phase detector to a RC generated delay of approxi-
mately 15 ns. To enter the locked state (LD = High), the
phase error must be less than the 15 ns RC delay for 5
consecutive reference cycles. Once in lock, the RC delay is
changed to approximately 30 ns. To exit the locked state, the
phase error must be greater than the 30 ns RC delay. When
a PLL is in power-down mode, the respective lock detect
output is always low. A flow chart of the digital lock detect
filter follows:
1.8 MULTI-FUNCTION OUTPUTS
The LMX2310/1/2/3U FoLD output pin is a multi-function
output that can be configured as an analog lock detect, a
digital lock detect, and a monitor of the output of the refer-
23
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1.0 Functional Description (Continued)
20043805
™
1.9 Fastlock OUTPUT
The PLL can be configured to be in either the Fastlock mode
continuously or in the Fastlock mode that uses a timeout
counter to switch it back to the normal mode. In the Fastlock
mode the charge pump current is set to 4 mA and the FL pin
is set low. If the user sets the PLL to be in the Fastlock mode
continuously he can send the R register with CPo_4X set low
(R[18] = 0) and sets TO_CNTR[11:0] to 1. The user can set
the PLL to normal mode (1 mA mode and set the FL pin to
TRI-STATE mode) by programming TO_CNTR[11:0] to 0. If
the user elects to use the timeout counter, he can program
the timeout counter from 4 to 4095. The timeout counter will
count down the programmed number of phase detector ref-
erence cycles. After the programmed number of phase de-
tector reference cycles is reached, it will automatically set
the charge pump current to the 1 mA mode and set the FL
pin to TRI-STATE mode. A complete programming descrip-
tion is in Section 3.4.2.
The FL pin can be used as the Fastlock output. The FL pin
can also be programmed as constant low, constant high
(referenced to VCC), or constant high impedance, selectable
through the T register. When the device is configured in
Fastlock mode, the charge pump current can be increased
4x while maintaining loop stability by synchronously switch-
ing a parallel loop filter resistor to ground with the FL pin,
resulting in a ∼2x increase in loop bandwidth. The loop
bandwidth, the zero gain crossover point of the open loop
gain, is effectively shifted up in frequency by a factor of the
square root of 4 = 2 during Fastlock mode. For ω' = 2 ω, the
phase margin during Fastlock also will remain constant. The
user calculates the loop filter component values for the
normal steady state considerations. The device configura-
tion ensures that as long as a second resistor, equal to the
primary resistor value, is wired in appropriately, the loop will
lock faster without any additional stability considerations.
www.national.com
24
the load point during power-down. When the device is pro-
grammed to normal operation, the oscillator buffer, RF pres-
caler, phase detector, and charge pump circuits are all pow-
ered on. The feedback divider and the reference divider are
held at the load point. This allows the RF prescaler, feedback
divider, reference oscillator, the reference divider and pres-
caler circuitry to reach proper bias levels. After a 1.5 µs
delay, the feedback and reference divider are enabled and
they resume counting in “close” alignment (The maximum
error is one prescaler cycle). The MICROWIRE control reg-
ister remains active and capable of loading and latching in
data while in the power-down mode.
2.0 Power-Down
The LMX2310/1/2/3U are power controlled through logical
control of the CE pin in conjunction with programming of the
PDWN and CPo_TRI bits. A truth table is provided that
describes how the state of the CE pin, the PDWN bit and
CPo_TRI bit set the operating mode of the device. A com-
plete programming description of Power-Down is provided in
Section 3.3.1.
CE PWDN CPo_TRI
Operating Mode
Power-down (Asynchronous)
Normal Operation
0
1
1
1
X
0
1
1
X
0
0
1
The synchronous power-down function is gated by the
charge pump. When the device is configured for synchro-
nous power-down, the device will enter the power-down
mode upon the completion of the next charge pump pulse
event.
Power-down (Synchronous)
Power-down (Asynchronous)
X = Don’t Care
When the device enters the power-down mode, the oscillator
buffer, RF prescaler, phase detector, and charge pump cir-
cuits are all disabled. The OSCIN, CPo, FIN, FINB, LD pins
are all forced to a high impedance state. The reference
divider and feedback divider circuits are disabled and held at
The asynchronous power-down function is NOT gated by the
completion of a charge pump pulse event. When the device
is configured for asynchronous power-down, the part will go
into power-down mode immediately.
3.0 Programming Description
3.1 MICROWIRE INTERFACE
The MICROWIRE interface is comprised of a 22-bit shift register and three control registers. The shift register consists of a 20-bit
DATA field and a 2-bit address (ADDR) field as shown below. Data is loaded into the shift register on the rising edges of the
CLOCK signal MSB first. When Latch Enable transitions HIGH, data stored in the shift register is loaded into either the R, N or
T register depending on the state of the ADDR bit. The DATA field assignments for the R, N and T registers are shown in Section
3.1.1.
MSB
LSB
DATA
ADDRESS
21
2
0
ADDR
Target Register
0
1
2
R register
N register
T register
3.1.1 Register Map
Register
Most Significant Bit
21 20 19
SHIFT REGISTER BIT LOCATION
Least Significant Bit
18
17
16 15
14
13 12 11 10
9
8
7
6
5
4
3
2
1
0
Address
Field
Data Field
CPo_ CP0_ PD_
R
FoLD1 FoLD0
R_CNTR[14:0]
0
0
TRI
4x
POL
N
T
PWDN
0
P
0
B_CNTR[12:0]
FoLD2
A_CNTR[4:0]
0
1
1
0
0
0
0
0
0
TO_CNTR[11:0]
25
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3.0 Programming Description (Continued)
3.2 R REGISTER
The R register contains the R_CNTR control word and PD_POL, CPo_4X, CP_TRI, FoLD0, FoLD1 control bits. The detailed
descriptions and programming information for each control word is discussed in the following sections.
Register Most Significant Bit
21 20
SHIFT REGISTER BIT LOCATION
Least Significant Bit
19
18
17
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Address
Field
Data Field
R
FoLD1 FoLD0 CPO_ CPO_ PD_
TRI 4X POL
R_CNTR[14:0]
0
0
3.2.1 R_CNTR[14:0]
Reference Divider (R COUNTER)
R[16:2]
The reference divider can be programmed to support divide ratios from 2 to 32,767. Divide ratios of less than 2 are prohibited.
Divider Value
R_CNTR[14:0]
2
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
0
•
0
0
0
•
0
0
•
0
0
•
0
0
•
1
1
•
0
1
•
3
•
0
•
0
•
32,767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3.2.2 PD_POL
Phase Detector Polarity
R[17]
The PD_POL control bit is used to set the polarity of the phase detector based on the VCO tuning characteristic.
Function
Control Bit Register Location
Description
0
1
PD_POL
R[17]
Phase Detector Polarity Negative VCO Tuning Characteristic Positive VCO Tuning Characteristic
VCO Characteristics
20043809
3.2.3 CPo_4X
Charge Pump Output Current
R[18]
The CPo_4X control bit allows the charge pump output current magnitude to be switched from 1 mA to 4 mA. This happens
asynchronously or immediately with the change in CPo_4X bit.
Function
Control Bit
CPo_4X
Register Location
R[18]
Description
Charge Pump Output Current Magnitude
R[19]
0
1
1X Current
4X Current
3.2.4 CPo_TRI
Charge Pump TRI-STATE
The CPo_TRI control bit allows the charge pump to be switched between a normal operating mode and a high impedance output
state. This happens asynchronously or immediately with the change in CPo_TRI bit.
Function
Control Bit Register Location
Description
0
1
CPo_TRI
R[19]
Charge Pump TRI-STATE Charge Pump Operates Normal Charge Pump Output in High
Impedance State
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26
3.0 Programming Description (Continued)
3.2.5 FoLD2,1,0
FoLD Output Truth Table
T[14],R[21],R[20]
The FoLD2, FoLD1 and FoLD0 are used to select which signal is routed to FoLD pin.
T[14]
R[21]
R[20]
FoLD Output State
Disabled (TRI-STATE FoLD)
FoLD2
FoLD1
FoLD0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Lock Detect—Analog (Push/Pull), Reference to Vµc
Lock Detect—Analog (Open Drain)
Reset R and N Dividers and TRI-STATE Charge Pump
Lock Detect—Digital (Push/Pull), Reference to VµC
R COUNTER Output (Push/Pull), Reference to VµC
N Counter Output (Push/Pull), Reference to VµC
Reserved (Do Not Use)
3.3 N REGISTER
The N register contains the PWDN (Power-Down), P (Prescaler), NA_CNTR, and NB_CNTR control words. The detailed
descriptions and programming information for each control word is discussed in the following sections.
Register
Most Significant Bit
SHIFT REGISTER BIT LOCATION
Least Significant Bit
21
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Address
Field
Data Field
N
PWDN
P
B_CNTR[12:0]
A_CNTR[4:0]
0
1
3.3.1 PWDN
Power-Down
N[21]
The PWDN control bit along with CPo_TRI control bit is used to power-down the PLL. The LMX2310/1/2/3U can be synchronous
or asynchronous powered down by first setting the CPo_TRI bit and then setting the PWDN bit. To power up from the synchronous
Power-Down mode, the CPo_TRI bit will have to be reset to 0.
N[21]
R[19]
Operating Mode
PWDN
CPO_TRI
0
1
1
0
0
1
Normal Operation
Power-down (Synchronous)
Power-down (Asynchronous)
3.3.2 P
Prescaler
N[20]
The LMX2310/1/2/3U contains two dual modulus prescalers. The P control bit is used to set the prescaler value.
Prescaler Value
LMX2310/1/2U
16/17
Prescaler Value
LMX2313U
8/9
N[20]
0
1
32/33
16/17
PLL Input Frequency
Allowable Prescaler Values
>
FIN 1.2 GHz
32/33
FIN ≤ 1.2 GHz
FIN ≤ 600 MHz
16/17 or 32/33
8/9 or 16/17
27
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3.0 Programming Description (Continued)
3.3.3 B_CNTR[12:0]
B COUNTER
N[19:7]
The NB_CNTR control word is used to program the B counter. The B counter is a 13-bit binary counter used in the programmable
feedback divider. The B counter can be programmed to values ranging from 3 to 8,191. See Section 1.4 for details on how the
value of the B counter should be selected.
Divider Value
B_CNTR[12:0]
3
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
1
0
•
1
1
•
4
•
8,191
1
1
1
1
1
1
1
1
1
1
1
1
1
NOTE: B counter divide ratio must be ≥ 3.
3.3.4 A_CNTR[4:0]
A Counter
N[6:2]
The NA_CNTR control word is used to program the A counter. The A counter is a 5-bit swallow counter used in the programmable
feedback divider. The A counter can be programmed to values ranging from 0 to 31. See Section 1.4 for details on how the value
of the A counter should be selected.
Divide
A_CNTR[4:0]
Ratio
0
1
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
•
31
1
1
1
1
1
NOTES: A counter divide ratio must be ≤ P and A counter divide ratio must be ≤ B counter divide ratio.
3.4 T REGISTER
The T register contains the TO_CNTR control word and FoLD2 control bit. The detailed descriptions and programming
information for each control word is discussed in the following sections.
Register
Most Significant Bit
SHIFT REGISTER BIT LOCATION
Least Significant Bit
21 20 19 18 17 16 15
14
13 12 11 10
9
8
7
6
5
4
3
2
1
0
Address
Field
Data Field
T
0
0
0
0
0
0
0
FoLD2
TO_CNTR[11:0]
1
0
3.4.1 FoLD2
FoLD Output (P/O Output Truth Table)
T[14]
See Section 3.2.5 for FoLD Output Truth Table details.
3.4.2 TO_CNTR[11:0]
Timeout Counter Table
T[13:2]
When the Fastlock Timeout counter (TO_CNTR) is loaded with 0, Fastlock is off, the FL pin will be in TRI-STATE mode, and the
charge pump current will be the value specified by the Charge Pump Magnitude bit, R[18]. When the Timeout counter is loaded
with 1, the FL pin is 0 (pulled low) and the charge pump current will be at the 4X state. When the Timeout counter is loaded with
2, the FL pin will again be set to 0 (pulled low), but the charge pump current will be controlled by R[18]. When the Timeout counter
is loaded with 3, the FL pin is 1 (pulled high) with the charge pump current will be controlled by R[18]. When loaded with 4 through
4095, Fastlock is active and will time-out after the specified number of phase detector events.
Count
TO_CNTR[11:0]
Notes
FL Pin Forced TRI-STATE
FL Pin Forced Low
FL Pin Forced Low
FL Pin Forced High
Min Count (4)
0
0
0
0
0
•
0
0
0
0
0
•
0
0
0
0
0
•
0
0
0
0
0
•
0
0
0
0
0
•
0
0
0
0
0
•
0
0
0
0
0
•
0
0
0
0
0
•
0
0
0
0
0
•
0
0
0
0
1
•
0
0
1
1
0
•
0
1
0
1
0
•
CP current controlled by R[18]
CP = 4 mA (manual Fastlock mode)
CP current controlled by R[18]
CP current controlled by R[18]
CP Current set to 4 mA, switches to 1 mA
when count reaches 0
•
Max Count (4095)
1
1
1
1
1
1
1
1
1
1
1
1
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28
Physical Dimensions inches (millimeters) unless otherwise noted
20-Pin Thin Chip Scale Package
Order Number LMX2310U, LMX2311U, LMX2312U or LMX2313U
NS Package Number SLD20A
For Tape and Reel (2500 Units Per Reel) Order Numbers: LMX2310USLDX, LMX2311USLDX, LMX2312USLDX,
LMX2313USLDX
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