LMX2314 [NSC]
1.2 GHz Frequency Synthesizer for RF Personal Communications; 1.2 GHz的频率合成器的射频个人通信
| 型号： | LMX2314 |
| 厂家： | 
National Semiconductor |
| 描述： | 1.2 GHz Frequency Synthesizer for RF Personal Communications |
| 文件： | 总20页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1995
LMX2314/LMX2315 PLLatinumTM
1.2 GHz Frequency Synthesizer
for RF Personal Communications
General Description
Features
Y
Y
Y
RF operation up to 1.2 GHz
The LMX2314 and the LMX2315 are high performance fre-
quency synthesizers with integrated prescalers designed for
RF operation up to 1.2 GHz. They are fabricated using Na-
tional’s ABiC IV BiCMOS process.
2.7V to 5.5V operation
Low current consumption:
e
e
3V
I
6 mA (typ) at V
CC
CC
Y
Y
Y
The LMX2314 and the LMX2315 contain dual modulus pre-
scalers which can select either a 64/65 or a 128/129 divide
ratio at input frequencies of up to 1.2 GHz. Using a proprie-
tary digital phase locked loop technique, the LMX2314/15’s
linear phase detector characteristics can generate very sta-
ble, low noise local oscillator signals.
Dual modulus prescaler: 64/65 or 128/129
Internal balanced, low leakage charge pump
Power down feature for sleep mode:
e
Small-outline, plastic, surface mount JEDEC, 0.150
e
3V
I
30 mA (typ) at V
CC
CC
Y
×
wide, (2314) or TSSOP, 0.173 wide, (2315) package
×
Serial data is transferred into the LMX2314 and the
LMX2315 via a three line MICROWIRETM interface (Data,
Enable, Clock). Supply voltage can range from 2.7V to 5.5V.
The LMX2314 and the LMX2315 feature very low current
consumption, typically 6 mA at 3V.
Applications
Y
Cellular telephone systems
(GSM, IS-54, IS-95, RCR-27)
Y
Portable wireless communications
(DECT, ISM902-928 CT-2)
The LMX2314 is available in a JEDEC 16-pin surface mount
plastic package. The LMX2315 is available in a TSSOP
20-pin surface mount plastic package.
Y
Other wireless communication systems
Block Diagram
TL/W/11766–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
MICROWIRETM and PLLatinumTM are trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/W/11766
RRD-B30M115/Printed in U. S. A.
Connection Diagrams
LMX2314
LMX2315
TL/W/11766–2
JEDEC 16-Lead (0.150 Wide) Small
×
Outline Molded Package (M)
TL/W/11766–3
Order Number LMX2314M or LMX2314MX
See NS Package Number M16A
20-Lead (0.173 Wide) Thin Shrink
×
Small Outline Package (TM)
Order Number LMX2315TM or LMX2315TMX
See NS Package Number MTC20
Pin Descriptions
Pin No.
2314
1
Pin No.
2315
1
Pin Name
I/O
Description
2314/2315
OSC
I
Oscillator input. A CMOS inverting gate input intended for connection to a crystal
resonator for operation as an oscillator. The input has a V /2 input threshold and
IN
CC
can be driven from an external CMOS or TTL logic gate. May also be used as a
buffer for an externally provided reference oscillator.
2
3
4
3
4
5
OSC
O
Oscillator output.
OUT
t
V
V
Power supply for charge pump. Must be
V
CC
.
P
Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass capacitors
should be placed as close as possible to this pin and be connected directly to the
ground plane.
CC
5
6
D
O
O
Internal charge pump output. For connection to a loop filter for driving the input of
an external VCO.
o
6
7
7
8
GND
LD
Ground.
Lock detect. Output provided to indicate when the VCO frequency is in ‘‘lock’’.
When the loop is locked, the pin’s output is HIGH with narrow low pulses.
8
9
10
11
f
I
I
Prescaler input. Small signal input from the VCO.
IN
CLOCK
DATA
LE
High impedance CMOS Clock input. Data is clocked in on the rising edge, into the
various counters and registers.
10
11
13
14
I
I
Binary serial data input. Data entered MSB first. LSB is control bit. High impedance
CMOS input.
Load enable input (with internal pull-up resistor). When LE transitions HIGH, data
stored in the shift registers is loaded into the appropriate latch (control bit
dependent). Clock must be low when LE toggles high or low. See Serial Data Input
Timing Diagram.
12
X
15
16
FC
I
Phase control select (with internal pull-up resistor). When FC is LOW, the polarity of
the phase comparator and charge pump combination is reversed.
BISW
O
Analog switch output. When LE is HIGH, the analog switch is ON, routing the
internal charge pump output through BISW (as well as through D ).
o
13
14
17
18
f
O
O
Monitor pin of phase comparator input. CMOS output.
OUT
w
Output for external charge pump. w is an open drain N-channel transistor and
p
p
requires a pull-up resistor.
15
19
PWDN
I
Power Down (with internal pull-up resistor).
e
e
PWDN
PWDN
HIGH for normal operation.
LOW for power saving.
Power down function is gated by the return of the charge pump to a TRI-STATE
condition.
16
X
20
w
O
Output for external charge pump. w is a CMOS logic output.
r
r
2,9,12
NC
No connect.
2
Functional Block Diagram
TL/W/11766–4
Note 1: The power down function is gated by the charge pump to prevent any unwanted frequency jumps. Once the power down pin is brought low the part will go
into power down mode when the charge pump reaches a TRI-STATE condition.
3
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Power Supply Voltage
V
CC
V
P
2.7V to 5.5V
a
to 5.5V
Power Supply Voltage
V
CC
40 C to 85 C
b
b
a
0.3V to 6.5V
a
0.3V to 6.5V
V
V
CC
P
b
a
Operating Temperature (T )
A
§
§
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Operating Ratings indicate conditions for which the
device is intended to be functional, but do not guarantee specific perform-
ance limits. For guaranteed specifications and test conditions, see the Elec-
trical Characteristics. The guaranteed specifications apply only for the test
conditions listed.
Voltage on Any Pin
e
b
a
0.3V to 6.5V
with GND
0V (V )
I
b
a
65 C to 150 C
Storage Temperature Range (T )
S
§
§
§
a
Lead Temperature (T ) (solder, 4 sec.)
L
260 C
k
k
85 C, except as specified
e
e
b
5.0V; 40 C
Electrical Characteristics V
5.0V, V
T
A
§
§
CC
P
Symbol
Parameter
Power Supply Current
Conditions
Min
Typ
6.0
6.5
30
Max
8.0
Units
mA
e
e
e
e
I
I
V
CC
V
CC
V
CC
V
CC
3.0V
5.0V
3.0V
5.0V
CC
8.5
mA
Power Down Current
180
350
mA
CC-PWDN
60
mA
f
f
Maximum Operating Frequency
Maximum Oscillator Frequency
1.2
20
40
10
GHz
MHz
MHz
MHz
IN
OSC
No Load on OSC Out
f
Maximum Phase Detector Frequency
Input Sensitivity
w
e
e
b
b
a
a
Pf
V
V
2.7V to 3.3V
3.3V to 5.5V
15
10
6
6
IN
CC
dBm
CC
V
V
V
Oscillator Sensitivity
OSC
0.5
0.7 V
V
PP
OSC
IN
High-Level Input Voltage
*
*
V
IH
CC
Low-Level Input Voltage
0.3 V
CC
V
IL
e
e
b
b
I
I
I
I
I
I
High-Level Input Current (Clock, Data)
Low-Level Input Current (Clock, Data)
Oscillator Input Current
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
5.5V
1.0
1.0
1.0
mA
mA
mA
mA
mA
mA
IH
CC
e
e
e
e
e
e
0V, V
CC
5.5V
1.0
IL
IH
IL
IH
IL
e
V
CC
5.5V
100
e
b
100
0V, V
5.5V
CC
e
b
1.0
High-Level Input Current (LE, FC)
Low-Level Input Current (LE, FC)
V
CC
5.5V
1.0
1.0
e
b
100
0V, V
5.5V
CC
*Except f and OSC
IN
IN
4
k
k
85 C, except as specified (Continued)
e
e
b
5.0V; 40 C
Electrical Characteristics V
5.0V, V
T
A
§
§
CC
P
Symbol
Parameter
Conditions
Min
Typ
Max
Units
mA
e
b
5.0
5.0
I
I
I
Charge Pump Output Current
V
V
V /2
P
D
-source
-sink
-Tri
D
o
o
o
o
e
V /2
P
mA
D
D
D
o
s
85 C
s
b
b
Charge Pump TRI-STATE Current
É
0.5V
e
V
V
V
0.5V
0.5V
D
P
o
o
b
2.5
2.5
15
nA
%
T
§
s
25 C
s
I
vs V
Charge Pump Output Current
Magnitude Variation vs Voltage
(Note 1)
0.5V
e
V
D
D
D
P
o
o
T
§
e
V /2
P
25 C
§
I
I
vs
Charge Pump Output Current
Sink vs Source Mismatch
(Note 2)
V
T
D
D
-sink
D
e
o
o
o
10
%
%
-source
k
V /2
k
85 C
b
I
vs T
Charge Pump Output Current
Magnitude Variation vs Temperature
(Note 3)
40 C
§
o
T
§
D
o
e
V
D
10
P
e b
b
b
V
OH
V
OL
V
OH
V
OL
High-Level Output Voltage
Low-Level Output Voltage
I
1.0 mA**
200 mA
V
V
0.8
0.8
V
V
OH
CC
e
I
I
I
1.0 mA**
0.4
0.4
OL
OH
OL
e b
High-Level Output Voltage (OSC
)
V
OUT
CC
e
Low-Level Output Voltage (OSC
)
200 mA
V
OUT
e
e
0.4V
I
I
Open Drain Output Current (w )
V
5.0V, V
1.0
mA
mA
X
OL
OH
p
CC
OH
OL
e
Open Drain Output Current (w )
V
5.5V
100
p
R
Analog Switch ON Resistance (2315)
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
100
ON
t
t
t
t
t
t
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
50
10
50
50
50
50
ns
ns
ns
ns
ns
ns
CS
CH
CWH
CWL
ES
Clock Pulse Width Low
Clock to Enable Set Up Time
Enable Pulse Width
EW
**Except OSC
OUT
Notes 1, 2, 3: See related equations in Charge Pump Current Specification Definitions
5
Typical Performance Characteristics
I
vs V
CC
I
TRI-STATE vs D Voltage
D o
o
CC
TL/W/11766–29
TL/W/11766–30
Charge Pump Current vs D Voltage
o
Charge Pump Current vs D Voltage
o
TL/W/11766–31
TL/W/11766–32
Charge Pump Current Variation
Oscillator Input Sensitivity
TL/W/11766–34
TL/W/11766–33
6
Typical Performance Characteristics (Continued)
Input Sensitivity vs Frequency
Input Sensitivity vs Frequency
TL/W/11766–35
TL/W/11766–36
Input Sensitivity at Temperature
e
Input Sensitivity at Temperature
e
3V
Variation, V
CC
5V
Variation, V
CC
TL/W/11766–37
TL/W/11766–38
LMX2314 Input Impedance vs Frequency
e
LMX2315 Input Impedance vs Frequency
e
e
e
2.7V to 5.5V, f 100 MHz to 1,600 MHz
IN
V
2.7V to 5.5V, f
IN
100 MHz to 1,600 MHz
V
CC
CC
TL/W/11766–40
TL/W/11766–39
e
e
e
e
e
e
e
b
b
b
126
b
e
e
e
e
e
e
e
b
b
b
Marker 1
Marker 2
Marker 3
Marker 4
500 MHz, Real
900 MHz, Real
67, Imag.
24, Imag.
e
9, Imag.
317
150
Marker 1
Marker 2
Marker 3
Marker 4
500 MHz, Real
900 MHz, Real
69, Imag.
36, Imag.
330
193
e
19, Imag.
e
35, Imag.
e
1,500 MHz, Real
e
1,500 MHz, Real
e
1 GHz, Real
1 GHz, Real
172
e
e
e
e b
30, Imag. 106
63
7
Charge Pump Current Specification Definitions
TL/W/11766–41
e
e
e
e
e
e
b
e
e
e
e
e
e
b
DV
I1
I2
I3
CP sink current at V
CP sink current at V
CP sink current at V
V
V
DV
I4
I5
I6
CP source current at V
CP source current at V
CP source current at V
V
V
D
D
D
P
P
D
D
D
P
P
o
o
o
o
o
o
/2
/2
DV
DV
e
DV
Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to V
and ground. Typical values are between 0.5V and 1.0V.
CC
e
b
e
À
1. I vs V
D
Charge Pump Output Current magnitude variation vs Voltage
D
o
o
À
a
Ó
b
a
Ó
]
I6 * 100%
[
]
[
]
[
]
[
(/2 * I1
I3 / (/2 * I1
I3
* 100% and (/2 * I4
I6 / (/2 * I4
l
l
vs I
l
l
l
l
l
l
l
l
l
l
l
l
l
l
e
e
2. I
D
Charge Pump Output Current Sink vs Source Mismatch
D
o-sink
o-source
b
À
a
Ó
]
I5
[
]
[
I2
I5 / (/2 * I2
* 100%
l
l
3. I vs T
l
l
l
l
l
l
e
A
e
Charge Pump Output Current magnitude variation vs Temperature
D
o
@
I2 temp
@
@
@
I5 temp
@
@
b
b
[
]
[
]
§
l l
I2 25 C / I2 25 C * 100% and
I5 25 C / I5 25 C * 100%
§
§
Phase detector/charge pump gain constant
§
l
l
l
l
l
l
l
l
l
l
e
e
4. Kw
À
a
Ó
I5
(/2 * I2
l
l
l
l
RF Sensitivity Test Block Diagram
TL/W/11766–42
e
e
e
64
Note 1: N
10,000
R
50
P
Note 2: Sensitivity limit is reached when the error of the divided RF output, f
, is greater than or equal to 1 Hz.
OUT
8
Functional Description
The simplified block diagram below shows the 19-bit data register, the 14-bit R Counter and the S Latch, and the 18-bit
N Counter (intermediate latches are not shown). The data stream is clocked (on the rising edge) into the DATA input, MSB first.
If the Control Bit (last bit input) is HIGH, the DATA is transferred into the R Counter (programmable reference divider) and the
S Latch (prescaler select: 64/65 or 128/129). If the Control Bit (LSB) is LOW, the DATA is transferred into the N Counter
(programmable divider).
TL/W/11766–5
PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND PRESCALER SELECT (S LATCH)
If the Control Bit (last bit shifted into the Data Register) is HIGH, data is transferred from the 19-bit shift register into a 14-bit
latch (which sets the 14-bit R Counter) and the 1-bit S Latch (S15, which sets the prescaler: 64/65 or 128/129). Serial data
format is shown below.
TL/W/11766–6
14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO
(R COUNTER)
1-BIT PRESCALER SELECT
(S LATCH)
Divide
Prescaler
S
Select
S
S
S
S
S
S
9
S
8
S
7
S
6
S
5
S
4
S
3
S
2
S
1
Ratio
R
14 13 12 11 10
15
P
3
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
1
#
1
0
#
1
0
#
128/129
64/65
0
1
4
#
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes: Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 16383
S1 to S14: These bits select the divide ratio of the programmable
reference divider.
C: Control bit (set to HIGH level to load R counter and S Latch)
Data is shifted in MSB first.
9
Functional Description (Continued)
PROGRAMMABLE DIVIDER (N COUNTER)
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control
Bit (last bit shifted into the Data Register) is LOW, data is transferred from the 19-bit shift register into a 7-bit latch (which sets
the 7-bit Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter). Serial data format is shown
below.
TL/W/11766–7
Note: S8 to S18: Programmable counter divide ratio control bits (3 to 2047)
7-BIT SWALLOW COUNTER DIVIDE RATIO
(A COUNTER)
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO
(B COUNTER)
Divide
Divide
S
7
S
6
S
5
S
4
S
3
S
2
S
1
S
S
S
S
S
S
S
S
S
S
9
S
8
Ratio
A
Ratio
B
18 17 16 15 14 13 12 11 10
0
1
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
1
#
3
4
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
1
#
1
0
#
1
0
#
#
#
127
1
1
1
1
1
1
1
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio: 0 to 127
Note: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited)
t
t
A
B
A
B
PULSE SWALLOW FUNCTION
e
c
(P B)
a
c
]
A f /R
OSC
[
f
f
VCO
: Output frequency of external voltage controlled oscil-
lator (VCO)
VCO
B:
A:
Preset divide ratio of binary 11-bit programmable
counter (3 to 2047)
Preset divide ratio of binary 7-bit swallow counter
s
s
s
127, A B)
(0
A
f
: Output frequency of the external reference frequency
oscillator
OSC
R:
P:
Preset divide ratio of binary 14-bit programmable ref-
erence counter (3 to 16383)
Preset modulus of dual moduIus prescaler (64 or
128)
10
Functional Description (Continued)
SERIAL DATA INPUT TIMING
TL/W/11766–8
Notes: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V /2. The test waveform has an edge rate of 0.6 V/ns with
CC
@
@
e
e
5.5V.
amplitudes of 2.2V
V
CC
2.7V and 2.6V
V
CC
Phase Characteristics
In normal operation, the FC pin is used to reverse the polari-
ty of the phase detector. Both the internal and any external
charge pump are affected.
VCO Characteristics
Depending upon VCO characteristics, FC pin should be set
accordingly:
When VCO characteristics are like (1), FC should be set
HIGH or OPEN CIRCUIT;
When VCO characteristics are like (2), FC should be set
LOW.
When FC is set HIGH or OPEN CIRCUIT, the monitor pin of
the phase comparator input, f , is set to the reference
out
TL/W/11766–9
divider output, f . When FC is set LOW, f
out
is set to the
r
programmable divider output, f .
p
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
TL/W/11766–10
b
a
Notes: Phase difference detection range: 2q to 2q
The minimum width pump up and pump down current pulses occur at the D pin when the loop is locked.
o
e
FC
HIGH
11
Analog Switch (2315 only)
The analog switch is useful for radio systems that utilize a frequency scanning mode and a narrow band mode. The purpose of
the analog switch is to decrease the loop filter time constant, allowing the VCO to adjust to its new frequency in a shorter
amount of time. This is achieved by adding another filter stage in parallel. The output of the charge pump is normally through the
D
o
pin, but when LE is set HIGH, the charge pump output also becomes available at BISW. A typical circuit is shown below. The
second filter stage (LPF-2) is effective only when the switch is closed (in the scanning mode).
TL/W/11766–11
Typical Crystal Oscillator Circuit
A typical circuit which can be used to implement a crystal
oscillator is shown below.
Typical Lock Detect Circuit
A lock detect circuit is needed in order to provide a steady
LOW signal when the PLL is in the locked state. A typical
circuit is shown below.
TL/W/11766–12
TL/W/11766–13
12
Typical Application Example
Operational Notes:
TL/W/11766–14
*
VCO is assumed AC coupled.
**
R increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10X to 200X depending on the VCO power
IN
level. f RF impedance ranges from 40X to 100X.
IN
*** 50X termination is often used on test boards to allow use of external reference oscillator. For most typical products a CMOS clock is used and no terminating
resistor is required. OSC may be AC or DC coupled. AC coupling is recommended because the input circuit provides its own bias. (See Figure below)
IN
TL/W/11766–15
Proper use of grounds and bypass capacitors is essential to achieve a high level of performance.
Crosstalk between pins can be reduced by careful board layout.
This is a static sensitive device. It should be handled only at static free work stations.
13
Application Information
LOOP FILTER DESIGN
A block diagram of the basic phase locked loop is shown.
TL/W/11766–16
FIGURE 1. Basic Charge Pump Phase Locked Loop
An example of a passive loop filter configuration, including
the transfer function of the loop filter, is shown in Figure 2.
TL/W/11766–17
a
s (C2 R2)
#
(C1 C2 R2)
1
e
Z(s)
2
a
a
sC2
s
sC1
#
#
FIGURE 2. 2nd Order Passive Filter
TL/W/11766–19
Define the time constants which determine the pole and
zero frequencies of the filter transfer function by letting
FIGURE 3. Open Loop Transfer Function
Thus we can calculate the 3rd order PLL Open Loop Gain in
terms of frequency
e
T2
R2 C2
#
(1a)
and
b
a
j0 T2) T1
Kw
K
(1
#
#
VCO
e
0
#
G(s) H(s)
#
#
e
l
s
j
C1 C2
#
2
a
0 C1 N(1
j0 T1)
#
T2 (2)
#
e
T1
R2
#
a
C1
C2
(1b)
From equation 2 we can see that the phase term will be
dependent on the single pole and zero such that
The PLL linear model control circuit is shown along with the
open loop transfer function in Figure 3. Using the phase
detector and VCO gain constants Kw and K
loop filter transfer function Z(s) , the open loop Bode plot
can be calculated. The loop bandwidth is shown on the
Bode plot (0p) as the point of unity gain. The phase margin
is shown to be the difference between the phase at the unity
b
b
1
1
e
b
a
e
w(0)
tan
(0 T2) tan
#
(0 T1)
180 (3)
§
#
[
]
and the
VCO
By setting
[
]
dw
T2
b
2
T1
e
0
2
a
a
(0 T1)
d0
1
(0 T2)
1
(4)
#
#
we find the frequency point corresponding to the phase in-
flection point in terms of the filter time constants T1 and T2.
This relationship is given in equation 5.
b
gain point and 180 .
§
e
0
1/ T2 T1
(5)
#
For the loop to be stable the unity gain point must occur
0
p
b
before the phase reaches
180 degrees. We therefore
want the phase margin to be at a maximum when the magni-
tude of the open loop gain equals 1. Equation 2 then gives
TL/W/11766–18
a
a
Kw
K
T1 (1
#
T2 (1
j0 T2)
#
#
VCO
N
p
e
C1
e
/Ns
VCO
e
H(s) G(s)
Open Loop Gain
e
i /i
i
e
2
0
j0 T1)
#
#
#
Ó
Ó
(6)
p
p
Kw Z(s) K
e
e
i
a
[
G(s)/ 1 H(s) G(s)
]
Closed Loop Gain
i /i
o
14
Application Information (Continued)
Therefore, if we specify the loop bandwidth, 0 , and the
In choosing the loop filter components a trade off must be
made between lock time, noise, stability, and reference
spurs. The greater the loop bandwidth the faster the lock
time will be, but a large loop bandwidth could result in higher
reference spurs. Wider loop bandwidths generally improve
close in phase noise but may increase integrated phase
noise depending on the reference input, VCO and division
ratios used. The reference spurs can be reduced by reduc-
ing the loop bandwidth or by adding more low pass filter
stages but the lock time will increase and stability will de-
crease as a result.
p
phase margin, w , Equations 1 through 6 allow us to calcu-
p
late the two time constants, T1 and T2, as shown in equa-
tions 7 and 8. A common rule of thumb is to begin your
design with a 45 phase margin.
§
b
secw
tanw
p
p
e
T1
0
(7)
(8)
p
1
e
T2
2
0
T1
#
p
From the time constants T1, and T2, and the loop band-
width, 0 , the values for C1, R2, and C2 are obtained in
THIRD ORDER FILTER
p
equations 9 to 11.
A low pass filter section may be needed for some applica-
tions that require additional rejection of the reference side-
bands, or spurs. This configuration is given in Figure 4. In
order to compensate for the added low pass section, the
component values are recalculated using the new open
loop unity gain frequency. The degradation of phase margin
caused by the added low pass is then mitigated by slightly
increasing C1 and C2 while slightly decreasing R2.
2
a
a
T1 Kw
K
1
1
(0 T2)
#
#
VCO
N
p
e
C1
#
2
2
T2
0
(0 T1)
(9)
(10)
(11)
#
#
0
T2
T1
p
p
e
b
1
C2
C1
R2
#
# J
T2
e
C2
K
(MHz/V)
Voltage Controlled Oscillator (VCO)
Tuning Voltage constant. The fre-
quency vs voltage tuning ratio.
The added attenuation from the low pass filter is:
2
VCO
e
a
]
1
[
ATTEN
20 log (2qf
R3 C3)
(12)
(13)
#
#
Defining the additional time constant as
ref
Kw (mA)
Phase detector/charge pump gain
constant. The ratio of the current out-
put to the input phase differential.
e
T3
R3 C3
#
Then in terms of the attenuation of the reference spurs add-
ed by the low pass pole we have
N
Main divider ratio. Equal to RF /f
opt ref
ATTEN/20
b
2
10
1
RF (MHz)
opt
Radio Frequency output of the VCO at
which the loop filter is optimized.
e
T3
(14)
0
(2q
f )
ref
#
We then use the calculated value for loop bandwidth 0 in
c
equation 11, to determine the loop filter component values
f
ref
(kHz)
Frequency of the phase detector in-
puts. Usually equivalent to the RF
channel spacing.
in equations 15–17. 0 is slightly less than 0 , therefore
c
the frequency jump lock time will increase.
p
1
e
e
e
T2
2
a
0
(T1
T3)
(15)
(16)
(17)
#
c
2
a
a
a
tanw (T1
T3)
(T1
T3)
T1 T3
#
T3)
#
T3)
a
b
1
0
1
#
c
2
2
a
a
a
[
]
[
]
(T1
T1 T3
#
tanw (T1
#
Ð0
(
2
#
c
2
T2 )
(/2
a
T1 Kw
K
VCO
(1
2
0
#
C1
#
#
2
2
2
2
T3 )
a
a
0
T2
0
N
(1
0
T1 ) (1
#
#
#
c
Ð
(
c
c
15
Application Information (Continued)
Consider the following application example:
Ý
Example
1
e
K
20 MHz/V
5 mA (Note 1)
VCO
e
Kw
RF
e
900 MHz
200 kHz
opt
e
F
ref
e
e
4500
N
0
w
RF /f
opt ref
e
e
2q * 20 kHz
45
1.256e5
p
e
§
p
e
T1
T3
ATTEN
20 dB
b
secw
tanw
p
p
e
e
b
3.29e 6
0
p
(20/20)
b
10
1
e
e
e
b
6
2.387e
2
0
(2q 200e3)
#
b
a
b
2.387e 6)
(3.29e
6
0
c
2
b
a
b
2.387e 6)
a
b
b
]
2.387e 6
[
(3.29e
6
3.29e
6
#
2
b
a
b
a
b
b
2.387e 6
(3.29e
6
2.387e 6)
3.29e
6
#
a
b
1
1
#
2
a
2.387e 6)
b
b
]
[
(3.29e
6
Ð0
1.085 nF
(
e
e
7.045e4
1
e
b
5
T2
C1
3.549e
2
b
a b
2.387e 6)
(7.045e4) (3.29e
6
#
2
(7.045e4) (3.549e 5)
2
(/2
b
b
(5e 3) 20e6
a
b
[
]
3.29e
6
1
#
#
1
e
e
#
2
2
(7.045e4) (3.29e 6)
2
] [
2
(7.045e4) (2.387e 6)
2
b
a
b
a
b
[
]
3.549e 5 (7.045e4) 4500
1
#
#
#
Ð
(
b
b
3.55e
3.29e
5
6
e
e
b
e
C2
R2
1.085 nF
1
10.6 nF;
#
#
J
b
b
3.55e
10.6e
5
9
e
3.35 kX;
b
2.34e
6
e
e
e
106 pF.
if we choose R3
22k; then C3
22e3
Converting to standard component values gives the follow-
ing filter values, which are shown in Figure 4.
e
e
e
e
e
C1
R2
C2
R3
C3
1000 pF
3.3 kX
10 nF
22 kX
100 pF
TL/W/11766–20
Note 1: See related equation for Kw in Charge Pump Current Specification
E
FIGURE 4. 20 kHz Loop Filter
e
Definitions. For this example V
5.0V. The value of Kw can then
be approximated using the curves in the Typical Peformance Char-
acteristics for Charge Pump Current vs. D Voltage. The units for
P
o
e
Kw are in mA. You may also use Kw
(5 mA/2q rad), but in this
case you must convert K to (rad/V) multiplying by 2q.
VCO
16
Application Information (Continued)
MEASUREMENT RESULTS
TL/W/11766–21
TL/W/11766–22
FIGURE 5. PLL Reference Spurs
@
FIGURE 7. PLL Phase Noise 1 kHz Offset
k
b
The reference spurious level is
74 dBc, due to the loop
b
The phase noise level at 1 kHz offset is 79.5 dBc/Hz.
filter attenuation and the low spurious noise level of the
LMX2315.
TL/W/11766–23
FIGURE 6. PLL Phase Noise 10 kHz Offset
b
The phase noise level at 10 kHz offset is 80 dBc/Hz.
TL/W/11766–24
FIGURE 8. Frequency Jump Lock Time
Of concern in any PLL loop filter design is the time it takes
to lock in to a new frequency when switching channels. Fig-
ure 8 shows the switching waveforms for a frequency jump
of 865 MHz to 915 MHz. By narrowing the frequency span
of the HP53310A Modulation Domain Analyzer enables
g
evaluation of the frequency lock time to within 500 Hz.
The lock time is seen to be less than 500 ms for a frequency
jump of 50 MHz.
17
Application Information (Continued)
EXTERNAL CHARGE PUMP
EXAMPLE
e
e
e
50
The LMX PLLatimum series of frequency synthesizers are
equipped with an internal balanced charge pump as well as
outputs for driving an external charge pump. Although the
superior performance of NSC’s on board charge pump elim-
inates the need for an external charge pump in most appli-
cations, certain system requirements are more stringent. In
these cases, using an external charge pump allows the de-
signer to take direct control of such parameters as charge
pump voltage swing, current magnitude, TRI-STATE leak-
age, and temperature compensation.
Typical Device Parameters
Typical System Parameters
b
100, b
n
p
V
V
V
I
5.0V;
P
e
b
4.5V;
0.5V
cntl
wp
e
e
e
0.0V; V
5.0V
wr
e
Design Parameters
I
5.0 mA;
SINK
SOURCE
e
e
V
fn
V
fp
0.8V
e
e
I
I
1 mA
rmax
pmax
e
e
0.3V
V
V
V
R5
R8
OLwp
e
e
100 mV
V
OHwr
One possible architecture for an external charge pump cur-
rent source is shown in Figure 9. The signals w and w in
p
r
the diagram, correspond to the phase detector outputs of
the LMX2314/2315 frequency synthesizers. These logic
signals are converted into current pulses, using the circuitry
shown in Figure 9, to enable either charging or discharging
of the loop filter components to control the output frequency
of the PLL.
Referring to Figure 9, the design goal is to generate a 5 mA
current which is relatively constant to within 5V of the power
supply rail. To accomplish this, it is important to establish as
large of a voltage drop across R5, R8 as possible without
saturating Q2, Q4. A voltage of approximately 300 mV pro-
vides a good compromise. This allows the current source
reference being generated to be relatively repeatable in the
absence of good Q1, Q2/Q3, Q4 matching. (Matched tran-
sistor pairs is recommended.) The wp and wr outputs are
rated for a maximum output load current of 1 mA while 5 mA
current sources are desired. The voltages developed across
R4,
42 mV
9 will consequently be approximately 258 mV, or
k
R8, 5, due to the current density differences
Ó
TL/W/11766–43
À
0.026*1n (5 mA/1 mA) through the Q1, Q2/Q3, Q4 pairs.
FIGURE 9
In order to calculate the value of R7 it is necessary to first
estimate the forward base to emitter voltage drop (Vfn,p) of
the transistors used, the V drop of wp, and the V
Therefore select
drop
OL
OH
b
0.3V 0.026 1n(5.0 mA/1.0 mA)
k
#
of wr’s under 1 mA loads. (wp’s V
0.1V and wr’s
OL
e
e
e
e
e
9
e
51.6X
R
R
R
R
R
4
5
8
6
k
V
0.1V.)
5 mA
OH
Knowing these parameters along with the desired current
allow us to design a simple external charge pump. Separat-
ing the pump up and pump down circuits facilitates the no-
dal analysis and give the following equations.
a
0.3V (50
1)
#
1.0 mA (50
e
332X
a
b
1) 5.0 mA
#
b
0.3V (100 1)
#
1.0 mA (100
e
315.6X
a
0.8V)
a
b
1) 5.0 mA
i
#
source
b
V
V
ln
#
R5
T
i
i
# J
p max
b
b
(5V 0.1V) (0.3V
e
R
4
e
e
3.8 kX
R
7
1.0 mA
source
i
sink
b
V
R8
V
T
ln
#
i
# J
n max
e
e
R
R
9
i
sink
a
V
(b
1)
#
R5
p
5
a
b
i
(b
1)
i
#
p max
V
p
source
a
n
(b
1)
#
(b
R8
e
e
R
R
R
8
a
i
1) i
#
r max
n
sink
b
b
a
a
(V
(V
V
)
(V
Vfp)
Vfn)
p
VOLwp
R5
6
i
p max
b
b
V
)
(V
P
VOHwr
R8
e
7
i
max
18
Physical Dimensions inches (millimeters)
JEDEC 16-Lead (0.150 Wide) Small Outline Molded Package (M)
×
Order Number LMX2314M
For Tape and Reel Order Number LMX2314MX (2500 Units per Reel)
NS Package Number M16A
19
Physical Dimensions millimeters (Continued)
NS Package Number MTC20
20-Lead (0.173 Wide) Thin Shrink Small Outline Package (TM)
×
Order Number LMX2315TM
For Tape and Reel Order Number LMX2315TMX (2500 Units per Reel)
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