LMX3305 [NSC]
Triple Phase Locked Loop for RF Personal Communications; 三重锁相环用于射频个人通信
| 型号： | LMX3305 |
| 厂家： | 
National Semiconductor |
| 描述： | Triple Phase Locked Loop for RF Personal Communications |
| 文件： | 总24页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
August 2000
LMX3305
Triple Phase Locked Loop for RF Personal
Communications
General Description
Features
n Three PLLs integrated on a single chip
n RF PLL fractional-N counter
The LMX3305 contains three Phase Locked Loops (PLL) on
a single chip. It has a RF PLL, an IF Rx PLL and an IF Tx
PLL for CDMA applications. The RF fractional-N PLL uses a
16/17/20/21 quadruple modulus prescaler for PCS applica-
tion and a 8/9/12/13 quadruple modulus prescaler for cellular
application. Both quadruple modulus prescalers offer
modulo 1 through 16 fractional compensation circuitry. The
RF fractional-N PLL can be programmed to operate from 800
MHz to 1400MHz in cellular band and 1200MHz to 2300
MHz in PCS band. The IF Rx PLL and the IF Tx PLL are
integer-N frequency synthesizers that operate from 45 MHz
to 600 MHz with 8/9 dual modulus prescalers. Serial data is
transferred into the LMX3305 via a microwire interface
(Clock, Data, & LE).
n 16/17/20/21 RF quadruple modulus prescaler for PCS
application
n 8/9/12/13 RF quadruple modulus prescaler for cellular
application
n 2.7V to 3.6V operation
n Low current consumption: ICC = 9 mA (typ) at 3.0V
n Programmable or logical power down mode: ICC
10 µA (typ) at 3.0V
n RF PLL Fastlock feature with timeout counter
n Digital lock detect
n Microwire Interface with data preset
n 24-pin CSP package
=
The RF PLL provides a fastlock feature allowing the loop
bandwidth to be increased by 3X during initial lock-on.
Applications
n CDMA Cellular telephone systems
The supply voltage of the LMX3305 ranges from 2.7V to
3.6V. It typically consumes 9 mA of supply current and is
packaged in a 24-pin CSP package.
Block Diagram
DS101361-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation
DS101361
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Functional Block Diagram
DS101361-2
Connection Diagram
DS101361-3
Top View
Order Number LMX3305SLBX
See NS Package Number SLB24A
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2
Pin Descriptions
Pin No.
Pin Name
I/O
Description
1
RF_CPo
O
Charge pump output for RF PLL. For connection to a loop filter for driving the input of
an external VCO.
2
3
4
RF_GND
RF_FIN
PWR
I
RF PLL ground.
RF prescaler input. Small signal input from the RF Cellular or PCS VCO.
RF_VCC
PWR
RF PLL power supply voltage. Input may range from 2.7V to 3.6V. Bypass capacitors
should be placed as close as possible to this pin and be connected directly to the
ground plane. Tx VCC = Rx VCC = RF VCC
.
5
Lock_Det
O
Multiplexed output of the RF, Rx, and Tx PLL’s analog or digital lock detects. The
outputs from the R, N and Fastlock counters can also be selected for test purposes.
Refer to Section 2.3.4 for more detail.
6
7
N/C
No Connect.
RF_En
I
I
I
I
RF PLL enable pin. A LOW on RF En powers down the RF PLL and TRI-STATE®s the
RF PLL charge pump.
8
9
Rx_En
Tx_En
Clock
Rx PLL enable pin. A LOW on Rx En powers down the Rx PLL and TRI-STATEs the
Rx PLL charge pump.
Tx PLL enable pin. A LOW on Tx En powers down the Tx PLL and TRI-STATEs the
Tx PLL charge pump.
10
High impedance CMOS clock input. Data for the various counters is clocked on the
rising edge into the CMOS input.
11
12
Data
LE
I
I
Binary serial data input. Data entered MSB first.
High impedance CMOS input. When LE goes LOW, data is transferred into the shift
registers. When LE goes HIGH, data is transferred from the internal registers into the
appropriate latches.
13
14
Tx_FIN
I
Tx prescaler input. Small signal input from the Tx VCO.
Tx_CPo
O
Charge pump output for Tx PLL. For connection to a loop filter for driving the input of
an external VCO.
15
16
Tx_GND
Tx_VCC
Tx PLL ground.
PWR
I
Tx PLL power supply voltage input. Input may range from 2.7V to 3.6V. Bypass
capacitors should be placed as close as possible to this pin and be connected directly
to the ground plane. Tx VCC = Rx VCC = RF VCC
.
17
18
OSCIN
PLL reference input which has a VCC/2 input threshold and can be driven from an
external CMOS or TLL logic gate. The R counter is clocked on the falling edge of the
OSCIN signal.
Rx_VCC
PWR
Rx PLL power supply voltage. Input ranges from 2.7V to 3.6V. Bypass capacitors
should be placed as close as possible to this pin and be connected directly to the
ground plane. Tx VCC = Rx VCC = RF VCC
.
19
20
Rx_GND
Rx_CPo
PWR
O
Rx PLL ground.
Charge pump output for Rx PLL. For connection to a loop filter for driving the input of
an external VCO.
21
22
Rx_FIN
I
Rx prescaler input. Small signal input from the Rx VCO.
RF_Sw1
O
An open drain NMOS output which can be use for bandswitching or Fastlocking the
RF PLL. (During Fastlock mode a second loop filter damping resistor can be switched
in parallel with the first to ground.) Refer to Section 2.5.3 for more detail.
23
24
RF_Sw2
VP
O
O
An open drain NMOS output which can be use for bandswitching or Fastlocking the
RF PLL. (During Fastlock mode a second loop filter damping resistor can be switched
in parallel with the first to ground.) Refer to Section 2.5.3 for more detail.
RF PLL charge pump power supply. An internal voltage doubler can be enabled in 3V
applications to allow the RF charge pump to operate over a wider tuning range.
3
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Absolute Maximum Ratings (Notes 1, 2)
Recommended Operating
Conditions (Note 1)
Power Supply Voltage (PLL VCC
(Note 3)
)
−0.3V to +6.5V
−0.3V to +6.5V
Power Supply Voltage (PLL VCC
(Note 3)
)
Supply Voltage (VP)
Voltage on any Pin with
GND = 0V (VI)
2.7V to 3.6V
PLL VCC to 5.5V
−30˚C to +85˚C
Supply Voltage (VP) (Note 3)
Operating Temperature (TA)
−0.3V to VCC +0.3V
−65˚C to +150˚C
+240˚C
Storage Temperature Range (TS)
Lead Temp. (solder, 4 sec.) (TL)
ESD - Whole Body Model (Note 2)
2 kV
Electrical Characteristics
<
<
(VCC = VP = 3V, −30˚C TA 85˚C except as specified)
Value
Typ
Symbol
Parameter
Conditions
Min
Unit
Max
GENERAL
ICC
Power Supply Current
RF = On, Rx = On, Tx = On
2.7V ≤ VCC ≤ 3.6V
9.0
10
15
mA
µA
ICC-PWDN Power Down Current
75
2300
1400
600
25
fIN
PCS Operating Frequency
Cellular Operating Frequency
IF Operating Frequency (Rx, Tx)
Oscillator Frequency
1200
800
45
MHz
fOSC
fφ
19.68
MHz
MHz
dBm
VPP
Phase Detector Frequency
PCS/Cellular/IF Input Sensitivity
Oscillator Sensitivity
10
PfIN
2.7V ≤ VCC ≤ 3.6V
FOUT = 1 GHz
−15
0.5
+0
PfOSC
RF PN
IF PN
VCC
RF Phase Noise
−70
−70
dBc/Hz
dBc
IF Phase Noise
@
Fractional Spur 10 kHz
1 kHz Loop Filter (Note 4)
−50
Fractional Spur Harmonic
Attenuate 6 dB/OCT
after 10 kHz
dBc
Tsw
Switching Speed
1 kHz Loop Filter, 60 MHz Jump to
Within 1 kHz
4.0
ms
CHARGE PUMP
RF IDo
Source
RF Charge Pump Source Current
VDo = VP/2 (Note 5)
VDo = VP/2 (Note 5)
VDo = VCC/2 (Note 5)
−22
−22
INOM
INOM
22
22
%
%
RF IDo
Sink
RF Charge Pump Sink Current
IF Charge Pump Source Current
IF IDo
Source
80
100
120
µA
IF IDo Sink IF Charge Pump Sink Current
Do-TRI Charge Pump TRI-STATE Current
VDo = VCC/2 (Note 5)
(Note 6)
−80
−100
−120
1000
µA
pA
I
IDo Sink
vs IDo
Charge Pump Sink vs Source Mismatch TA = 25˚C (Note 7)
3
10
%
Source
IDo vs VDo Charge Pump Current vs Voltage
IDo vs TA Charge Pump Current vs Temperature
DIGITAL INPUTS AND OUTPUTS
TA = 25˚C (Note 6)
(Note 7)
8
5
15
10
%
%
VIH
VIL
VOL
IIH
High-Level Input Voltage
Low-Level Input Voltage
VCC = 2.7V to 3.6V
VCC = 2.7V to 3.6V
IOL = 2 mA
0.8 VCC
V
V
0.2 VCC
0.4
Low-Level Output Voltage
High-Level Input Current
Low-Level Input Current
V
VIH = VCC = 3.6V
VIL = 0V, VCC = 3.6V
VIH = VCC = 3.6V
VIL = 0V, VCC = 3.6V
−1.0
−1.0
1.0
µA
µA
µA
µA
IIL
1.0
IIH
OSCIN High-Level Input Current
OSCIN Low-Level Input Current
100
IIL
−100
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4
Electrical Characteristics (Continued)
<
<
(VCC = VP = 3V, −30˚C TA 85˚C except as specified)
Symbol Parameter
DIGITAL INPUTS AND OUTPUTS
Value
Typ
Conditions
Unit
Min
Max
tCS
Data to Clock Setup Time
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
Clock to Load_En Setup Time
Load_En Pulse Width
50
10
50
50
50
50
ns
ns
ns
ns
ns
ns
tCH
tCWH
TCWL
tENSL
tENW
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which
the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Char-
acteristics.
Note 2: This device is a high performance RF integrated circuit and is ESD sensitive. Handling and assembly of this device should be done on ESD protected work-
stations.
Note 3: PLL V
represents RF V , Tx V
and Rx V
collectively.
CC
CC
CC
CC
Note 4: Guaranteed by design. Not tested in production.
Note 5: I = 100 µA, 400 µA, 700 µA or 900 µA for RF charge pump.
NOM
Note 6: For RF charge pump, 0.5 ≤ V ≤ V - 0.5; for IF charge pump, 0.5 ≤ V ≤ V - 0.5.
CC
Do
P
Do
Note 7: For RF charge pump, V = V /2, for IF charge pump, V = V /2.
Do
P
Do
CC
5
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Charge Pump Current Specification Definitions
DS101361-4
I1 = CP sink current at V = V − ∆V
Do
P
I2 = CP sink current at V = V /2
Do
P
I3 = CP sink current at V = ∆V
Do
I4 = CP source current at V = V − ∆V
Do
P
I5 = CP source current at V = V /2
Do
P
I6 = CP source current at V = ∆V
Do
∆V = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to V
and ground. Typical values are between 0.5V and 1.0V.
CC
1. I vs V = Charge Pump Output Current magnitude variation vs Voltage =
Do
Do
[1⁄
2
{|I1| − |I3|}] / [ ⁄
vs I
2
{|I1| + |I3|}] 100% and [ ⁄
= Charge Pump Output Current Sink vs Source Mismatch =
Do-source
2
{|I4| − |I6|}] / [ ⁄
2
1
1
1
*
*
*
*
* *
{|I4| + |I6|}] 100%
2. I
Do-sink
[|I2| − |I5|] / [1⁄
2
*
*
{|I2| + |I5|}] 100%
3. I vs T = Charge Pump Output Current magnitude variation vs Temperature =
Do
A
@
@
@
*
@
@
@
*
[|I2 temp| − |I2 25˚C|] / |I2 25˚C| 100% and [|I5 temp| − |I5 25˚C|] / |I5 25˚C| 100%
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4-bit fractional portion of the RF counter represents the frac-
tion’s numerator. The fraction’s denominator base is deter-
mined by the four FRAC_D register bits.
1.0 Functional Description
The LMX3305 phase-lock-loop (PLL) system configuration
consists of a high-stability crystal reference oscillator, three
frequency synthesizers, three voltage controlled oscillators
(VCO), and three passive loop filters. Each of the frequency
synthesizers includes a phase detector, a current mode
charge pump, as well as programmable reference [R] and
feedback [N] frequency dividers. The VCO frequency is es-
tablished by dividing the crystal reference signal down via
the R-counter to obtain a comparison reference frequency.
This reference signal (fR) is then presented to the input of a
phase/frequency detector and compared with the feedback
signal (fN), which is obtained by dividing the VCO frequency
down by way of the N-counter, and fractional circuitry. The
phase/frequency detector’s current source output pumps
charge into the loop filter, which then converts the charge
into the VCO’s control voltage. The function of phase/
frequency comparator is to adjust the voltage presented to
the VCO until the feedback signal frequency and phase
match that of the reference signal. When the RF PLL is in a
“Phase-Locked” condition, the RF VCO frequency will be (N
+ F) times that of the comparison frequency, where N is the
integer divide ratio, and F is the fractional component. The
fractional synthesis allows the phase detector frequency to
be increased while maintaining the same frequency step
size for channel selection. The divider ratio N is thereby re-
duced giving a lower phase noise referred to the phase de-
tector input, and the comparison frequency is increased al-
lowing faster switching time.
The Rx and Tx N-counters are each a 13-bit integer divisor,
fully programmable from 56 to 8,191 over the frequency
range from 45 MHz–600 MHz. The Rx and Tx N-counters do
not include fractional compensation.
1.5 FRACTIONAL COMPENSATION
The fractional compensation circuitry of the LMX3305 RF di-
vider allows the user to adjust the VCO tuning resolution in
1/2 through 1/16th increments of the phase detector com-
parison frequency. A 4-bit denominator register (FRAC_D)
selects the fractional modulo base. The integer averaging is
accomplished by using a 4-bit accumulator. A variable phase
delay stage compensates for the accumulated integer phase
error, minimizes the charge pump duty cycle and reduces
the spurious levels. This technique eliminates the need for
compensation current injection into the loop filter. An over-
flow signal generated by the accumulator is equivalent to
one full RF VCO cycle, and results in a pulse swallow.
1.6 PHASE/FREQUENCY DETECTORS
The RF and IF phase/frequency detectors are driven from
their respective N- and R-counter outputs. The maximum fre-
quency at the phase detector inputs is 10 MHz unless limited
by the minimum continuous divide ratio of the multi-modulus
prescaler. The phase detector output controls the charge
pump. The polarity of the pump-up or pump-down control is
programmed using RF_PD_POL, Rx_PD_POL, or
Tx_PD_POL depending on whether RF or IF VCO charac-
teristics are positive or negative. The phase detector also re-
ceives a feedback signal from the charge pump in order to
eliminate dead zones.
1.1 REFERENCE OSCILLATOR INPUTS
The reference oscillator frequency for the RF and IF PLLs
are provided from the external references through the OSCIN
pin. OSCIN input can operate up to 25 MHz with input sensi-
tivity of 0.5 VPP minimum and it drives RF, Rx and Tx
R-counters. OSCIN input has a VCC/2 input threshold that
can be driven from an external CMOS or TTL logic gate.
Typically, the OSCIN is connected to the output of a crystal
oscillator.
1.7 CHARGE PUMPS
The phase detector’s current source output pumps charge
into an external loop filter, which then converts it into the
VCO’s control voltage. The charge pump steers the charge
pump output CPo to VCC (pump-up) or Ground (pump-
down). When locked, CPo is primarily in a TRI-STATE mode
with small corrections. The IF charge pump output current
magnitudes are nominally 100 µA. The RF charge pump out-
put currents can be programmed by the RF_Icpo bits at
100 µA, 400 µA, 700 µA, or 900 µA.
1.2 REFERENCE DIVIDERS (R-COUNTERS)
The RF, Rx and Tx R-counters are clocked through the oscil-
lator block. The maximum frequency is 25 MHz. All RF, Rx
and Tx R-counters are CMOS design. The RF R-counter is
8-bit in length with programmable divider ratio from 2 to 255.
The Rx and Tx R-counters are 10-bit in length with program-
mable divider ratio from 2 to 1023.
1.8 VOLTAGE DOUBLER (VP)
The VP pin is normally driven from an external power supply
over a range of VCC to 5.5V to provide current for the RF
charge pump circuit. An internal voltage doubler circuit con-
nected between the VCC and VP supply pins alternately al-
1.3 PRESCALERS
The LMX3305 has a 16/17/20/21 quadruple modulus pres-
caler for the PCS application and a 8/9/12/13 quadruple
modulus prescaler for the cellular application. The Rx and Tx
prescalers are dual modulus with 8/9 modulus ratio. Both
RF/IF prescalers’ outputs drive the subsequent CMOS flip-
±
lows VCC = 3V ( 10%) users to run the RF charge pump cir-
cuit at close to twice the VCC power supply voltage. The
voltage doubler mode is enabled by setting the V2X bit to a
HIGH level. The voltage doubler’s charge pump driver origi-
nates from the oscillator input. The device will not totally
powerdown until the V2X bit is programmed LOW. The aver-
age delivery current of the doubler is less than the instanta-
neous current demand of the RF charge pump when active
and is thus not capable of sustaining a continuous out of lock
condition. A large external capacitor connected to VP
(=0.1 µF) is needed to control power supply droop when
changing frequencies.
flop chain comprising the programmable
counters.
N feedback
1.4 FEEDBACK DIVIDERS (N-COUNTERS)
The RF, Rx and Tx N-counters are clocked by the output of
RF, Rx and Tx prescalers respectively. The RF N-counter is
composed of two parts: the 15 MSB bits comprise the integer
portion and the 4 LSB bits comprise the fractional portion.
The RF fractional N divider is fully programmable from 80 to
32767 over the frequency range from 1200 MHz-2300 MHz
for PCS application and 40 to 16383 over the frequency
range from 800 MHz-1400 MHz for cellular application. The
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1.0 Functional Description (Continued)
1.9 MICROWIRE INTERFACE
The programmable register set is accessed through the mi-
crowire serial interface. The interface is comprised of three
signal pins: Clock, Data, and LE. After the LE goes LOW, se-
rial data is clocked into the 32-bit shift register upon the ris-
ing edge of Clock MSB first. The last three data bits shifted
into the shift register select one of five addresses. When LE
goes HIGH, data is transferred from the shift registers into
one of the four register bank latches. Selecting the address
<
>
000 presets the data in the four register banks. The syn-
thesizer can be programmed even in the power down (or not
enabled) state.
1.10 LOCK DETECT OUTPUTS
The open-drain Lock Detect is available in the LMX3305 to
provide a digital or analog lock detect indication for the sum
of the active PLLs. In the digital lock detect mode, an internal
digital filter produces a logic level HIGH at the lock detect
output when the error between the phase detector inputs is
less than 15 ns for five consecutive comparison cycles. The
lock detect output is LOW when the error between the phase
detector inputs is more than 30 ns for one comparison cycle.
In the analog lock detect mode, the lock detect pin becomes
active low whenever any of the active PLLs are charge
pumping. The Lock_Det pin can also be programmed to
provide the outputs of the R, N or fastlock timeout counters.
1.11 POWER CONTROL
Each PLL is individually power controlled by the microwire
power down bits Rx_PWDN, Tx_PWDN and RF_PWDN. Al-
ternatively, the PLLs can also be power controlled by the
Tx_En, Rx_En, and RF_En pins. The enable pins override
the power down bits except for the V2X bit. When the re-
spective PLL’s enable pin is high, the power down bits deter-
mine the state of power control. Activation of any PLL power
down modes result in the disabling of the respective N
counter and de-biasing of its respective fIN input (to a high
impedance state). The R counter functionality also becomes
disabled when the power down bit is activated. The refer-
ence oscillator block powers down and the OSCIN pin reverts
to a high impedance state when all of the enable pins are
LOW or all of the power down bits are programmed HIGH,
unless V2X bit is HIGH. Power down forces the respective
charge pump and phase comparator logic to a TRI-STATE
condition. A power down counter reset function resets both N
and R counters of the respective PLL. Upon powering up the
N counter resumes counting in “close” alignment with the R
counter (the maximum error is one prescaler cycle). The mi-
crowire control register remains active and capable of load-
ing and latching in data during all of the power down modes.
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8
2.0 Programming Description
iFled
dAers
I F _ R 0
R x _ R S T I F _ R 1
R x _ P D _ P O I F L _ R 2
I F _ R 3
I F _ N 0
R x _ P W D N I F _ N 1
I F _ N 2
V 2 X
R F _ R 0
R F _ N 0
R F _ N 1
R F _ R S T R F _ R 1
R F _ P D _ P O R L F _ R 2
R F _ R 3
R F _ N 2
I F _ N 3
R F _ P W D N R F _ N 3
I F _ R 4
I F _ R 5
I F _ R 6
I F _ R 7
I F _ R 8
I F _ R 9
I F _ R 1 0
I F _ R 1 1
I F _ R 1 2
I F _ R 1 3
I F _ R 1 4
I F _ N 4
I F _ N 5
I F _ N 6
I F _ N 7
I F _ N 8
I F _ N 9
I F _ N 1 0
I F _ N 1 1
I F _ N 1 2
I F _ N 1 3
I F _ N 1 4
R F _ I c p o R F _ R 4
R F _ R 5
P C S
F b p s
R F _ N 4
R F _ N 5
R F _ N 6
R F _ N 7
R F _ N 8
R F _ N 9
R F _ N 1 0
R F _ N 1 1
R F _ N 1 2
R F _ N 1 3
R F _ N 1 4
R F _ R 6
R F _ R 7
R F _ R 8
R F _ R 9
F S T S W 1 R F _ R 1 0
F S T S W 2 R F _ R 1 1
F S T M 1
F S T M 2
R F _ R 1 2
R F _ R 1 3
R F _ R 1 4
iFled
tDa
I F _ R 1 5
T x _ P W D N I F _ N 1 5
R F _ R 1 5
R F _ N 1 5
I F _ R 1 6
T x _ R S T I F _ R 1 7
T x _ P D _ P O I F L _ R 1 8
I F _ R 1 9
I F _ N 1 6
I F _ N 1 7
I F _ N 1 8
I F _ N 1 9
I F _ N 2 0
I F _ N 2 1
I F _ N 2 2
I F _ N 2 3
I F _ N 2 4
I F _ N 2 5
I F _ N 2 6
I F _ N 2 7
R F _ R 1 6
R F _ R 1 7
R F _ R 1 8
R F _ R 1 9
R F _ R 2 0
R F _ R 2 1
R F _ R 2 2
R F _ R 2 3
R F _ R 2 4
R F _ R 2 5
R F _ R 2 6
R F _ R 2 7
R F _ R 2 8
R F _ N 1 6
R F _ N 1 7
R F _ N 1 8
R F _ N 1 9
R F _ N 2 0
R F _ N 2 1
R F _ N 2 2
R F _ N 2 3
R F _ N 2 4
R F _ N 2 5
R F _ N 2 6
R F _ N 2 7
R F _ N 2 8
I F _ R 2 0
I F _ R 2 1
I F _ R 2 2
I F _ R 2 3
I F _ R 2 4
I F _ R 2 5
I F _ R 2 6
I F _ R 2 7
I F _ R 2 8
I F _ N 2 8
P
I F _ R
I F _ N
R F _ R
R F _ N
9
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2.0 Programming Description (Continued)
iFled
dAers
I F _ R 0
I F _ R 1
I F _ N 0
I F _ N 1
I F _ N 2
I F _ N 3
V 2 X
R F _ R 0
R F _ R 1
R F _ N 0
R F _ N 1
R F _ N 2
R F _ N 3
R x _ R S T
R x _ P W D N
R F _ R S T
R x _ P D _ P O L I F _ R 2
I F _ R 3
R F _ P D _ P O L R F _ R 2
R F _ R 3
R F _ P W D N
I F _ R 4
I F _ R 5
I F _ R 6
I F _ R 7
I F _ R 8
I F _ R 9
I F _ R 1 0
I F _ R 1 1
I F _ R 1 2
I F _ R 1 3
I F _ R 1 4
I F _ N 4
I F _ N 5
I F _ N 6
I F _ N 7
I F _ N 8
I F _ N 9
I F _ N 1 0
I F _ N 1 1
I F _ N 1 2
I F _ N 1 3
I F _ N 1 4
R F _ I c p o
R F _ R 4
R F _ R 5
R F _ R 6
R F _ R 7
R F _ R 8
R F _ R 9
R F _ R 1 0
R F _ R 1 1
R F _ R 1 2
R F _ R 1 3
R F _ R 1 4
P C S
F b p s
R F _ N 4
R F _ N 5
R F _ N 6
R F _ N 7
R F _ N 8
R F _ N 9
R F _ N 1 0
R F _ N 1 1
R F _ N 1 2
R F _ N 1 3
R F _ N 1 4
F S T S W 1
F S T S W 2
F S T M 1
F S T M 2
iFled
tDa
I F _ R 1 5
I F _ R 1 6
T x _ P W D N
I F _ N 1 5
R F _ R 1 5
R F _ N 1 5
I F _ N 1 6
I F _ N 1 7
I F _ N 1 8
I F _ N 1 9
I F _ N 2 0
I F _ N 2 1
I F _ N 2 2
I F _ N 2 3
I F _ N 2 4
I F _ N 2 5
I F _ N 2 6
I F _ N 2 7
I F _ N 2 8
R F _ R 1 6
R F _ R 1 7
R F _ R 1 8
R F _ R 1 9
R F _ R 2 0
R F _ R 2 1
R F _ R 2 2
R F _ R 2 3
R F _ R 2 4
R F _ R 2 5
R F _ R 2 6
R F _ R 2 7
R F _ R 2 8
R F _ N 1 6
R F _ N 1 7
R F _ N 1 8
R F _ N 1 9
R F _ N 2 0
R F _ N 2 1
R F _ N 2 2
R F _ N 2 3
R F _ N 2 4
R F _ N 2 5
R F _ N 2 6
R F _ N 2 7
R F _ N 2 8
T x _ R S T
I F _ R 1 7
T x _ P D _ P O L I F _ R 1 8
I F _ R 1 9
I F _ R 2 0
I F _ R 2 1
I F _ R 2 2
I F _ R 2 3
I F _ R 2 4
I F _ R 2 5
I F _ R 2 6
I F _ R 2 7
I F _ R 2 8
P
I F _ R
I F _ N
R F _ R
R F _ N
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10
2.0 Programming Description (Continued)
iFled
dAers
I F _ R 0
R x _ R S T I F _ R 1
R x _ P D _ P O I F L _ R 2
I F _ R 3
I F _ R 4
I F _ R 5
I F _ R 6
I F _ R 7
I F _ R 8
I F _ R 9
I F _ R 1 0
I F _ R 1 1
I F _ R 1 2
I F _ R 1 3
I F _ R 1 4
iFled
tDa
I F _ R 1 5
I F _ R 1 6
T x _ R S T I F _ R 1 7
T x _ P D _ P O I F L _ R 1 8
I F _ R 1 9
I F _ R 2 0
I F _ R 2 1
I F _ R 2 2
I F _ R 2 3
I F _ R 2 4
I F _ R 2 5
I F _ R 2 6
I F _ R 2 7
I F _ R 2 8
I F _ R
11
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2.0 Programming Description (Continued)
2.3.1 10-Bit IF Programming Reference Divider Ratio (Tx R Counter, Rx R Counter)
Divide Ratio
Tx_R_CNTR [9:0] or Rx_R_CNTR [9:0]
2
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
1
1
•
0
1
•
3
•
1023
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio for both Tx and Rx R counters are from 2 to 1023.
2.3.2 Tx_PD_POL (IF_R[18])
This bit sets the polarity of the Tx phase detector. It is set to one when Tx VCO characteristics are positive. When Tx VCO fre-
quency decreases with increasing control voltage, Tx_PD_POL should be set to zero.
2.3.3 Tx_RST (IF_R[17])
This bit will reset the Tx R and N counters when it is set to one. For normal operation, Tx_RST should be set to zero.
2.3.4 LD (IF_R[16]-[13])
The LD pin is a multiplexed output. When in lock detect mode, LD does ANDing function on the active PLLs. The RF fractional
test mode is only intended for factory testing.
Lock Detect Output Truth Table
LD [3:0]
LD Pin Function
Digital Lock Detect
Output Format
Open Drain
Open Drain
CMOS
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
Analog Lock Detect
Rx R Counter
Rx N Counter
CMOS
Tx R Counter
CMOS
Tx N Counter
CMOS
RF R Counter
CMOS
RF N Counter
CMOS
RF Fastlock Timeout Counter
RF Fractional Test Mode
CMOS
Analog
Lock Detect Digital Filter
The Lock Detect Digital Filter compares the difference between the phase of the inputs of the phase detector to a RC generated
delay of approximately 15 ns. To enter the locked state (Lock Det = HIGH) the phase error must be less than the 15 ns RC delay
for five consecutive reference cycles. Once in lock (Lock Det = HIGH), the RC delay is changed to approximately 30 ns. To exit
the locked state (Lock Det = LOW), the phase error must become greater than the 30 ns RC delay. When the PLL is in the pow-
erdown mode, Lock Det is forced HIGH. A flow chart of the digital filter is shown below.
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12
2.0 Programming Description (Continued)
DS101361-5
13
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2.0 Programming Description (Continued)
Typical Lock Detect Timing
DS101361-6
2.3.5 Rx_PD_POL (IF_R[2])
This bit sets the polarity of the Rx phase detector. It is set to one when Rx VCO characteristics are positive. When Rx VCO fre-
quency decreases with increasing control voltage, Rx_PD_POL should set to zero.
2.3.6 Rx_RST (IF_R[1])
This bit will reset the Rx R and N counters when it is set to one. For normal operation, Rx_RST should be set to zero.
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14
2.0 Programming Description (Continued)
iFled
dAers
I F _ N 0
R x _ P W D N I F _ N 1
I F _ N 2
I F _ N 3
I F _ N 4
I F _ N 5
I F _ N 6
I F _ N 7
I F _ N 8
I F _ N 9
I F _ N 1 0
I F _ N 1 1
I F _ N 1 2
I F _ N 1 3
I F _ N 1 4
T x _ P W D N I F _ N 1 5
I F _ N 1 6
I F _ N 1 7
I F _ N 1 8
I F _ N 1 9
I F _ N 2 0
I F _ N 2 1
I F _ N 2 2
I F _ N 2 3
I F _ N 2 4
I F _ N 2 5
I F _ N 2 6
I F _ N 2 7
iFled
tDa
I F _ N 2 8
I F _ N
15
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2.0 Programming Description (Continued)
2.4.1 3-Bit IF Swallow Counter Divide Ratio (Tx A Counter, Rx A Counter)
Divide Ratio
Tx_NA_CNTR [2:0] or Rx_NA_CNTR [2:0]
0
0
0
•
0
0
•
0
1
•
1
•
7
1
1
1
Divide ratio is from 0 to 7
Tx_NB_CNTR ≥ Tx_NA_CNTR and Rx_NB_CNTR ≥ Rx_NA_CNTR
2.4.2 10-Bit IF Programmable Counter Divide Ratio (Tx B Counter, Rx B Counter)
Divide Ratio
Tx_NB_CNTR [9:0] or Rx_NB_CNTR [9:0]
3
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
1
0
•
1
0
•
4
•
1023
1
1
1
1
1
1
1
1
1
1
Divide ratio is from 3 to 1023 (Divide ratios less than 3 are prohibited)
Tx_NB_CNTR ≥ Tx_NA_CNTR and Rx_NB_CNTR ≥ Rx_NA_CNTR
N = PB + A
B = N div P
A = N mod P
2.4.3 Tx_PWDN (IF_N[15])
This bit will asynchronously powerdown the Tx PLL when set to one. For normal operation, it should be set to zero.
2.4.4 Rx_PWDN (IF_N[1])
This bit will asynchronously powerdown the Rx PLL when set to one. For normal operation, it should be set to zero.
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16
2.0 Programming Description (Continued)
iFled
dAers
V 2 X
R F _ R 0
R F _ R S T R F _ R 1
R F _ P D _ P O R L F _ R 2
R F _ R 3
R F _ I c p o R F _ R 4
R F _ R 5
R F _ R 6
R F _ R 7
R F _ R 8
R F _ R 9
F S T S W 1 R F _ R 1 0
F S T S W 2 R F _ R 1 1
F S T M 1
F S T M 2
R F _ R 1 2
R F _ R 1 3
R F _ R 1 4
R F _ R 1 5
R F _ R 1 6
R F _ R 1 7
R F _ R 1 8
R F _ R 1 9
R F _ R 2 0
R F _ R 2 1
R F _ R 2 2
R F _ R 2 3
R F _ R 2 4
R F _ R 2 5
R F _ R 2 6
R F _ R 2 7
R F _ R 2 8
iFled
tDa
R F _ R
17
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2.0 Programming Description (Continued)
2.5.1 8-Bit RF Programming Reference Divider Ratio (RF R Counter)
Divide Ratio
RF_R_CNTR [7:0]
2
3
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
1
1
•
0
1
•
•
255
1
1
1
1
1
1
1
1
Divide ratio for RF R counter is from 2 to 255.
2.5.2 FSTL_CNTR (RF_R[20]-[14])
The Fastlock Timeout Counter is a 10 bit counter wherein only the seven MSB bits are programmable. (The number of phase de-
tector cycles the fastlock mode remains in HIGH gain is the binary FSTL_CNTR value loaded multiplied by eight.)
Phase Detect Cycles
FSTL_CNTR [6:0]
24
32
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
1
0
•
1
0
•
•
1008
1016
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2.5.3 FSTM (RF_R[13]-[12]) and FSTSW (RF_R[11]-[10])
Fastlock enables the designer to achieve both fast frequency transitions and good phase noise performance by dynamically
changing the PLL loop bandwidth. The Fastlock modes allow wide band PLL fast locking with seamless transition to a low phase
noise narrow band PLL. Consistent gain and phase margins are maintained by simultaneously changing charge pump current
magnitude and loop filter damping resistor. In the LMX3305, the RF fastlock can achieve substantial improvement in lock time by
increasing the charge pump current by 4X, 7X or 9X, which causes a 2X, 2.6X or 3X increase in the loop bandwidth respectively.
The damping resistors are connected to FSTSW pins.
When bit FSTM2 and/or FSTM1 is set HIGH, the RF fastlock is enabled. As a new frequency is loaded, RF_Sw2 pin and/or
RF_Sw1 pin goes to a LOW state to switch in the damping resistors, the RF CPo is set to a higher gain, and fastlock timeout
counter starts counting. Once the timeout counter finishes counting, the PLL returns to its normal operation (the Icpo gain is
forced to 100 µA irrespective of RF_Icpo bits).
When bit FSTM2 and/or FSTM1 is set LOW, pins RF_Sw2 and/or RF_Sw1 can be toggled HIGH or LOW to drive other devices.
RF_Sw2 and/or RF_Sw1 can also be set LOW to switch in different damping resistors to change the loop filter performance.
FSTSW bits control the output states of the RF_Sw2 and RF_Sw1 pins.
RF_R[12] FSTM1
RF_R[10] FSTSW1
RF_Sw1 Output Function
RF_Sw1 pin reflects RF_SwBit “0” logic state
RF_Sw1 pin reflects RF_SwBit “1” logic state
RF_Sw1 pin LOW while T.O. counter is active
0
0
1
0
1
x
RF_R[13] FSTM2
RF_R[11] FSTSW2
RF_Sw2 Output Function
RF_Sw2 pin reflects RF_SwBit “0” logic state
RF_Sw2 pin reflects RF_SwBit “1” logic state
RF_Sw2 pin LOW while T.O. counter is active
0
0
1
0
1
x
2.5.4 FRAC_CAL (RF_R[9]-[5])
These five bits allow the users to optimize the fractional circuitry, therefore reducing the fractional reference spurs. The MSB bit,
RF_R[9], activates the other four calibration bits RF_R[8]-[5]. These four bits can be adjusted to improve fractional spur. Improve-
ments can be made by selecting the bits to be one greater or less than the denominator value. For example, in the 1/16 fractional
mode, these four bits can be programmed to 15 or 17. In normal operation, these bits should be set to zero.
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18
2.0 Programming Description (Continued)
2.5.5 RF_Icpo (RF_R[4]-[3])
These two bits set the charge pump gain of the RF PLL. The user is able to set the charge pump gain during the acquisition phase
of the fastlock mode to 4X, 7X or 9X.
Charge Pump
Gain
RF_R[4]
RF_R[3]
100 µA
0
0
1
1
0
1
0
1
400 µA
700 µA
900 µA
2.5.6 RF_PD_POL (RF_R[2])
This bit sets the polarity of the RF phase detector. It is set to one when RF VCO characteristics are positive. When RF VCO fre-
quency decreases with increasing control voltage, RF_PD_POL should be set to zero.
2.5.7 RF_RST (RF_R[1])
This bit will reset the RF R and N counters when it is set to one. For normal operation, RF_RST should be set to zero.
2.5.8 V2X (RF_R[0])
V2X when set high enables the voltage doubler for the RF charge pump supply.
19
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2.0 Programming Description (Continued)
iFled
dAers
R F _ N 0
R F _ N 1
R F _ N 2
R F _ P W D N R F _ N 3
P C S
F b p s
R F _ N 4
R F _ N 5
R F _ N 6
R F _ N 7
R F _ N 8
R F _ N 9
R F _ N 1 0
R F _ N 1 1
R F _ N 1 2
R F _ N 1 3
R F _ N 1 4
R F _ N 1 5
R F _ N 1 6
R F _ N 1 7
R F _ N 1 8
R F _ N 1 9
R F _ N 2 0
R F _ N 2 1
R F _ N 2 2
R F _ N 2 3
R F _ N 2 4
R F _ N 2 5
R F _ N 2 6
R F _ N 2 7
R F _ N 2 8
iFled
tDa
R F _ N
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20
2.0 Programming Description (Continued)
2.6.1 RF_N_CNTR (RF_N[28]-[14])
The RF N counter value is determined by three counter values that work in conjunction with four prescalers. This quadruple
modulus prescaler architecture allows lower minimum continuous divide ratios than are possible with a dual modulus prescaler
architecture. For the determination of the A, B, and C counter values, the fundamental relationships are shown below.
N = PC + 4B + A
C ≥ max {A,B} + 2
The A, B, and C values can be determined as follows:
C = N div P
B = (N - CP) div 4
A = (N - CP) mod 4
N REGISTER FOR THE CELLULAR (8/9/12/13) PRESCALER OPERATING IN FRACTIONAL MODE
Divide
Ratio
1-23
24-39
40
RF_N_CNTR [14:0]
C Word
B Word
A Word
Divide Ratios Less than 24 are impossible since it is required that C ≥ 3
Some of these N values are Legal Divide Ratios, some are not
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
1
1
.
0
0
.
1
1
.
0
0
0
0
0
0
.
0
0
.
0
1
.
41
…
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N REGISTER FOR THE PCS (16/17/20/21) PRESCALER OPERATING IN FRACTIONAL MODE
Divide
Ratio
1-47
48-79
80
RF_N_CNTR [14:0]
C Word
B Word
A Word
Divide Ratios Less than 48 are impossible since it is required that C ≥ 3
Some of these N values are Legal Divide Ratios, some are not
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
1
1
.
0
0
.
1
1
.
0
0
0
1
0
0
.
0
0
.
0
1
.
81
…
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2.6.2 FRAC_N (RF_N[13]-[10])
These four bits, the fractional accumulator modulus numerator, set the fractional numerator values in the fraction.
Modulus Numerator
FRAC_N [3:0]
0
1
0
0
0
•
0
0
0
•
0
0
1
•
0
1
0
•
2
•
14
15
1
1
1
1
1
1
0
1
21
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2.0 Programming Description (Continued)
2.6.3 FRAC_D (RF_N[9]-[6])
These four bits, the fractional accumulator modulus denominator, set the fractional denominator from 1/2 to 1/16 resolution.
Modulus Denominator
FRAC_D [3:0]
1-8
9
Not Allowed
1
•
0
•
0
•
1
•
10-14
15
1
0
1
0
1
0
1
0
16
MODULUS NUMERATOR (FRAC_N) AND DENOMINATOR (FRAC_D) PROGRAMMING
Fractional
Numerator
(FRAC_N)
Fractional Denominator, (FRAC_D)
RF_N[9]-[6]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RF_N[13]-[10]
0001 0010
0011
0100
0101
0110
0111
1000 1001 1010 1011 1100 1101 1110 1111
0000
0=0000
1=0001
2=0010
3=0011
4=0100
5=0101
6=0110
7=0111
8=1000
9=1001
10=1010
11=1011
12=1100
13=1101
14=1110
15=1111
Functions like an integer-N PLL as fractional component is set to 0.
*
*
*
*
*
*
*
(8/16) (5/15) (4/16) (3/15) (2/12) (2/14) (2/16)
1/9
2/9
3/9
4/9
5/9
6/9
7/9
8/9
1/10
2/10
3/10
4/10
5/10
6/10
7/10
8/10
9/10
1/11
2/11
3/11
4/11
5/11
6/11
7/11
8/11
9/11
1/12
2/12
3/12
4/12
5/12
6/12
7/12
8/12
9/12
1/13
2/13
3/13
4/13
5/13
6/13
7/13
8/13
9/13
1/14
2/14
3/14
4/14
5/14
6/14
7/14
8/14
9/14
1/15
2/15
3/15
4/15
5/15
6/15
7/15
8/15
9/15
1/16
2/16
*
*
*
*
*
*
(10/15) (8/16) (6/15) (4/12) (4/14) (4/16)
*
*
*
*
*
(12/16) (9/15) (6/12) (6/14) (6/16)
3/16
*
*
*
*
(12/15) (8/12) (8/14) (8/16)
4/16
*
*
*
(10/12) (10/14) (10/16)
5/16
*
*
(12/14) (12/16)
6/16
*
(14/16)
7/16
FRAC_D values between 1 to 8 are not allowed.
8/16
9/16
10/11 10/12 10/13 10/14 10/15
11/12 11/13 11/14 11/15
12/13 12/14 12/15
13/14 13/15
10/16
11/16
12/16
13/16
14/16
15/16
14/15
*
Remark: The (FRAC_N / FRAC_D) denotes that the fraction number can be represented by (FRAC_N / FRAC_D) as indicated in the parenthesis. For example,
1/2 can be represented by 8/16.
2.6.4 FBPS (RF_N[5])
This bit when set to one will bypass the delay line calculation used in the fractional circuitry. This will improve the phase noise
while sacrificing performance on reference spurs. When the bit is set to zero, the delay line circuit is in effect to reduce reference
spur.
2.6.5 PCS (RF_N[4])
This bit will determine whether the RF PLL should operate in PCS frequency range or cellular frequency range. When the bit is
set to one, the RF PLL will operate in the PCS mode and when it is set to zero, the cellular mode.
2.6.6 RF_PWDN (RF_N[3])
This bit will asynchronously powerdown the RF PLL when set to one. For normal operation, it should be set to zero.
2.6.7 Test (RF_N[2]-[0])
These bits are the internal factory testing only. They should be set to zero for normal operation.
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22
2.0 Programming Description (Continued)
SERIAL DATA INPUT TIMING
DS101361-7
Notes: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an
@
@
edge rate of 0.6 V/ns with amplitudes of 1.84V VCC = 2.3V and 4.4V VCC = 5.5V.
23
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
LMX3305 Package Drawing
Order Number LMX3305SLBX
NS Package Number SLB24A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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