LMZ14203TZ-ADJ/NOPB [NSC]

IC SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PSSO7, 10.16 X 13.77 MM, 4.57 MM HEIGHT, TO-PMOD, 7 PIN, Switching Regulator or Controller;


型号：	LMZ14203TZ-ADJ/NOPB
厂家：	National Semiconductor
描述：	IC SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PSSO7, 10.16 X 13.77 MM, 4.57 MM HEIGHT, TO-PMOD, 7 PIN, Switching Regulator or Controller 电源电路
文件：	总18页 (文件大小：1132K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

April 12, 2010

LMZ14203

3A SIMPLE SWITCHER® Power Module with 42V Maximum

Input Voltage

Easy to use 7 pin package

Performance Benefits

Operates at high ambient temperature with no thermal

■

derating

High efficiency reduces system heat generation

■

Low radiated emissions (EMI) complies with EN55022

class B standard

Passes 10V/m radiated immunity EMI test standard

EN61000 4-3

■

30107086

System Performance

TO-PMOD 7 Pin Package

10.16 x 13.77 x 4.57 mm (0.4 x 0.542 x 0.18 in)

_JA= 20°C/W, θ_JC= 1.9°C/W

Efficiency V_IN= 24V V_OUT= 5.0V

RoHS Compliant

Electrical Specifications

18W maximum total output power

■

Up to 3A output current

Input voltage range 6V to 42V

Output voltage range 0.8V to 6V

Efficiency up to 90%

■

Key Features

Integrated shielded inductor

■

30107036

Simple PCB layout

Thermal derating curve

V_IN= 24V, V_OUT= 5.0V,

Flexible startup sequencing using external soft-start and

precision enable

Protection against inrush currents and faults such as input

UVLO and output short circuit

■

– 40°C to 125°C junction temperature range

■

Single exposed pad and standard pinout for easy

mounting and manufacturing

Fast transient response for powering FPGAs and ASICs

■

Low output voltage ripple

Pin-to-pin compatible family:

LMZ14203/2/1 (42V max 3A, 2A, 1A)

LMZ12003/2/1 (20V max 3A, 2A, 1A)

30107037

Fully enabled for Webench® Power Designer

■

Radiated Emissions (EN 55022 Class B)

from Evaluation Board

Applications

Point of load conversions from 12V and 24V input rail

■

Time critical projects

Space constrained / high thermal requirement applications

Negative output voltage applications (See AN-2027)

30107038

301070

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Simplified Application Schematic

30107001

Connection Diagram

30107002

Top View

7-Lead TO-PMOD

Ordering Information

Order Number

LMZ14203TZ-ADJ

LMZ14203TZX-ADJ

LMZ14203TZE-ADJ

Package Type

TO-PMOD-7

NSC Package Drawing

TZA07A

Supplied As

250 Units on Tape and Reel

500 Units on Tape and Reel

45 Units in a Rail

TZA07A

Pin Descriptions

Name Description

VIN Supply input — Nominal operating range is 6V to 42V . A small amount of internal capacitance is contained within the

package assembly. Additional external input capacitance is required between this pin and exposed pad.

RON On Time Resistor — An external resistor from V_INto this pin sets the on-time of the application. Typical values range

from 25k to 124k ohms.

Enable — Input to the precision enable comparator. Rising threshold is 1.18V nominal; 90 mV hysteresis nominal.

Maximum recommended input level is 6.5V.

GND Ground — Reference point for all stated voltages. Must be externally connected to EP.

Soft-Start — An internal 8 µA current source charges an external capacitor to produce the soft-start function. This node

is discharged at 200 µA during disable, over-current, thermal shutdown and internal UVLO conditions.

Feedback — Internally connected to the regulation, over-voltage, and short-circuit comparators. The regulation

reference point is 0.8V at this input pin. Connected the feedback resistor divider between the output and ground to set

the output voltage.

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Name Description

VOUT Output Voltage — Output from the internal inductor. Connect the output capacitor between this pin and exposed pad.

Exposed Pad — Internally connected to pin 4. Used to dissipate heat from the package during operation. Must be

electrically connected to pin 4 external to the package.

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ESD Susceptibility(Note 2)

For soldering specifications:

see product folder at www.national.com and

www.national.com/ms/MS/MS-SOLDERING.pdf

± 2 kV

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

VIN, RON to GND

EN, FB, SS to GND

Junction Temperature

Storage Temperature Range

-0.3V to 43.5V

-0.3V to 7V

150°C

Operating Ratings (Note 1)

V_IN

6V to 42V

0V to 6.5V

−40°C to 125°C

-65°C to 150°C

Operation Junction Temperature

Electrical Characteristics Limits in standard type are for T_J= 25°C only; limits in boldface type apply over the

junction temperature (T_J) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design or statistical

correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference purposes only.

Unless otherwise stated the following conditions apply: V_IN= 24V, Vout = 3.3V

Min

(Note 3)

Typ

Max

Symbol

Parameter

Conditions

Units

(Note 4) (Note 3)

SYSTEM PARAMETERS

Enable Control

V_EN

V_EN-HYS

Soft-Start

I_SS

EN threshold trip point

V_ENrising

V_ENfalling

1.1

1.18

1.25

EN threshold hysteresis

SS source current

V_SS= 0V

µA

I_SS-DIS

SS discharge current

-200

Current Limit

I_CL

Current limit threshold

d.c. average

3.2

4.2

5.25

V_IN= 12V to 24V

ON/OFF Timer

t_ON-MIN

ON timer minimum pulse width

OFF timer pulse width

150

260

t_OFF

Regulation and Over-Voltage Comparator

V_FB

In-regulation feedback voltage V_SS>+ 0.8V

T_J= -40°C to 125°C

0.784

0.804

0.802

0.92

0.825

I_O= 3A

V_SS>+ 0.8V

T_J= 25°C

0.786

0.818

I_O= 10 mA

V_FB-OV

Feedback over-voltage

protection threshold

I_FB

I_Q

Feedback input bias current

Non Switching Input Current

μA

V_FB= 0.86V

I_SD

Shut Down Quiescent Current V_EN= 0V

Thermal Characteristics

T_SD

T_SD-HYST

θ_JA

Thermal Shutdown

Rising

Falling

165

°C

Thermal shutdown hysteresis

Junction to Ambient

4 layer JEDEC Printed Circuit Board,

100 vias, No air flow

19.3

°C/W

2 layer JEDEC Printed Circuit Board, No

air flow

21.5

1.9

°C/W

Junction to Case

No air flow

θ_JC

PERFORMANCE PARAMETERS

Output Voltage Ripple

Line Regulation

mV _PP

ΔV_O

V_IN= 12V to 42V, I_O= 3A

V_IN= 24V

.01

1.5

ΔV_O/ΔV_IN

ΔV_O/I_OUT

Load Regulation

mV/A

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Min

(Note 3)

Typ

Max

Symbol

Parameter

Conditions

Units

(Note 4) (Note 3)

Efficiency

V_IN= 24V V_O= 3.3V I_O= 1A

V_IN= 24V V_O= 3.3V I_O= 3A

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the

device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD-22-114.

Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical

Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

Note 4: Typical numbers are at 25°C and represent the most likely parametric norm.

Note 5: EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. See AN-2024 and layout for information on device under test.

Note 6: Theta JA measured on a 1.705” x 3.0” four layer board, with one ounce copper, thirty five 12 mil thermal vias, no air flow, and 1W power dissipation.

Refer to PCB layout diagrams

Typical Performance Characteristics

Unless otherwise specified, the following conditions apply: V_IN= 24V; Cin = 10uF X7R Ceramic; C_O= 100uF X7R Ceramic; Tam-

bient = 25 C for efficiency curves and waveforms.

Efficiency 6V Input @ 25°C

Dissipation 6V Input @ 25°C

30107031

30107032

Efficiency 12V Input @ 25°C

Dissipation 12V Input @ 25°C

30107003

30107004

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Efficiency 24V Input @ 25°C

Dissipation 24V Input @ 25°C

30107026

30107027

Efficiency 36V Input @ 25°C

Dissipation 36V Input @ 25°C

30107029

30107030

Efficiency 6V Input @ 85°C

Dissipation 6V input @ 85°C

30107033

30107034

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Efficiency 8V input 85°C

Efficiency 12V input@ 85°C

Efficiency 24V input @ 85°C

Dissipation 8V input 85°C

Dissipation 12V input @ 85°C

Dissipation 24V input @ 85°C

30107041

30107043

30107045

30107040

30107042

30107044

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Efficiency 36V input @ 85°C

Dissipation 36V input @ 85°C

30107046

30107047

Line and Load Regulation @ 25°C

Output Ripple

24V_IN3.3V_O3A, BW = 200 MHz

30107005

30107048

Transient Response

24V_IN3.3V_O0.6A to 3A Step

Thermal Derating V_OUT= 3.3V

30107006

30107051

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Application Block Diagram

30107008

The function of this resistive divider is to allow the designer to

COT Control Circuit Overview

choose an input voltage below which the circuit will be dis-

abled. This implements the feature of programmable under

voltage lockout. This is often used in battery powered systems

to prevent deep discharge of the system battery. It is also

useful in system designs for sequencing of output rails or to

prevent early turn-on of the supply as the main input voltage

rail rises at power-up. Applying the enable divider to the main

input rail is often done in the case of higher input voltage sys-

tems such as 24V AC/DC systems where a lower boundary

of operation should be established. In the case of sequencing

supplies, the divider is connected to a rail that becomes active

earlier in the power-up cycle than the LMZ14203 output rail.

The two resistors should be chosen based on the following

ratio:

Constant On Time control is based on a comparator and an

on-time one shot, with the output voltage feedback compared

with an internal 0.8V reference. If the feedback voltage is be-

low the reference, the main MOSFET is turned on for a fixed

on-time determined by a programming resistor R_ON. R_ONis

connected to V_INsuch that on-time is reduced with increasing

input supply voltage. Following this on-time, the main MOS-

FET remains off for a minimum of 260 ns. If the voltage on the

feedback pin falls below the reference level again the on-time

cycle is repeated. Regulation is achieved in this manner.

Design Steps for the LMZ14203

Application

The LMZ14203 is fully supported by Webench® and offers

the following: Component selection, electrical and thermal

simulations as well as the build-it board for a reduction in de-

sign time. The following list of steps can be used to manually

design the LMZ14203 application.

R_ENT/ R_ENB= (V_{IN UVLO}/ 1.18V) – 1 (1)

The LMZ14203 demonstration and evaluation boards use

11.8kΩ for R_ENBand 68.1kΩ for R_ENTresulting in a rising UV-

LO of 8V. This divider presents 6.25V to the EN input when

the divider input is raised to 42V.

• Select minimum operating V_INwith enable divider resistors

• Program V_Owith divider resistor selection

• Program turn-on time with soft-start capacitor selection

• Select C_O

OUTPUT VOLTAGE SELECTION

Output voltage is determined by a divider of two resistors

connected between V_Oand ground. The midpoint of the di-

vider is connected to the FB input. The voltage at FB is

compared to a 0.8V internal reference. In normal operation

an on-time cycle is initiated when the voltage on the FB pin

falls below 0.8V. The main MOSFET on-time cycle causes the

output voltage to rise and the voltage at the FB to exceed

0.8V. As long as the voltage at FB is above 0.8V, on-time

cycles will not occur.

• Select C_IN

• Set operating frequency with R_ON

• Determine module dissipation

• Layout PCB for required thermal performance

ENABLE DIVIDER, R_ENTAND R_ENBSELECTION

The regulated output voltage determined by the external di-

vider resistors RFBT and RFBB is:

The enable input provides a precise 1.18V band-gap rising

threshold to allow direct logic drive or connection to a voltage

divider from a higher enable voltage such as V_IN. The enable

input also incorporates 90 mV (typ) of hysteresis resulting in

a falling threshold of 1.09V. The maximum recommended

voltage into the EN pin is 6.5V. For applications where the

midpoint of the enable divider exceeds 6.5V, a small zener

can be added to limit this voltage.

V_O= 0.8V * (1 + R_FBT/ R_FBB) (2)

Rearranging terms; the ratio of the feedback resistors for a

desired output voltage is:

R_FBT/ R_FBB= (V_O/ 0.8V) - 1 (3)

These resistors should be chosen from values in the range of

1.0 kohm to 10.0 kohm.

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For V_O= 0.8V the FB pin can be connected to the output di-

rectly so long as an output preload resistor remains that draws

more than 20uA. Converter operation requires this minimum

load to create a small inductor ripple current and maintain

proper regulation when no load is present.

ternal to the module to handle the input ripple current of the

application. This input capacitance should be located in very

close proximity to the module. Input capacitor selection is

generally directed to satisfy the input ripple current require-

ments rather than by capacitance value. Worst case input

ripple current rating is dictated by the equation:

A feed-forward capacitor is placed in parallel with R_FBTto im-

prove load step transient response. Its value is usually deter-

mined experimentally by load stepping between DCM and

CCM conduction modes and adjusting for best transient re-

sponse and minimum output ripple.

I(C_IN(RMS)) ≊ 1 /2 * I_O* √ (D / 1-D) (8)

where D ≊ V_O/ V_IN

(As a point of reference, the worst case ripple current will oc-

cur when the module is presented with full load current and

when V_IN= 2 * V_O).

A table of values for R_FBT, R_FBB, C_FFand R_ONis included in

the applications schematic.

Recommended minimum input capacitance is 10uF X7R ce-

ramic with a voltage rating at least 25% higher than the

maximum applied input voltage for the application. It is also

recommended that attention be paid to the voltage and tem-

perature deratings of the capacitor selected. It should be

noted that ripple current rating of ceramic capacitors may be

missing from the capacitor data sheet and you may have to

contact the capacitor manufacturer for this rating.

SOFT-START CAPACITOR SELECTION

Programmable soft-start permits the regulator to slowly ramp

to its steady state operating point after being enabled, thereby

reducing current inrush from the input supply and slowing the

output voltage rise-time to prevent overshoot.

Upon turn-on, after all UVLO conditions have been passed,

an internal 8uA current source begins charging the external

soft-start capacitor. The soft-start time duration to reach

steady state operation is given by the formula:

If the system design requires a certain minimum value of input

ripple voltage ΔV_INbe maintained then the following equation

may be used.

t_SS= V_REF* C_SS/ Iss = 0.8V * C_SS/ 8uA (4)

This equation can be rearranged as follows:

C_SS= t_SS* 8 μA / 0.8V (5)

C_IN≥ I_O* D * (1–D) / f_SW-CCM* ΔV_IN(9)

If ΔV_INis 1% of V_INfor a 24V input to 3.3V output application

this equals 240 mV and f_SW= 400 kHz.

Use of a 0.022μF capacitor results in 2.2 msec soft-start du-

ration. This is recommended as a minimum value.

C_IN≥ 3A * 3.3V/24V * (1– 3.3V/24V) / (400000 * 0.240 V)

≥ 3.7μF

Additional bulk capacitance with higher ESR may be required

to damp any resonant effects of the input capacitance and

parasitic inductance of the incoming supply lines.

As the soft-start input exceeds 0.8V the output of the power

stage will be in regulation. The soft-start capacitor continues

charging until it reaches approximately 3.8V on the SS pin.

Voltage levels between 0.8V and 3.8V have no effect on other

circuit operation. Note that the following conditions will reset

the soft-start capacitor by discharging the SS input to ground

with an internal 200 μA current sink.

• The enable input being “pulled low”

• Thermal shutdown condition

• Over-current fault

R_ONRESISTOR SELECTION

Many designs will begin with a desired switching frequency in

mind. For that purpose the following equation can be used.

f_SW(CCM)≊ V_O/ (1.3 * 10^-10* R_ON) (10)

This can be rearranged as

• Internal Vcc UVLO (Approx 4V input to V_IN)

R_ON≊ V_O/ (1.3 * 10 ^-10* f_SW(CCM)(11)

C_OSELECTION

The selection of RON and f_SW(CCM)must be confined by limi-

tations in the on-time and off-time for the COT control section.

None of the required C_Ooutput capacitance is contained with-

in the module. At a minimum, the output capacitor must meet

the worst case minimum ripple current rating of 0.5 * I_{LR P-P}

The on-time of the LMZ14203 timer is determined by the re-

sistor R_ONand the input voltage V_IN. It is calculated as follows:

as calculated in equation (19) below. Beyond that, additional

capacitance will reduce output ripple so long as the ESR is

low enough to permit it. A minimum value of 10 μF is generally

required. Experimentation will be required if attempting to op-

erate with a minimum value. Ceramic capacitors or other low

ESR types are recommended. See AN-2024 for more detail.

t_ON= (1.3 * 10^-10* R_ON) / V_IN(12)

The inverse relationship of t_ONand V_INgives a nearly constant

switching frequency as V_INis varied. R_ONshould be selected

such that the on-time at maximum V_INis greater than 150 ns.

The on-timer has a limiter to ensure a minimum of 150 ns for

t_ON. This limits the maximum operating frequency, which is

governed by the following equation:

The following equation provides a good first pass approxima-

tion of C_Ofor load transient requirements:

f_SW(MAX)= V_O/ (V_IN(MAX)* 150 nsec) (13)

C_O≥I_STEP*V_FB*L*V_IN/ (4*V_O*(V_IN—V_O)*V_OUT-TRAN)(6)

Solving:

This equation can be used to select R_ONif a certain operating

frequency is desired so long as the minimum on-time of 150

ns is observed. The limit for R_ONcan be calculated as follows:

C_O≥ 3A*0.8V*6.8μH*24V / (4*3.3V*( 24V — 3.3V)*33mV)

≥ 43μF (7)

The LMZ14203 demonstration and evaluation boards are

populated with a 100 uF 6.3V X5R output capacitor. Locations

for extra output capacitors are provided.

R_ON≥ V_IN(MAX)* 150 nsec / (1.3 * 10 ^-10) (14)

If R_ONcalculated in (11) is less than the minimum value de-

termined in (14) a lower frequency should be selected. Alter-

natively, V_IN(MAX)can also be limited in order to keep the

frequency unchanged.

C_INSELECTION

The LMZ14203 module contains an internal 0.47 µF input ce-

ramic capacitor. Additional input capacitance is required ex-

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Transition Mode Operation

V_IN= 24V, V_O= 3.3V, I_O= 0.5 A 2 μsec/div

Additionally note, the minimum off-time of 260 ns limits the

maximum duty ratio. Larger R_ON(lower F_SW) should be se-

lected in any application requiring large duty ratio.

Discontinuous Conduction and Continuous Conduction

Modes

At light load the regulator will operate in discontinuous con-

duction mode (DCM). With load currents above the critical

conduction point, it will operate in continuous conduction

mode (CCM). When operating in DCM the switching cycle

begins at zero amps inductor current; increases up to a peak

value, and then recedes back to zero before the end of the

off-time. Note that during the period of time that inductor cur-

rent is zero, all load current is supplied by the output capacitor.

The next on-time period starts when the voltage on the at the

FB pin falls below the internal reference. The switching fre-

quency is lower in DCM and varies more with load current as

compared to CCM. Conversion efficiency in DCM is main-

tained since conduction and switching losses are reduced

with the smaller load and lower switching frequency. Operat-

ing frequency in DCM can be calculated as follows:

30107014

The inductor internal to the module is 6.8 μH. This value was

chosen as a good balance between low and high input voltage

applications. The main parameter affected by the inductor is

the amplitude of the inductor ripple current (I_LR). I_LRcan be

calculated with:

f_SW(DCM)≊V_O*(V_IN-1)*6.8μH*1.18*10²⁰*I_O/(V_IN–V_O)*R_ON²(15)

In CCM, current flows through the inductor through the entire

switching cycle and never falls to zero during the off-time. The

switching frequency remains relatively constant with load cur-

rent and line voltage variations. The CCM operating frequen-

cy can be calculated using equation 7 above.

I_{LR P-P}=V_O*(V_IN- V_O)/(6.8µH*f_SW*V_IN) (17)

Where V_INis the maximum input voltage and f_SWis deter-

mined from equation 10.

If the output current I_Ois determined by assuming that I_O

I_L, the higher and lower peak of I_LRcan be determined. Be

aware that the lower peak of I_LRmust be positive if CCM op-

eration is required.

Following is a comparison pair of waveforms of the showing

both CCM (upper) and DCM operating modes.

CCM and DCM Operating Modes

V_IN= 24V, V_O= 3.3V, I_O= 3A/0.4A 2 μsec/div

POWER DISSIPATION AND BOARD THERMAL

REQUIREMENTS

For the design case of V_IN= 24V, V_O= 3.3V, I_O= 3A, T_AMB

_(MAX)= 85°C , and T_JUNCTION= 125°C, the device must see a

thermal resistance from case to ambient of:

_CA< (T_J-MAX— T_AMB(MAX)) / P_IC-LOSS- θ_JC(18)

Given the typical thermal resistance from junction to case to

be 1.9 °C/W. Use the 85°C power dissipation curves in the

Typical Performance Characteristics section to estimate the

P_IC-LOSSfor the application being designed. In this application

it is 2.25W.

_CA<(125 — 85) / 2.25W — 1.9 = 15.8

To reach θ_CA= 15.8, the PCB is required to dissipate heat

effectively. With no airflow and no external heat, a good esti-

mate of the required board area covered by 1 oz. copper on

both the top and bottom metal layers is:

30107012

The approximate formula for determining the DCM/CCM

boundary is as follows:

Board Area_cm²> 500°C x cm²/W / θ_CA(19)

I_DCB≊V_O*(V_IN–V_O)/(2*6.8 μH*f_SW(CCM)*V_IN) (16)

Following is a typical waveform showing the boundary condi-

tion.

As a result, approximately 31.5 square cm of 1 oz copper on

top and bottom layers is required for the PCB design. The

PCB copper heat sink must be connected to the exposed pad.

Approximately thirty six, 10mils (254 μm) thermal vias spaced

59mils (1.5 mm) apart must connect the top copper to the

bottom copper. For an example of a high thermal performance

PCB layout, refer to the Evaluation Board application note

AN-2024.

PC BOARD LAYOUT GUIDELINES

PC board layout is an important part of DC-DC converter de-

sign. Poor board layout can disrupt the performance of a DC-

DC converter and surrounding circuitry by contributing to EMI,

ground bounce and resistive voltage drop in the traces. These

can send erroneous signals to the DC-DC converter resulting

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in poor regulation or instability. Good layout can be imple-

mented by following a few simple design rules.

Additional Features

OUTPUT OVER-VOLTAGE COMPARATOR

The voltage at FB is compared to a 0.92V internal reference.

If FB rises above 0.92V the on-time is immediately terminat-

ed. This condition is known as over-voltage protection (OVP).

It can occur if the input voltage is increased very suddenly or

if the output load is decreased very suddenly. Once OVP is

activated, the top MOSFET on-times will be inhibited until the

condition clears. Additionally, the synchronous MOSFET will

remain on until inductor current falls to zero.

CURRENT LIMIT

Current limit detection is carried out during the off-time by

monitoring the current in the synchronous MOSFET. Refer-

ring to the Functional Block Diagram, when the top MOSFET

is turned off, the inductor current flows through the load, the

PGND pin and the internal synchronous MOSFET. If this cur-

rent exceeds 4.2A (typical) the current limit comparator dis-

ables the start of the next on-time period. The next switching

cycle will occur only if the FB input is less than 0.8V and the

inductor current has decreased below 4.2A. Inductor current

is monitored during the period of time the synchronous MOS-

FET is conducting. So long as inductor current exceeds 4.2A,

further on-time intervals for the top MOSFET will not occur.

Switching frequency is lower during current limit due to the

longer off-time. It should also be noted that current limit is

dependent on both duty cycle and temperature.

30107011

1. Minimize area of switched current loops.

From an EMI reduction standpoint, it is imperative to minimize

the high di/dt paths during PC board layout. The high current

loops that do not overlap have high di/dt content that will

cause observable high frequency noise on the output pin if

the input capacitor (Cin1) is placed at a distance away from

the LMZ14203. Therefore place C_IN1as close as possible to

the LMZ14203 VIN and GND exposed pad. This will minimize

the high di/dt area and reduce radiated EMI. Additionally,

grounding for both the input and output capacitor should con-

sist of a localized top side plane that connects to the GND

exposed pad (EP).

2. Have a single point ground.

THERMAL PROTECTION

The ground connections for the feedback, soft-start, and en-

able components should be routed to the GND pin of the

device. This prevents any switched or load currents from

flowing in the analog ground traces. If not properly handled,

poor grounding can result in degraded load regulation or er-

ratic output voltage ripple behavior. Provide the single point

ground connection from pin 4 to EP.

The junction temperature of the LMZ14203 should not be al-

lowed to exceed its maximum ratings. Thermal protection is

implemented by an internal Thermal Shutdown circuit which

activates at 165 °C (typ) causing the device to enter a low

power standby state. In this state the main MOSFET remains

off causing V_Oto fall, and additionally the CSS capacitor is

discharged to ground. Thermal protection helps prevent

catastrophic failures for accidental device overheating. When

the junction temperature falls back below 145 °C (typ Hyst =

20 °C) the SS pin is released, V_Orises smoothly, and normal

operation resumes.

3. Minimize trace length to the FB pin.

Both feedback resistors, R_FBTand R_FBB, and the feed forward

capacitor C_FF, should be located close to the FB pin. Since

the FB node is high impedance, maintain the copper area as

small as possible. The trace are from R_FBT, R_FBB, and C_FF

should be routed away from the body of the LMZ14203 to

minimize noise.

Applications requiring maximum output current especially

those at high input voltage may require application derating

at elevated temperatures.

4. Make input and output bus connections as wide as

possible.

ZERO COIL CURRENT DETECTION

This reduces any voltage drops on the input or output of the

converter and maximizes efficiency. To optimize voltage ac-

curacy at the load, ensure that a separate feedback voltage

sense trace is made to the load. Doing so will correct for volt-

age drops and provide optimum output accuracy.

The current of the lower (synchronous) MOSFET is monitored

by a zero coil current detection circuit which inhibits the syn-

chronous MOSFET when its current reaches zero until the

next on-time. This circuit enables the DCM operating mode,

which improves efficiency at light loads.

5. Provide adequate device heat-sinking.

Use an array of heat-sinking vias to connect the exposed pad

to the ground plane on the bottom PCB layer. If the PCB has

a plurality of copper layers, these thermal vias can also be

employed to make connection to inner layer heat-spreading

ground planes. For best results use a 6 x 6 via array with

minimum via diameter of 10mils (254 μm) thermal vias spaced

59mils (1.5 mm). Ensure enough copper area is used for heat-

sinking to keep the junction temperature below 125°C.

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Pre-Biased Startup

PRE-BIASED STARTUP

The LMZ14203 will properly start up into a pre-biased output.

This startup situation is common in multiple rail logic applica-

tions where current paths may exist between different power

rails during the startup sequence. The following scope cap-

ture shows proper behavior during this event.

30107025

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Evaluation Board Schematic Diagram

30107007

Ref Des

Description

SIMPLE SWITCHER ®

1 µF, 50V, X7R

Case Size

TO-PMOD-7

1206

Case Size

National Semiconductor

Taiyo Yuden

Vishay Dale

TDK

Manufacturer P/N

LMZ14203TZ

C_in1

UMK316B7105KL-T

UMK325BJ106MM-T

'UMK316B7105KL-T

JMK325BJ107MM-T

CRCW06033K32FKEA

CRCW06031K07FKEA

CRCW060361k9FKEA

CRCW060368k1FKEA

CRCW060311k8FKEA

C1608X7R1H223K

C_in2

10 µF, 50V, X7R

1 µF, 50V, X7R

1210

C_O1

1206

C_O2

100 µF, 6.3V, X7R

1210

R_FBT

R_FBB

R_ON

R_ENT

R_ENB

C_FF

0603

3.32 kΩ

1.07 kΩ

0603

61.9 kΩ

0603

68.1 kΩ

0603

11.8 kΩ

22 nF, ±10%, X7R, 16V

0603

C_SS

22 nF, ±10%, X7R, 16V

0603

TDK

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30107016

30107017

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

7-Lead TZA Package

NS Package Number TZA07A

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Notes

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Notes

For more National Semiconductor product information and proven design tools, visit the following Web sites at:

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Voltage References

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LMZ14203TZ-ADJ/NOPB [NSC]

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