LP38502ASD-ADJ [NSC]

1.5A FlexCap Low Dropout Linear Regulator for 2.7V to 5.5V Inputs; 1.5A FlexCap低压差线性稳压器的2.7V至5.5V输入


型号：	LP38502ASD-ADJ
厂家：	National Semiconductor
描述：	1.5A FlexCap Low Dropout Linear Regulator for 2.7V to 5.5V Inputs 1.5A FlexCap低压差线性稳压器的2.7V至5.5V输入线性稳压器IC 调节器电源电路光电二极管输出元件
文件：	总16页 (文件大小：343K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

May 19, 2008

LP38500/2-ADJ, LP38500A/2A-ADJ

1.5A FlexCap Low Dropout Linear Regulator for 2.7V to

5.5V Inputs

General Description

Features

National's FlexCap LDO's feature unique compensation that

allows the use of any type of output capacitor with no limits

on minimum or maximum ESR. The LP38500/2 series of low-

dropout linear regulators operates from a +2.7V to +5.5V input

supply. These ultra low dropout linear regulators respond very

quickly to step changes in load, which makes them suitable

for low voltage microprocessor applications. Developed on a

CMOS process, (utilizing a PMOS pass transistor), the

LP38500/2 has low quiescent current that changes little with

load current.

FlexCap: Stable with ceramic, tantalum, or aluminum

■

capacitors

Stable with 10 µF input/output capacitor

■

Adjustable output voltage from 0.6V to 5V

Low ground pin current

25 nA quiescent current in shutdown mode

Guaranteed output current of 1.5A

Available in TO-263, TO-263 THIN, and LLP-8 packages

Guaranteed V_ADJaccuracy of ±1.5% @ 25°C (A Grade)

Ground Pin Current: Typically 2 mA at 1.5A load current.

Disable Mode: Typically 25 nA quiescent current when the

Enable pin is pulled low.

Guaranteed accuracy of ±3.5% @ 25°C (STD)

Over-Temperature and Over-Current protection

■

−40°C to +125°C operating T_Jrange

Simplified Compensation: Stable with any type of output

capacitor, regardless of ESR.

Enable pin (LP38502)

Precision Output: "A" grade versions available with 1.5%

V_ADJtolerance (25°C) and 3% over line, load and tempera-

ture.

Applications

ASIC Power Supplies In:

■

Printers, Graphics Cards, DVD Players

Set Top Boxes, Copiers, Routers

DSP and FPGA Power Supplies

■

SMPS Regulator

Conversion from 3.3V or 5V Rail

Typical Application Circuit

30036119

300361

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Connection Diagrams for TO-263 (TS) Package

30036121

30036122

Top View (LP38500TS-ADJ)

Top View (LP38502TS-ADJ)

TO-263 Package

Connection Diagrams for TO-263 THIN (TJ) Package

30036163

30036162

Top View (LP38500TJ-ADJ, LP38500ATJ-ADJ)

TO-263 THIN Package

Top View (LP38502TJ-ADJ, LP38502ATJ-ADJ)

TO-263 THIN Package

Pin Descriptions for TO-263 (TS), TO-263 THIN (TJ) Packages

Pin #

Designation

Function

Enable (LP38502 only). Pull high to enable the output, low to disable the output. This pin has

no internal bias and must be either tied to the input voltage, or actively driven.

In the LP38500, this pin has no internal connections. It can be left floating or used for trace

routing.

N/C

Input Supply

GND

OUT

ADJ

Ground

Regulated Output Voltage

Sets output voltage

The DAP is used to remove heat from the device by conducting it to the copper clad area on

the PCB which acts as the heatsink. The DAP is electrically connected to the backside of the

die. The DAP must be connected to ground potential, but can not be used as the only ground

connection.

DAP

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Connection Diagrams for LLP-8 (SD) Package

30036160

30036159

Top View (LP38502SD-ADJ, LP38502ASD-ADJ)

LLP-8 Package

Top View (LP38500SD-ADJ, LP38500ASD-ADJ)

LLP-8 Package

Pin Descriptions for LLP-8 (SD) Package

Pin #

Designation

Function

GND

Ground

Input Supply (LP38500 only). Input Supply pins share current and must be connected

together on the PC Board.

Enable (LP38502 only). Pull high to enable the output, low to disable the output. This pin has

no internal bias and must be either tied to the input voltage, or actively driven.

Input Supply. Input Supply pins share current and must be connected together on the PC

Board.

3, 4

Regulated Output Voltage. Output pins share current and must be connected together on the

PC Board.

5, 6, 7

OUT

ADJ

Sets output voltage

The DAP is used to remove heat from the device by conducting it to a copper clad area on

the PCB which acts as a heatsink. The DAP is electrically connected to the backside of the

die. The DAP must be connected to ground potential, but can not be used as the only ground

connection.

DAP

Ordering Information

TABLE 1. Package Marking and Ordering Information

Output

Voltage

Order Number

Package Type

Package Marking

Supplied As:

LP38500SDX-ADJ

LP38500SD-ADJ

LP38502SDX-ADJ

LP38502SD-ADJ

LP38500ASDX-ADJ

LP38500ASD-ADJ

LP38502ASDX-ADJ

LP38502ASD-ADJ

LP38500TSX-ADJ

LP38500TS-ADJ

LP38502TSX-ADJ

LP38502TS-ADJ

LP38500TJ-ADJ

LP38502TJ-ADJ

LP38500ATJ-ADJ

LP38502ATJ-ADJ

LP38500SD-ADJ

LP38502SD-ADJ

LP38500ASD-ADJ

LP38502ASD-ADJ

LP38500TS-ADJ

LP38502TS-ADJ

LP38500TJ-ADJ

LP38502TJ-ADJ

LP38500ATJ-ADJ

LP38502ATJ-ADJ

Tape and Reel of 4500 Units

Tape and Reel of 1000 Units

Tape and Reel of 4500 Units

Tape and Reel of 1000 Units

Tape and Reel of 4500 Units

Tape and Reel of 1000 Units

Tape and Reel of 4500 Units

Tape and Reel of 1000 Units

Tape and Reel of 500 Units

Rail of 45 Units

ADJ

LLP-8

ADJ

TO-263

Tape and Reel of 500 Units

Rail of 45 Units

Tape and Reel of 1000 Units

TO-263 THIN

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Absolute Maximum Ratings (Note 1)

Operating Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Input Supply Voltage

Enable Input Voltage

Output Current (DC)

Junction Temperature(Note 3)

V_OUT

2.7V to 5.5V

0.0V to 5.5V

0 to 1.5A

Storage Temperature Range

Lead Temperature

−65°C to +150°C

−40°C to +125°C

0.6V to 5V

(Soldering, 5 sec.)

ESD Rating (Note 2)

260°C

±2 kV

Power Dissipation(Note 3)

Input Pin Voltage (Survival)

Enable Pin Voltage (Survival)

Output Pin Voltage (Survival)

I_OUT(Survival)

Internally Limited

−0.3V to +6.0V

Internally Limited

Electrical Characteristics

LP38500/2–ADJ

Unless otherwise specified: V_IN= 3.3V, I_OUT= 10 mA, C_IN= 10 µF, C_OUT= 10 µF, V_EN= V_IN, V_OUT= 1.8V. Limits in standard type

are for T_J= 25°C only; limits in boldface type apply over the junction temperature (T_J) range of -40°C to +125°C. Minimum and

Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric

norm at T_J= 25°C, and are provided for reference purposes only.

Symbol

Parameter

Conditions

2.7V ≤ V_IN≤ 5.5V

10 mA ≤ I_OUT≤ 1.5A

Min

Typ

Max

Units

0.584

0.575

0.626

0.635

V_ADJ

Adjust Pin Voltage (Note 6)

0.605

2.7V ≤ V_IN≤ 5.5V

10 mA ≤ I_OUT≤ 1.5A

Adjust Pin Voltage (Note 6)

"A" GRADE

0.596

0.587

0.614

0.623

V_ADJ

0.605

I_ADJ

V_DO

Adjust Pin Bias Current

Dropout Voltage (Note 7)

Output Voltage Line

750

2.7V ≤ V_IN≤ 5.5V

275

375

I_OUT= 1.5A

220

0.04

0.05

ΔV_OUT/ΔV_INRegulation

%/V

%/A

2.7V ≤ V_IN≤ 5.5V

—

(Notes 4, 6)

Output Voltage Load

0.18

0.33

ΔV_OUT/ΔI_OUTRegulation

10 mA ≤ I_OUT≤ 1.5A

(Notes 5, 6)

Ground Pin Current In Normal

Operation Mode

3.5

4.5

I_GND

µA

10 mA ≤ I_OUT≤ 1.5A

—

0.125

I_DISABLED

V_EN< V_IL(EN)

Ground Pin Current

0.025

I_OUT(PK)

I_SC

Peak Output Current

Short Circuit Current

3.6

3.7

V_OUT≥ V_OUT(NOM)- 5%

V_OUT= 0V

Enable Input (LP38502 Only)

V_IH(EN)

V_IL(EN)

V_OUT= ON

Enable Logic High

Enable Logic Low

1.4

—

V_OUT= OFF

0.65

—

Time from V_EN< V_IL(EN)to V_OUT

t_d(off)

Turn-off delay

Turn-on delay

OFF

I_LOAD= 1.5A

—

µs

Time from V_EN>V_IH(EN)to V_OUT

t_d(on)

I_LOAD= 1.5A

I_IH(EN)

I_IL(EN)

V_EN= V_IN

V_EN= 0V

Enable Pin High Current

Enable Pin Low Current

—

0.1

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

AC Parameters

V_IN= 3.0V, I_OUT= 1.5A

f = 120Hz

—

PSRR

Ripple Rejection

V_IN= 3.0V, I_OUT= 1.5A

f = 1 kHz

1.0

100

—

f = 120Hz, C_OUT= 10 µF CER

ρ_n(l/f)

Output Noise Density

Output Noise Voltage

µV/√Hz

BW = 100Hz – 100kHz

C_OUT= 10 µF CER

e_n

µV (rms)

Thermal Characteristics

T_SD

T_Jrising

Thermal Shutdown

170

—

°C

T_Jfalling from T_SD

ΔT_SD

Thermal Shutdown Hysteresis

Thermal Resistance

Junction to Ambient

TO-263, TO-263 THIN(Note 8)

1 sq. in. copper

—

θ_J-A

°C/W

Thermal Resistance

Junction to Ambient

LLP-8 (Note 9)

TO-263, TO-263 THIN

LLP-8

—

Thermal Resistance

Junction to Case

θ_J-C

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics.

Note 2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.

Note 3: Operating junction temperature must be evaluated, and derated as needed, based on ambient temperature (T_A), power dissipation (P_D), maximum

allowable operating junction temperature (T_J(MAX)), and package thermal resistance (θ_JA). See Application Information.

Note 4: Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the voltage at the input.

Note 5: Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in the load current.

Note 6: The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the adjust

voltage tolerance specification.

Note 7: Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. For any output

voltage less than 2.5V, the minimum V_INoperating voltage is the limiting factor.

Note 8: The value of θ_JAfor the TO-263 (TS) package and TO-263 THIN (TJ) package can range from approximately 30 to 60°C/W depending on the amount of

PCB copper dedicated to heat transfer (See Application Information).

Note 9: θ_JAfor the LLP-8 package was measured using the LP38502SD-ADJ evaluation board (See Application Information).

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Typical Performance Characteristics Unless otherwise specified: T_J= 25°C, V_IN= 2.7V, V_EN= V_IN,

C_IN= 10 µF, C_OUT= 10 µF, I_OUT= 10 mA, V_OUT= 1.8V

Noise Density

30036114

30036110

I_GNDvs Load Current

I_GND(OFF)vs Temperature

30036112

30036111

V_ADJvs Temperature

Dropout Voltage vs Load Current

30036113

30036115

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V_ENvs Temperature

Turn-on Characteristics

30036116

30036117

Turn-on Time

30036156

30036155

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Block Diagrams (TO-263, TO-263 THIN)

LP38500-ADJ TO-263 Block Diagram

30036150

LP38502-ADJ TO-263 Block Diagram

30036151

Block Diagrams (LLP-8)

LP38500-ADJ LLP-8 Block Diagram

30036158

LP38502-ADJ LLP-8 Block Diagram

30036151

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Application Information

EXTERNAL CAPACITORS

The value of R2 should always be less than or equal to 10

kΩ for good loop compensation. R1 can be selected for a giv-

en V_OUTusing the following formula:

The LP3850X requires that at least 10 µF (±20%) capacitors

be used at the input and output pins located within one cm of

the IC. Larger capacitors may be used without limit on size for

both C_INand C_OUT. Capacitor tolerances such as temperature

variation and voltage loading effects must be considered

when selecting capacitors to ensure that they will provide the

minimum required amount of capacitance under all operating

conditions for the application.

V_OUT= V_ADJ(1 + R1/R2) + I_ADJ(R1)

Where V_ADJis the adjust pin voltage and I_ADJis the bias cur-

rent flowing into the adjust pin.

In general, ceramic capacitors are best for noise bypassing

and transient response because of their ultra low ESR. It must

be noted that if ceramics are used, only the types with X5R

or X7R dielectric ratings should be used (never Z5U or Y5F).

Capacitors which have the Z5U or Y5F characteristics will see

a drop in capacitance of as much as 50% if their temperature

increases from 25°C to 85°C. In addition, the capacitance

drops significantly with applied voltage: a typical Z5U or Y5F

capacitor can lose as much as 60% of it’s rated capacitance

if only half of the rated voltage is applied to it. For these rea-

sons, only X5R and X7R ceramics should be used.

STABILITY AND PHASE MARGIN

Any regulator which operates using a feedback loop must be

compensated in such a way as to ensure adequate phase

margin, which is defined as the difference between the phase

shift and -180 degrees at the frequency where the loop gain

crosses unity (0 dB). For most LDO regulators, the ESR of the

output capacitor is required to create a zero to add enough

phase lead to ensure stable operation. The LP38500/2-ADJ

has a unique internal compensation circuit which maintains

phase margin regardless of the ESR of the output capacitor,

so any type of capacitor may be used.

INPUT CAPACITOR

Figure 2 shows the gain/phase plot of the LP38500/2-ADJ

with an output of 1.2V, 10 µF ceramic output capacitor, deliv-

ering 1.5A of load current. It can be seen that the unity-gain

crossover occurs at 150 kHz, and the phase margin is about

40° (which is very stable).

All linear regulators can be affected by the source impedance

of the voltage which is connected to the input. If the source

impedance is too high, the reactive component of the source

may affect the control loop’s phase margin. To ensure prop-

er loop operation, the ESR of the capacitor used for C_IN

must not exceed 0.5 Ohms. Any good quality ceramic ca-

pacitor will meet this requirement, as well as many good

quality tantalums. Aluminum electrolytic capacitors may also

work, but can possibly have an ESR which increases signifi-

cantly at cold temperatures. If the ESR of the input capacitor

may exceed 0.5 Ohms, it is recommended that a 2.2 µF ce-

ramic capacitor be used in parallel, as this will assure stable

loop operation.

OUTPUT CAPACITOR

Any type of capacitor may be used for C_OUT, with no limita-

tions on minimum or maximum ESR, as long as the minimum

amount of capacitance is present. The amount of capacitance

can be increased without limit. Increasing the size of C_OUT

typically will give improved load transient response.

SETTING THE OUTPUT VOLTAGE

30036153

The output voltage of the LP38500/2-ADJ can be set to any

value between 0.6V and 5V using two external resistors

shown as R1 and R2 in Figure 1.

FIGURE 2. Gain-Bandwidth Plot for 1.5A Load

Figure 3 shows the gain and phase with no external load. In

this case, the only load is provided by the gain setting resistors

(about 12 kΩ total in this test). It is immediately obvious that

the unity-gain frequency is significantly lower (dropping to

about 500 Hz), at which point the phase margin is 125°.

30036161

FIGURE 1.

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30036157

30036154

FIGURE 4. Load Transient Response

FIGURE 3. Gain-Bandwidth Plot for No Load

In cases where extremely fast load changes occur, the output

capacitance may have to be increased. When selecting ca-

pacitors, it must be understood that the better performing

ones usually cost the most. For fast changing loads, the in-

ternal parasitics of ESR (equivalent series resistance) and

ESL (equivalent series inductance) degrade the capacitor’s

ability to source current quickly to the load. The best capacitor

types for transient performance are (in order):

The reduction in unity-gain bandwidth as load current is re-

duced is normal for any LDO regulator using a P-FET or PNP

pass transistor, because they have a pole in the loop gain

function given by:

1. Multilayer Ceramic: with the lowest values of ESR and

ESL, they can have ESR values in the range of a few milli

Ohms. Disadvantage: capacitance values above about

22 µF significantly increase in cost.

This illustrates how the pole goes to the highest frequency

when R_Lis minimum value (maximum load current). In gen-

eral, LDO’s have maximum bandwidth (and lowest phase

margin) at full load current. In the case of the LP38500/2-ADJ,

it can be seen that it has good phase margin even when using

ceramic capacitors with ESR values of only a few milli Ohms.

2. Low-ESR Aluminum Electrolytics: these are aluminum

types (like OSCON) with a special electrolyte which

provides extremely low ESR values, and are the closest

to ceramic performance while still providing large

amounts of capacitance. These are cheaper (by

capacitance) than ceramic.

LOAD TRANSIENT RESPONSE

Load transient response is defined as the change in regulated

output voltage which occurs as a result of a change in load

current. Many applications have loads which vary, and the

control loop of the voltage regulator must adjust the current

in the pass FET transistor in response to load current

changes. For this reason, regulators with wider bandwidths

often have better transient response.

3. Solid tantalum: can provide several hundred µF of

capacitance, transient performance is slightly worse than

OSCON type capacitors, cheaper than ceramic in large

values.

4. General purpose aluminum electrolytics: cheap and

provide a lot of capacitance, but give the worst

performance.

The LP38500/2-ADJ employs an internal feedforward design

which makes the load transient response much faster than

would be predicted simply by loop speed: this feedforward

means any voltage changes appearing on the output are cou-

pled through to the high-speed driver used to control the gate

of the pass FET along a signal path using very fast FET de-

vices. Because of this, the pass transistor’s current can

change very quickly.

In general, managing load transients is done by paralleling

ceramic capacitance with a larger bulk capacitance. In this

way, the ceramic can source current during the rapidly chang-

ing edge and the bulk capacitor can support the load current

after the first initial spike in current.

PRINTED CIRCUIT BOARD LAYOUT

Good layout practices will minimize voltage error and prevent

instability which can result from ground loops. The input and

output capacitors should be directly connected to the IC pins

with short traces that have no other current flowing in them

(Kelvin connect).

Figure 3 shows the output voltage load transient which occurs

on a 1.8V output when the load changes from 0.1A to 1.5A at

an average slew rate of 0.5A/µs. As shown, the peak output

voltage change from nominal is about 40 mV, which is about

2.2%.

The best way to do this is to place the capacitors very near

the IC and make connections directly to the IC pins via short

traces on the top layer of the PCB. The regulator’s ground pin

should be connected through vias to the internal or backside

ground plane so that the regulator has a single point ground.

The external resistors which set the output voltage must also

be located very near the IC with all connections directly tied

via short traces to the pins of the IC (Kelvin connect). Do not

connect the resistive divider to the load point or DC error will

be induced.

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RFI/EMI SUSCEPTIBILITY

(about 170°C). The hysteresis of the thermal shutdown cir-

cuitry can result in a “cyclic” behavior on the output as the die

temperature heats and cools.

RFI (Radio Frequency Interference) and EMI (Electro-Mag-

netic Interference) can degrade any integrated circuit's per-

formance because of the small dimensions of the geometries

inside the device. In applications where circuit sources are

present which generate signals with significant high frequen-

cy energy content (> 1 MHz), care must be taken to ensure

that this does not affect the IC regulator.

ENABLE OPERATION (LP38502-ADJ Only)

The Enable pin (EN) must be actively terminated by either a

10 kΩ pull-up resistor to V_IN, or a driver which actively pulls

high and low (such as a CMOS rail to rail comparator). If active

drive is used, the pull-up resistor is not required. This pin must

be tied to V_INif not used (it must not be left floating).

If RFI/EMI noise is present on the input side of the regulator

(such as applications where the input source comes from the

output of a switching regulator), good ceramic bypass capac-

itors must be used at the input pin of the IC to reduce the

amount of EMI conducted into the IC.

DROPOUT VOLTAGE

The dropout voltage of a regulator is defined as the input-to-

output differential required by the regulator to keep the output

voltage within 2% of the nominal value. For CMOS LDOs, the

dropout voltage is the product of the load current and the

R_DS(on)of the internal MOSFET pass element.

If the LP38500/2-ADJ output is connected to a load which

switches at high speed (such as a clock), the high-frequency

current pulses required by the load must be supplied by the

capacitors on the IC output. Since the bandwidth of the reg-

ulator loop is less than 300 kHz, the control circuitry cannot

respond to load changes above that frequency. This means

the effective output impedance of the IC at frequencies above

300 kHz is determined only by the output capacitor(s). Ce-

ramic capacitors provide the best performance in this type of

application.

Since the output voltage is beginning to “drop out” of regula-

tion when it drops by 2%, electrical performance of the device

will be reduced compared to the values listed in the Electrical

Characteristics table for some parameters (line and load reg-

ulation and PSRR would be affected).

REVERSE CURRENT PATH

In applications where the load is switching at high speed, the

output of the IC may need RF isolation from the load. In such

cases, it is recommended that some inductance be placed

between the output capacitor and the load, and good RF by-

pass capacitors be placed directly across the load. PCB

layout is also critical in high noise environments, since RFI/

EMI is easily radiated directly into PC traces. Noisy circuitry

should be isolated from "clean" circuits where possible, and

grounded through a separate path. At MHz frequencies,

ground planes begin to look inductive and RFI/EMI can cause

ground bounce across the ground plane. In multi-layer PC

Board applications, care should be taken in layout so that

noisy power and ground planes do not radiate directly into

adjacent layers which carry analog power and ground.

The internal MOSFET pass element in the LP38500/2-ADJ

has an inherent parasitic diode. During normal operation, the

input voltage is higher than the output voltage and the para-

sitic diode is reverse biased. However, if the output is pulled

above the input in an application, then current flows from the

output to the input as the parasitic diode gets forward biased.

The output can be pulled above the input as long as the cur-

rent in the parasitic diode is limited to 200 mA continuous and

1A peak. The regulator output pin should not be taken below

ground potential. If the LP38500/2-ADJ is used in a dual-sup-

ply system where the regulator load is returned to a negative

supply, the output must be diode-clamped to ground.

POWER DISSIPATION/HEATSINKING

The maximum power dissipation (P_D(MAX)) of the LP38500/2-

ADJ is limited by the maximum junction temperature of

125°C, along with the maximum ambient temperature (T_A

_(MAX)) of the application, and the thermal resistance (θ_JA) of

the package. Under all possible conditions, the junction tem-

perature (T_J) must be within the range specified in the Oper-

ating Ratings. The total power dissipation of the device is

given by:

OUTPUT NOISE

Noise is specified in two ways:

Spot Noise or Output noise density is the RMS sum of all

noise sources, measured at the regulator output, at a specific

frequency (measured with a 1Hz bandwidth). This type of

noise is usually plotted on a curve as a function of frequency.

Total output noise voltage or Broadband noise is the RMS

sum of spot noise over a specified bandwidth, usually several

decades of frequencies. Attention should be paid to the units

of measurement.

P_D= ((V_IN− V_OUT) x I_OUT) + (V_INx I_GND

)

(1)

Spot noise is measured in units µV/√Hz or nV/√Hz and total

output noise is measured in µV(rms). The primary source of

noise in low-dropout regulators is the internal reference. In

CMOS regulators, noise has a low frequency component and

a high frequency component, which depend strongly on the

silicon area and quiescent current.

where I_GNDis the operating ground current of the device

(specified under Electrical Characteristics).

The maximum allowable junction temperature rise (ΔT_J) de-

pends on the maximum expected ambient temperature

(T_A(MAX)) of the application, and the maximum allowable junc-

tion temperature (T_J(MAX)):

Noise can generally be reduced in two ways: increase the

transistor area or increase the reference current. However,

enlarging the transisitors will increase die size, and increasing

the reference current means higher total supply current

(ground pin current).

ΔT_J= T_J(MAX)− T_A(MAX)

(2)

The maximum allowable value for junction to ambient Ther-

mal Resistance, θ_JA, can be calculated using the formula:

SHORT-CIRCUIT PROTECTION

The LP38500/2-ADJ contains internal current limiting which

will reduce output current to a safe value if the output is over-

loaded or shorted. Depending upon the value of V_IN, thermal

limiting may also become active as the average power dissi-

pated causes the die temperature to increase to the limit value

θ_JA= ΔT_J/ P_D(MAX)

(3)

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The LP38500/2-ADJ is available in the TO-263 and LLP-8

packages. The thermal resistance depends on the amount of

copper area allocated to heat transfer.

As shown in the figure, increasing the copper area beyond 1.5

square inch produces very little improvement.

HEATSINKING LLP-8 PACKAGE

HEATSINKING TO-263 and TO-263 THIN PACKAGES

The junction-to-ambient thermal resistance for the LLP-8

package is dependent on how much PCB copper is present

to conduct heat away from the device. The LP38502SD-ADJ

evaluation board (980600046-100) was tested and gave a

result of about 80°C/W with a power dissipation of 1W and no

external airflow. This evaluation board is a two layer board

using two ounce copper, and the copper area on topside for

heatsinking is approximately two square inches. Multiple vias

under the DAP also thermally connect to the backside layer

which has about three square inches of copper dedicated to

heatsinking.

The TO-263 package and TO-263 THIN package use the

copper plane on the PCB as a heatsink. The DAP of the pack-

age is soldered to the copper plane for heat sinking. Figure

5 shows a typical curve for the θ_JAof the TO-263 package for

different copper area sizes (the thermal performance of both

TO-263 and TO-263 THIN are the same). The tests were

done using a PCB with 1 ounce copper on top side only, with

copper patterns which were square in shape.

Finite modeling of the LP38502SD-ADJ with a four layer

board (JEDEC JESD51-7 and JESD51-5) with one thermal

via directly under the DAP to the first copper plane predicts a

_JAof 72°C/W.

With four thermal vias directly under the DAP to the first cop-

per plane, the modeling predicts a θ_JAof 50°C/W.

Adding a dog-bone copper area with four additional thermal

vias in the dog-bone area to the first copper plane can improve

_JAto 45C°C/W.

See Application Note AN-1520 A Guide to Board Layout for

Best Thermal Resistance for Exposed Packages for addition-

al thermal considerations for printed circuit board layouts.

30036152

FIGURE 5. θ_JAvs Copper Area for TO-263 Package

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Physical Dimensions inches (millimeters) unless otherwise noted

TO-263 5-Lead, Molded, Surface Mount Package

NS Package Number TS5B

TO-263 THIN 5-Lead, Molded, Surface Mount Package

NS Package Number TJ5A

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8-Lead LLP Package

NS Package Number SDA08C

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Notes

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Notes

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