LP38513TJ-ADJ [NSC]
3A Fast-Transient Response Adjustable Low-Dropout Linear Voltage Regulator; 3A快速瞬态响应可调，低压差线性稳压器
| 型号： | LP38513TJ-ADJ |
| 厂家： | 
National Semiconductor |
| 描述： | 3A Fast-Transient Response Adjustable Low-Dropout Linear Voltage Regulator |
| 文件： | 总12页 (文件大小：370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 12, 2009
LP38513-ADJ
3A Fast-Transient Response Adjustable Low-Dropout
Linear Voltage Regulator
General Description
Features
The LP38513-ADJ Fast-Transient Response Low-Dropout
Voltage Regulator offers the highest-performance in meeting
AC and DC accuracy requirements for powering Digital
Cores. The LP38513-ADJ uses a proprietary control loop that
enables extremely fast response to change in line conditions
and load demands. Output Voltage DC accuracy is guaran-
teed at 2.5% over line, load and full temperature range from
-40°C to +125°C. The LP38513-ADJ is designed for inputs
from the 2.5V, 3.3V, and 5.0V rail, is stable with 10 μF ceramic
capacitors, and has an adjustable output voltage. The
LP38513-ADJ provides excellent transient performance to
meet the demand of high performance digital core ASICs,
DSPs, and FPGAs found in highly-intensive applications such
as servers, routers/switches, and base stations.
2.25V to 5.5V Input Voltage Range
■
■
■
■
Adjustable Output Voltage Range of 0.5V to 4.5V
3.0A Output Load Current
±2.0% Accuracy over Line, Load, and Full-Temperature
Range from -40°C to +125°C
Stable with tiny 10 µF ceramic capacitors
■
■
■
Enable pin
Typically less than 1uA of Ground pin current when Enable
pin is low
25dB of PSRR at 100 kHz
■
■
■
Over-Temperature and Over-Current Protection
TO263-5 THIN Surface Mount Package
Applications
Digital Core ASICs, FPGAs, and DSPs
■
■
■
■
■
■
Servers
Routers and Switches
Base Stations
Storage Area Networks
DDR2 Memory
Typical Application Circuit
30020701
© 2009 National Semiconductor Corporation
300207
www.national.com
Ordering Information
Output
Voltage
Order
Number
Package
Type
Package
Marking
Supplied
As
ADJ
LP38513TJ-ADJ
TO-263 THIN
LP38513TJ-ADJ
Tape and Reel
Connection Diagram
30020705
Top View
TO-263 THIN 5 Pin Package
Pin Descriptions for TO-263 THIN (TJ) Package
Pin #
Pin Name
Function
Enable. Pull high to enable the output, low to disable the output. This pin has no internal bias and
must be tied to the input voltage, or actively driven.
1
EN
2
3
4
5
IN
Input Supply Pin
GND
OUT
ADJ
Ground
Regulated Output Voltage Pin
The feedback to the internal Error Amplifier to set the output voltage
The TO-263 THIN DAP connection is used as a thermal connection to remove heat from the device
to an external heat-sink in the form of the copper area on the printed circuit board. The DAP is
physically connected to backside of the die, but is not internally connected to device ground. The
DAP should be soldered to the Ground Plane copper..
DAP
DAP
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2
Absolute Maximum Ratings (Note 1)
Operating Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Input Supply Voltage, VIN
2.25V to 5.5V
VADJ to 5V
Output Voltage, VOUT
Enable Input Voltage, VEN
Output Current (DC)
Junction Temperature (Note 4)
0.0V to 5.5V
1 mA to 3A
−40°C to +125°C
Storage Temperature Range
Soldering Temperature (Note 3)
Thin TO-263
−65°C to +150°C
260°C, 10s
±2 kV
ESD Rating (Note 2)
Power Dissipation (Note 4)
Input Pin Voltage (Survival)
Enable Pin Voltage (Survival)
Output Pin Voltage (Survival)
ADJ Pin Voltage (Survival)
IOUT (Survival)
Internally Limited
-0.3V to +6.0V
-0.3V to +6.0V
-0.3V to +6.0V
-0.3V to +6.0V
Internally Limited
Electrical Characteristics
Unless otherwise specified: VIN= 2.50V, VOUT = VADJ, IOUT= 10 mA, CIN= 10 µF, COUT= 10 µF, VEN= 2.0V. Limits in standard type
are for TJ= 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and
Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric
norm at TJ= 25°C, and are provided for reference purposes only.
Symbol
Parameter
Conditions
2.25V ≤ VIN ≤ 5.5V
10 mA ≤ IOUT ≤ 3A
Min
Typ
500.
1
Max
Units
VADJ Accuracy
495.0
490.0
505.0
510.0
VADJ
mV
(Note 7)
IADJ
ADJ Pin Bias Current
-
-
-
-
nA
2.25V ≤ VIN ≤ 5.5V
VADJ Line Regulation
(Notes 5, 7)
0.03
0.06
ΔVADJ/ΔVIN
%/V
2.25V ≤ VIN ≤ 5.5V
10 mA ≤ IOUT ≤ 3A
IOUT = 3A
VADJ Load Regulation
(Notes 6, 7)
0.15
0.20
ΔVADJ/ΔIOUT
-
-
-
-
-
%/A
mV
Dropout Voltage
(Note 8)
VDO
-
470
10
12
IOUT = 10 mA
IOUT = 3A
8
Ground Pin Current, Output
Enabled
mA
14
16
IGND
12
Ground Pin Current, Output
Disabled
5
10
VEN = 0.50V
VOUT = 0V
-
-
1
µA
A
ISC
Short Circuit Current
5.2
-
Enable Input
VEN rising from <0.5V until VOUT
ON
=
0.90
0.80
1.50
1.60
VEN(ON)
Enable ON Voltage Threshold
1.20
1.00
V
VEN falling from 1.6V until VOUT
OFF
=
Enable OFF Voltage
Threshold
0.70
0.60
1.30
1.40
VEN(OFF)
VEN(HYS)
IEN
VEN(ON) - VEN(OFF)
Enable Voltage Hysteresis
-
-
-
200
1
-
-
-
mV
nA
VEN = VIN
VEN = 0V
Enable Pin Current
-1
Time from VEN < VEN(TH) to VOUT
OFF, ILOAD = 3A
=
td(OFF)
td(ON)
Turn-off delay
Turn-on delay
-
-
5
5
-
-
µs
Time from VEN >VEN(TH) to VOUT
ON, ILOAD = 3A
=
3
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
AC Parameters
VIN = 2.5V
f = 120Hz
VIN = 2.5V
f = 1 kHz
-
-
73
70
-
-
PSRR
Ripple Rejection
dB
ρn(l/f)
Output Noise Density
Output Noise Voltage
f = 120Hz
-
-
0.4
25
-
-
µV/√Hz
µVRMS
en
BW = 10Hz - 100kHz
Thermal Characteristics
TSD
TJ rising
Thermal Shutdown
-
-
165
10
-
-
°C
TJ falling from TSD
ΔTSD
Thermal Shutdown Hysteresis
Thermal Resistance
Junction to Ambient
(Note 4)
θJ-A
TO-263 THIN
TO-263 THIN
-
-
67
2
-
-
°C/W
°C/W
Thermal Resistance
Junction to Case
θJ-C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics.
Note 2: The human body model (HBM) is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD22-A114.
Note 3: Refer to JEDEC J-STD-020C for surface mount device (SMD) package reflow profiles and conditions. Unless otherwise stated, the temperatures and
times are for Sn-Pb (STD) only.
Note 4: Device operation must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum allowable operating
junction temperature (TJ(MAX)), and package thermal resistance (θJA). The typical θJA rating given is worst case based on minimum land area on two-layer PCB
(EIA/JESD51-3). See POWER DISSIPATION/HEAT-SINKING for details.
Note 5: Line regulation is defined as the change in VADJ from the nominal value due to change in the voltage at the input.
Note 6: Load regulation is defined as the change in VADJ from the nominal value due to change in the load current at the output.
Note 7: The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the output
voltage tolerance specification.
Note 8: Dropout voltage (VDO) is typically defined as the input to output voltage differential (VIN - VOUT) where the input voltage is low enough to cause the output
voltage to drop 2%. For the LP38513-ADJ, the minimum operating voltage of 2.25V is the limiting factor when the programed output voltage is less than typically
1.80V.
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4
Typical Performance Characteristics Unless otherwise specified: TJ = 25°C, VIN = 2.50V, VOUT
=
VADJ, VEN = 2.0V, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA.
VADJ vs Temperature
VOUT vs VIN
30020711
30020715
Ground Pin Current (IGND) vs VIN
Ground Pin Current (IGND) vs Temperature
30020712
30020713
Ground Pin Current (IGND) vs Temperature
Enable Threshold vs Temperature
30020716
30020714
5
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VOUT vs VEN
Load regulation vs Temperature
Current Limit vs Temperature
Load Transient, 10 mA to 3A
30020720
30020732
Line Regulation vs Temperature
30020721
30020722
Load Transient, 10mA to 3A
VOUT = VADJ, COUT = 10 μF Ceramic
VOUT = 1.20V, COUT = 10 μF Ceramic
30020724
30020723
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6
Load Transient, 1A to 3A
VOUT = 1.20V, COUT = 10 μF Ceramic
Line Transient
VOUT = VADJ, COUT = 10 μF Ceramic
30020726
30020725
Line Transient
PSRR, IOUT = 100 mA
VOUT = 1.20V, COUT = 10 μF Ceramic
VOUT = VADJ, COUT = 10 μF Ceramic
30020727
30020729
PSRR, IOUT = 3.0A
VOUT = VADJ, COUT = 10 μF Ceramic
Output Noise Density
VOUT = VADJ, COUT = 10 μF Ceramic
30020731
30020730
7
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Block Diagram
30020707
Application Information
EXTERNAL CAPACITORS
voltage becomes reversed. A less common condition is when
an alternate voltage source is connected to the output.
Like any low-dropout regulator, external capacitors are re-
quired to assure stability. These capacitors must be correctly
selected for proper performance.
There are two possible paths for current to flow from the out-
put pin back to the input during a reverse voltage condition.
While VIN is high enough to keep the control circuity alive, and
the Enable pin is above the VEN(ON) threshold, the control cir-
cuitry will attempt to regulate the output voltage. Since the
input voltage is less than the programmed output voltage, the
control circuit will drive the gate of the pass element to the full
on condition when the output voltage begins to fall. In this
condition, reverse current will flow from the output pin to the
input pin, limited only by the RDS(ON) of the pass element and
the output to input voltage differential. Discharging an output
capacitor up to 1000 µF in this manner will not damage the
device as the current will rapidly decay. However, continuous
reverse current should be avoided. When the Enable is low
this condition will be prevented.
Input Capacitor
A ceramic input capacitor of at least 10 µF is required. For
general usage across all load currents and operating condi-
tions, a 10 µF ceramic input capacitor will provide satisfactory
performance.
Output Capacitor
A ceramic capacitor with a minimum value of 10 µF is required
at the output pin for loop stability. It must be located less than
1 cm from the device and connected directly to the output and
ground pin using traces which have no other currents flowing
through them. As long as the minimum of 10 µF ceramic is
met, there is no limitation on any additional capacitance.
The internal PFET pass element in the LP38513-ADJ has an
inherent parasitic diode. During normal operation, the input
voltage is higher than the output voltage and the parasitic
diode is reverse biased. However, if the output voltage to input
voltage differential is more than 500 mV (typical) the parasitic
diode becomes forward biased and current flows from the
output pin to the input pin through the diode. The current in
the parasitic diode should be limited to less than 1A continu-
ous and 5A peak.
X7R and X5R dielectric ceramic capacitors are strongly rec-
ommended, as they typically maintain a capacitance range
within ±20% of nominal over full operating ratings of temper-
ature and voltage. Of course, they are typically larger and
more costly than Z5U/Y5U types for a given voltage and ca-
pacitance.
Z5U and Y5V dielectric ceramics are not recommended as
the capacitance will drop severely with applied voltage. A typ-
ical Z5U or Y5V capacitor can lose 60% of its rated capaci-
tance with half of the rated voltage applied to it. The Z5U and
Y5V also exhibit a severe temperature effect, losing more
than 50% of nominal capacitance at high and low limits of the
temperature range.
If used in a dual-supply system where the regulator output
load is returned to a negative supply, the output pin must be
diode clamped to ground. A Schottky diode is recommended
for this protective clamp.
SHORT-CIRCUIT PROTECTION
REVERSE VOLTAGE
The LP38513-ADJ is short circuit protected, and in the event
of a peak over-current condition the short-circuit control loop
will rapidly drive the output PMOS pass element off. Once the
power pass element shuts down, the control loop will rapidly
cycle the output on and off until the average power dissipation
A reverse voltage condition will exist when the voltage at the
output pin is higher than the voltage at the input pin. Typically
this will happen when VIN is abruptly taken low and COUT con-
tinues to hold a sufficient charge such that the input to output
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8
causes the thermal shutdown circuit to respond to servo the
on/off cycling to a lower frequency. Please refer to the POW-
ER DISSIPATION/HEAT-SINKING section for power dissi-
pation calculations.
on this compensation technique alone is adequate only for
higher output voltages.
Table 1 lists some suggested, best fit, standard ±1% resistor
values for R1 and R2, and a standard ±10% capacitor values
for CFF, for a range of VOUT values. Other values of R1, R2,
and CFF are available that will give similar results.
SETTING THE OUTPUT VOLTAGE
The output voltage is set using the external resistive divider
R1 and R2. The output voltage is given by the formula:
TABLE 1.
VOUT
0.80V
1.00V
1.20V
1.50V
1.80V
2.00V
2.50V
3.00V
3.30V
CFF
FZ
R1
R2
VOUT = VADJ x (1 + (R1/R2))
(1)
4700 pF
4700 pF
3300 pF
2700 pF
1500 pF
4700 pF
4700 pF
4700 pF
2700 pF
31.6 kHz
33.8 kHz
34.4 kHz
29.5 kHz
36.1 kHz
33.2 kHz
33.2 kHz
33.8 kHz
29.5 kHz
1.07 kΩ
1.00 kΩ
1.40 kΩ
2.00 kΩ
2.94 kΩ
1.02 kΩ
1.02 kΩ
1.00 kΩ
2.00 kΩ
1.78 kΩ
1.00 kΩ
1.00 kΩ
1.00 kΩ
1.13 kΩ
340Ω
The resistors used for R1 and R2 should be high quality, tight
tolerance, and with matching temperature coefficients. It is
important to remember that, although the value of VADJ is
guaranteed, the final value of VOUT is not. The use of low
quality resistors for R1 and R2 can easily produce a VOUT
value that is unacceptable.
It is recommended that the values selected for R1 and R2 are
such that the parallel value is less than 1.00 kΩ. This is to
reduce the possibility of any internal parasitic capacitances
on the ADJ pin from creating an undesirable phase shift that
may interfere with device stability.
255Ω
200Ω
357Ω
Please refer to Application Note AN-1378 Method For Calcu-
lating Output Voltage Tolerances in Adjustable Regulators for
additional information on how resistor tolerances affect the
calculated VOUT value.
( (R1 x R2) / (R1 + R2) ) ≤ 1.00 kΩ
(2)
ENABLE OPERATION
FEED FORWARD CAPACITOR, CFF
The Enable ON threshold is typically 1.2V, and the OFF
threshold is typically 1.0V. To ensure reliable operation the
Enable pin voltage must rise above the maximum VEN(ON)
threshold and must fall below the minimum VEN(OFF) thresh-
old. The Enable threshold has typically 200mV of hysteresis
to improve noise immunity.
When using a ceramic capacitor for COUT, the typical ESR
value will be too small to provide any meaningful positive
phase compensation, FZ, to offset the internal negative phase
shifts in the gain loop.
The Enable pin (EN) has no internal pull-up or pull-down to
establish a default condition and, as a result, this pin must be
terminated either actively or passively.
FZ = 1 / (2 x π x COUT x ESR)
(3)
A capacitor placed across the gain resistor R1 will provide
additional phase margin to improve load transient response
of the device. This capacitor, CFF, in parallel with R1, will form
a zero in the loop response given by the formula:
If the Enable pin is driven from a single ended device (such
as the collector of a discrete transistor) a pull-up resistor to
VIN, or a pull-down resistor to ground, will be required for
proper operation. A 1 kΩ to 100 kΩ resistor can be used as
the pull-up or pull-down resistor to establish default condition
for the EN pin. The resistor value selected should be appro-
priate to swamp out any leakage in the external single ended
device, as well as any stray capacitance.
FZ = 1 / (2 x π x CFF x R1)
(4)
For optimum load transient response select CFF so the zero
frequency, FZ, falls between 20 kHz and 40 kHz.
If the Enable pin is driven from a source that actively pulls high
and low (such as a CMOS rail to rail comparator output), the
pull-up, or pull-down, resistor is not required.
If the application does not require the Enable function, the pin
should be connected directly to the adjacent VIN pin.
CFF = 1 / (2 x π x R1 x FZ)
(5)
POWER DISSIPATION/HEAT-SINKING
The phase lead provided by CFF diminishes as the DC gain
approaches unity, or VOUT approaches VADJ. This is because
CFF also forms a pole with a frequency of:
A heat-sink may be required depending on the maximum
power dissipation (PD(MAX)), maximum ambient temperature
(TA(MAX))of the application, and the thermal resistance (θJA) of
the package. Under all possible conditions, the junction tem-
perature (TJ) must be within the range specified in the Oper-
ating Ratings. The total power dissipation of the device is
given by:
FP = 1 / (2 x π x CFF x (R1 || R2) )
(6)
It's important to note that at higher output voltages, where R1
is much larger than R2, the pole and zero are far apart in fre-
quency. At lower output voltages the frequency of the pole
and the zero mover closer together. The phase lead provided
from CFF diminishes quickly as the output voltage is reduced,
and has no effect when VOUT = VADJ. For this reason, relying
PD = ( (VIN−VOUT) x IOUT) + ((VIN) x IGND
)
(7)
where IGND is the operating ground current of the device
(specified under Electrical Characteristics).
9
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The maximum allowable junction temperature rise (ΔTJ) de-
pends on the maximum expected ambient temperature (TA
(MAX)) of the application, and the maximum allowable junction
temperature (TJ(MAX)):
Figure 2 shows the thermal performance when the Thin
TO-263 is mounted to a two layer PCB where the copper area
is predominately directly under the exposed DAP. .As shown
in the figure, increasing the copper area beyond 1 square inch
produces very little improvement.
ΔTJ = TJ(MAX) − TA(MAX)
(8)
The maximum allowable value for junction to ambient Ther-
mal Resistance, θJA, can be calculated using the formula:
θJA = ΔTJ / PD(MAX)
(9)
LP38513-ADJ is available in the TO-263 THIN surface mount
package. For a comparison of the TO-263 THIN package to
the standard TO-263 package see Application Note AN-1797
TO-263 THIN Package. The thermal resistance depends on
amount of copper area, or heat sink, and on air flow. See Ap-
plication Note AN-1520 A Guide to Board Layout for Best
Thermal Resistance for Exposed Packages for guidelines.
Heat-Sinking the TO-263 THIN Package
The DAP of the TO-263 THIN package is soldered to the cop-
per plane for heat sinking. The TO-263 THIN package has a
30020736
θ
JA rating of 67°C/W, and a θJC rating of 2°C/W. The θJA rating
FIGURE 2. θJA vs Copper Area for the TO-263 THIN
of 67°C/W includes the device DAP soldered to an area of
0.055 square inches (0.22 in x 0.25 in) of 1 ounce copper on
a two sided PCB, with no airflow. See JEDEC standard EIA/
JESD51-3 for more information.
Package
Figure 1 shows a curve for the θJA of TO-263 THIN package
for different thermal via counts under the exposed DAP, using
a four layer PCB for heat sinking. The thermal vias connect
the copper area directly under the exposed DAP to the first
internal copper plane only. See JEDEC standards EIA/
JESD51-5 and EIA/JESD51-7 for more information.
30020735
FIGURE 1. θJA vs Thermal Via Count for the TO-263 THIN
Package on 4–Layer PCB
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10
Physical Dimensions inches (millimeters) unless otherwise noted
TO-263 THIN, 5 Lead, Molded, 1.7mm Pitch, Surface Mount
NS Package Number TJ5A
11
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相关型号：
LP3852EMP-1.8/NOPB
IC VREG 1.8 V FIXED POSITIVE LDO REGULATOR, 0.435 V DROPOUT, PDSO5, SOT-223, 5 PIN, Fixed Positive Single Output LDO Regulator
NSC
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