LP3947 [NSC]

USB/AC Adaptor, Single Cell Li-Ion Battery Charger IC; USB / AC适配器,单节锂离子电池充电器IC
LP3947
型号: LP3947
厂家: National Semiconductor    National Semiconductor
描述:

USB/AC Adaptor, Single Cell Li-Ion Battery Charger IC
USB / AC适配器,单节锂离子电池充电器IC

电池
文件: 总14页 (文件大小:647K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
November 2004  
LP3947  
USB/AC Adaptor, Single Cell Li-Ion Battery Charger IC  
n Near-Depleted Battery Preconditioning  
n Monitors Battery Temperature  
The LP3947 is a complete charge management system that  
n Built-In 5.6 hour timer  
General Description  
safely charges and maintains a Li-Ion battery from either  
USB power source or AC adaptor. In USB mode, the LP3947  
n Under Voltage and Over Voltage Lockout  
n Charge Status Indicators  
n Charge Current Monitor Analog Output  
n LDO Mode Operation can source 1 Amp  
n Continuous Over Current/Temperature Protection  
supports charging in low power or high power mode. Alter-  
natively, the LP3947 can take charge from AC adaptor. In  
both USB and AC adaptor modes, charge current, battery  
regulation voltage, and End of Charge (EOC) point can be  
selected via I2C interface. The LP3947 can also operate on  
default values that are pre-programmed in the factory. The  
battery temperature is monitored continuously at the Ts pin  
to safeguard against hazardous charging conditions. The  
charger also has under-voltage and over-voltage protection  
as well as an internal 5.6 hr timer to protect the battery. The  
pass transistor and charge current sensing resistor are all  
integrated inside the LP3947.  
Key Specifications  
n 1% Charger Voltage Accuracy Over 0˚C TJ 85˚C  
n 4.3V to 6.0V Input Voltage Range  
n 100 mA to 750 mA charge current range, in charger  
mode  
n 100mA to 500mA charge current range, in USB mode  
n LLP Package Power Dissipation: 2.7W at TA = 25˚C  
The LP3947 operates in four modes: pre-qualification, con-  
stant current, constant voltage and maintenance modes.  
There are two open drain outputs for status indication. An  
internal amplifier readily converts the charge current into a  
voltage. Also, the charger can operate in an LDO mode  
providing a maximum of 1.2 Amp to the load.  
Applications  
n Cellular Phones  
n PDAs  
n Digital Cameras  
n USB Powered Devices  
n Programmable Current Sources  
Features  
n Supports USB Charging Scheme  
n Integrated Pass Transistor  
Typical Application Circuit  
20111001  
More Application Circuit can be found in the Application Note section.  
© 2004 National Semiconductor Corporation  
DS201110  
www.national.com  
Connection Diagrams and Package Mark Information  
20111002  
(Top View)  
See NS Package Number SDA14B  
Pin Description  
Pin #  
Name  
EN  
Description  
1
Charger Enable Input. Internally pulled high to CHG-IN pin. A HIGH enables the charger and a  
LOW disables the charger.  
2
3
4
5
6
7
SCL  
I2C serial Interface Clock input.  
I2C serial Interface Data input/out.  
SDA  
BATT  
VT  
Battery supply input terminal. Must have 10 µF ceramic capacitor to GND  
Regulated 2.78V output used for biasing the battery temperature monitoring thermistor.  
Battery Voltage Sense connected to the positive terminal of the battery.  
Select pin between AC adaptor and USB port. A LOW sets the LP3947 in USB port and a HIGH  
sets it in the AC adaptor.  
VBSENSE  
MODE  
8
9
Diff-Amp  
Ts  
Charge current monitoring differential amplifier output. Voltage output representation of the charge  
current.  
Multi function pin. Battery temperature monitoring input and LDO/Charger mode.  
Pulling this pin to VT, or removing the thermistor by physically disconnecting the battery, sets the  
device in LDO mode.  
10  
EOC  
Active Low Open Drain Output. Active when USB port or AC adaptor is connected and battery is  
fully charged. For more information, refer to “LED Charge Status Indicators” section.  
Ground  
11  
12  
GND  
CHG  
Active Low Open Drain Output. Active when USB port or AC adaptor is connected and battery is  
being charged. For more information, refer to “LED Charge Status Indicators” section.  
Control pin to switch between low power (100 mA) mode and high power (500 mA) mode in USB  
mode. This pin is pulled high internally as default to set the USB in 100 mA mode. This pin has to  
be externally pulled low to go into 500 mA mode.  
13  
14  
ISEL  
CHG-IN  
Charger input from a regulated, current limited power source. Must have a 1 µF ceramic capacitor  
to GND  
Ordering Information  
LP3947  
Supplied as 1000 Units,  
Tape and Reel  
LP3947  
Supplied as 4500 Units  
Tape and Reel  
Default  
Options*  
Package  
Marking  
LP3947ISD-09  
LP3947ISDX-09  
ICHG = 500 mA  
VBATT = 4.1V  
EOC = 0.1C  
L00055B  
LP3947ISD-51  
LP3947ISDX-51  
ICHG = 500 mA  
VBATT = 4.2V  
EOC = 0.1C  
L00056B  
*Other default options are available. Please contact National Semiconductor sales office/distributors for availability and specifications.  
www.national.com  
2
LP3947 Functional Block Diagram  
20111003  
3
www.national.com  
Absolute Maximum Ratings (Notes 1,  
2)  
Operating Ratings (Notes 1, 2)  
CHG-IN  
0.3V to 6.5V  
0V to 6V  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales Office/  
Distributors for availability and specifications.  
EN, ISEL, MODE, SCL, SDA,  
VT (Note 3)  
Junction Temperature  
Operating Temperature  
Thermal Resistance θJA  
Maximum Power Dissipation  
(Note 6)  
−40˚C to +125˚C  
−40˚C to +85˚C  
37˚C/W  
CHG-IN  
−0.3V to +6.5V  
All pins except GND and CHG-IN  
(Note 3)  
−0.3V to +6V  
150˚C  
1.21W  
Junction Temperature  
Storage Temperature  
Power Dissipation (Note 4)  
ESD (Note 5)  
−40˚C to +150˚C  
1.89W  
Human Body Model  
Machine Model  
2 kV  
200V  
Electrical Characteristics  
Unless otherwise noted, VCHG-IN = 5V, VBATT = 4V, CCHG-IN = 1 µF, CBATT = 10 µF. Typical values and limits appearing in nor-  
mal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation,  
TJ = −40˚C to +85˚C. (Notes 7, 8, 9)  
Limit  
Symbol  
Parameter  
Conditions  
Typ  
Units  
Min  
Max  
VCC SUPPLY  
VCHG-IN  
VUSB  
Input Voltage Range  
4.5  
4.3  
6
6
V
ICC  
Quiescent Current  
VCHG-IN 4V  
2
20  
µA  
EOC = Low, adaptor connected,  
VBATT = 4.1V  
50  
150  
VOK-TSHD  
Adaptor OK Trip Point (CHG-IN)  
VCHG-IN –VBATT (Rising)  
VCHG-IN –VBATT (Falling)  
VCHG-IN (Rising)  
60  
50  
mV  
mV  
V
VUVLO-TSHD Under Voltage Lock-Out Trip Point  
VOVLO-TSHD Over Voltage Lock-Out Trip Point  
3.95  
3.75  
5.9  
5.7  
160  
20  
3.6  
3.4  
4.3  
4.1  
VCHG-IN (Falling)  
V
VCHG-IN (Rising)  
V
VCHG-IN (Falling)  
Thermal Shutdown Temperature  
Thermal Shutdown Hysteresis  
(Note 8)  
˚C  
BATTERY CHARGER  
ICHG  
Fast Charge Current Range  
ISEL = High, In USB Mode  
ISEL = Low, In USB Mode  
In AC Adaptor Mode  
100  
500  
mA  
100  
−20  
−10  
45  
750  
+20  
+10  
70  
Fast Charge Current Accuracy  
ICHARGE = 100 mA or 150 mA  
ICHARGE 200 mA  
mA  
%
IPRE-CHG  
IEOC  
Pre-Charge Current  
VBATT = 2V  
mA  
End of Charge Current Accuracy  
100 mA to 450 mA, 0.1C EOC Only  
(Note 10)  
−10  
+10  
mA  
%
500 mA to 750 mA, All EOC Points  
−20  
+20  
VBATT  
Battery Regulation Voltage (For 4.1V TJ = 0˚C to +85˚C  
Cell)  
Battery Regulation Voltage (For 4.2V TJ = 0˚C to +85˚C  
4.1  
4.1  
4.1  
4.2  
4.059  
4.038  
4.158  
4.137  
4.141  
4.162  
4.242  
4.263  
TJ = −40˚C to +85˚C  
V
V
Cell)  
TJ = −40˚C to +85˚C  
VCHG-Q  
Full Charge Qualification Threshold  
VBATT Rising, Transition from  
Pre-Charge to Full Current  
3.0  
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4
Electrical Characteristics (Continued)  
Unless otherwise noted, VCHG-IN = 5V, VBATT = 4V, CCHG-IN = 1 µF, CBATT = 10 µF. Typical values and limits appearing in nor-  
mal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation,  
TJ = −40˚C to +85˚C. (Notes 7, 8, 9)  
Limit  
Symbol  
Parameter  
Conditions  
Typ  
Units  
Min  
Max  
BATTERY CHARGER  
VBAT-RST  
Restart Threshold Voltage  
(For 4.1V Cell)  
VBATT Falling, Transition from EOC,  
to Pre-Qualification State  
VBATT Falling, Transition from EOC,  
to Pre-Qualification State  
(Note 8)  
3.9  
3.77  
3.86  
4.02  
4.12  
V
Restart Threshold Voltage  
(For 4.2V Cell)  
4.00  
120  
RSENSE  
Internal Current Sense Resistance  
Internal Current Sense Resistor  
Load Current  
mΩ  
1.2  
A
ICHGMON  
Diff-Amp Output  
ICHG = 50 mA  
0.583  
0.663  
1.790  
5.625  
5.625  
100  
ICHG = 100 mA  
V
ICHG = 750 mA  
tOUT  
VOL  
Charger Time Out  
TJ = 0˚C to 85˚C  
4.78  
4.5  
6.42  
6.75  
Hrs  
mV  
TJ = −40˚C to +85˚C  
EOC, CHG Pins each at 9 mA  
Low Level Output Voltage  
TEMPERATURE SENSE COMPARATORS  
VUTLO  
VOTLO  
Low Voltage Threshold  
Voltage at Ts Pin, Rising  
Voltage at Ts Pin, Falling  
Voltage at Ts Pin, Rising  
Voltage at Ts Pin, Falling  
Voltage at Ts Pin, % of VT  
2.427  
2.369  
1.470  
1.390  
97  
V
V
High Voltage Threshold  
VLDO  
VT  
LDO Mode Voltage Threshold  
Voltage Output  
%
V
2.787  
LDO MODE (Ts = HIGH)  
VOUT  
Output Voltage Regulation  
ILOAD = 50 mA  
ILOAD = 750 mA  
4.10  
4.06  
V
LOGIC LEVELS  
VIL  
VIH  
IIL  
Low Level Input Voltage  
EN, ISEL, MODE  
EN, ISEL, MODE  
EN, ISEL = LOW  
MODE = LOW  
0.4  
V
High Level Input Voltage  
Input Current  
2.0  
−10  
−5  
V
+10  
+5  
µA  
µA  
µA  
IIH  
Input Current  
EN, ISEL, MODE = HIGH  
−5  
+5  
Electrical Characteristics, I2C Interface  
Unless otherwise noted, VCHG-IN = VDD = 5V, VBATT = 4V. Typical values and limits appearing in normal type apply for TJ  
=
25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = −40˚C to +125˚C.  
(Notes 7, 8, 9)  
Limit  
Symbol  
VIL  
Parameter  
Conditions  
SDA & SCL (Note 8)  
Typ  
Units  
Min  
0.4  
Max  
Low Level Input Voltage  
High Level Input Voltage  
Low Level Output Voltage  
Schmitt Trigger Input Hysteresis  
Clock Frequency  
0.3 VDD  
VDD +0.5  
0.2 VDD  
V
V
VIH  
SDA & SCL (Note 8)  
SDA & SCL (Note 8)  
SDA & SCL (Note 8)  
(Note 8)  
0.7 VDD  
0
VOL  
V
VHYS  
FCLK  
tHOLD  
0.1 VDD  
V
400  
kHz  
Hold Time Repeated START  
Condition  
(Note 8)  
0.6  
µs  
tCLK-LP  
tCLK-HP  
CLK Low Period  
(Note 8)  
(Note 8)  
1.3  
0.6  
µs  
µs  
CLK High Period  
5
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Electrical Characteristics, I2C Interface (Continued)  
Unless otherwise noted, VCHG-IN = VDD = 5V, VBATT = 4V. Typical values and limits appearing in normal type apply for TJ  
=
25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = −40˚C to +125˚C.  
(Notes 7, 8, 9)  
Limit  
Symbol  
tSU  
Parameter  
Conditions  
Typ  
Units  
Min  
0.6  
Max  
Set-Up Time Repeated START  
Condition  
(Note 8)  
µs  
tDATA-HOLD Data Hold Time  
(Note 8)  
(Note 8)  
(Note 8)  
300  
100  
0.6  
ns  
ns  
µs  
tDATA-SU  
tSU  
Data Set-Up Time  
Set-Up Time for STOP Condition  
tTRANS  
Maximum Pulse Width of Spikes that (Note 8)  
must be Suppressed by the Input  
50  
ns  
Filter of both DATA & CLK Signals.  
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device  
is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical  
Characteristics tables.  
Note 2: All voltages are with respect to the potential at the GND pin.  
Note 3: Caution must be taken to avoid raising pins EN and V 0.3V higher than V  
and raising pins ISEL, MODE, SCL and SDA 0.3V higher than V  
.
BATT  
T
CHG-IN  
Note 4: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula  
P = (TJ – TA)θJA  
,
(1)  
where T is the junction temperature, T is the ambient temperature, and θ is the junction-to-ambient thermal resistance. The 1.89W rating appearing under  
J
A
JA  
Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature, 150˚C, for T , 80˚C for T , and 37˚C/W for θ . More power can  
J
A
JA  
be dissipated safely at ambient temperatures below 80˚C. Less power can be dissipated safely at ambient temperatures above 80˚C. The Absolute Maximum power  
dissipation can be increased by 27 mW for each degree below 80˚C, and it must be de-rated by 27 mW for each degree above 80˚C.  
Note 5: The human-body model is used. The human-body model is 100 pF discharged through 1.5 k.  
Note 6: Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 1.21W rating  
appearing under Operating Ratings results from substituting the maximum junction temperature for operation, 125˚C, for T , 80˚C for T , and 37˚C/W for θ into  
J
A
JA  
(1) above. More power can be dissipated at ambient temperatures below 80˚C. Less power can be dissipated at ambient temperatures above 80˚C. The maximum  
power dissipation for operation can be increased by 27 mW for each degree below 80˚C, and it must be de-rated by 27 mW for each degree above 80˚C.  
Note 7: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with T = 25˚C. All hot and cold limits are  
J
guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.  
Note 8: Guaranteed by design.  
Note 9: LP3947 is not intended as a Li-Ion battery protection device, any battery used in this application should have an adequate internal protection.  
Note 10: The 10 mA limits apply to all charge currents from 100 mA to 450 mA, to 0.1C End Of Charge (EOC). The limits increase proportionally with higher EOC  
points. For example, at 0.2C, the End Of Charge current accuracy becomes 20 mA.  
20111004  
FIGURE 1. Li-Ion Charging Profile  
www.national.com  
6
VBATT voltage across the battery terminals. During this cycle,  
the charge current, ICHG, continues to decrease with time  
and when it drops below 0.1C (default value), the EOC  
signal is activated indicating successful completion of the  
charge cycle. The EOC current can be programmed to 0.1C,  
0.15C, or 0.2C. The default value is 0.1C. After completing  
the full charge cycle, the controller will start the maintenance  
cycle where battery pack voltage is monitored continuously.  
During the maintenance cycle, if the pack voltage drops 200  
mV below the termination voltage, charge cycle will be initi-  
ated providing that the wall adaptor is plugged in and is alive.  
Application Notes  
LP3947 CHARGER OPERATION  
The LP3947 charge cycle is initiated with AC adaptor or USB  
power source insertion. If the voltage on the CHG-IN pin  
meets under-voltage (VUVLO-TSHD), over-voltage (VOVLO-  
TSHD) requirements, and the Adaptor OK signal is detected,  
then pre-qualification cycle begins (see Figure 1). In this  
cycle, a safe current level, less than 70mA, is pumped into  
the battery while the voltage across the battery terminals is  
measured. Once this voltage exceeds 3.0V, the controller  
will initiate constant current fast charge cycle. If the CHG-IN  
pin is connected to an AC adaptor, the default charge current  
is 500 mA and I2C interface can be used to program this  
parameter. If the CHG-IN pin is connected to the USB port,  
constant current cycle will start with a default of 100 mA.  
During this cycle, the 5.6 hr safety timer starts counting.  
Charging terminates when the battery temperature is out of  
range. For more explanation, please refer to “Ts Pin” section.  
The LP3947 with I2C interface allows maximum flexibility in  
selecting the charge current, battery regulation voltage and  
EOC current. The LP3947 operates in default mode during  
power up. See the “I2C Interface” section for more detail.  
When charging source comes from the USB port, charging  
starts with 100 mA (low power mode, ISEL = high). The USB  
controller can set the ISEL pin low to charge the battery at  
500 mA. A simple external circuit selects between an AC  
adaptor or the USB port. The circuit is designed with priority  
given to the AC adaptor.  
If the 5.6 hr safety timers times out during constant current  
cycle, charging is terminated. As the battery is charged  
during constant current mode, the voltage across pack ter-  
minal increases until it reaches 4.2V (or 4.1V). As soon as  
pack terminal reaches 4.2V (or 4.1V), the controller starts  
operating in constant voltage mode by applying regulated  
20111006  
FIGURE 2. LP3947 with External Switch  
7
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Application Notes (Continued)  
20111007  
FIGURE 3. LP3947 Charger Flow Chart  
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8
Application Notes (Continued)  
CHARGE CURRENT SELECTION IN CONSTANT  
CURRENT MODE  
to set the charge current in the LP3947. In the USB mode,  
the LP3947 will initially charge with 100 mA (ISEL = high). By  
setting the ISEL pin low, charge current can be programmed  
to 500 mA. In addition, with ISEL = low, the charge current  
can be programmed to different values via the I2C interface.  
In the AC adaptor mode, the LP3947 is designed to provide  
a charge current ranging from 100 mA to 750 mA, in steps of  
50 mA, to support batteries with different capacity ratings.  
The default value is 500 mA. No external resistor is required  
TABLE 1. Charge Current Selection in AC Adaptor/USB Mode  
MODE Pin  
AC Adaptor Mode HIGH  
ISEL Pin  
HIGH  
Functions  
ISEL polarity is irrelevant. Default 500 mA charge current. Can be  
reprogrammed via I2C.  
HIGH  
LOW  
LOW  
LOW  
USB Mode  
HIGH  
100 mA charge current  
Default 500 mA charge current. Can be reprogrammed via I2C.  
LOW  
BATTERY VOLTAGE SELECTION  
CHARGE CURRENT SENSE DIFFERENTIAL AMPLIFIER  
The battery voltage regulation can be set to 4.1V or 4.2V by  
default. Please refer to the Ordering Information table for  
more detail.  
The charge current is monitored across the internal 120 mΩ  
current sense resistor. The differential amplifier provides the  
analog representation of the charge current. Charge current  
can be calculated using the following equation:  
END OF CHARGE (EOC) CURRENT SELECTION  
The EOC thresholds can be programmed to 0.1C, 0.15C or  
0.2C in the LP3947. The default value is 0.1C, which pro-  
vides the highest energy storage, but at the expense of  
longer charging time. On the other hand, 0.2C takes the  
least amount of charging time, but yields the least energy  
storage.  
Where voltage at Diff Amp output (VDIFF) is in volt, and  
charge current (ICHG) is in amps.  
20111009  
FIGURE 4. Charge Current Monitoring Circuit (Diff-Amp)  
Monitoring the Diff Amp output during constant voltage cycle  
can provide an accurate indication of the battery charge  
status and time remaining to EOC. This feature is particularly  
useful during constant voltage mode. The current sense  
circuit is operational in the LDO mode as well. It can be used  
to monitor the system current consumption during testing.  
LED CHARGE STATUS INDICATORS  
The LP3947 is equipped with two open drain outputs to drive  
a green LED and a red LED. These two LEDs work together  
in combinations to indicate charge status or fault conditions.  
Table 2 shows all the conditions.  
9
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Application Notes (Continued)  
TABLE 2. LED Indicator Summary  
RED LED  
GREEN LED  
(EOC)  
OFF  
(CHG)  
OFF  
ON  
Charger Off  
Charging Li Ion Battery*  
OFF  
Maintenance Mode  
OFF  
OFF  
OFF  
OFF  
ON  
ON  
Charging Li Ion Battery after Passing Maintenance Mode  
EN Pin = LOW  
ON  
ON  
LDO Mode  
OFF  
5.6 Hr Safety Timer Flag/Battery Temperature Violation  
ON  
* Charging Li Ion battery for the first time after V  
insertion.  
CHG-IN  
Ts PIN  
Voltage on the Ts Pin  
Charger Status  
The LP3947 continuously monitors the battery temperature  
by measuring the voltage between the Ts pin and ground.  
Charging stops if the battery temperature is outside the  
permitted temperature range set by the battery’s internal  
thermistor RT and the external bias resistor RS. A 1% preci-  
sion resistor should be used for RS. A curve 2 type thermistor  
is recommended for RT. The voltage across RT is propor-  
tional to the battery temperature. If the battery temperature is  
outside of the range during the charge cycle, the LP3947 will  
suspend charging. As an example, for a temperature range  
of 0˚C to 50˚C, a 10kfor the thermistor and a 4.1kfor Rs  
should be used. When battery temperature returns to the  
permitted range, charging resumes from the beginning of the  
flow chart and the 5.6 hr safety timer is reset. Refer to Figure  
3. LP3947 Charger Flow Chart for more information.  
<
2.427v Ts 2.7V  
Charger Off  
0V Ts 1.39V  
<
<
1.39V Ts 2.427V  
Charger On  
LDO MODE  
The charger is in the LDO mode when the Ts pin is left  
floating. This mode of operation is used primarily during  
system level testing of the handset to eliminate the need for  
battery insertion. CAUTION: battery may be damaged if  
device is operating in LDO mode with battery connected.  
The internal power FET provides up to 1.2 amp of current at  
BATT pin in this mode. The LDO output is set to 4.1V. When  
operating at higher output currents, care must be taken not  
to exceed the package power dissipation rating. See “Ther-  
mal Performance of LLP Package” section for more detail.  
In absence of the thermistor, Ts pin will be pulled high to VT  
and the LP3947 goes into LDO mode. In this mode, the  
internal power FET provides up to 1.2 amp of current at the  
BATT pin. The LDO output is set to 4.1V or 4.2V, depending  
on the programmed battery regulation voltage. When oper-  
ating at higher output currents, care must be taken not to  
exceed the package power dissipation rating. See “Thermal  
Performance of LLP Package” section for more detail.  
EN PIN  
The Enable pin is used to enable/disable the charger, in both  
the charger mode and the LDO mode, see Figures 5, 6. The  
enable pin is internally pulled HIGH to the CHG-IN pin. When  
the charger is disabled, it draws less than 4 µA of current.  
Charger Status in Relation to Ts Voltage  
Voltage on the Ts Pin  
Charger Status  
Ts 2.7V  
LDO Mode  
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10  
Application Notes (Continued)  
20111010  
<
<
FIGURE 5. Power Up Timing Diagram in Charger Mode (1.39V Ts 2.427V)  
20111011  
FIGURE 6. Power Up Timing Diagram in LDO Mode (Ts 2.7V)  
MODE PIN  
mode. It will turn the charger off when the 5.6 hr timer is up  
while the charger is still in constant current mode. In this  
case, both LEDs will turn on, indicating a fault condition.  
The mode pin toggles the LP3947 between the AC adaptor  
mode and the USB mode. When CHG-IN is connected to a  
USB port, this pin must be set low. When CHG-IN is con-  
nected to an AC adaptor, this pin must be tied high to either  
the BATT pin or to the wall adaptor input. Caution: MODE pin  
should never be tied to CHG-IN pin directly, as it will turn on  
an internal diode.  
When the battery temperature is outside the specified tem-  
perature range, the 5.6 hr safety timer will reset upon recov-  
ery of the battery temperature.  
I2C INTERFACE  
I2C interface is used in the LP3947 to program various  
parameters as shown in Table 3. The LP3947 operates on  
default settings following power up. Once programmed, the  
LP3947 retains the register data as long as the battery  
voltage is above 2.85V.  
5.6 HR SAFETY TIMER IN CHARGER MODE  
The LP3947 has a built-in 5.6 hr back up safety timer to  
prevent over-charging a Li Ion battery. The 5.6 hr timer starts  
counting when the charger enters the constant current  
11  
www.national.com  
Application Notes (Continued)  
TABLE 3. LP3947 Serial Port Communication address code 7h’47  
LP3947 Control and Data Codes  
Addrs  
Register  
Charger  
7
6
5
4
3
AC Adaptor  
Charge  
Current  
Code 3  
(1)  
2
AC Adaptor  
Charge  
Current  
Code 2  
(0)  
1
AC Adaptor  
Charge  
Current  
Code 1  
(0)  
0
8'h00  
Batt Voltage  
(0) = 4.1V  
1 = 4.2V  
AC Adaptor  
Charge  
Current  
Code 0  
(0)  
Register -1  
8'h01  
8'h02  
Charger  
EOC  
(Green LED)  
R/O  
Charging  
(Red LED)  
R/O  
EOC  
EOC  
Register -2  
SEL-1  
(0)  
SEL-0  
(1)  
Charger  
USB  
USB  
USB  
USB  
Charge  
Current  
Code 0  
(0)  
Register -3  
Charge  
Current  
Code 3  
(1)  
Charge  
Current  
Code 2  
(0)  
Charge  
Current  
Code 1  
(0)  
Numbers in parentheses indicate default setting. “0” bit is set to low state, and “1” bit is set to high state. R/O –Read Only, All other bits are Read and Write.  
TABLE 4. Charger Current and EOC Current Programming Code  
Charger Current  
Selection Code ISET (mA)  
End of Charge Current  
Selection Code  
Data Code  
4h'00  
4h'01  
4h'02  
4h'03  
4h'04  
4h'05  
4h'06  
4h'07  
4h'08  
4h'09  
4h'0A  
4h'0B  
4h'0C  
4h'0D  
100  
150  
200  
250  
300  
350  
400  
450  
500  
550  
600  
650  
700  
750  
0.1C  
0.15C  
0.2C  
20111012  
w = write (sda = “0”)  
r = read (sda = “1”)  
ack = acknowledge (sda pulled low by either master or slave)  
Nack = No Acknowledge  
rs = repeated start  
FIGURE 7. LP3947 (Slave) Register Write  
www.national.com  
12  
Application Notes (Continued)  
20111013  
w = write (sda = “0”)  
r = read (sda = “1”)  
ack = acknowledge (sda pulled low by either master or slave)  
Nack = No Acknowledge  
rs = repeated start  
FIGURE 8. LP3947 (Slave) Register Read  
THERMAL PERFORMANCE OF LLP PACKAGE  
charged, then 740 mA of ICHG can safely charge the battery.  
More power can be dissipated at ambient temperatures  
below 70˚C. Less power can be dissipated at ambient tem-  
peratures above 70˚C. The maximum power dissipation for  
operation can be increased by 27 mW for each degree below  
70˚C, and it must be de-rated by 27 mW for each degree  
above 70˚C.  
The LP3947 is a monolithic device with an integrated pass  
transistor. To enhance the power dissipation performance,  
the Leadless Lead frame Package, or LLP, is used. The LLP  
package is designed for improved thermal performance be-  
cause of the exposed die attach pad at the bottom center of  
the package. It brings advantage to thermal performance by  
creating a very direct path for thermal dissipation. Compared  
to the traditional leaded packages where the die attach pad  
is embedded inside the mold compound, the LLP reduces a  
layer of thermal path.  
LAYOUT CONSIDERATION  
The LP3947 has an exposed die attach pad located at the  
bottom center of the LLP package. It is imperative to create  
a thermal land on the PCB board when designing a PCB  
layout for the LLP package. The thermal land helps to con-  
duct heat away from the die, and the land should be the  
same dimension as the exposed pad on the bottom of the  
LLP (1:1 ratio). In addition, thermal vias should be added  
inside the thermal land to conduct more heat away from the  
surface of the PCB to the ground plane. Typical pitch and  
outer diameter for these thermal vias are 1.27 mm and 0.33  
mm respectively. Typical copper via barrel plating is 1oz  
although thicker copper may be used to improve thermal  
performance. The LP3947 bottom pad is connected to  
ground. Therefore, the thermal land and vias on the PCB  
board need to be connected to ground.  
The thermal advantage of the LLP package is fully realized  
only when the exposed die attach pad is soldered down to a  
thermal land on the PCB board and thermal vias are planted  
underneath the thermal land. Based on a LLP thermal mea-  
surement, junction to ambient thermal resistance (θJA) can  
be improved by as much as two times if a LLP is soldered on  
the board with thermal land and thermal vias than if not.  
An example of how to calculate for LLP thermal performance  
is shown below:  
For more information on board layout techniques, refer to  
Application Note 1187 “Leadless Leadframe Package  
(LLP).” The application note also discusses package han-  
dling, solder stencil, and assembly.  
By substituting 37˚C/W for θJA, 125˚C for TJ and 70˚C for TA,  
the maximum power dissipation allowed from the chip is  
1.48W. If VCHG-IN is at 5.0V and a 3.0V battery is being  
13  
www.national.com  
Physical Dimensions inches (millimeters) unless otherwise noted  
NS Package Number SDA14B  
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves  
the right at any time without notice to change said circuitry and specifications.  
For the most current product information visit us at www.national.com.  
LIFE SUPPORT POLICY  
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS  
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR  
CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the body, or  
(b) support or sustain life, and whose failure to perform when  
properly used in accordance with instructions for use  
provided in the labeling, can be reasonably expected to result  
in a significant injury to the user.  
2. A critical component is any component of a life support  
device or system whose failure to perform can be reasonably  
expected to cause the failure of the life support device or  
system, or to affect its safety or effectiveness.  
BANNED SUBSTANCE COMPLIANCE  
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship  
Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned  
Substances’’ as defined in CSP-9-111S2.  
National Semiconductor  
Americas Customer  
Support Center  
National Semiconductor  
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Fax: +49 (0) 180-530 85 86  
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