LP3964ESX-1.8 [NSC]

800mA Fast Ultra Low Dropout Linear Regulators; 800毫安快速超低压降线性稳压器


型号：	LP3964ESX-1.8
厂家：	National Semiconductor
描述：	800mA Fast Ultra Low Dropout Linear Regulators 800毫安快速超低压降线性稳压器稳压器
文件：	总20页 (文件大小：379K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

May 2000

LP3961/LP3964

800mA Fast Ultra Low Dropout Linear Regulators

General Description

Features

n Ultra low dropout voltage

n Low ground pin current

The LP3961/LP3964 series of fast ultra low-dropout linear

regulators operate from a +2.5V to +7.0V input supply. Wide

range of preset output voltage options are available. These

ultra low dropout linear regulators respond very fast to step

changes in load which makes them suitable for low voltage

microprocessor applications. The LP3961/LP3964 are de-

veloped on a CMOS process which allows low quiescent

current operation independent of output load current. This

CMOS process also allows the LP3961/LP3964 to operate

under extremely low dropout conditions.

n Load regulation of 0.02%

n 15µA quiescent current in shutdown mode

n Guaranteed output current of 0.8A DC

n Available in SOT-223,TO-263 and TO-220 packages

n Output voltage accuracy 1.5%

n Error flag indicates output status (LP3961)

n Sense option improves better load regulation (LP3964)

n Extremely low output capacitor requirements

n Overtemperature/overcurrent protection

Dropout Voltage: Ultra low dropout voltage; typically 24mV

at 80mA load current and 240mV at 800mA load current.

n −40˚C to +125˚C junction temperature range

Ground Pin Current: Typically 4mA at 800mA load current.

Shutdown Mode: Typically 15µA quiescent current when

the shutdown pin is pulled low.

Applications

n Microprocessor power supplies

n GTL, GTL+, BTL, and SSTL bus terminators

n Power supplies for DSPs

n SCSI terminator

Error Flag: Error flag goes low when the output voltage

drops 10% below nominal value (for LP3961).

SENSE: Sense pin improves regulation at remote loads.

(For LP3964)

n Post regulators

Precision Output Voltage: Multiple output voltage options

n High efficiency linear regulators

n Battery chargers

are available ranging from 1.2V to 5.0V and adjustable, with

a guaranteed accuracy of 1.5% at room temperature, and

3.0% over all conditions ( varying line, load, and tempera-

n Other battery powered applications

ture).

Typical Application Circuits

DS101129-1

# Minimum output capacitance is 10 µF to ensure stability over full load current range. More capacitance provides superior dynamic performance and additional

stability margin.

*SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this function is not used. See applications sec-

tion for more information.

DS101129

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Typical Application Circuits (Continued)

DS101129-2

# Minimum output capacitance is 10 µF to ensure stability over full load current range. More capacitance provides superior dynamic performance and additional sta-

bility margin.

*SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this function is not used. See applications section

for more information.

Block Diagram LP3961

DS101129-3

www.national.com

Block Diagram LP3964

DS101129-29

Block Diagram LP3964-ADJ

DS101129-30

Connection Diagrams

DS101129-4

Top View

SOT 223-5 Package

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Connection Diagrams (Continued)

DS101129-5

Top View

TO220-5 Package

Bent, Staggered Leads

DS101129-6

Top View

TO263-5 Package

Pin Description for SOT223-5 Package

LP3961

LP3964

Name

Function

Shutdown

Name

Function

Shutdown

V_IN

Input Supply

Output Voltage

ERROR Flag

Input Supply

V_OUT

ERROR

V_OUT

Output Voltage

SENSE/ADJ

Remote Sense Pin

or output Adjust Pin

GND

Ground

GND

Ground

Pin Description for TO220-5 and TO263-5 Packages

LP3961

LP3964

Name

Function

Shutdown

Name

Function

Shutdown

V_IN

Input Supply

Ground

V_IN

Input Supply

Ground

GND

V_OUT

ERROR

GND

Output Voltage

ERROR Flag

V_OUT

Output Voltage

SENSE/ADJ

Remote Sense Pin

or output Adjust Pin

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Ordering Information

DS101129-31

Package Type Designator is ″MP″ for SOT223 package, ″T″ for TO220 package, and ″S″ for TO263 package.

TABLE 1. Package Marking and Ordering Information

Output

Voltage

5.0

Order Number

LP3961EMP-5.0

Description

(Current, Option)

800mA, Error Flag

Package

Type

Package Marking

LBSB

Supplied As:

SOT223-5

1000 units on

Tape and Reel

5.0

3.3

2.5

1.8

5.0

3.3

2.5

1.8

ADJ

LP3961EMPX-5.0

LP3961EMP-3.3

LP3961EMPX-3.3

LP3961EMP-2.5

LP3961EMPX-2.5

LP3961EMP-1.8

LP3961EMPX-1.8

LP3964EMP-5.0

LP3964EMPX-5.0

LP3964EMP-3.3

LP3964EMPX-3.3

LP3964EMP-2.5

LP3964EMPX-2.5

LP3964EMP-1.8

LP3964EMPX-1.8

LP3964EMP-ADJ

800mA, Error Flag

800mA, SENSE

800mA, ADJ

SOT223-5

LBSB

LAZB

LBBB

LBAB

LBUB

LBJB

LBHB

LBFB

LBPB

2000 units on

Tape and Reel

1000 units on

Tape and Reel

2000 units on

Tape and Reel

1000 units on

Tape and Reel

2000 units on

Tape and Reel

1000 units on

Tape and Reel

2000 units on

Tape and Reel

1000 units on

Tape and Reel

2000 units on

Tape and Reel

1000 units on

Tape and Reel

2000 units on

Tape and Reel

1000 units on

Tape and Reel

2000 units on

Tape and Reel

1000 units on

Tape and Reel

2000 units on

Tape and Reel

1000 units on

Tape and Reel

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Ordering Information (Continued)

TABLE 1. Package Marking and Ordering Information (Continued)

Output

Voltage

ADJ

Order Number

Description

Package

Type

Package Marking

Supplied As:

(Current, Option)

LP3964EMPX-ADJ

800mA, ADJ

SOT223-5

LBPB

2000 units on

Tape and Reel

5.0

3.3

2.5

1.8

5.0

3.3

2.5

1.8

ADJ

5.0

3.3

2.5

1.8

5.0

3.3

2.5

1.8

ADJ

LP3961ES-5.0

LP3961ESX-5.0

LP3961ES-3.3

LP3961ESX-3.3

LP3961ES-2.5

LP3961ESX-2.5

LP3961ES-1.8

LP3961ESX-1.8

LP3964ES-5.0

LP3964ESX-5.0

LP3964ES-3.3

LP3964ESX-3.3

LP3964ES-2.5

LP3964ESX-2.5

LP3964ES-1.8

LP3964ESX-1.8

LP3964ES-ADJ

LP3964ESX-ADJ

LP3961ET-5.0

LP3961ET-3.3

LP3961ET-2.5

LP3961ET-1.8

LP3964ET-5.0

LP3964ET-3.3

LP3964ET-2.5

LP3964ET-1.8

LP3964ET-ADJ

800mA, Error Flag

800mA, SENSE

800mA, ADJ

TO263-5

TO220-5

LP3961ES-5.0

LP3961ESX-5.0

LP3961ES-3.3

LP3961ES-2.5

LP3961ES-1.8

LP3964ES-5.0

LP3964ES-3.3

LP3964ES-2.5

LP3964ES-1.8

LP3964ES-ADJ

LP3961ET-5.0

LP3961ET-3.3

LP3961ET-2.5

LP3961ET-1.8

LP3964ET-5.0

LP3964ET-3.3

LP3964ET-2.5

LP3964ET-1.8

LP3964ET-ADJ

Rail

Tape and Reel

Rail

Tape and Reel

Rail

Tape and Reel

Rail

Tape and Reel

Rail

Tape and Reel

Rail

Tape and Reel

Rail

Tape and Reel

Rail

Tape and Reel

Rail

800mA, ADJ

Tape and Reel

800mA, Error Flag

800mA, SENSE

800mA, ADJ

Rail

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

I_OUT(Survival)

Short Circuit Protected

V_IN+0.3V

Maximum Voltage for ERROR Pin

Maximum Voltage for SENSE Pin

V_OUT+0.3V

Operating Ratings

Storage Temperature Range

Lead Temperature

−65˚C to +150˚C

Input Supply Voltage (Operating)

2.5V to 7.0V

(Soldering, 5 sec.)

260˚C

2 kV

Shutdown Input Voltage

(Operating)

ESD Rating (Note 3)

−0.3V to V_IN+0.3V

Power Dissipation (Note 2)

Input Supply Voltage (Survival)

Shutdown Input Voltage (Survival)

Internally Limited

−0.3V to +7.5V

−0.3V to V_IN+0.3V

Maximum Operating Current

(DC)

0.8A

Operating Junction Temp. Range

−40˚C to +125˚C

Output Voltage (Survival), (Note

6), (Note 7)

−0.3V to +7.5V

Electrical Characteristics

LP3961/LP3964

Limits in standard typeface are for T_J= 25˚C, and limits in boldface type apply over the full operating temperature

range. Unless otherwise specified: V_IN= V_O(NOM)+ 1V, I_L= 10 mA, C_OUT=10µF, V_SD= V_IN-0.3V.

Symbol

Parameter

Conditions

Typ(Note

LP3961/4 (Note 5)

Units

Min

Max

V_OUT+1V V_IN7.0V

Output Voltage

Tolerance

(Note 8)

10 mA I_L800 mA

-1.5

-3.0

+1.5

+3.0

V_O

3.135 ≤ V_IN≤ 7.0 for

V_OUT= 2.5V

∆V _OL

Output Voltage Line

Regulation (Note 8)

V_OUT+1V V_IN7.0V,

0.02

0.06

∆V_O/

∆I_OUT

Output Voltage Load

Regulation

10 mA I_L800 mA

0.02

0.08

(Note 8)

V_IN

V_OUT

I_L= 80 mA

I_L= 800 mA

I_L= 80 mA

I_L= 800 mA

V_SD≤ 0.2V

240

Dropout Voltage

(Note 10)

300

350

Ground Pin Current In

Normal Operation

Mode

I_GND

µA

I_GND

Ground Pin Current In

Shutdown Mode

(Note 11)

I_O(PK)

Peak Output Current

(Note 2)

1.5

2.8

1.2

1.1

SHORT CIRCUIT PROTECTION

I_SCShort Circuit Current

OVER TEMPERATURE PROTECTION

Tsh(t)

Shutdown Threshold

165

˚C

Tsh(h)

Thermal Shutdown

Hysteresis

SHUTDOWN INPUT

Output = High

Output = Low

I_L= 800 mA

V_SD= V_IN

V_IN

V_IN–0.3

V_SDT

Shutdown Threshold

0.2

T_dOFF

T_dON

I_SD

Turn-off delay

Turn-on delay

SD Input Current

µs

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Electrical Characteristics

LP3961/LP3964 ^(Continued)

Limits in standard typeface are for T_J= 25˚C, and limits in boldface type apply over the full operating temperature

range. Unless otherwise specified: V_IN= V_O(NOM)+ 1V, I_L= 10 mA, C_OUT=10µF, V_SD= V_IN-0.3V.

Symbol

Parameter

Conditions

Typ(Note

LP3961/4 (Note 5)

Units

Min

Max

ERROR FLAG COMPARATOR

V_T

V_TH

V_EF(Sat)

Threshold

(Note 9)

Threshold Hysteresis

Error Flag Saturation

Flag Reset Delay

(Note 9)

I_sink= 100µA

0.02

0.1

µs

I_lk

Error Flag Pin Leakage

Current

I_max

Error Flag Pin Sink

Current

V_Error= 0.5V (over

temp.)

AC PARAMETERS

V_IN= V_OUT+ 1.5V

C_OUT= 100uF

V_OUT= 3.3V

PSRR

Ripple Rejection

µV

V_IN= V_OUT+ 0.3V

C_OUT= 100uF

V_OUT= 3.3V

ρ_n(l/f

Output Noise Density

f = 120Hz

0.8

150

100

BW = 10Hz – 100kHz

BW = 300Hz – 300kHz

Output Noise Voltage

(rms)

µV

(rms)

e_n

Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is in-

tended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions, see Electrical Charateristics. The guar-

anteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO220 package must be derated at θ = 50˚C/W

(with 0.5in , 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the TO263 surface-mount package must be derated at θ = 60˚C/W (with

0.5in , 1oz. copper area), junction-to-ambient. The devices in SOT223 package must be derated at θ = 90˚C/W (with 0.5in , 1oz. copper area), junction-to-ambient.

Note 3: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.

Note 4: Typical numbers are at 25˚C and represent the most likely parametric norm.

Note 5: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control

(SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

Note 6: If used in a dual-supply system where the regulator load is returned to a negative supply, the LP396X output must be diode-clamped to ground.

Note 7: The output PMOS structure contains a diode between the V and V

terminals. This diode is normally reverse biased. This diode will get forward biased

OUT

if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can typically withstand 200mA of DC current and 1Amp

of peak current.

Note 8: Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage. Output voltage load

regulation is defined as the change in output voltage from the nominal value due to change in load current. The line and load regulation specification contains only

the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification.

Note 9: Error Flag threshold and hysteresis are specified as percentage of regulated output voltage.

Note 10: Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. Dropout voltage speci-

fication applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is nothing but the input to output differential, since

the minimum input voltage is 2.5V.

Note 11: This specification has been tested for −40˚C ≤ T ≤ 85˚C since the temperature rise of the device is negligible under shutdown conditions.

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Typical Performance Characteristics Unless otherwise specified, V_IN=V_O(NOM)+ 1V, V_OUT= 2.5V,

C_OUT=10µF, I_OUT= 10mA, C_IN=10µF, V_SD= V_IN, and T_A= 25˚C.

Drop-Out Voltage Vs Temperature for Different Load

Drop-Out Voltage Vs Temperature for Different Output

Currents

Voltages (I_OUT= 800mA)

DS101129-9

DS101129-10

Ground Pin Current Vs Input Voltage (V_SD=V_IN

)

Ground Pin Current Vs Input Voltage (V_SD=100mV)

DS101129-11

DS101129-15

Ground Current Vs Temperature (V_SD=V_IN

)

Ground Current Vs Temperature (V_SD=0V

DS101129-18

DS101129-12

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Typical Performance Characteristics Unless otherwise specified, V_IN=V_O(NOM)+ 1V, V_OUT= 2.5V,

C_OUT=10µF, I_OUT= 10mA, C_IN=10µF, V_SD= V_IN, and T_A= 25˚C. (Continued)

Ground Pin Current Vs Shutdown Pin Voltage

Input Voltage Vs Output Voltage

DS101129-16

DS101129-17

Output Noise Density, V_OUT= 2.5V

Output Noise Density, V_OUT= 5V

DS101129-13

DS101129-14

www.national.com

quency component and a high frequency component, which

depend strongly on the silicon area and quiescent current.

Noise can be reduced in two ways: by increasing the transis-

tor area or by increasing the current drawn by the internal

reference. Increasing the area will decrease the chance of

fitting the die into a smaller package. Increasing the current

drawn by the internal reference increases the total supply

current (ground pin current). Using an optimized trade-off of

ground pin current and die size, LP3961/LP3964 achieves

low noise performance and low quiescent current operation.

Applications Information

Input Capacitor Selection

The LP3961 and LP3964 require a minimum input capaci-

tance of 10µF between the input and ground pins to prevent

any impedance interactions with the supply. This capacitor

should be located very close to the V_INpin. This capacitor

can be of any type such as ceramic, tantalum, or aluminium.

Any good quality capacitor which has good tolerance over

temperature and frequency is recommended.

The total output noise specification for LP3961/LP3964 is

presented in the Electrical Characteristics table. The Output

noise density at different frequencies is represented by a

curve under typical performance characteristics.

Output Capacitor Selection

The LP3961 and LP3964 require a minimum of 10µF capaci-

tance between the output and ground pins for proper opera-

tion. LP3961 and LP3964 work best with Tantalum or Elec-

trolytic capacitor. The output capacitor should have a good

tolerance over temperature, voltage, and frequency. Larger

capacitance provides better improved load dynamics and

noise performance. The output capacitor should be con-

nected very close to the Vout pin.

Short-Circuit Protection

The LP3961and LP3964 is short circuit protected and in the

event of a peak over-current condition, the short-circuit con-

trol loop will rapidly drive the output PMOS pass element off.

Once the power pass element shuts down, the control loop

will rapidly cycle the output on and off until the average

power dissipation causes the thermal shutdown circuit to re-

spond to servo the on/off cycling to a lower frequency.

Please refer to the section on thermal information for power

dissipation calculations.

Output Adjustment

An adjustable output device has output voltage range of

1.215V to 5.1V. To obtain a desired output voltage, the fol-

lowing equation can be used with R1 always a 10kΩ resistor.

Error Flag Operation

The LP3961/LP3964 produces a logic low signal at the Error

Flag pin when the output drops out of regulation due to low

input voltage, current limiting, or thermal limiting. This flag

has a built in hysteresis. The timing diagram in Figure 1

shows the relationship between the ERROR and the output

voltage. In this example, the input voltage is changed to

demonstrate the functionality of the Error Flag.

For output stability, C_Fmust be between 68pF and 100pF.

Output Noise

Noise is specified in two ways-

Spot Noise or Output noise density is the RMS sum of all

noise sources, measured at the regulator output, at a spe-

cific frequency (measured with a 1Hz bandwidth). This type

of noise is usually plotted on a curve as a function of fre-

quency.

The internal Error flag comparator has an open drain output

stage. Hence, the ERROR pin should be pulled high through

a pull up resistor. Although the ERROR pin can sink current

of 1mA, this current is energy drain from the input supply.

Hence, the value of the pull up resistor should be in the

range of 100kΩ to 1MΩ. The ERROR pin must be con-

nected to ground if this function is not used. It should

also be noted that when the shutdown pin is pulled low, the

ERROR pin is forced to be invalid for reasons of saving

power in shutdown mode.

Total output Noise or Broad-band noise is the RMS sum

of spot noise over a specified bandwidth, usually several de-

cades of frequencies.

Attention should be paid to the units of measurement. Spot

√

noise is measured in units µV/ Hz or nV/ Hz and total output

noise is measured in µV(rms).

The primary source of noise in low-dropout regulators is the

internal reference. In CMOS regulators, noise has a low fre-

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Applications Information (Continued)

DS101129-7

FIGURE 1. Error Flag Operation

Sense Pin

tance. For example, in the case of a 3.3V output, if the trace

resistance is 100mΩ, the voltage at the remote load will be

3.22V with 800mAmps of load current, I_LOAD. The LP3964

regulates the voltage at the sense pin. Connecting the sense

pin to the remote load will provide regulation at the remote

load, as shown in Figure 2. If the sense option pin is not re-

quired, the sense pin must be connected to the V_OUTpin.

In applications where the regulator output is not very close to

the load, LP3964 can provide better remote load regulation

using the SENSE pin. Figure 2 depicts the advantage of the

SENSE option. LP3961 regulates the voltage at the output

pin. Hence, the voltage at the remote load will be the regula-

tor output voltage minus the drop across the trace resis-

DS101129-8

FIGURE 2. Improving remote load regulation using LP3964

Shutdown Operation

pin is driven from a source that actively pulls high and low

(such as a CMOS rail to rail comparator), the pull-up resistor

is not required. This pin must be tied to Vin if not used.

A CMOS Logic level signal at the shutdown ( SD) pin will

turn-off the regulator. Pin SD must be actively terminated

through a 10kΩ pull-up resistor for a proper operation. If this

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pends on method of attachment, insulator, etc. θ_CHvaries

between 1.5˚C/W to 2.5˚C/W. If the exact value is unknown,

2˚C/W can be assumed.

Applications Information (Continued)

Dropout Voltage

The dropout voltage of a regulator is defined as the minimum

input-to-output differential required to stay within 2% of the

output voltage. The LP3961/LP3964 use an internal MOS-

FET with an Rds(on) of 240mΩ (typically). For CMOS LDOs,

the dropout voltage is the product of the load current and the

Rds(on) of the internal MOSFET.

Heatsinking TO-263 and SOT-223 Packages

The TO-263 and SOT223 packages use the copper plane on

the PCB as a heatsink. The tab of these packages are sol-

dered to the copper plane for heat sinking. Figure 3 shows a

curve for the θ_JAof TO-263 package for different copper area

sizes, using a typical PCB with 1 ounce copper and no solder

mask over the copper area for heat sinking.

Reverse Current Path

The internal MOSFET in LP3961and LP3964 has an inher-

ent parasitic diode. During normal operation, the input volt-

age is higher than the output voltage and the parasitic diode

is reverse biased. However, if the output is pulled above the

input in an application, then current flows from the output to

the input as the parasitic diode gets forward biased. The out-

put can be pulled above the input as long as the current in

the parasitic diode is limited to 200mA continuous and 1A

peak.

Maximum Output Current Capability

LP3961 and LP3964 can deliver a continuous current of

800mA over the full operating temperature range. A heatsink

may be required depending on the maximum power dissipa-

tion and maximum ambient temperature of the application.

Under all possible conditions, the junction temperature must

be within the range specified under operating conditions.

The total power dissipation of the device is given by:

DS101129-32

FIGURE 3. θ_JAvs Copper(1 Ounce) Area for TO-263

package

P_D= (V_IN−V_OUT)I_OUT+ (V_IN)I_GND

where I_GNDis the operating ground current of the device

(specified under Electrical Characteristics).

As shown in the figure, increasing the copper area beyond 1

square inch produces very little improvement. The minimum

value for θ_JAfor the TO-263 packag mounted to a PCB is

32˚C/W.

The maximum allowable temperature rise (T_Rmax) depends

on the maximum ambient temperature (T_Amax) of the appli-

cation, and the maximum allowable junction temperature(T_J

^max):

Figure 4 shows the maximum allowable power dissipation

for TO-263 packages for different ambient temperatures, as-

suming θ_JAis 35˚C/W and the maximum junction tempera-

ture is 125˚C.

T_Rmax= T_Jmax− T_Amax

The maximum allowable value for junction to ambient Ther-

mal Resistance, θ_JA, can be calculated using the formula:

θ_JA= T_Rmax/ P_D

LP3961 and LP3964 are available in TO-220, TO-263, and

SOT-223 packages. The thermal resistance depends on

amount of copper area or heat sink, and on air flow. If the

maximum allowable value of θ_JAcalculated above is ≥ 60

˚C/W for TO-220 package, ≥60 ˚C/W for TO-263 package,

and ≥ 140 ˚C/W for SOT-223 package, no heatsink is

needed since the package can dissipate enough heat to sat-

isfy these requirements. If the value for allowable θ_JAfalls

below these limits, a heat sink is required.

Heatsinking TO-220 Packages

The thermal resistance of a TO220 package can be reduced

by attaching it to a heat sink or a copper plane on a PC

board. If a copper plane is to be used, the values of θ_JAwill

be same as shown in next section for TO263 package.

DS101129-33

FIGURE 4. Maximum power dissipation vs ambient

temperature for TO-263 package

The heatsink to be used in the application should have a

heatsink to ambient thermal resistance,

Figure 5 shows a curve for the θ_JAof SOT-223 package for

different copper area sizes, using a typical PCB with 1 ounce

copper and no solder mask over the copper area for heat

sinking.

_HA≤ θ_JA− θ_CH− θ_JC.

In this equation, θ_CHis the thermal resistance from the junc-

tion to the surface of the heat sink and θ_JCis the thermal re-

sistance from the junction to the surface of the case. θ_JCis

about 3˚C/W for a TO220 package. The value for θ_CHde-

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Applications Information (Continued)

DS101129-19

FIGURE 5. θ_JAvs Copper(1 Ounce) Area for SOT-223

package

The following figures show different layout scenarios for

SOT-223 package.

DS101129-22

FIGURE 8. SCENARIO C, θ_JA= 92˚C/W

DS101129-20

FIGURE 6. SCENARIO A, θ_JA= 148˚C/W

DS101129-21

FIGURE 7. SCENARIO B, θ_JA= 125˚C/W

DS101129-23

FIGURE 9. SCENARIO D, θ_JA= 83˚C/W

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Applications Information (Continued)

DS101129-25

DS101129-24

FIGURE 11. SCENARIO F, θ_JA= 75˚C/W

FIGURE 10. SCENARIO E, θ_JA= 77˚C/W

DS101129-26

FIGURE 12. SCENARIO G, θ_JA= 113˚C/W

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Applications Information (Continued)

DS101129-27

FIGURE 13. SCENARIO H, θ_JA= 79˚C/W

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Applications Information (Continued)

DS101129-28

FIGURE 14. SCENARIO I, θ_JA= 78.5˚C/W

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Physical Dimensions inches (millimeters) unless otherwise noted

TO220 5-lead, Molded, Stagger Bend Package (TO220-5)

NS Package Number T05D

For Order Numbers, refer to the “Ordering Information” section of this document.

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Physical Dimensions inches (millimeters) unless otherwise noted

TO263 5-Lead, Molded, Surface Mount Package (TO263-5)

NS Package Number TS5B

For Order Numbers, refer to the “Ordering Information” section of this document.

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Physical Dimensions inches (millimeters) unless otherwise noted

SOT223, 5-Lead, Molded, Surface Mount Package (SOT223-5)

NS Package Number MA05C

For Order Numbers, refer to the “Ordering Information” section of this document.

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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

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Tel: 1-800-272-9959

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Email: support@nsc.com

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

LP3964ESX-1.8 [NSC]

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