LP3996SDX-3308 [NSC]

Dual Linear Regulator with 300mA and 150mA Outputs and Power-On-Reset; 双路线性稳压300毫安到150mA输出和上电复位


型号：	LP3996SDX-3308
厂家：	National Semiconductor
描述：	Dual Linear Regulator with 300mA and 150mA Outputs and Power-On-Reset 双路线性稳压300毫安到150mA输出和上电复位
文件：	总16页 (文件大小：877K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

November 2006

LP3996

Dual Linear Regulator with 300mA and 150mA Outputs

and Power-On-Reset

General Description

Key Specifications

n Input Voltage Range

2.0V to 6.0V

210mV at 300mA

35µA

The LP3996 is a dual low dropout regulator with power-on-

reset circuit. The first regulator can source 150mA, while the

second is capable of sourcing 300mA and has a power-on-

reset function included.

n Low Dropout Voltage

n Ultra-Low I_Q(enabled)

n Virtually Zero I_Q(disabled)

10nA

The LP3996 provides 1.5% accuracy requiring an ultra low

quiescent current of 35µA. Separate enable pins allow each

output of the LP3996 to be shut down, drawing virtually zero

current.

Package

All available in Lead Free option.

The LP3996 is designed to be stable with small footprint

ceramic capacitors down to 1µF. An external capacitor may

be used to set the POR delay time as required.

10 pin LLP 3mm x 3mm

For other package options contact your NSC sales office.

The LP3996 is available in fixed output voltages and comes

in a 10 pin, 3mm x 3mm, LLP package. .

Applications

n Cellular Handsets

n PDA’s

Features

n Wireless Network Adaptors

n 2 LDO Outputs with Independent Enable

n 1.5% Accuracy at Room Temperature, 3% over

Temperature

n Power-On-Reset Function with Adjustable Delay

n Thermal Shutdown Protection

n Stable with Ceramic Capacitors

Typical Application Circuit

20145801

DS201458

www.national.com

Functional Block Diagram

20145806

Pin Descriptions

LLP-10 Package

Name and Function

Pin No

Symbol

V_IN

Voltage Supply Input. Connect a 1µF capacitor between this

pin and GND.

EN1

EN2

C_BYP

Enable Input to Regulator 1. Active high input.

High = On. Low = OFF.

Enable Input to Regulator 2. Active high input.

High = On. Low = OFF.

Internal Voltage Reference Bypass. Connect a 10nF capacitor

from this pin to GND to reduce output noise and improve line

transient and PSRR.

This pin may be left open.

SET

Set Delay Input. Connect a capacitor between this pin and

GND to set the POR delay time. If left open, there will be no

delay.

GND

N/C

Common Ground pin. Connect externally to exposed pad.

No Connection. Do not connect to any other pin.

Power-On Reset Output. Open drain output. Active low

indicates under-voltage output on Regulator 2. A pull-up

resistor is required for correct operation.

POR

V_OUT2Output of Regulator 2. 300mA maximum current output.

Connect a 1µF capacitor between this pin and GND.

V_OUT1Output of Regulator 1. 150mA maximum current output.

Connect a 1µF capacitor between this pin and GND.

Pad

GND

Common Ground. Connect to Pin 6.

www.national.com

Connection Diagram

LLP-10 Package

20145803

See NS package number SDA10A

www.national.com

Ordering Information (LLP-10)

For other voltage options, please contact your local NSC sales office

Output

Package

Marking

L167B

Order Number

Spec

Voltage (V)

Supplied As

0.8 / 3.3

LP3996SD-0833

NOPB

1000 Units, Tape-and-Reel

4500 Units, Tape-and-Reel

1000 Units, Tape-and-Reel

4500 Units, Tape-and-Reel

1000 Units, Tape-and-Reel

4500 Units, Tape-and-Reel

1000 Units, Tape-and-Reel

4500 Units, Tape-and-Reel

1000 Units, Tape-and-Reel

4500 Units, Tape-and-Reel

1000 Units, Tape-and-Reel

4500 Units, Tape-and-Reel

1000 Units, Tape-and-Reel

4500 Units, Tape-and-Reel

1000 Units, Tape-and-Reel

4500 Units, Tape-and-Reel

1000 Units, Tape-and-Reel

4500 Units, Tape-and-Reel

1000 Units, Tape-and-Reel

4500 Units, Tape-and-Reel

1000 Units, Tape-and-Reel

4500 Units, Tape-and-Reel

1000 Units, Tape-and-Reel

4500 Units, Tape-and-Reel

1000 Units, Tape-and-Reel

4500 Units, Tape-and-Reel

1000 Units, Tape-and-Reel

4500 Units, Tape-and-Reel

LP3996SDX-0833

LP3996SD-0833

LP3996SDX-0833

LP3996SD-1525

LP3996SDX-1525

LP3996SD-1525

LP3996SDX-1525

LP3996SD-2828

LP3996SDX-2828

LP3996SD-2828

LP3996SDX-2828

LP3996SD-3030

LP3996SDX-3030

LP3996SD-3030

LP3996SDX-3030

LP3996SD-3033

LP3996SDX-3033

LP3996SD-3033

LP3996SDX-3033

LP3996SD-3308

LP3996SDX-3308

LP3996SD-3308

LP3996SDX-3308

LP3996SD-3333

LP3996SDX-3333

LP3996SD-3333

LP3996SDX-3333

1.5 / 2.5

2.8 / 2.8

3.0 / 3.0

3.0 / 3.3

3.3 / 0.8

3.3 / 3.3

NOPB

L168B

L171B

L172B

L170B

L188B

L173B

NOPB

www.national.com

Absolute Maximum Ratings

(Notes 1, 2)

Operating Ratings(Notes 1, 2)

Input Voltage

2.0V to 6.0V

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

EN1, EN2, POR Voltage

0 to (V_IN+ 0.3V) to

6.0V (max)

Junction Temperature

Ambient Temperature T_ARange

(Note 6)

-40˚C to 125˚C

-40˚C to 85˚C

Input Voltage to GND

_OUT1, V_OUT2EN1 and EN2

-0.3V to 6.5V

-0.3V to (V_IN+ 0.3V) with

6.5V (max)

Voltage to GND

POR to GND

-0.3V to 6.5V

Thermal Properties(Note 1)

Junction To Ambient Thermal

Resistance(Note 7)

Junction Temperature (T_J-MAX

Lead/Pad Temp. (Note 3)

Storage Temperature

)

150˚C

235˚C

-65˚C to 150˚C

_JALLP-10 Package

55˚C/W

Continuous Power Dissipation

Internally Limited(Note 4)

ESD Rating(Note 5)

Human Body Model

2.0kV

200V

Machine Model

Electrical Characteristics(Notes 2, 8)

Unless otherwise noted, V_EN= 950mV, V_IN= V_OUT+ 1.0V, or 2.0V, whichever is higher, where V_OUTis the higher of V_OUT1

and V_OUT2. C_IN= 1 µF, I_OUT= 1 mA, C_OUT1= C_OUT2= 1.0µF. Typical values and limits appearing in normal type apply for T_A

= 25˚C. Limits appearing in boldface type apply over the full junction temperature range for operation, −40 to +125˚C.

Limit

Symbol

V_IN

Parameter

Input Voltage

Conditions

Typ

Units

Min

Max

(Note 9)

∆V_OUT

Output Voltage Tolerance

I_OUT= 1mA

1.5V V_OUT≤ 3.3V

-2.5

-3.75

-2.75

-4

+2.5

+3.75

+2.75

V_OUT≤ 1.5V

Line Regulation Error

Load Regulation Error

V_IN= (V_OUT(NOM)+ 1.0V) to 6.0V

I_OUT= 1mA to 150mA

(LDO 1)

0.03

0.3

%/V

155

µV/mA

I_OUT= 1mA to 300mA

(LDO 2)

110

210

V_DO

Dropout Voltage

(Note 10)

I_OUT= 1mA to 150mA

(LDO 1)

220

550

100

110

170

µA

I_OUT= 1mA to 300mA

(LDO 2)

I_Q

Quiescent Current

LDO 1 ON, LDO 2 ON

I_OUT1= I_OUT2= 0mA

LDO 1 ON, LDO 2 OFF

I_OUT1= 150mA

LDO 1 OFF, LDO 2 ON

I_OUT2= 300mA

LDO 1 ON, LDO 2 ON

I_OUT1= 150mA, I_OUT2= 300mA

V_EN1= V_EN2= 0.4V

LDO 1

0.5

420

550

I_SC

Short Circuit Current Limit

Maximum Output Current

750

840

LDO 2

I_OUT

LDO 1

150

300

LDO 2

www.national.com

Electrical Characteristics(Notes 2, 8) (Continued)

Unless otherwise noted, V_EN= 950mV, V_IN= V_OUT+ 1.0V, or 2.0V, whichever is higher, where V_OUTis the higher of V_OUT1

and V_OUT2. C_IN= 1 µF, I_OUT= 1 mA, C_OUT1= C_OUT2= 1.0µF. Typical values and limits appearing in normal type apply for T_A

= 25˚C. Limits appearing in boldface type apply over the full junction temperature range for operation, −40 to +125˚C.

Limit

Symbol

PSRR

Parameter

Conditions

Typ

Units

Min

Max

Power Supply Rejection Ratio

(Note 11)

f = 1kHz, I_OUTLDO1

= 1mA to

150mA

LDO2

C_BYP= 10nF

f = 20kHz, I_OUTLDO1

= 1mA to

150mA

LDO2

C_BYP= 10nF

e_n

Output noise Voltage (Note 11)

BW = 10Hz to V_OUT= 0.8V

100kHz

µV_RMS

V_OUT= 3.3V

C_BYP= 10nF

T_SHUTDOWNThermal Shutdown

Temperature

Hysteresis

160

˚C

Enable Control Characteristics

I_EN

V_IL

V_IH

Input Current at V_EN1or V_EN2

V_EN= 0.0V

V_EN= 6V

0.005

0.1

µA

Low Input Threshold at V_EN1or

0.4

V_EN2

High Input Threshold at V_EN1or

V_EN2

0.95

POR Output Characteristics

V_TH

Low Threshold % 0f V_{OUT2 (NOM)}Flag ON

High Threshold % 0f V_OUT2

Flag OFF

(NOM)

I_POR

V_OL

Leakage Current

Flag OFF, V_POR= 6.5V

I_SINK= 250µA

Flag Output Low Voltage

Timing Characteristics

T_ON

Turn On Time (Note 11)

To 95% Level

C_BYP= 10nF

300

µs

Transient

Response

Line Transient Response |δV_OUT| T_rise= T_fall= 10µs

(Note 11)

δV_IN= 1VC_BYP= 10nF

Load Transient Response

T_rise= T_fall

1µs

LDO 1

|δV_OUT

I_OUT= 1mA to

150mA

175

150

(Note 11)

(pk - pk)

LDO 2

I_OUT= 1mA to

300mA

SET Input Characteristics

I_SET

SET Pin Current Source

SET Pin Threshold Voltage

V_SET= 0V

1.3

µA

V_TH(SET)

POR = High

1.25

www.national.com

Electrical Characteristics(Notes 2, 8) (Continued)

Note 1: Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the device is

guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical

Characteristics tables.

Note 2: All Voltages are with respect to the potential at the GND pin.

Note 3: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN-1187, Leadless Leadframe Package.

Note 4: Internal thermal shutdown circuitry protects the device from permanent damage.

Note 5: The human body model is 100pF discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into each

pin.

Note 6: The maximum ambient temperature (T

) is dependant on the maximum operating junction temperature (T

= 125˚C), the maximum power

A(max)

J(max-op)

dissipation of the device in the application (P

), and the junction to ambient thermal resistance of the part/package in the application (θ ), as given by the

D(max)

following equation: T

= T

- (θ x P

A(max)

J(max-op)

D(max)

Note 7: Junction to ambient thermal resistance is dependant on the application and board layout. In applications where high maximum power dissipation is possible,

special care must be paid to thermal dissipation issues in board design.

Note 8: Min Max limits are guaranteed by design, test or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.

Note 9: V

= V

+ 0.5V, or 2.0V, whichever is higher.

OUT(NOM)

IN(MIN)

Note 10: Dropout voltage is voltage difference between input and output at which the output voltage drops to 100mV below its nominal value. This parameter only

for output voltages above 2.0V

Note 11: This electrical specification is guaranteed by design.

Output Capacitor, Recommended Specifications

Limit

Symbol

C_OUT

Parameter

Conditions

Nom

1.0

Units

Min

0.7

Max

Output Capacitance

Capacitance

(Note 12)

ESR

µF

500

mΩ

Note 12: The Capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be considered when selecting

a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended capacitor is X7R. However, depending on the application, X5R,

Y5V and Z5U can also be used. (See capacitor section in Applications Hints).

Transient Test Conditions

20145808

FIGURE 1. PSRR Input Signal

www.national.com

Transient Test Conditions (Continued)

20145804

FIGURE 2. Line Transient Input Test Signal

20145805

FIGURE 3. Load Transient Input Signal

www.national.com

Typical Performance Characteristics. Unless otherwise specified, C_IN= 1.0µF Ceramic, C_OUT1

C_OUT2= 1.0µF Ceramic, C_BYP= 10nF, V_IN= V_OUT2(NOM)+ 1.0V, T_A= 25˚C, V_OUT1(NOM)= 3.3V, V_OUT2(NOM)= 3.3V, Enable

pins are tied to V_IN

Output Voltage Change vs Temperature

Ground Current vs Load Current, LDO1

20145810

20145813

Ground Current vs Load Current, LDO2

Ground Current vs V_IN. I_LOAD= 1mA

20145814

20145815

Dropout Voltage vs I_LOAD, LDO1

Dropout Voltage vs I_LOAD, LDO2

20145811

20145812

www.national.com

Typical Performance Characteristics. Unless otherwise specified, C_IN= 1.0µF Ceramic, C_OUT1

C_OUT2= 1.0µF Ceramic, C_BYP= 10nF, V_IN= V_OUT2(NOM)+ 1.0V, T_A= 25˚C, V_OUT1(NOM)= 3.3V, V_OUT2(NOM)= 3.3V, Enable

pins are tied to V_IN. (Continued)

Short Circuit Current, LDO1

Short Circuit Current, LDO2

20145852

20145853

Power Supply Rejection Ratio, LDO1

Power Supply Rejection Ratio, LDO2

20145855

20145854

Enable Start-up Time, C_BYP=0

Enable Start-up Time, C_BYP=10nF

20145860

20145861

www.national.com

Typical Performance Characteristics. Unless otherwise specified, C_IN= 1.0µF Ceramic, C_OUT1

C_OUT2= 1.0µF Ceramic, C_BYP= 10nF, V_IN= V_OUT2(NOM)+ 1.0V, T_A= 25˚C, V_OUT1(NOM)= 3.3V, V_OUT2(NOM)= 3.3V, Enable

pins are tied to V_IN. (Continued)

Line Transient, C_BYP=10nF

Load Transient, LDO1

Noise Density LDO1

Line Transient, C_BYP=0

Load Transient, LDO2

Noise Density, LDO2

20145820

20145819

20145851

20145850

20145857

20145856

www.national.com

Typical Performance Characteristics. Unless otherwise specified, C_IN= 1.0µF Ceramic, C_OUT1

C_OUT2= 1.0µF Ceramic, C_BYP= 10nF, V_IN= V_OUT2(NOM)+ 1.0V, T_A= 25˚C, V_OUT1(NOM)= 3.3V, V_OUT2(NOM)= 3.3V, Enable

pins are tied to V_IN. (Continued)

Power-on-Reset Start-up Operation

Power-on-Reset Shutdown Operation

20145817

20145816

POR Delay Time

20145818

www.national.com

high frequency noise. The ESR of a typical 1.0µF ceramic

capacitor is in the range of 20mΩ to 40mΩ, which easily

meets the ESR requirement for stability for the LP3996.

Application Hints

OPERATION DESCRIPTION

For both input and output capacitors, careful interpretation of

the capacitor specification is required to ensure correct de-

vice operation. The capacitor value can change greatly, de-

pending on the operating conditions and capacitor type.

The LP3996 is a low quiescent current, power management

IC, designed specifically for portable applications requiring

minimum board space and smallest components. The

LP3996 contains two independently selectable LDOs. The

first is capable of sourcing 150mA at outputs between 0.8V

and 3.3V. The second can source 300mA at an output volt-

age of 0.8V to 3.3V. In addition, LDO2 contains power good

flag circuit, which monitors the output voltage and indicates

when it is within 8% of its nominal value. The flag will also act

as a power-on-reset signal and, by adding an external ca-

pacitor; a delay may be programmed for the POR output.

In particular, the output capacitor selection should take ac-

count of all the capacitor parameters, to ensure that the

specification is met within the application. The capacitance

can vary with DC bias conditions as well as temperature and

frequency of operation. Capacitor values will also show

some decrease over time due to aging. The capacitor pa-

rameters are also dependant on the particular case size,

with smaller sizes giving poorer performance figures in gen-

eral. As an example, Figure 4 shows a typical graph com-

paring different capacitor case sizes in a Capacitance vs. DC

Bias plot. As shown in the graph, increasing the DC Bias

condition can result in the capacitance value falling below

the minimum value given in the recommended capacitor

specifications table (0.7µF in this case). Note that the graph

shows the capacitance out of spec for the 0402 case size

capacitor at higher bias voltages. It is therefore recom-

mended that the capacitor manufacturers’ specifications for

the nominal value capacitor are consulted for all conditions,

as some capacitor sizes (e.g. 0402) may not be suitable in

the actual application.

INPUT CAPACITOR

An input capacitor is required for stability. It is recommended

that a 1.0µF capacitor be connected between the LP3996

input pin and ground (this capacitance value may be in-

creased without limit).

This capacitor must be located a distance of not more than

1cm from the input pin and returned to a clean analogue

ground. Any good quality ceramic, tantalum, or film capacitor

may be used at the input.

Important: Tantalum capacitors can suffer catastrophic fail-

ures due to surge current when connected to a low-

impedance source of power (like a battery or a very large

capacitor). If a tantalum capacitor is used at the input, it must

be guaranteed by the manufacturer to have a surge current

rating sufficient for the application.

There are no requirements for the ESR (Equivalent Series

Resistance) on the input capacitor, but tolerance and tem-

perature coefficient must be considered when selecting the

capacitor to ensure the capacitance will remain approxi-

mately 1.0µF over the entire operating temperature range.

OUTPUT CAPACITOR

The LP3996 is designed specifically to work with very small

ceramic output capacitors. A 1.0µF ceramic capacitor (tem-

perature types Z5U, Y5V or X7R) with ESR between 5mΩ to

500mΩ, is suitable in the LP3996 application circuit.

For this device the output capacitor should be connected

between the V_OUTpin and ground.

It is also possible to use tantalum or film capacitors at the

device output, C_OUT(or V_OUT), but these are not as attrac-

tive for reasons of size and cost (see the section Capacitor

Characteristics).

20145840

FIGURE 4. Graph Showing a Typical Variation in

Capacitance vs DC Bias

The output capacitor must meet the requirement for the

minimum value of capacitance and also have an ESR value

that is within the range 5mΩ to 500mΩ for stability.

The ceramic capacitor’s capacitance can vary with tempera-

ture. The capacitor type X7R, which operates over a tem-

perature range of -55˚C to +125˚C, will only vary the capaci-

tance to within 15%. The capacitor type X5R has a similar

tolerance over a reduced temperature range of -55˚C to

+85˚C. Many large value ceramic capacitors, larger than 1µF

are manufactured with Z5U or Y5V temperature characteris-

tics. Their capacitance can drop by more than 50% as the

temperature varies from 25˚C to 85˚C. Therefore X7R is

recommended over Z5U and Y5V in applications where the

ambient temperature will change significantly above or be-

low 25˚C.

NO-LOAD STABILITY

The LP3996 will remain stable and in regulation with no

external load. This is an important consideration in some

circuits, for example CMOS RAM keep-alive applications.

CAPACITOR CHARACTERISTICS

The LP3996 is designed to work with ceramic capacitors on

the output to take advantage of the benefits they offer. For

capacitance values in the range of 0.47µF to 4.7µF, ceramic

capacitors are the smallest, least expensive and have the

lowest ESR values, thus making them best for eliminating

Tantalum capacitors are less desirable than ceramic for use

as output capacitors because they are more expensive when

comparing equivalent capacitance and voltage ratings in the

0.47µF to 4.7µF range.

www.national.com

The duration of the delay is determined by the time to charge

the delay capacitor to a threshold voltage of 1.25V at 1.2µA

from the SET pin as in the formula below.

Application Hints (Continued)

Another important consideration is that tantalum capacitors

have higher ESR values than equivalent size ceramics. This

means that while it may be possible to find a tantalum

capacitor with an ESR value within the stable range, it would

have to be larger in capacitance (which means bigger and

more costly) than a ceramic capacitor with the same ESR

value. It should also be noted that the ESR of a typical

tantalum will increase about 2:1 as the temperature goes

from 25˚C down to -40˚C, so some guard band must be

allowed.

20145841

A 0.1µF capacitor will introduce a delay of approximately

100ms.

BYPASS CAPACITOR

The internal voltage reference circuit of the LP3996 is con-

nected to the C_BYPpin via a high value internal resistor. An

external capacitor, connected to this pin, forms a low-pass

filter which reduces the noise level on both outputs of the

device. There is also some improvement in PSSR and line

transient performance. Internal circuitry ensures rapid charg-

ing of the C_BYPcapacitor during start-up. A 10nF, high quality

ceramic capacitor with either NPO or COG dielectric is rec-

ommended due to their low leakage characteristics and low

noise performance.

ENABLE CONTROL

The LP3996 features active high enable pins for each regu-

lator, EN1 and EN2, which turns the corresponding LDO off

when pulled low. The device outputs are enabled when the

enable lines are set to high. When not enabled the regulator

output is off and the device typically consumes 2nA.

If the application does not require the Enable switching

feature, one or both enable pins should be tied to V_INto keep

the regulator output permanently on.

To ensure proper operation, the signal source used to drive

the enable inputs must be able to swing above and below the

specified turn-on / off voltage thresholds listed in the Electri-

SAFE AREA OF OPERATION

Due consideration should be given to operating conditions to

avoid excessive thermal dissipation of the LP3996 or trigger-

ing its thermal shutdown circuit. When both outputs are

cal Characteristics section under V_ILand V_IH

POWER-ON-RESET

enabled,

the

total

power

dissipation

will

The POR pin is an open-drain output which will be set to Low

whenever the output of LDO2 falls out of regulation to ap-

proximately 90% of its nominal value. An external pull-up

resistor, connected to V_OUTor V_IN, is required on this pin.

During start-up, or whenever a fault condition is removed,

the POR flag will return to the High state after the output

reaches approximately 96% of its nominal value. By con-

necting a capacitor from the SET pin to GND, a delay to the

rising condition of the POR flag may be introduced. The

delayed signal may then be used as a Power-on -Reset for a

microprocessor within the user’s application.

P_D(LDO1)+ P_D(LDO2)Where P_D= (V_IN- V_OUT) x I_OUTfor each

LDO.

In general, device options which have a large difference in

output voltage will dissipate more power when both outputs

are enabled, due to the input voltage required for the higher

output voltage LDO. In such cases, especially at elevated

ambient temperature, it may not be possible to operate both

outputs at maximum current at the same time.

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

LLP, 10 Lead, Package

NS Package Number SDA10A

www.national.com

THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION

(″NATIONAL″) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR

COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO

SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED,

ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.

TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT

NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL

PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS

ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING

NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS,

BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.

EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO

LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR

USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL

OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose

failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in

a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be

reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

National Semiconductor and the National Semiconductor logo are trademarks or registered trademarks of National Semiconductor

Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders.

For the most current product information visit us at www.national.com.

National Semiconductor

Americas Customer

Support Center

National Semiconductor

Europe Customer Support Center

Fax: +49 (0) 180-530 85 86

National Semiconductor

Asia Pacific Customer

Support Center

National Semiconductor

Japan Customer Support Center

Fax: 81-3-5639-7507

Email: new.feedback@nsc.com

Tel: 1-800-272-9959

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 8790

Email: ap.support@nsc.com

Email: jpn.feedback@nsc.com

Tel: 81-3-5639-7560

www.national.com

LP3996SDX-3308 [NSC]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E