MM54C165W [NSC]
IC,SHIFT REGISTER,CMOS,FP,16PIN,CERAMIC;
| 型号： | MM54C165W |
| 厂家： | 
National Semiconductor |
| 描述： | IC,SHIFT REGISTER,CMOS,FP,16PIN,CERAMIC 移位寄存器 |
| 文件： | 总6页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 1992
MM54C165/MM74C165
Parallel-Load 8-Bit Shift Register
General Description
Features
Wide supply voltage range
Guaranteed noise margin
High noise immunity
Y
Y
Y
Y
3V to 15V
1V
The MM54C165/MM74C165 functions as an 8-bit parallel-
load, serial shift register. Data is loaded into the register
independent of the state of the clock(s) when PARALLEL
LOAD (PL) is low. Shifting is inhibited as long as PL is low.
0.45 V
CC
(typ.)
Low power TTL compatibility
fan out of 2
driving 74L
Data is sequentially shifted from complementary outputs, Q
7
and Q , highest-order bit (P7) first. New serial data may be
7
Y
Y
Y
Parallel loading independent of clock
Dual clock inputs
entered via the SERIAL DATA (Ds) input. Serial shifting oc-
curs on the rising edge of CLOCK1 or CLOCK2. Clock in-
puts may be used separately or together for combined
clocking from independent sources. Either clock input may
be used also as an active-low clock enable. To prevent dou-
ble-clocking when a clock input is used as an enable, the
enable must be changed to a high level (disabled) only while
the clock is high.
Fully static operation
Connection and Block Diagrams
Dual-In-Line Package
TL/F/5897–2
Order Number MM54C165* or MM74C165*
*Please look into Section 8, Appendix D
for availability of various package types.
TL/F/5897–1
Top View
TL/F/5897–3
C
1995 National Semiconductor Corporation
TL/F/5897
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b
a
65 C to 150 C
Storage Temperature Range
§
§
18V
Absolute Maximum V
CC
Power Dissipation
Dual-In-Line
Small Outline
b
a
0.3V
Voltage at Any Pin
0.3V to V
CC
700 mW
500 mW
Operating Temperature Range
MM54C165
MM74C165
b
b
a
a
55 C to 125 C
§
§
40 C to 85 C
Operating V Range
CC
3V to 15V
§
§
Lead Temperature (Soldering, 10 sec.)
260 C
§
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
e
e
V
V
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
V
V
5V
3.5
8.0
V
V
IN(1)
CC
10V
CC
e
e
V
V
5V
1.5
2.0
V
V
IN(0)
CC
10V
CC
e
e
e b
10 mA
V
V
5V, I
O
4.5
9.0
V
V
OUT(1)
OUT(0)
CC
e b
10V, I
10 mA
e a
10 mA
CC
O
e
e
V
V
5V, I
0.5
1.0
V
V
CC
O
e a
10V, I
15V, V
15V, V
15V
10 mA
CC
O
e
e
e
e
e
I
I
I
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
Supply Current
V
CC
V
CC
V
CC
15V
0V
0.005
1.0
mA
mA
mA
IN(1)
IN(0)
CC
IN
IN
b
b
1.0
0.005
0.05
300
CMOS TO LPTTL INTERFACE
e
e
b
b
V
V
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
54C
74C
V
4.5V
V
V
1.5
1.5
V
V
IN(1)
CC
CC
V
4.75V
CC
CC
e
e
54C
74C
V
V
4.5V
0.8
0.8
V
V
IN(0)
CC
4.75V
CC
e
e
e b
4.5V, I
O
54C
74C
V
V
360 mA
e b
2.4
2.4
V
V
OUT(1)
OUT(0)
CC
4.75V, I
360 mA
e
360 mA
CC
O
e
e
54C
74C
V
V
4.5V, I
0.4
0.4
V
V
CC
O
e
4.75V, I
360 mA
CC
O
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (short circuit current)
e
5V
I
I
I
I
Output Source Current
(P-Channel)
V
T
SOURCE
SOURCE
SINK
CC
b
b
3.3
1.75
mA
mA
mA
mA
e
e
e
e
e
25 C, V
§
0V
0V
V
A
OUT
OUT
OUT
OUT
e
Output Source Current
(P-Channel)
V
CC
10V
b
b
15
8.0
e
T
25 C, V
§
A
e
Output Sink Current
(N-Channel)
V
T
5V
CC
1.75
8.0
3.6
e
25 C, V
§
A
CC
e
CC
Output Sink Current
(N-Channel)
V
10V
SINK
16
e
T
25 C, V
§
V
CC
A
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
2
e
e
50 pF, unless otherwise noted
AC Electrical Characteristics* T
25 C, C
§
A
L
Symbol
Parameter
Conditions
Min
Typ
Max
Units
e
e
t
t
t
t
t
t
t
t
t
f
, t
pd0 pd1
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from Clock or Load to Q or Q
V
V
5V
200
80
400
200
ns
ns
CC
10V
CC
e
e
, t
pd0 pd1
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from H to Q or Q
V
V
5V
200
80
400
200
ns
ns
CC
10V
CC
e
e
Clock Inhibit Set-up Time
V
V
5V
150
60
75
30
ns
ns
S
CC
10V
CC
e
e
Serial Input Set-up Time
V
V
5V
50
30
25
15
ns
ns
S
CC
10V
CC
e
e
Serial Input Hold Time
V
V
5V
50
30
0
0
ns
ns
H
CC
10V
CC
e
e
Parallel Input Set-Up Time
Parallel Input Hold Time
V
V
5V
150
60
75
30
ns
ns
S
CC
10V
CC
e
e
V
V
5V
50
30
0
0
ns
ns
H
CC
10V
CC
e
e
Minimum Clock Pulse Width
Minimum Load Pulse Width
Maximum Clock Frequency
Maximum Clock Rise and Fall Time
V
V
5V
70
30
200
100
ns
ns
W
W
MAX
CC
10V
CC
e
e
V
V
5V
85
30
180
90
ns
ns
CC
10V
CC
e
e
V
V
5V
2.5
5
6
MHz
MHz
CC
10V
12
CC
e
e
t , t
r
V
V
5V
10
5
ms
ms
f
CC
10V
CC
C
C
Input Capacitance
(Note 2)
(Note 3)
5
pF
pF
IN
Power Dissipation Capacitance
65
PD
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: C determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note
PD
AN-90.
Switching Time Waveform
TL/F/5897–4
Note A: The remaining six data and the serial input are low.
Note B: Prior to test, high level data is loaded into the P7 input.
3
Truth Table
Inputs
Internal
Outputs
State
Clock2
PL
Clock1
Ds
P0 thru P7
Q0
Q1
Q7
Q7
(as enable)
Parallel Load
Enable
L
H
H
H
H
X
L
X
L
X
X
H
L
P0 . . . P7
P0
P0
H
P1
P1
P0
H
P7
P7
P6
P5
P5
P7
P7
P6
P5
P5
X
X
X
X
Shift (with Ds)
Shift (with Ds)
Hold (Disable)
L
u
u
u
L
L
H
X
L
H
e
e
e
X
H
L
don’t care
V
IN(1)
V
IN(0)
e
clock transition from V
e
to V
IN(1)
u
IN(0)
P0 thru P7
Q0 thru Q6
data present (and loaded into) parallel inputs
Internal flip-flop outputs
e
Logic Waveform
TL/F/5897–5
4
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C165J or MM74C165J
NS Package Number J16A
5
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number MM54C165N or MM74C165N
NS Package Number N16E
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to the user.
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support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
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effectiveness.
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