MM54HC74J [NSC]
Dual D Flip-Flop with Preset and Clear; 双D触发器与预置和清除
| 型号： | MM54HC74J |
| 厂家： | 
National Semiconductor |
| 描述： | Dual D Flip-Flop with Preset and Clear |
| 文件： | 总4页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1988
MM54HC74A/MM74HC74A
Dual D Flip-Flop with Preset and Clear
General Description
The MM54HC74A/MM74HC74A utilizes advanced silicon-
gate CMOS technology to achieve operating speeds similar
to the equivalent LS-TTL part. It possesses the high noise
immunity and low power consumption of standard CMOS
integrated circuits, along with the ability to drive 10 LS-TTL
loads.
The 54HC/74HC logic family is functionally and pinout com-
patible with the standard 54LS/74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to V
and ground.
CC
Features
Y
This flip-flop has independent data, preset, clear, and clock
inputs and Q and Q outputs. The logic level present at the
data input is transferred to the output during the positive-go-
ing transition of the clock pulse. Preset and clear are inde-
pendent of the clock and accomplished by a low level at the
appropriate input.
Typical propagation delay: 20 ns
Y
Y
Y
Y
Wide power supply range: 2–6V
Low quiescent current: 40 mA maximum (74HC Series)
Low input current: 1 mA maximum
Fanout of 10 LS-TTL loads
Connection and Logic Diagrams
Truth Table
Dual-In-Line Package
Inputs
Outputs
PR
CLR
CLK
D
Q
Q
L
H
L
H
L
X
X
X
X
X
H
L
H
L
L
H*
H
H
H*
L
L
X
H
H
H
H
H
H
u
u
L
L
H
X
Q0
Q0
e
Note: Q0 the level of Q before the indicated input condi-
tions were established.
* This configuration is nonstable; that is, it will not persist
when preset and clear inputs return to their inactive (high)
level.
TL/F/5106–1
Order Number MM54HC74A or MM74HC74A
TL/F/5106–2
C
1995 National Semiconductor Corporation
TL/F/5106
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
6
Units
V
Supply Voltage (V
)
CC
2
DC Input or Output Voltage
(V
0
V
CC
V
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
,
IN OUT
)
b
b
a
a
DC Input Voltage (V
)
1.5 to V
1.5V
0.5V
Operating Temp. Range (T )
A
MM74HC
MM54HC
IN
CC
CC
b
b
a
85
40
55
C
C
§
DC Output Voltage (V
)
0.5 to V
OUT
a
125
§
g
g
g
Clamp Diode Current (I , I
)
20 mA
25 mA
50 mA
IK OK
Input Rise or Fall Times
DC Output Current, per pin (I
)
OUT
e
e
e
(t , t )
r f
V
V
V
2.0V
4.5V
6.0V
1000
500
400
ns
ns
ns
CC
CC
CC
DC V or GND Current, per pin (I
CC
)
CC
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temp. (T ) (Soldering 10 seconds)
L
260 C
§
DC Electrical Characteristics (Note 4)
74HC
eb
54HC
e
T
A
25 C
§
eb
A
T
A
40 to 85 C
§
T
55 to 125 C
§
Symbol
Parameter
Conditions
V
CC
Units
Typ
Guaranteed Limits
V
V
V
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
IH
Maximum Low Level
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
IL
Input Voltage**
e
V or V
IH IL
Minimum High Level
Output Voltage
V
I
OH
IN
s
20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
4.0 mA
5.2 mA
4.5V
6.0V
4.3
5.2
3.98
5.48
3.84
5.34
3.7
5.2
V
V
l
l
OUT
OUT
l
l
I
e
V or V
IH IL
V
OL
Maximum Low Level
Output Voltage
V
IN
s
I
20 mA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
4.0 mA
5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
l
l
OUT
OUT
l
l
I
e
g
g
g
1.0
I
I
Maximum Input
Current
V
V
or GND 6.0V
0.1
1.0
mA
IN
IN
CC
e
Maximum Quiescent
Supply Current
V
IN
V
CC
or GND 6.0V
4.0
40
80
mA
CC
e
I
0 mA
OUT
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
§
§
g
OH OL
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and
IH IN CC
e
with this supply. Worst case V and V occur at V
IH IL
CC
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V limits are currently tested at 20% of V . The above V specification (30% of V ) will be implemented no later than Q1, CY’89.
IL CC IL CC
2
e
e
e
e e
15 pF, t t 6 ns
r f
AC Electrical Characteristics V
5V, T
25 C, C
§
CC
A
L
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ
Units
f
t
t
t
t
t
t
Maximum Operating
Frequency
72
10
17
6
30
30
40
5
MHz
MAX
, t
PHL PLH
Maximum Propagation
Delay Clock to Q or Q
ns
ns
ns
ns
ns
ns
, t
PHL PLH
Maximum Propagation
Delay Preset or Clear to Q or Q
Minimum Removal Time,
Preset or Clear to Clock
REM
s
Minimum Setup Time
Data to Clock
10
0
20
0
Minimum Hold Time
Clock to Data
H
Minimum Pulse Width
Clock, Preset or Clear
8
16
W
e
e e
t 6 ns (unless otherwise specified)
f
AC Electrical Characteristics C 50 pF, t
L
r
74HC
40 to 85 C
54HC
55 to 125 C
e
T
25 C
§
A
eb
eb
T
T
Symbol
Parameter
Conditions
V
§
Guaranteed Limits
§
Units
A
A
CC
Typ
f
t
t
t
t
t
t
t
Maximum Operating
Frequency
2.0V
4.5V
6.0V
22
72
94
6
30
35
5
24
28
4
20
24
MHz
MHz
MHz
MAX
, t
PHL PLH
Maximum Propagation
Delay Clock to Q or Q
2.0V
4.5V
6.0V
34
12
10
110
22
19
140
28
24
165
33
28
ns
ns
ns
, t
PHL PLH
Maximum Propagation
Delay Preset or Clear
To Q or Q
2.0V
4.5V
6.0V
66
20
16
150
30
26
190
38
33
225
45
38
ns
ns
ns
Minimum Removal Time
Preset or Clear
To Clock
2.0V
4.5V
6.0V
20
6
5
50
10
9
65
13
11
75
15
13
ns
ns
ns
REM
s
Minimum Setup Time
Data to Clock
2.0V
4.5V
6.0V
35
10
8
80
16
14
100
20
17
120
24
20
ns
ns
ns
Minimum Hold Time
Clock to Data
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
H
Minimum, Pulse Width
Clock, Preset or Clear
2.0V
4.5V
6.0V
30
9
8
80
16
14
101
20
17
119
24
20
ns
ns
ns
W
, t
TLH THL
Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
25
7
6
75
15
13
95
19
16
110
22
19
ns
ns
ns
t , t
r f
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
C
C
Power Dissipation
Capacitance (Note 5)
(per flip-flop)
80
pF
PD
Maximum Input
Capacitance
5
10
10
10
pF
IN
2
e
a
e
a
f I
PD CC CC
Note 5: C determines the no load dynamic power consumption, P
PD
C
V
PD CC
f
I
V
CC CC
, and the no load dynamic current consumption, I
C
V
.
D
S
3
Physical Dimensions inches (millimeters)
Order Number MM54HC74J or MM74HC74J
NS Package J14A
Order Number MM74HC74N
NS Package N14A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
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Hong Kong Ltd.
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Japan Ltd.
a
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