NM27LV010T150 [NSC]
IC 128K X 8 OTPROM, 150 ns, PDSO32, 8 X 20 MM, EIAJ, PLASTIC, TSOP1-32, Programmable ROM;
| 型号： | NM27LV010T150 |
| 厂家： | 
National Semiconductor |
| 描述： | IC 128K X 8 OTPROM, 150 ns, PDSO32, 8 X 20 MM, EIAJ, PLASTIC, TSOP1-32, Programmable ROM 可编程只读存储器 OTP只读存储器 光电二极管 |
| 文件： | 总10页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1994
NM27LV010
1,048,576-Bit (128k x 8) Low Voltage EPROM
General Description
The NM27LV010 is a high performance Low Voltage Electri-
cally Programmable Read Only Memory. It is manufactured
using National’s latest 0.8m CMOS split gate AMGTM
EPROM technology. This technology allows the part to op-
erate at speeds as fast as 150 ns over Industrial tempera-
The NM27LV010 is one member of National’s growing Low
Voltage product Family.
Features
Y
3.0V to 3.6V operation
b
a
tures ( 40 C to 85 C).
§
§
Y
150 ns access time
This Low Voltage and Low Power EPROM is designed with
power sensitive hand held and portable battery products in
mind. This allows for code storage of firmware for applica-
tions like notebook computers, palm top computers, cellular
phones, and HDD.
Y
Low current operation
Ð 8 mA I
CC
@
active current
standby current
5 MHz (typ.)
@
Ð 20 mA I
5 MHz (typ.)
CC
Y
Y
Ultra low power operation
Ð 66 mW standby power
Ð 50 mW active power
@
3.3V
3.3V
Small outline packages are just as critical to portable appli-
cations as Low Voltage and Low Power. National Semicon-
ductor has foreseen this need and provides windowed LCC
for prototyping and software development, PLCC for pro-
duction runs, and TSOP for PC board sensitive applications.
@
Surface mount package options
Ð 32-pin TSOP
Ð 32-pin PLCC
Block Diagram
TL/D/11377–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
AMGTM is a trademark of WSI, Incorporated.
C
1995 National Semiconductor Corporation
TL/D/11377
RRD-B30M65/Printed in U. S. A.
Connection Diagrams
PLCC and CLCC Pin Configuration
TSOP Pin Configuration
TL/D/11377–6
Top View
TL/D/11377–2
Top View
a
Commercial Temperature Range (0 C to 70 C)
b
a
Industrial Temperature Range ( 40 C to 85 C)
§
§
§
§
e
e
g
3.3 0.3
g
3.3 0.3
V
V
CC
CC
Parameter/Order Number
NM27LV010 C, V, T 150
NM27LV010 C, V, T 200
NM27LV010 C, V, T 250
Access Time (ns)
Parameter/Order Number
NM27LV010CE, VE, TE
NM27LV010CE, VE, TE
NM27LV010CE, VE, TE
Access Time (ns)
150
200
250
150
200
250
Note: Surface mount PLCC available for commercial and extended tempera-
ture ranges only.
Pin Names
Addresses
Package Types: NM27LV010 C, V, T
A0–A16
CE
e
e
e
C
V
T
Quartz-Windowed LCC Package
PLCC
TSOP
Chip Enable
OE
Output Enable
Outputs
All packages conform to the JEDEC standard.
#
#
#
O0–O7
PGM
XX
All versions are guaranteed to function for slower speeds.
Program
Consult the NSC Sales office on new released products
and packages.
Don’t Care (During Read)
Programming Voltage
V
PP
Consult the NSC representative for custom products for
your specific application.
#
2
Absolute Maximum Ratings (Note 1)
Operating Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Range
Temperature
V
Tolerance
CC
a
g
g
Commercial
Industrial
0 C to 70 C
§
3.3V
3.3V
0.3V
0.3V
§
b
a
40 C to 85 C
b
a
65 C to 150 C
Storage Temperature
§
§
§
§
All Input Voltages except A9 with
Respect to Ground (Note 10)
b
a
0.6V to 7V
b a
0.6V to 14V
V
V
and A9 with Respect to Ground
Supply Voltage with
PP
CC
b
a
0.6V to 7V
Respect to Ground
l
ESD Protection
2000V
a
1.0V
b
All Output Voltages with
Respect to Ground (Note 10)
V
CC
to GND 0.6V
e
DC Electrical Characteristics Over Operating Range with V
V
CC
PP
Symbol
Parameter
Input Low Level
Test Conditions
Min
Max
Units
b
V
V
V
V
V
V
0.3
0.7
V
V
V
V
V
IL
a
Input High Level
2.0
V
0.3
IH
CC
e
Output Low Voltage (TTL)
Output High Voltage (TTL)
Output Low Voltage
I
I
I
I
2.0 mA
0.4
OL1
OH1
OL2
OH2
SB1
OL
OH
OL
OH
e b
2.0 mA
2.4
e
100 mA
0.2
e b
e
b
Output High Voltage (CMOS)
100 mA
V
CC
0.3
g
0.3V
I
V
Standby Current
CE
V
CC
(CMOS)
CC
50
100
15
mA
mA
mA
e
I
I
V
V
Standby Current(TTL)
Active Current
CE
V
IH
SB2
CC
e
e
e
e
f 5 MHz
CE
OE
V ,
IL
CC
CC
I/O
0 mA
e
I
V
V
Supply Current
Read Voltage
V
PP
V
CC
10
mA
V
PP
PP
b
V
V
CC
0.7
V
CC
PP
PP
e
I
Input Load Current
V
V
3.0V or GND
1
mA
mA
LI
LO
IN
e
b
1
I
Output Leakage Current
3.0V or GND
10
OUT
e
AC Electrical Characteristics Over Operating Range with V
V
CC
PP
150
200
250
Symbol
Parameter
Units
Min
Max
150
150
65
Min
Max
200
200
70
Min
Max
250
250
75
t
t
t
t
Address to Output Delay
CE to Output Delay
ACC
CE
OE to Output Delay
OE
DF
Output Disable to Output Float
ns
50
50
50
(Note 2)
t
Output Hold from Addresses,
CE or OE, Whichever
Occurred First
OH
(Note 2)
0
0
0
3
e a
e
Capacitance T
25 C, 1
§
1 MHz (Note 2)
A
Symbol
Parameter
Conditions
Typ
9
Max
15
Units
pF
e
C
C
Input Capacitance
Output Capacitance
V
V
0V
IN
IN
e
0V
12
15
pF
OUT
OUT
AC Test Conditions
Output Load
1 TTL Gate and
100 pF (Note 8)
Timing Measurement Reference Level
Inputs
Outputs
e
C
L
0.8V and 2V
0.8V and 2V
s
Input Rise and Fall Times
Input Pulse Levels
5 ns
0.45V to 2.4V
AC Waveforms (Notes 6, 7, and 9)
TL/D/11377–3
Note 1: Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operations sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
b
Note 3: OE may be delayed up to t
t
after the falling edge of CE without impacting t
.
ACC
ACC
CE
Note 4: The t and t compare level is determined as follows:
DF CF
b
High to TRI-STATE , the measured V
(DC)
a
0.10V;
0.10V.
Note 5: TRI-STATE may be attained using OE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.2 mF ceramic capacitor be used on
every device between V and GND.
É
OH1
(DC)
Low to TRI-STATE, the measured V
OL1
CC
Note 7: The outputs must be restricted to V
a
1.0V to avoid latch-up and device damage.
400 mA.
C : 100 pF includes fixture capacitance.
CC
e
e b
Note 8: 1 TTL Gate: I
OL
1.6 mA, I
OH
L
Note 9: V may be connected to V
PP
except during programming.
CC
b
Note 10: Inputs and outputs can undershoot to 2.0V for 20 ns Max.
4
Programming Characteristics (Notes 1, 2, 3, 4 and 5)
Symbol
Parameter
Address Setup Time
OE Setup Time
Conditions
Min
1
Typ
Max
Units
ms
t
t
t
t
t
t
t
t
t
AS
1
ms
OES
CES
DS
CE Setup Time
1
ms
Data Setup Time
1
ms
V
V
Setup Time
Setup Time
1
ms
VPS
VCS
AH
PP
1
ms
CC
Address Hold Time
Data Hold Time
0
ms
1
ms
DH
e
Output Enable to Output
Float Delay
CE/PGM
V
DF
IL
0
60
ns
t
t
Program Pulse Width
Data Valid from OE
95
100
105
100
ms
PW
OE
PP
e
e
CE/PGM
CE/PGM
V
V
ns
IL
I
V
Supply Current
PP
during Programming Pulse
IL
20
mA
mA
I
V
CC
Supply Current
20
30
CC
T
Temperature Ambient
20
6.0
12.5
5
25
C
§
A
V
Power Supply Voltage
6.25
12.75
6.5
13.0
V
CC
PP
V
Programming Supply Voltage
Input Rise, Fall Time
V
t
FR
ns
V
V
V
Input Low Voltage
0.0
4.0
0.45
IL
Input High Voltage
2.4
0.8
0.8
V
IH
t
Input Timing Reference Voltage
Output Timing Reference Voltage
2.0
2.0
V
IN
OUT
t
V
Programming Waveform (Note 3)
TL/D/11377–4
Note 1: National’s standard product warranty applies to devices programmed to specifications described herein.
Note 2: V must be applied simultaneously or before V and removed simultaneously or after V . The EPROM must not be inserted into or removed from a
CC
board with voltage applied to V or V
P
P
P
P
.
CC
PP
Note 3: The maximum absolute allowable voltage which may be applied to the V pin during programming is 14V. Care must be taken when switching the V
PP
to GND to suppress
PP
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 mF capacitor is required across V , V
spurious voltage transients which may damage the device.
PP CC
Note 4: Programming and program verify are tested with the fast Program Algorithm, at typical power supply voltages and timings.
t
Note 5: During power up the PGM pin must be brought high (
V
) either coincident with or before power is applied to V
IH
.
PP
5
Fast Programming Algorithm Flow Chart
TL/D/11377–5
FIGURE 1
6
Functional Description
DEVICE OPERATION
The EPROM is in the programming mode when the V
PP
power supply is at 12.75V and OE is at V . It is required
IH
that at least a 0.1 mF capacitor be placed across V and
PP
The six modes of operation of the EPROM are listed in Ta-
ble I. It should be noted that all inputs for the six modes are
V
to ground to suppress spurious voltage transients
CC
at TTL levels. The power supplies required are V
CC
and
which may damage the device. The data to be programmed
is applied 8 bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL.
V
. The V power supply must be at 12.75V during the
PP PP
three programming modes, and must be at 3.3V in the other
three modes. The V power supply must be at 6.25V dur-
CC
ing the three programming modes, and at 3.3V in the other
three modes.
When the address and data are stable, an active low, TTL
program pulse is applied to the PGM input. A program pulse
must be applied at each address location to be pro-
grammed. The EPROM is programmed with the Fast Pro-
gramming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100 ms pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100 ms pulse.
Read Mode
The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (CE) is the power control and should be used
for device selection. Output Enable (OE) is the output con-
trol and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
The EPROM must not be programmed with a DC signal ap-
plied to the PGM input.
are stable, address access time (t ) is equal to the delay
ACC
Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of the
programming requirements. Like inputs of the parallel
EPROM may be connected together when they are pro-
grammed with the same data. A low level TTL pulse applied
to the PGM input programs the paralleled EPROM.
from CE to output (t ). Data is available at the outputs t
CE OE
after the falling edge of OE, assuming that CE has been low
and addresses have been stable for at least t
–t .
ACC OE
Standby Mode
The EPROM has a standby mode which reduces the active
power dissipation by over 99%, from 50 mW to 66 mW. The
EPROM is placed in the standby mode by applying a CMOS
high signal to the CE input. When in standby mode, the
outputs are in a high impedance state, independent of the
OE input.
Program Inhibit
Programming multiple EPROM’s in parallel with different
data is also easily accomplished. Except for CE, all like in-
puts (including OE and PGM) of the parallel
EPROM may be common. A TTL low level program pulse
Output Disable
applied to an EPROM’s PGM input with CE at V and V
IL PP
at 12.75V will program that EPROM. A TTL high level CE
input inhibits the other EPROM’s from being programmed.
The EPROM is placed in output disable by applying a TTL
high signal to the OE input. When in output disable all cir-
cuitry is enabled, except the outputs are in a high imped-
ance state (TRI-STATE).
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with V at 6.25V. V must be at
Output OR-Tying
Because the EPROM is usually used in larger memory ar-
rays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
PP
PP
V
, except during programming and program verify.
CC
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window
to prevent unintentional erasure. Covering the window will
also prevent temporary functional failure due to the genera-
tion of photo currents.
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recom-
mended that CE be decoded and used as the primary de-
vice selecting function, while OE be made a common con-
nection to all devices in the array and connected to the
READ line from the system control bus. This assures that all
deselected memory devices are in their low power standby
modes and that the output pins are active only when data is
desired from a particular memory device.
MANUFACTURER’S IDENTIFICATION CODE
The EPROM has a manufacturer’s identification code to aid
in programming. When the device is inserted in an EPROM
programmer socket, the programmer reads the code and
then automatically calls up the specific programming algo-
rithm for the part. This automatic programming control is
only possible with programmers which have the capability of
reading the code.
Programming
The Manufacturer’s Identification code, shown in Table II,
specifically identifies the manufacturer and device type. The
code for the NM27LV010 is ‘‘8F86’’, where ‘‘8F’’ designates
that it is made by National Semiconductor, and ‘‘86’’ desig-
nates a 1 Megabit (128k x 8) part.
CAUTION: Exceeding 14V on pin 1 (V ) will damage the
PP
EPROM.
Initially, and after each erasure, all bits of the EPROM are in
the ‘‘1’s’’ state. Data is introduced by selectively program-
ming ‘‘0’s’’ into the desired bit locations. Although only
‘‘0’s’’ will be programmed, both ‘‘1’s’’ and ‘‘0’s’’ can be pre-
sented in the data word. The only way to change a ‘‘0’’ to a
‘‘1’’ is by ultraviolet light erasure.
g
The code is accessed by applying 12V 0.5V to address
pin A9. Addresses A1–A8, A10–A16, and all control pins
are held at V . Address pin A0 is held at V for the manu-
IL IL
facturer’s code, and held at V for the device code. The
IH
code is read on the lower eight data pins, O0–07. Proper
g
code access is only guaranteed at 25 C
§
5 C.
§
7
Functional Description (Continued)
ERASURE CHARACTERISTICS
mers, components, and even system designs have been
erroneously suspected when incomplete erasure was the
problem.
The erasure characteristics of the device are such that era-
sure begins to occur when exposed to light with wave-
lengths shorter than approximately 4000 Angstroms (Ð). It
should be noted that sunlight and certain types of fluores-
cent lamps have wavelengths in the 3000Ж4000Рrange.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, I
,
CC
The recommended erasure procedure for the EPROM is ex-
posure to short wave ultraviolet light which has a wave-
has three segments that are of interest to the system de-
signer: the standby current level, the active current level,
and the transient current peaks that are produced by volt-
age transitions on input pins. The magnitude of these tran-
sient current peaks is dependent on the output capacitance
c
exposure time) for erasure should be a minimum of 30W-
length of 2537Ð. The integrated dose (i.e., UV intensity
2
sec/cm .
The EPROM should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure.
loading of the device. The associated V transient voltage
CC
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 mF ceramic
capacitor be used on every device between V
CC
and GND.
This should be a high frequency capacitor of low inherent
An erasure system should be calibrated periodically. The
distance from lamp to device should be maintained at one
inch. The erasure time increases as the square of the dis-
tance from the lamp (if distance is doubled the erasure time
increases by factor of 4). Lamps lose intensity as they age.
When a lamp has aged, the system should be checked to
make certain full erasure is occurring. Incomplete erasure
will cause symptoms that can be misleading. Program-
inductance. In addition, at least a 4.7 mF bulk electrolytic
capacitor should be used between V
CC
and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The pur-
pose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
Mode Selection
The modes of operation of the NM27LV010 are listed in Table I. A single 3.3V power supply is required in the read mode. All
inputs are TTL levels except for V and A9 for device signature.
PP
TABLE I. Modes Selection
Pins
CE
OE
PGM
V
PP
V
CC
Outputs
Mode
Read
V
V
X
X
X
V
CC
V
CC
V
CC
3.3V
3.3V
D
OUT
IL
IL
Output Disable
Standby
X (Note 1)
V
IH
High Z
High Z
V
IH
X
3.3V
Programming
Program Verify
Program Inhibit
V
V
V
V
12.75V
12.75V
12.75V
6.25V
12.75V
6.25V
D
IN
IL
IL
IH
IH
IL
V
V
IH
D
OUT
IL
V
V
IH
X
High Z
Note 1: X can be V or V
IL
.
IH
TABLE II. Manufacturer’s Identification Code
A0 A9 O7 O6 O5 O4 O3 O2 O1 O0 Hex
(12) (26) (21) (20) (19) (18) (17) (15) (14) (13) Data
Pins
Manufacturer Code
Device Code
V
12V
12V
1
1
0
0
0
0
0
0
1
0
1
1
1
1
1
0
8F
86
IL
V
IH
8
Physical Dimensions (millimeters)
32-Lead TSOP Package (T)
Order Number NM27LV010TXXX
NS Package Number MBH32A
9
Physical Dimensions inches (millimeters) (Continued)
32-Lead PLCC Package
Order Number NM27LV010VXXX
NS Package Number VA32A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
Tel: 1(800) 272-9959
TWX: (910) 339-9240
National Semiconductor
GmbH
Livry-Gargan-Str. 10
D-82256 Furstenfeldbruck
Germany
Tel: (81-41) 35-0
Telex: 527649
Fax: (81-41) 35-1
National Semiconductor National Semiconductor
National Semiconductores
Do Brazil Ltda.
Rue Deputado Lacorda Franco
120-3A
Sao Paulo-SP
Brazil 05418-000
Tel: (55-11) 212-5066
Telex: 391-1131931 NSBR BR
Fax: (55-11) 212-1181
National Semiconductor
(Australia) Pty, Ltd.
Building 16
Business Park Drive
Monash Business Park
Nottinghill, Melbourne
Victoria 3168 Australia
Tel: (3) 558-9999
Japan Ltd.
Hong Kong Ltd.
Sumitomo Chemical
Engineering Center
Bldg. 7F
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
1-7-1, Nakase, Mihama-Ku Hong Kong
Chiba-City,
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Ciba Prefecture 261
Tel: (043) 299-2300
Fax: (043) 299-2500
Fax: (3) 558-9998
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
©2020 ICPDF网 联系我们和版权申明