NM95MS14VBH [NSC]
Plug n Play Front-End Devices for ISA-Bus Systems; 插头N播放前端设备的ISA总线系统
| 型号： | NM95MS14VBH |
| 厂家： | 
National Semiconductor |
| 描述： | Plug n Play Front-End Devices for ISA-Bus Systems |
| 文件： | 总8页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1996
NM95MS14
Plug ’n Play Front-End Devices for ISA-Bus Systems
General Description
Features
Y
Complete implementation of Plug ’n Play standard
Ð Direct interface to ISA bus
The NM95MS14 is the smaller of a family of devices de-
signed to provide complete Plug ’n Play Capability for ISA
bus systems. The NM95MS14 includes the necessary state
machine logic to manage the Plug ’n Play protocol in addi-
tion to switches for steering Interrupt and DMA requests. It
also features a built-in 2k bits of serial EEPROM for storing
the resource data specified in the Plug ’n Play Standard. In
addition, 4k bits of EEPROM is available for use by other on-
board logic. This device provides a ‘‘truly complete’’ single-
chip solution for implementing Plug ’n Play on ISA-Bus
Adapter cards. The NM95MS14 supports one logical device
with a flexible choice of DMA/IRQ selection and I/O Chip-
select generation.
Y
Two modes of operation
Ð DMA mode
Ð Extended Interrupt mode
Y
6 or 8 ISA bus interrupt lines and 2 DRQ/DACK lines
supported
Y
On-chip EEPROM for resource request table
Y
Additional 4 Kbits of on-chip EEPROM available for ex-
ternal access
Y
24 mA drivers for data outputs
Y
48-pin TQFP
NM95MS14 is implemented using National’s Advanced
CMOS process and operates single power supply. The
NM95MS14 is available in a 48-pin TQFP package.
Block Diagram
TL/D/12315–1
C
1996 National Semiconductor Corporation
TL/D/12315
RRD-B30M126/Printed in U. S. A.
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Connection Diagram
a
Commercial Temperature Range (0 C to 70 C)
§
§
TL/D/12315–2
Order Number NM95MS14VBH
Description
Signals
Type
k
SA 11:0
l
I
Address inputs from the ISA bus.
IORD*
IOWR*
AEN
I
I/O read strobe from the ISA bus.
I/O write strobe from the ISA bus.
I
I
Address Enable from ISA BusÐused in conjunction with DMA.
Data busÐlower byteÐfrom/to the ISA bus.
k
SD 7:0
l
I/O
OSC (Note 1)
RSTDRV
CS
I
I
I
‘‘OSC’’ Clock from the ISA busÐused for internal state machines.
Reset input from the ISA bus.
Chip select for Microwire port. There should be a pulldown resistor of 4.7k on CS pin if
unused externally or directly connected to GND.
SK, DI
DO
I
Clock and Data input lines for Microwire bus connection to access a portion (4k) on chip
EEPROM.
O
O
Data output line for the Microwire interface detailed above.
k
IRQOUT 5:0
l
Connection to ISA bus interrupt request pins. On-chip interrupt request(s) may be connected to
any 6 of the ISA IRQ lines.
k
IRQIN 1:0
l
I
I
Interrupt request from on-board logic
DRQin/IOCS2*
DMA request from on-board logic, or Programmable chipselect (2) depending on mode
selected.
DACKOUT*/IOCS3*
O
O
I
DMA Acknowledge for on-board logic or Programmable chipselect (3) depending on mode
selected.
k
l
/
ISADRQ 1:0
Connection for two ISA bus DMA Request lines, or additional interrupt request lines depending
on the mode selected.
k
IRQOUT 7:6
l
k
l
ISADACK 1:0 */
DMA Acknowledge from the ISA bus or additional address lines depending on the mode
selected.
k
SA 13:12
l
k
IOCS 1:0
l
*
O
Programmable chip selects to address on-board peripheral.
*Signal name with a ‘‘*’’ means its an active low signal.
Note 1: ‘‘OSC’’ clock from ISA Bus is fixed at a standard frequency of 14.318 MHz. NM95MS14 is designed and tested for 14.318 MHz. However the NM95MS14
can handle frequencies up to 24 MHz though it is not 100% tested.
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2
Pinout Details for the NM95MS14
e
e
Mode 00
DMA Mode; Mode 01
Extended Interrupt Mode
Ý
Ý
Ý
Pin
Pin
Pin Name
DMA
Pin
Pin Name
DMA
Pin Name
DMA
SA8
TQFP
1
Ext. Intr. PLCC
TQFP
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Ext. Intr. PLCC
TQFP
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Ext. Intr. PLCC
RSTDRV
IOCS1*
IOCS0*
IORD*
RSTDRV
IOCS1*
IOCS0*
IORD*
47
48
49
50
51
52
2
IRQOUT0
ISADRQ0
ISADRQ1
IRQOUT0
IRQOUT6
IRQOUT7
12
13
15
16
17
18
19
20
21
22
23
24
25
26
28
29
SA8
SA9
SA10
SA11
DI
30
31
32
33
34
35
36
37
38
39
41
42
43
44
45
46
2
SA9
3
SA10
SA11
DI
4
ISADACK0* SA12
ISADACK1* SA13
5
IOWR*
IOWR*
6
V
CC
V
CS
CS
DO
DO
CC
7
DRQIN
IOCS2*
SK
SK
AEN
OSC
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
AEN
OSC
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
8
DACKOUT* IOCS3*
3
SA0
SA1
SA2
SA3
SA4
GND
SA5
SA6
SA7
SA0
SA1
SA2
SA3
SA4
GND
SA5
SA6
SA7
9
GND
GND
4
10
11
12
13
14
15
16
IRQIN1
IRQIN1
5
IRQIN0
IRQIN0
6
IRQOUT5
IRQOUT4
IRQOUT3
IRQOUT2
IRQOUT1
IRQOUT5
IRQOUT4
IRQOUT3
IRQOUT2
IRQOUT1
7
8
9
10
11
Note: Mode selection (00 or 01) is done by setting MS bits in the EEPROM configuration register. Detailed information about this is described in User’s Guide.
3
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Absolute Maximum Ratings
b
Operating Conditions
Ambient Operating Temperature
NM95MS14
a
65 C to 150 C
Ambient Storage Temperature
§
§
a
0 C to 70 C
All Input or Output Voltages
with Respect to Ground
§ §
4.5V to 5.5V
a
b
1V to 0.3V
V
CC
Positive Power Supply (V
)
CC
Lead Temperature
(Soldering, 10 seconds)
a
300 C
§
2000V Min
ESD Rating
DC Electrical Characteristics
Limits
Typ
Symbol
Parameter
Test Conditions
Units
Min
Max
(Note 1)
e
SCL
I
I
I
Active Power Supply Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
f
100 kHz
TBD
10.0
1.0
1.0
0.8
a
mA
mA
mA
V
CCA
e
V
V
GND or V
CC
0.2
LI
IN
e
GND to V
CC
LO
OUT
b
V
V
V
0.1
IL
Input High Voltage
2.0
V
CC
1.0
V
V
IH
OL
e
e
Output Low Voltage
I
I
24 mA (Note 3)
2.1 mA (Note 4)
OL
0.4
OL
e b
e b
V
OH
Output High Voltage
I
I
3 mA (Note 3)
2.4
2.4
V
V
OH
400 mA (Note 4)
OH
e a
e
e
Capacitance T
25 C, f
§
1.0 MHz, V
CC
5V
A
Symbol
Test
Conditions
Max
Units
pF
e
I/O
C
C
C
(Note 2)
Input/Output Capacitance
Input Capacitance
V
V
V
0V
8
6
6
I/O
e
(Note 2)
0V
pF
IN
IN
OUT
e
(Note 2)
Output Capacitance
0V
pF
OUT
e
Note 1: Typical values are for T
25 C and nominal supply voltage (5V).
§
Note 2: This parameter is periodically sampled and not 100% tested.
A
[
]
Note 3: These values are for ISA signals like SD 0:7 , IRQx, DRQx.
[
]
Note 4: These values are for card signal like IOCS 0:3 *, DO(EEPROM).
AC Electrical Characteristics
Symbol
Parameter
AEN Valid to Command Active
Address Valid to Command Active
Active Read to Valid Data
Min
100
88
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
AEN
AC
200
5
RVD
AH
Address, AEN Hold from Inactive Command
Read Data Hold from Inactive Read
Write Data Valid before Write Active
Write Data Hold after Write Inactive
Chip Selects Valid from Address Valid
Chip Selects Valid from Command Active
Propagation Delay for IRQ/DRQ/DACK
30
RDH
WD
22
25
5
WDH
CSA
CSC
IDD
25
25
25
5
5
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4
Timing Diagrams
(1) Timings for ISA Read/Write Cycle
TL/D/12315–3
(2) Decode Delay for Chipselect Generation
TL/D/12315–4
(3) Propagation Delay for IRQ/DRQ/DACK
TL/D/12315–5
5
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INTRODUCTION
configuration registers (Refer to the User’s guide for de-
tailed information). Each of these modes are discussed be-
low.
The NM95MS14 is a single-chip solution for the ISA Plug ’n
Play (PnP) specification. It implements the complete state
machine and the necessary logic for supporting configura-
ble Interrrupts and DMA channels on the ISA bus for one
logical device. Apart from providing ‘‘Plug ’n Play’’ capabili-
ty, it has built-in EEPROM that eliminates external
EEPROM. This device is available in a space saving 48-pin
Thin Quad Flat Pack (TQFP) package.
DMA Mode
In the DMA mode, support is provided for
A) One on-board DMA request that is switchable to any two
DMA channels on the ISA bus.
B) Two on-board interrupt request lines switchable to any
six IRQ lines on the ISA bus.
Functional Description
C) Two programmable I/O chip selects for on-board logic.
NM95MS14 has two modes of operation, viz, ‘‘DMA mode’’
and ‘‘Extended Interrupt mode’’. These modes are pro-
grammed using the mode select (MS) bits in one of the
Figure 1 shows a Block Diagram of NM95MS14 configured
for DMA Mode.
Block Diagrams (Continued)
TL/D/12315–6
FIGURE 1
Extended Interrupt Mode
In the Ext. Int mode, support is provided for:
A) Two on-board interrupt request lines switchable to any eight IRQ lines on the ISA bus.
B) Four programmable I/O chip selects for on-board logic.
C) ISA address SA12 and SA13 are also included for extended decode.
Figure 2 shows a Block Diagram of NM95MS14 configured for Extended Interrupt Mode.
TL/D/12315–7
FIGURE 2
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6
Chipselect Generation
EEPROM Programming
Individual I/O chipselect can be generated in the following
two ways:
The entire 6k bits of EEPROM can be programmed through
the ISA bus. The EEPROM can be programmed by putting
the device (NM95MS14) in the Config. state (as defined in
the PnP standard). Under this state 4 registers at address
0xF0–0xF3 are accessible to program the EEPROM. The
data to be programmed is loaded in register at address
0xF3 and 0xF2 (LSB and MSB respectively). The address to
be programmed is loaded in register at address 0xF1. The
Ninth bit of address for 6k bits of memory is provided
through the register at address 0xF0. Both read write are
possible. The actual operation does not begin until Go
Ahead (GA) bit is set. Programming a word takes approxi-
mately 10 ms. The status of the operation can be polled by
the Status bit. This bit is set when the operation is in prog-
ress and will be reset when complete. The register at ad-
dress 0xF0 is COMMAND register. This is the handshake
register in programming the EEPROM and is explained be-
low in a tabular format.
A) Address Decode only
B) Address Decode qualified by Command (IORD*, IOWR*).
On-Chip EEPROM
NM95MS14 has 6k of EEPROM on chip. All the PnP re-
source data structure for the logical device is stored in this
EEPROM. Of the 6k bits, 4k bits are available for the logical
device’s external usage. The logical device can access the
EEPROM through a microwire port, which is essentially a
4-wire serial bus. The pins CS, SK, DI & DO follow the exact
timing as the standard microwire bus and are compatible to
the NM93Cxx family of EEPROMs.
[
]
]
COMMAND register
0xF0
Bit 1:0
- OP Code bits
GA(Go ahead bits)
10 - Read operation
01 - Write operation
[ ]
Bit 2
If set to 1 the programming will continue.
- Reserved, should be 0.
- It provides A8 of the address. A 0:7 is provided by 0xF1 reg. (Note 1)
[
Bit 6:3
[ ]
Bit 7
[
]
[
AddressRegister A0–A7
]
Address Register
Data Register
0xF1
0xF2
0xF3
0x05
[
Data Byte MSB
]
[
]
Data Register
Data Byte LSB
[ ]
- Status/Busy bit
STATUS Register
Bit 0
‘‘0’’ is busy, ‘‘1’’ is done.
[
]
of register 0XF0 (Address A8) should be
Note 1: The PNP resource data portion of the internal memory is at high address. Hence to program that portion, Bit
7
set to ‘‘1’’.
7
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Physical Dimensions inches (millimeters) unless otherwise noted
TQFP Package (VBH)
Package Number VBH48A
Order Number NM95MS14VBH
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