NM95MS15VEH [NSC]
Plug and Play Front-End Device for ISA-Bus Systems; 即插即用前端设备的ISA总线系统
| 型号： | NM95MS15VEH |
| 厂家： | 
National Semiconductor |
| 描述： | Plug and Play Front-End Device for ISA-Bus Systems |
| 文件： | 总10页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1996
NM95MS15
Plug and Play Front-End Device for ISA-Bus Systems
General Description
Features
Y
Single chip implementation of complete Plug and Play
Standard
Ð Direct interface to ISA-bus
The NM95MS15 is one of the family of single chip solutions
designed to provide complete Plug and Play capability for
ISA bus systems. The NM95MS15 includes the necessary
state machine logic to manage the Plug and Play protocol in
addition to switches for steering Interrupt and DMA re-
quests. It also features a built-in 4k bits of serial EEPROM
for storing the resource data specified in the Plug and Play
Standard. In addition, 4k bits of the EEPROM is available for
use by other on-board logic. This device provides a truly
complete single-chip solution for implementing Plug and
Play on ISA-Bus adapter cards. The NM95MS15 supports
two logical devices with a flexible choice of DMA/IRQ selec-
tion, I/O, and MEMORY Chip Select generation.
Y
Three modes of operation
Ð Normal DMA mode
Ð Extended Interrupt mode
Ð Extended DMA mode
Y
6, 8, or 11 ISA-bus interrupt lines and 3 DRQ/DACK
lines supported (IRQ’s and DRQ’s are mode
dependent)
Y
On-chip EEPROM for resource request table
Y
Additional 4k bits of on-chip EEPROM available for ex-
ternal access
NM95MS15 is implemented using National’s advanced
CMOS process and operates from a single power supply.
The NM95MS15 is available in a 64-pin TQFP package.
Y
24 mA drivers for data outputs
Y
64-pin TQFP package
Block Diagram
TL/D/12394–1
C
1996 National Semiconductor Corporation
TL/D/12394
RRD-B30M126/Printed in U. S. A.
http://www.national.com
Connection Diagram
TL/D/12394–2
a
Commercial Temperature Range (0 C to 70 C)
§
Order Number NM95MS15S
§
Signals
Type
Description
k
SA 19:0
l
I
Address inputs from the ISA bus.
IORD*, SMEMR*
IOWR*, SMEMW*
AEN
I
I/O and memory read strobes from the ISA bus.
I
I/O write and memory write strobes from the ISA bus.
I
Address Enable from ISA busÐused in conjunction with DMA.
Data busÐlower byteÐfrom/to the ISA bus.
k
SD 7:0
l
I/O
OSC (Note 1)
RSTDRV
SK,DI
I
I
I
‘‘OSC’’ Clock from ISA busÐused for internal state machines.
Reset input from the ISA bus.
Clock and Data input lines for microwire bus connection to access a portion (4k) on chip
EEPROM.
CS
I
Chip select for microwire bus connection to access 4k on chip EEPROM. This pin should be
pulled down to GND, if the 4k user portion is not used.
DO
O
O
Data output line for the Microwire interface detailed above.
k
IRQOUT 5:0
l
Connection to ISA bus interrupt request pins. On-chip interrupt requests may be connected
to any of the 6 lines.
IRQOUT6/DRQIN1
I or O
Interrupt request line to the ISA bus or DMA request line from on-board logic.
Interrupt request line to the ISA bus or DMA ackowledge for on-board logic.
Interrupt request from on-board logic.
IRQOUT7/DACKOUT1*
O
k
IRQIN 1:0
l
I
I or O
O
DRQIN0/IOCS2*
DMA request from on-board logic or IOCS2 depending on mode selected.
DMA Acknowledge for on-board logic or IOCS3 depending on mode selected.
DACKOUT0*/IOCS3*
k
l
/
l
ISADRQ 2:0
O
Connection for three ISA bus DMA Request lines, or additional interrupt request lines
depending on the mode selected.
k
IRQOUT 10:8
k
ISADACK 2:0
l
*
I
DMA acknowledge from the ISA bus.
k
IOCS 1:0
l
*
l
*
O
O
Programmable chip selects to address on-board peripherals
Programmable chip selects to address on-board ROM/Memory.
k
MEMCS 1:0
* Means active low signal
Note 1: ‘‘OSC’’ clock from ISA Bus is fixed at a standard frequency of 14.318 MHz. NM95MS15 is designed and tested for this frequency. However NM95MS15
can handle frequencies up to 24 MHz though it is not 100% tested.
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2
Pinout Details for the NM95MS15
e
e
e
Mode 00
DMA Mode; Mode 01
Pin Name
Extended Interrupt Mode; Mode 10
Extended DMA Mode
Pin Name
Ý
Ý
Pin
Pin
TQFP
(TQFP)
Mode ‘‘00’’
RSTDRV
IOCS1*
Mode ‘‘01’’
RSTDRV
IOCS1*
Mode ‘‘10’’
RSTDRV
IOCS1*
Mode ‘‘00’’
SA1
Mode ‘‘01’’
SA1
Mode ‘‘10’’
1
2
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SA1
SA2
SA3
SA4
GND
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
DI
SA2
SA2
3
IOCS0*
IOCS0*
IOCS0*
SA3
SA3
4
MEMCS1*
MEMCS0*
SMEMR*
SMEMW*
IOWR*
MEMCS1*
MEMCS0*
SMEMR*
SMEMW*
IOWR*
MEMCS1*
MEMCS0*
SMEMR*
SMEMW*
IOWR*
SA4
SA4
5
GND
SA5
GND
SA5
6
7
SA6
SA6
8
SA7
SA7
9
IORD*
IORD*
IORD*
SA8
SA8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V
V
CC
V
CC
SA9
SA9
CC
DRQIN0
DACKOUT0*
GND
IOCS2*
DRQIN0
DACKOUT0*
GND
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
DI
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
DI
IOCS3*
GND
IRQIN1
IRQIN1
IRQIN1
IRQIN0
IRQIN0
IRQIN0
IRQOUT5
IRQOUT6
IRQOUT7
IRQOUT4
IRQOUT3
IRQOUT2
IRQOUT1
IRQOUT0
ISADRQ0
ISADRQ1
ISADRQ2
ISADACK0*
ISADACK1*
ISADACK2*
CS
IRQOUT5
IRQOUT6
IRQOUT7
IRQOUT4
IRQOUT3
IRQOUT2
IRQOUT1
IRQOUT0
IRQOUT8
IRQOUT9
IRQOUT5
DRQIN1
DACKOUT1*
IRQOUT4
IRQOUT3
IRQOUT2
IRQOUT1
IRQOUT0
ISADRQ0
ISADRQ1
ISADRQ2
ISADACK0*
ISADACK1*
ISADACK2*
CS
DO
DO
DO
SA18
SA19
AEN
OSC
SD0
SA18
SA19
AEN
OSC
SD0
SA18
SA19
AEN
OSC
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
²
²
²
IRQOUT10
NC
SD1
SD1
SD2
SD2
NC
SD3
SD3
NC
SD4
SD4
CS
SD5
SD5
SK
SK
SK
SD6
SD6
SA0
SA0
SA0
SD7
SD7
Note: Mode selection (00, 01 or 10) is done by setting MS bits in the EEPROM configuration register. Detailed information about this is described in User’s Guide.
²
In Mode ‘‘01’’, IRQOUT8, 9, 10 are hardwired to ISA Bus interrupts IRQ10, IRQ11, IRQ12 respectively. This information supercedes the description in the
‘‘NM95MS15 User’s Guide’’.
3
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Absolute Maximum Ratings
b
Operating Conditions
Ambient Operating Temperature
NM95MS15
a
65 C to 150 C
Ambient Storage Temperature
§
§
a
0 C to 70 C
All Input or Output Voltages
with Respect to Ground
§ §
4.5V to 5.5V
a
b
1V to 0.3V
V
CC
Positive Power Supply (V
)
CC
Lead Temperature
(Soldering, 10 seconds)
a
300 C
§
2000V Min
ESD Rating
DC Electrical Characteristics
Limits
Typ
Symbol
Parameter
Test Conditions
Units
Min
Max
(Note 1)
e
SCL
I
I
I
Active Power Supply Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
f
100 kHz
6
20
15
15
0.8
a
mA
mA
mA
V
CCA
e
V
V
GND to V
CC
0.2
LI
IN
e
GND to V
CC
LO
OUT
b
V
V
V
0.1
IL
Input High Voltage
2.0
V
CC
1.0
V
V
IH
OL
e
e
Output Low Voltage
I
I
24 mA (Note 3)
2.1 mA (Note 4)
OL
0.4
OL
e b
e b
V
OH
Output High Voltage
I
I
3 mA (Note 3)
2.4
2.4
V
V
OH
400 mA (Note 4)
OH
e a
e
e
Capacitance T
25 C, f
§
1.0 MHz, V
CC
5V
A
Symbol
(Note 2)
Test
Conditions
Max
Units
pF
e
I/O
C
C
C
Input/Output Capacitance
Input Capacitance
V
V
V
0V
8
6
6
I/O
(Note 2)
e
0V
pF
IN
IN
OUT
e
(Note 2)
Output Capacitance
0V
pF
OUT
e
Note 1: Typical values are for T
25 C and nominal supply voltage (5V).
§
Note 2: This parameter is periodically sampled and not 100% tested.
A
[
]
Note 3: These values are for ISA signals SD 0:7 , IRQx, DRQx.
[
]
[
]
Note 4: These values are for card signal IOCS 0:3 *, MEMCS 0:1 *, DO(EEPROM).
AC Electrical Characteristics
Symbol
Parameter
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
AEN Valid to Command Active
100
88
AEN
Address Valid to Command Active
Active Read to Valid Data
AC
200
5
RVD
AH
Address, AEN Hold from Inactive Command
Read Data Hold from Inactive Read
Write Data Valid before Write Active
Write Data Hold after Write Inactive
Chip Selects Valid from Address Valid
Chip Selects Valid from Command Active
Propagation Delay for IRQ/DRQ/DACK
30
RDH
WD
22
25
5
WDH
CSA
CSC
IDD
25
25
25
5
5
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4
Resource Allocation Amongst the Two Logical Devices
Ý
Ý
NM95MS15 supports two Plug n Play logical devices: Logical Device 0, and Logical Device 1. The total resource structure
supported by the NM95MS15 is allocated to each of these logical devices as follows:
Mode ‘‘00’’
Ý
0
Ý
1
Logical Device
Logical Device
1) I/O chipselects
2) Memory chipselects
3) Local IRQ input
4) Local DQR input
IOCS0*
MEMCS0*
IRQIN0
IOCS1*
MEMCS1*
IRQIN1
––
DRQIN0
Mode ‘‘01’’
Ý
0
Ý
1
Logical Device
Logical Device
1) I/O chipselects
2) Memory chipselects
3) Local IRQ input
IOCS0* and IOCS2*
MEMCS0*
IRQIN0
IOCS1* and IOCS3*
MEMCS1*
IRQIN1
Mode ‘‘10’’
Ý
0
Ý
1
Logical Device
Logical Device
1) I/O chipselects
2) Memory chipselects
3) Local IRQ input
4) Local DQR input
IOCS0*
MEMCS0*
IRQIN0
IOCS1*
MEMCS1*
IRQIN1
DRQIN0
DRQIN1
5
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(1) Timings for ISA Read/Write Cycle
TL/D/12394–3
(2) Decode Delay for Chip select Generation
TL/D/12394–4
Note: CMD* means IORD*, IOWR*, SMEMR* and SMEMW*.
(3) Propagation Delay for IRQ/DRQ/DACK
TL/D/12394–5
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6
INTRODUCTION
(Refer to the User’s guide for detailed information). Each of
these modes are discussed below.
The NM95MS15 is a single-chip solution for the ISA Plug
and Play (PnP) specification. It implements the complete
state machine and the necessary logic for supporting con-
figurable Interrupts and DMA channels on the ISA bus for
one logical device. Apart from providing ‘‘PnP’’ capability, it
has built-in EEPROM that eliminates external EEPROM.
This device is available in a space saving 64-pin Thin Quad
Flat Pack (TQFP) package.
Normal DMA Mode
In the Normal DMA mode, support is provided for
A) One on-board DMA request that is switchable to any
three DMA channels on the ISA bus.
B) Two on-board interrupt request lines switchable to any
eight IRQ lines on the ISA bus.
C) Two programmable I/O chip selects for on-board logic.
Functional Description
D) Two programmable Memory chip selects for on-board
logic.
NM95MS15 has three modes of operation, viz, ‘‘Normal
DMA mode’’, ‘‘Extended Interrupt Mode’’ and ‘‘Extended
DMA mode’’. These modes are programmed using the
mode select (MS) bits in one of the configuration registers
Figure 1 shows a Block Diagram of NM95MS15 configured
for Normal DMA Mode.
TL/D/12394–6
FIGURE 1
Extended Interrupt Mode
In the Ext. Int mode, support is provided for:
A) Two on-board interrupt request lines switchable to any eleven IRQ lines on the ISA bus.
B) Four programmable I/O chip selects for on-board logic.
C) Two programmable Memory chip selects for on-board logic.
Figure 2 shows a Block Diagram of NM95MS15 configured for Extended Interrupt Mode.
TL/D/12394–7
FIGURE 2
7
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Extended DMA Mode
C) Two programmable I/O chip selects for on-board logic.
In the Extended DMA mode, support is provided for:
D) Two programmable Memory chip selects for on-board
logic.
A) Two on-board DMA request that is switchable to any
three DMA channels on the ISA bus.
Figure 3 shows a Block Diagram of NM95MS15 configured
for Extended DMA Mode.
B) Two on-board interrupt request lines switchable to any
six IRQ lines on the ISA bus.
TL/D/12394–8
FIGURE 3
Chip Select Generation
EEPROM Programming
Individual I/O or Memory chip select can be generated in
the following two ways:
The entire 8k bits of EEPROM can be programmed through
the ISA bus. The EEPROM can be programmed by putting
the device (NM95MS15) in the Configuration state (as de-
fined in the PnP standard). Under this state 4 registers at
address 0xF0–0xF3 are accessible to program the
EEPROM. The data to be programmed is loaded in register
at address 0xF3 and 0xF2 (LSB and MSB respectively). The
address to be programmed is loaded in register at address
0xF1. The Ninth bit of address for 8k bits of memory is
provided through the register at address 0xF0. Both read
write are possible. The actual operation does not begin until
Go Ahead (GA) bit is set. Programming a word takes ap-
proximately 10 ms. The status of the operation can be
polled by the Status bit. This bit is set when the operation is
in progress and will be reset when complete. The register at
address 0xF0 is the COMMAND register. This is the hand-
shake register in programming the EEPROM and is ex-
plained below in a tabular format.
A) Address Decode only
B) Address Decode qualified by Command (IORD*, IOWR*
or SMEMR*, SMEMW*).
On-Chip EEPROM
NM95MS15 has 8k bits of EEPROM on chip. All the PnP
resource data structure for the logical device is stored in this
EEPROM. Of the 8k bits, 4k bits are available for the logical
device’s external usage. The logical device can access the
EEPROM through a microwire port, which is essentially a
4-wire serial bus. The pins CS, SK, DI & DO follow the exact
timing as the standard microwire bus and are compatible to
the NM93Cxx family of EEPROMs.
[
]
COMMAND register 0xF0 Bit 1:0 - OP Code bits
10 - Read operation
01 - Write operation
[ ]
Bit 2
GA(Go ahead bits)
If set to 1 the programming will continue.
[
]
Bit 6:3 - Reserved, should be 0.
[ ]
Bit 7
[
]
- It provides A8 of the address. A 0:7 is provided by 0xF1 reg.*
[ ]
0x05 Bit 0 - Status/Busy bit during programming
STATUS register
‘‘0’’ is busy, ‘‘1’’ is done.
[ ]
0xF1 Address Register A0–A7
Address Register
Data Register
Data Register
[
0xF2 Data Byte MSB
]
[
0xF3 Data Byte LSB
]
[
]
of register 0xF0 (A8) should be set to 1.
*The PNP resource data portion of the internal memory is at high address. Hence to program that portion, bit
7
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8
9
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Physical Dimensions inches (millimeters) unless otherwise noted
TQFP Packages (VEH)
Order Number NM95MS15VEH
NS Package Number VEH64A
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