PC87391-VJG_技术文档

PRELIMINARY

September 2000

Revision 1.41

PC87391, PC87392, PC87393, PC87393F

100-Pin LPC SuperI/O Devices for Portable Applications

General Description

Outstanding Features

●

National Semiconductor’s PC8739x family of LPC SuperI/O

devices is targeted for a wide range of portable applications.

PC99 and ACPI compliant, the PC8739x family features

an X-Bus Extension for read and write operations over the

X-Bus, a full IEEE 1284 Parallel Port with a Parallel Port Mul-

tiplexer (PPM) for external Floppy Disk Drive (FDD) support,

a Musical Instrument Digital Interface (MIDI) port, and a

Game port. Like all National LPC SuperI/O devices, the

PC8739x offers a single-chip solution to the most commonly

used PC I/O peripherals.

X-Bus Extension for read and write operations

●

LPC bus interface, based on Intel’s LPC Interface Spec-

ification Rev. 1.01, February 1999 (supports CLKRUN

and LPCPD signals) and Intel FWH transactions

●

PC99 and ACPI compliant

●

Serial IRQ support (15 options)

●

Interrupt Serializer (four Parallel IRQs to Serial IRQ)

●

PPM for external FDD signal support

●

The PC8739x family also incorporates: a Floppy Disk Con-

troller (FDC), two enhanced Serial Ports (UARTs), one with

Fast Infrared (FIR, IrDA 1.1 compliant), General-Purpose

Input/Output (GPIO) support for a total of 32 ports, Interrupt

Serializer for Parallel IRQs and an enhanced WATCH-

DOG timer.

MIDI interface compatible with MPU-401 UART mode

●

Game port inputs for up to two joysticks

●

Protection features, including GPIO lock and pin con-

ﬁguration lock

●

32 GPIO ports (16 standard, 16 with Assert IRQ/SMI)

The following features apply to the PC87393F. The feature

lists for other PC8739x devices may differ. See the table on

page 3 for a list of features for each device.

●

5V tolerant and back-drive protected pins (except LPC

bus pins)

●

100-pin TQFP Package

Block Diagram

Parallel Port\

Floppy Drive Interface

PC87393 / PC87393F

Parallel

IRQs

Serial

LPC

Interface IRQ

PPM

Floppy Drive

Interface

I/O

Ports

Serial

Interface

Infrared

Interface Interface

Serial

SMI

Bus

Interface

Serial Port 2

with FIR

Interrupt

Serializer

IEEE 1284

Parallel Port

Floppy Disk

Controller

Serial Port 1

GPIO Ports

V_DD

WATCHDOG

Wake-Up

Control

X-Bus

Extension

MIDI Port

Game Port

Timer

MIDI

Interface

X-Bus Interface

Game Device

Interface

WDO

PWUREQ

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All other brand or product names are trademarks or registered trademarks of their respective holders.

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— Input debounce mechanism

Features

• Floppy Disk Controller (FDC)

• LPC System Interface

— Programmable write protect

— Synchronous cycles, up to 33 MHz bus clock

— FM and MFM mode support

— 8-bit I/O cycles

— Enhanced mode command for three-mode Floppy

— Up to four 8-bit DMA channels

— LPCPD and CLKRUN support

Disk Drive (FDD) support

— Perpendicular recording drive support for 2.88 MB

— Burst and non-burst modes

— Implements PCI mobile design guide recommenda-

tion (PCI Mobile Design Guide 1.1, Dec. 18, 1998)

— Full support for IBM Tape Drive register (TDR) im-

— Memory and FWH transaction support

plementation of AT and PS/2 drive types

• Interrupt Serializer

— 16-byte data FIFO

— Four Parallel IRQs to Serial IRQ

— Error-free handling of data overrun and underrun

— Software compatible with the PC8477, which con-

tains a superset of the FDC functions in the

µDP8473, the NEC µPD765A and the N82077

• Musical Instrument Digital Interface (MIDI) Port

— Compatible with MPU-401 UART mode

— 16-byte Receive and Transmit FIFOs

— Loopback mode support

— High-performance, digital separator

— Standard 5.25” and 3.5” FDD support

— Supports up to four ﬂoppy disk drives

• Game Port

— Supports fast tape drives (2 Mbps) and standard

— Compatible with the Legacy Game Port deﬁnition

tape drives (1 Mbps, 500 Kbps and 250 Kbps)

— Full digital implementation

— Supports external drive via parallel port pins

— Supports up to two analog joysticks

• IEEE 1284 compliant Parallel Port

• X-Bus Extension

— ECP, including Level 2 (14 mA sink and source out-

— Supports read and write operations

put buffers)

— 8-bit data bus

— Software or hardware control

— Up to 28-bit address bus supports up to 256MB data

— Two chip select pins

— Enhanced Parallel Port (EPP) compatible with EPP

1.7 and EPP 1.9

— EPP support as mode 4 of the Extended Control

— Interrupt routing via PIRQ pins

— Supports BIOS ﬂash devices

Register (ECR)

— Selection of internal pull-up or pull-down resistor for

• PC99 and ACPI Compliant

Paper End (PE) pin

— PnP Conﬁguration Register structure

— Flexible resource allocation for all logical devices

❏ Relocatable base address

— Supports a demand DMA mode mechanism and a

DMA fairness mechanism for improved bus utilization

— Protection circuit that prevents damage to the paral-

lel port when a printer connected to it powers up or

is operated at high voltages, even if the device is in

power-down

❏ Fifteen IRQ routing options

❏ Four optional 8-bit DMA channels (where applica-

ble)

— Parallel Port Multiplexer (PPM) to support additional

external FDC signals on parallel port pins for FDD use

• Clock Sources

• Serial Port 1 (SP1)

— 32.768 KHz, 14.318 MHz or 48 MHz clock input

— Software compatible with the 16550A and the 16450

— Shadow register support for write-only bit monitoring

— UART data rates up to 1.5 Mbaud

— LPC clock, up to 33 MHz

• Power Supply

— 3.3V supply operation

• Serial Port 2 with Fast Infrared (SP2 with FIR)

— All pins are 5V tolerant

— Software compatible with the 16550A and the 16450

— Shadow register support for write-only bit monitoring

— UART data rates up to 1.5 Mbaud

— FIR IrDA 1.1 compliant

— All pins are back-drive protected, except LPC bus

pins

• Wake-Up Control

— Optional routing of IRQ to power-up event

— HP-SIR

• 32 General-Purpose I/O (GPIO) Ports

— ASK-IR option of SHARP-IR

— Sixteen standard, with Assert IRQ/SMI for 16 ports

— DASK-IR option of SHARP-IR

— Programmable drive type for each output pin (open-

— Consumer Remote Control supports RC-5, RC-6,

drain, push-pull or output disable)

NEC, RCA and RECS 80

— Programmable option for internal pull-up resistor on

— DMA support − one or two channels

— PnP dongle support

each input pin

— Output lock option

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2

Features (Continued)

• WATCHDOG Timer

• Strap Conﬁguration

— Times out the system based on user-programmable

— Base Address (BADDR) strap to determine the base

time-out period

address of the Index-Data register pair

— System power-down capability for power saving

— User-deﬁned trigger events to restart WATCHDOG

— Test strap to force the device into test mode (re-

served for National Semiconductor use)

— X-Bus straps (XCNF2-0) deﬁne the functionality of

— Optional routing of WATCHDOG output on IRQ

the X-Bus at reset

and/or SMI lines

Device-speciﬁc Information

The following table shows the main features for each device in the PC87393 family.

1

Function

PC87391

PC87392

PC87393 PC87393F

LPC System Interface

✔

Interrupt Serializer

Musical Instrument Digital Interface (MIDI) Port

Game Port

✘

X-Bus Extension

✘

FWH Emulation

✘

PC99 and ACPI Compliant

Wake-Up Control

✔

General-Purpose I/O (GPIO) Ports

Floppy Disk Controller (FDC)

IEEE 1284 compliant Parallel Port

Serial Port 1 (SP1)

✘

✔

Serial Port 2 with Fast Infrared (SP2 with FIR)

WATCHDOG Timer

✔

1.

This datasheet contains notes that are device-speciﬁc. These notes can be found

by searching for the speciﬁc device number.

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3

Features (Continued)

The following set of device-specific Block Diagrams show the modules for each device in the PC87393 family.

Parallel Port\

Floppy Drive Interface

PC87391

Parallel

IRQs

Serial

PPM

Floppy Drive

Interface

LPC

Serial

Interface

Infrared

Interface Interface

Serial

Interface IRQ

SMI

Bus

Interface

Serial Port 2

with FIR

Interrupt

Serializer

IEEE 1284

Parallel Port

Floppy Disk

Controller

Serial Port 1

V_DD

WATCHDOG

Wake-Up

Control

Timer

WDO

PWUREQ

Parallel Port\

Floppy Drive Interface

PC87392

Parallel

IRQs

PPM

Serial

LPC

Interface IRQ

Floppy Drive

Interface

I/O

Ports

Serial

Interface

Infrared

Interface Interface

Serial

SMI

Bus

Interface

Serial Port 2

with FIR

Interrupt

Serializer

IEEE 1284

Parallel Port

Floppy Disk

Controller

Serial Port 1

GPIO Ports

V_DD

WATCHDOG

Wake-Up

Control

Timer

WDO

PWUREQ

Parallel Port\

Floppy Drive Interface

PC87393 / PC87393F

Parallel

IRQs

PPM

Serial

LPC

Interface IRQ

Floppy Drive

Interface

I/O

Ports

Serial

Interface

Infrared

Interface Interface

Serial

SMI

Bus

Interface

Serial Port 2

with FIR

Interrupt

Serializer

IEEE 1284

Parallel Port

Floppy Disk

Controller

Serial Port 1

GPIO Ports

V_DD

WATCHDOG

Wake-Up

Control

X-Bus

Extension

MIDI Port

Game Port

Timer

MIDI

Interface

X-Bus Interface

Game Device

Interface

WDO

PWUREQ

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4

Table of Contents

1.0 Signal/Pin Connection and Description

1.1

1.2

1.3

1.4

1.5

CONNECTION DIAGRAMS ......................................................................................................11

BUFFER TYPES AND SIGNAL/PIN DIRECTORY ....................................................................15

PIN MULTIPLEXING .................................................................................................................15

PARALLEL PORT MULTIPLEXER (PPM) ................................................................................17

DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................18

1.5.1

1.5.2

1.5.3

1.5.4

1.5.5

1.5.6

1.5.7

1.5.8

1.5.9

Bus Interface ...............................................................................................................18

Clock ............................................................................................................................18

Infrared (IR) ................................................................................................................18

Floppy Disk Controller (FDC) .....................................................................................19

Game Port (PC87393 and PC87393F) .......................................................................20

General-Purpose Input/Output (GPIO) Ports (PC87392, PC87393 and PC87393F) 20

Musical Instrument Digital Interface (MIDI) Port (PC87393 and PC87393F) ............20

Parallel Port ................................................................................................................21

Power and Ground .....................................................................................................21

1.5.10 Serial Port 1 and Serial Port 2 (SP1 and SP2) ............................................................22

1.5.11 Strap Configuration ......................................................................................................23

1.5.12 Wake-Up Control .........................................................................................................23

1.5.13 WATCHDOG Timer .....................................................................................................23

1.5.14 X-Bus Extension (PC87393 and PC87393F) .............................................................23

1.6

INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................24

2.0 Device Architecture and Configuration

2.1

2.2

OVERVIEW ...............................................................................................................................26

CONFIGURATION STRUCTURE AND ACCESS .....................................................................26

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

The Index-Data Register Pair ......................................................................................26

Banked Logical Device Registers Structure ................................................................28

Standard Logical Device Configuration Register Definitions .......................................29

Standard Configuration Registers ...............................................................................31

Default Configuration Setup ........................................................................................32

Power States ...............................................................................................................32

Address Decoding .......................................................................................................32

2.3

THE CLOCK MULTIPLIER ........................................................................................................33

2.3.1

2.3.2

2.3.3

2.3.4

Functionality ................................................................................................................33

Chip Power-Up ............................................................................................................33

Disabling the Clock ......................................................................................................33

Specifications ..............................................................................................................33

2.4

2.5

2.6

INTERRUPT SERIALIZER ........................................................................................................34

WAKE-UP CONTROL ...............................................................................................................34

THE PARALLEL PORT MULTIPLEXER (PPM) ........................................................................34

2.6.1

PPM Power Save Mode ..............................................................................................35

2.7

PROTECTION ...........................................................................................................................36

2.7.1

Pin Configuration Lock ................................................................................................36

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Table of Contents (Continued)

2.7.2

GPIO Pin Function Lock ..............................................................................................36

2.8

LPC INTERFACE ......................................................................................................................36

2.8.1

2.8.2

2.8.3

LPC Transactions Supported ......................................................................................36

CLKRUN Functionality .................................................................................................37

LPCPD Functionality ...................................................................................................37

2.9

REGISTER TYPE ABBREVIATIONS ........................................................................................37

2.10 SUPERI/O CONFIGURATION REGISTERS .............................................................................37

2.10.1 SuperI/O ID Register (SID) ..........................................................................................38

2.10.2 SuperI/O Configuration 1 Register (SIOCF1) ..............................................................38

2.10.3 SuperI/O Configuration 2 Register (SIOCF2) ..............................................................39

2.10.4 SuperI/O Configuration 3 Register (SIOCF3) ..............................................................40

2.10.5 SuperI/O Configuration 4 Register (SIOCF4) ..............................................................41

2.10.6 SuperI/O Configuration 5 Register (SIOCF5) ..............................................................42

2.10.7 SuperI/O Configuration 6 Register (SIOCF6) ..............................................................43

2.10.8 SuperI/O Revision ID Register (SRID) ........................................................................43

2.10.9 SuperI/O Configuration 8 Register (SIOCF8) ..............................................................44

2.10.10 SuperI/O Configuration 9 Register (SIOCF9) ..............................................................45

2.10.11 SuperI/O Configuration A Register (SIOCFA) .............................................................46

2.11 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION ........................................................47

2.11.1 General Description .....................................................................................................47

2.11.2 Logical Device 0 (FDC) Configuration .........................................................................47

2.11.3 FDC Configuration Register ........................................................................................48

2.11.4 Drive ID Register .........................................................................................................49

2.12 PARALLEL PORT CONFIGURATION ......................................................................................50

2.12.1 General Description .....................................................................................................50

2.12.2 Logical Device 1 (PP) Configuration ............................................................................51

2.12.3 Parallel Port Configuration Register ............................................................................52

2.13 SERIAL PORT 2 CONFIGURATION .........................................................................................53

2.13.1 General Description .....................................................................................................53

2.13.2 Logical Device 2 (SP2) Configuration ..........................................................................53

2.13.3 Serial Port 2 Configuration Register ............................................................................54

2.14 SERIAL PORT 1 CONFIGURATION .........................................................................................55

2.14.1 Logical Device 3 (SP1) Configuration ..........................................................................55

2.14.2 Serial Port 1 Configuration Register ............................................................................55

2.15 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION ..........................56

2.15.1 General Description .....................................................................................................56

2.15.2 Implementation ............................................................................................................56

2.15.3 Logical Device 7 (GPIO) Configuration .......................................................................57

2.15.4 GPIO Pin Select Register ............................................................................................58

2.15.5 GPIO Pin Configuration Register .................................................................................59

2.15.6 GPIO Event Routing Register ......................................................................................60

2.16 WATCHDOG TIMER (WDT) CONFIGURATION ......................................................................61

2.16.1 Logical Device 10 (WDT) Configuration ......................................................................61

2.16.2 WATCHDOG Timer Configuration Register ................................................................61

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Table of Contents (Continued)

2.17 GAME PORT (GMP) CONFIGURATION ..................................................................................62

2.17.1 Logical Device 11 (GMP) Configuration ......................................................................62

2.17.2 Game Port Configuration Register ..............................................................................62

2.18 MIDI PORT (MIDI) CONFIGURATION ......................................................................................64

2.18.1 Logical Device 12 (MIDI) Configuration .......................................................................64

2.18.2 MIDI Port Configuration Register .................................................................................64

2.19 X-BUS CONFIGURATION .........................................................................................................65

2.19.1 Logical Device 15 (X-Bus) Configuration .....................................................................65

2.19.2 X-Bus I/O Range Programming ...................................................................................65

2.19.3 X-Bus Memory Range Programming ...........................................................................66

2.19.4 X-Bus I/O Configuration Register ................................................................................66

2.19.5 X-Bus I/O Base Address High Byte Register ...............................................................68

2.19.6 X-Bus I/O Base Address Low Byte Register ...............................................................68

2.19.7 X-Bus I/O Size Configuration Register ........................................................................68

2.19.8 X-Bus Memory Configuration Register ........................................................................69

2.19.9 X-Bus Memory Base Address High Byte Register ......................................................69

2.19.10 X-Bus Memory Base Address Low Byte Register .......................................................70

2.19.11 X-Bus Memory Size Configuration Register ................................................................70

2.19.12 X-Bus PIRQA and PIRQB Mapping Register ..............................................................71

2.19.13 X-Bus PIRQC and PIRQD Mapping Register ..............................................................71

3.0 General-Purpose Input/Output (GPIO) Port

3.1

3.2

OVERVIEW ...............................................................................................................................72

BASIC FUNCTIONALITY ..........................................................................................................73

3.2.1

3.2.2

Configuration Options ..................................................................................................73

Operation .....................................................................................................................73

3.3

3.4

EVENT HANDLING AND SYSTEM NOTIFICATION ................................................................74

3.3.1

3.3.2

Event Configuration .....................................................................................................74

System Notification ......................................................................................................74

GPIO PORT REGISTERS .........................................................................................................75

3.4.1

3.4.2

3.4.3

3.4.4

3.4.5

3.4.6

3.4.7

GPIO Pin Configuration (GPCFG) Register ................................................................76

GPIO Pin Event Routing (GPEVR) Register ...............................................................77

GPIO Port Runtime Register Map ...............................................................................77

GPIO Data Out Register (GPDO) ................................................................................78

GPIO Data In Register (GPDI) ....................................................................................78

GPIO Event Enable Register (GPEVEN) ....................................................................79

GPIO Event Status Register (GPEVST) ......................................................................79

4.0 WATCHDOG Timer (WDT)

4.1

4.2

4.3

OVERVIEW ...............................................................................................................................80

FUNCTIONAL DESCRIPTION ..................................................................................................80

WATCHDOG TIMER REGISTERS ...........................................................................................81

4.3.1

4.3.2

4.3.3

WATCHDOG Timer Register Map ...............................................................................81

WATCHDOG Timeout Register (WDTO) ....................................................................81

WATCHDOG Mask Register (WDMSK) ......................................................................82

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Table of Contents (Continued)

4.3.4

WATCHDOG Status Register (WDST) ........................................................................83

4.4

WATCHDOG TIMER REGISTER BITMAP ...............................................................................83

5.0 Game Port (GMP)

5.1

5.2

OVERVIEW ...............................................................................................................................84

FUNCTIONAL DESCRIPTION ..................................................................................................84

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

Game Device Axis Position Indication .........................................................................84

Capturing the Position .................................................................................................85

Button Status Indication ...............................................................................................85

Operation Modes .........................................................................................................86

Operation Control ........................................................................................................87

5.3

GAME PORT REGISTERS .......................................................................................................87

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

Game Port Register Map .............................................................................................87

Game Port Control Register (GMPCTL) ......................................................................88

Game Port Legacy Status Register (GMPLST) ...........................................................89

Game Port Extended Status Register (GMPXST) .......................................................90

Game Port Interrupt Enable Register (GMPIEN) .........................................................91

Game Device A X-Axis Position Low Byte (GMPAXL) ................................................92

Game Device A X-Axis Position High Byte (GMPAXH) ...............................................92

Game Device A Y-Axis Position Low Byte (GMPAYL) ................................................92

Game Device A Y-Axis Position High Byte (GMPAYH) ...............................................92

5.3.10 Game Device B X-Axis Position Low Byte (GMPBXL) ................................................93

5.3.11 Game Device B X-Axis Position High Byte (GMPBXH) ...............................................93

5.3.12 Game Device B Y-Axis Position Low Byte (GMPBYL) ................................................93

5.3.13 Game Device B Y-Axis Position High Byte (GMPBYH) ...............................................93

5.3.14 Game Port Event Polarity Register (GMPEPOL) ........................................................94

5.4

GAME PORT BITMAP ...............................................................................................................95

6.0 Musical Instrument Digital Interface (MIDI) Port

6.1

6.2

OVERVIEW ...............................................................................................................................96

FUNCTIONAL DESCRIPTION ..................................................................................................96

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

6.2.8

6.2.9

Internal Bus Interface Unit ...........................................................................................97

Port Control and Status Registers ...............................................................................97

Data Buffers and FIFOs ...............................................................................................97

MIDI Communication Engine .......................................................................................97

MIDI Signals Routing Control Logic .............................................................................98

Operation Modes .........................................................................................................98

MIDI Port Status Flags ................................................................................................99

MIDI Port Interrupts ...................................................................................................100

Enhanced MIDI Port Features ...................................................................................101

6.3

MIDI PORT REGISTERS ........................................................................................................102

6.3.1

6.3.2

6.3.3

6.3.4

MIDI Port Register Map .............................................................................................102

MIDI Data In Register (MDI) ......................................................................................102

MIDI Data Out Register (MDO) .................................................................................102

MIDI Status Register (MSTAT) ..................................................................................103

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Table of Contents (Continued)

6.3.5

6.3.6

MIDI Command Register (MCOM) ............................................................................103

MIDI Control Register (MCNTL) ................................................................................104

6.4

MIDI PORT BITMAP ................................................................................................................105

7.0 X-Bus Extension

7.1

7.2

7.3

OVERVIEW .............................................................................................................................106

IRQ ROUTING .........................................................................................................................106

X-BUS TRANSACTIONS .........................................................................................................106

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.6

Programmable I/O Range Chip Select ......................................................................107

LPC and FWH Address to X-Bus Address Translation .............................................107

Extended Read/Write Signal Mode ...........................................................................108

Indirect Memory Read and Write Transaction ...........................................................108

Normal Address Mode X-Bus Transactions ..............................................................108

Latched Address Mode X-Bus Transactions .............................................................110

7.4

X-BUS CONFIGURATION REGISTERS .................................................................................112

7.4.1

7.4.2

7.4.3

7.4.4

7.4.5

7.4.6

7.4.7

7.4.8

7.4.9

X-Bus Register Map ..................................................................................................112

X-Bus Configuration Register (XBCNF) ....................................................................112

X-Bus Select 0 Configuration Register (XZCNF0) .....................................................114

X-Bus Select 1 Configuration Register (XZCNF1) .....................................................115

X-Bus PIRQx Input Registers (XIRQCA to XIRQCD) ................................................116

X-Bus Indirect Memory Address Register 0 (XIMA0) ................................................117

X-Bus Indirect Memory Address Register 1 (XIMA1) ................................................117

X-Bus Indirect Memory Address Register 2 (XIMA2) ................................................118

X-Bus Indirect Memory Address Register 3 (XIMA3) ................................................118

7.4.10 X-Bus Indirect Memory Data Register (XIMD) ...........................................................118

USAGE HINTS .......................................................................................................................118

X-BUS EXTENSION BITMAP ..................................................................................................120

7.5

7.6

8.0 Legacy Functional Blocks

8.1

8.2

8.3

FLOPPY DISK CONTROLLER (FDC) .....................................................................................121

8.1.1

8.1.2

8.1.3

General Description ...................................................................................................121

FDC Register Map .....................................................................................................121

FDC Bitmap Summary ...............................................................................................122

PARALLEL PORT ....................................................................................................................123

8.2.1

8.2.2

8.2.3

General Description ...................................................................................................123

Parallel Port Register Map .........................................................................................123

Parallel Port Bitmap Summary ..................................................................................124

UART FUNCTIONALITY (SP1 AND SP2) ...............................................................................126

8.3.1

8.3.2

8.3.3

8.3.4

General Description ...................................................................................................126

UART Mode Register Bank Overview .......................................................................126

SP1 and SP2 Register Maps for UART Functionality ................................................127

SP1 and SP2 Bitmap Summary for UART Functionality ...........................................129

8.4

IR FUNCTIONALITY (SP2) .....................................................................................................131

8.4.1

General Description ...................................................................................................131

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Table of Contents (Continued)

8.4.2

8.4.3

8.4.4

IR Mode Register Bank Overview .............................................................................131

SP2 Register Map for IR Functionality ......................................................................132

SP2 Bitmap Summary for IR Functionality ................................................................133

9.0 Device Characteristics

9.1

GENERAL DC ELECTRICAL CHARACTERISTICS ...............................................................135

9.1.1

9.1.2

9.1.3

9.1.4

Recommended Operating Conditions .......................................................................135

Absolute Maximum Ratings .......................................................................................135

Capacitance ..............................................................................................................135

Power Consumption under Recommended Operating Conditions ............................135

9.2

DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES ................................................135

9.2.1

9.2.2

9.2.3

9.2.4

9.2.5

9.2.6

9.2.7

9.2.8

9.2.9

Input, CMOS Compatible ...........................................................................................136

Input, PCI 3.3V ..........................................................................................................136

Input, Strap Pin ..........................................................................................................136

Input, TTL Compatible ...............................................................................................136

Input, TTL Compatible with Schmitt Trigger ..............................................................137

Output, PCI 3.3V .......................................................................................................137

Output, Totem-Pole Buffer .........................................................................................137

Output, Open-Drain Buffer .........................................................................................137

Exceptions .................................................................................................................137

9.3

9.4

INTERNAL RESISTORS .........................................................................................................138

9.3.1

9.3.2

Pull-Up Resistor .........................................................................................................138

Pull-Down Resistor ....................................................................................................138

AC ELECTRICAL CHARACTERISTICS ..................................................................................139

9.4.1

9.4.2

9.4.3

9.4.4

9.4.5

9.4.6

9.4.7

9.4.8

9.4.9

AC Test Conditions ....................................................................................................139

Clock Timing ..............................................................................................................139

LCLK and LRESET ....................................................................................................140

LPC and SERIRQ Signals .........................................................................................141

Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing ...........................142

Modem Control Timing ..............................................................................................143

FDC Write Data Timing .............................................................................................143

FDC Drive Control Timing .........................................................................................144

FDC Read Data Timing .............................................................................................144

9.4.10 Standard Parallel Port Timing ....................................................................................145

9.4.11 Enhanced Parallel Port Timing ..................................................................................145

9.4.12 Extended Capabilities Port (ECP) Timing ..................................................................146

9.4.13 X-Bus Signals (PC87393 and PC87393F only) ......................................................147

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10

1.0 Signal/Pin Connection and Description

1.1 CONNECTION DIAGRAMS

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

PD1/TRK0

SIN2

RTS2

SOUT2

CTS2

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

76

77

78

79

80

81

82

83

84

85

INIT/DIR

PD2/WP

SLIN_ASTRB/STEP

PD3/RDATA

PD4/DSKCHG

DTR2_BOUT2

RI2

NC

PD5/MSEN0

PD6/DRATE0

PD7/MSEN1

ACK/DR1

NC

MTR1

NC

BUSY_WAIT/MTR1

VDD

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

1

NC

VDD

VSS

PE/WDATA

PC87391-VJG

VSS

(XCNF2) NC

SLCT/WGATE

PNF

DRATE0/IRSL2

DENSEL

INDEX

NC

MTR0

DR0

DIR

STEP

WDATA

WGATE

2

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

NC - Not Connected (these pins should be left unconnected)

Thin Quad Flatpack (TQFP), JEDEC

Order Number PC87391-VJG

See NS Package Number VLJ100A

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11

1.0 Signal/Pin Connection and Description (Continued)

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

PD1/TRK0

GPIO15/SIN2

GPIO14/RTS2

GPIO13/SOUT2

GPIO12/CTS2

GPIO11/DTR2_BOUT2

GPIO10/RI2

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

76

77

78

79

80

81

82

83

84

85

INIT/DIR

PD2/WP

SLIN_ASTRB/STEP

PD3/RDATA

PD4/DSKCHG

GPIO33

PD5/MSEN0

PD6/DRATE0

PD7/MSEN1

ACK/DR1

GPIO32

GPIO31/MTR1

GPIO30

GPIO27

GPIO26

VDD

BUSY_WAIT/MTR1

VDD

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

1

VSS

PE/WDATA

PC87392-VJG

VSS

(XCNF2) NC

GPIO24

GPIO23

GPIO22

GPIO21

GPIO20

GPIO07

GPIO06

GPIO05

GPIO04

GPIO03

SLCT/WGATE

PNF

DRATE0/IRSL2

DENSEL

INDEX

MTR0

DR0

DIR

STEP

WDATA

WGATE

2

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

NC - Not Connected (these pins should be left unconnected)

Thin Quad Flatpack (TQFP), JEDEC

Order Number PC87392-VJG

See NS Package Number VJG100A

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12

1.0 Signal/Pin Connection and Description (Continued)

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

PD1/TRK0

GPIO15/JOYAX/SIN2/XA17

GPIO14/JOYBX/RTS2/XA16

GPIO13/JOYBY/SOUT2/XA15

GPIO12/JOYAY/CTS2/XA14

GPIO11/JOYBBTN1/DTR2_BOUT2/XA13

GPIO10/JOYABTN1/RI2/XA12

GPIO33/XIOWR/MDTX/XA11

GPIO32/XIORD/MDRX/XA10

GPIO31/MTR1/PIRQD/XA9

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

76

77

78

79

80

81

82

83

84

85

INIT/DIR

PD2/WP

SLIN_ASTRB/STEP

PD3/RDATA

PD4/DSKCHG

PD5/MSEN0

PD6/DRATE0

PD7/MSEN1

ACK/DR1

GPIO30/PIRQC/XA8

GPIO27/PIRQB/XA7

GPIO26/PIRQA/XSTB2/XA6

VDD

BUSY_WAIT/MTR1

VDD

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

1

VSS

PE/WDATA

PC87393-VJG

VSS

XSTB1/XCNF2/XA5

GPIO24/XSTB0/XA4

GPIO23/XA3

SLCT/WGATE

PNF/XRDY

DRATE0/IRSL2

DENSEL

INDEX

GPIO22/XA2

GPIO21/XA1

MTR0

DR0

GPIO20/XA0

GPIO07/JOYABTN0/XD7

GPIO06/JOYBBTN0/XD6

GPIO05/JOYAX/XD5

GPIO04/JOYBX/XD4

GPIO03/JOYBY/XD3

DIR

STEP

WDATA

WGATE

2

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

NC - Not Connected (these pins should be left unconnected)

Thin Quad Flatpack (TQFP), JEDEC

Order Number PC87393-VJG

See NS Package Number VJG100A

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13

1.0 Signal/Pin Connection and Description (Continued)

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

PD1/TRK0

GPIO15/JOYAX/SIN2/XA17

GPIO14/JOYBX/RTS2/XA16

GPIO13/JOYBY/SOUT2/XA15

GPIO12/JOYAY/CTS2/XA14

GPIO11/JOYBBTN1/DTR2_BOUT2/XA13

GPIO10/JOYABTN1/RI2/XA12

GPIO33/XIOWR/MDTX/XA11

GPIO32/XIORD/MDRX/XA10

GPIO31/MTR1/PIRQD/XA9

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

76

77

78

79

80

81

82

83

84

85

INIT/DIR

PD2/WP

SLIN_ASTRB/STEP

PD3/RDATA

PD4/DSKCHG

PD5/MSEN0

PD6/DRATE0

PD7/MSEN1

ACK/DR1

GPIO30/PIRQC/XA8

GPIO27/PIRQB/XA7

GPIO26/PIRQA/XSTB2/XA6

VDD

BUSY_WAIT/MTR1

VDD

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

1

VSS

PE/WDATA

PC87393F-VJG

VSS

XSTB1/XCNF2/XA5

GPIO24/XSTB0/XA4

GPIO23/XA3

SLCT/WGATE

PNF/XRDY

DRATE0/IRSL2

DENSEL

INDEX

GPIO22/XA2

GPIO21/XA1

MTR0

DR0

GPIO20/XA0

GPIO07/JOYABTN0/XD7

GPIO06/JOYBBTN0/XD6

GPIO05/JOYAX/XD5

GPIO04/JOYBX/XD4

GPIO03/JOYBY/XD3

DIR

STEP

WDATA

WGATE

2

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

NC - Not Connected (these pins should be left unconnected)

Thin Quad Flatpack (TQFP), JEDEC

Order Number PC87393-VJG

See NS Package Number VJG100A

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14

1.0 Signal/Pin Connection and Description (Continued)

1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY

The signal DC characteristics are denoted by a buffer type symbol, described briefly below and in further detail in Section

9.2. The pin multiplexing information refers to three different types of multiplexing:

●

Multiplexed, denoted by a slash (/) between pins in the diagram in Section 1.1. Pins are shared between two different

functions. Each function is associated with different board connectivity, and normally, the function selection is deter-

mined by the board design and cannot be changed dynamically. The multiplexing options must be conﬁgured by the

BIOS upon power-up, in order to comply with the board implementation.

●

Multiple Mode, denoted by an underscore (_) between pins in the diagram in Section 1.1. Pins have two or more

modes of operation within the same function. These modes are associated with the same external (board) connectiv-

ity. Mode selection may be controlled by the device driver, through the registers of the functional block, and do not

require a special BIOS setup upon power-up. These pins are not considered multiplexed pins from the SuperI/O con-

ﬁguration perspective. The mode selection method (registers and bits) as well as the signal speciﬁcation in each

mode, are described within the functional description of the relevant functional block.

●

Parallel Port Multiplexer, denoted by a slash (/) between pins in the diagram in Section 1.1. Parallel Port pins can be

used to support external Floppy Disk Controller signals when the PPM is enabled and bit 7 of the SuperI/O Conﬁgu-

ration 5 register (SIOCF5) is cleared. See Table 3 for a summary of all PPM options.

Table 1. Buffer Types

Symbol

IN_C

Description

Input, CMOS compatible

Input, PCI 3.3V

IN_PCI

IN_STRP

IN_T

Input, Strap pin with weak pull-down during strap time

Input, TTL compatible

IN_TS

O_PCI

O_p/n

Input, TTL compatible with Schmidt Trigger

Output, PCI 3.3V

Output, push-pull buffer that is capable of sourcing p mA and sinking n mA

OD_n

Output, open-drain output buffer that is capable of sinking n mA

PWR

GND

Power pin

Ground pin

1.3 PIN MULTIPLEXING

Table 2 groups all multiplexed PC8739x pins in their associated functional blocks, and provides links to the relevant config-

uration registers and bit values for selecting multiplexed options.

Table 2. Pin Multiplexing Conﬁguration

Functional

Block

Functional

Block

Functional

Block

Functional

Block

Conﬁg

Section

Signal

GPIO00

Signal

XD0

Signal

GPIO

X-Bus

Game Port

JOYABTN1

JOYBBTN1

JOYAY

2.10.3

GPIO01

GPIO02

GPIO03

GPIO04

GPIO05

GPIO06

XD1

XD2

XD3

XD4

XD5

XD6

2.10.3

JOYBY

JOYBX

JOYAX

JOYBBTN0

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15

1.0 Signal/Pin Connection and Description (Continued)

Functional

Block

Functional

Block

Functional

Block

Functional

Block

Conﬁg

Section

Signal

GPIO07

Signal

XD7

Signal

GPIO

X-Bus

LPC Bus

FDC

Game Port

Serial Port

JOYABTN0

RI2

2.10.3

Game Port JOYABTN1 2.10.3

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO20

GPIO21

GPIO22

GPIO23

GPIO24

GPIO25

GPIO26

GPIO27

GPIO30

GPIO31

GPIO32

GPIO33

GPIO34

GPIO35

GPIO36

GPIO37

XCS1

XA12

XA13

XA14

XA15

XA16

XA17

XA18

XA19

XA0

DTR2_BOUT2 Game Port JOYBBTN1 2.10.3

CTS2

SOUT2

RTS2

SIN2

Game Port JOYAY

Game Port JOYBY

Game Port JOYBX

Game Port JOYAX

2.10.3

DSR2

DCD2

Game Port JOYBBTN0 2.10.3

Game Port JOYABTN0 2.10.3

2.10.3

XA1

XA2

XA3

XA4

X-Bus

XSTB0

XRDY

XCS0

XA6

X-Bus

FDC

DR1

2.10.5

2.10.3

2.10.4

2.10.5

2.10.6

2.10.5

X-Bus

PIRQA

PIRQB

PIRQC

PIRQD

MDRX

MDTX

X-Bus

XSTB2

XA7

X-Bus

XA8

X-Bus

XA9

X-Bus

FDC

MTR1

XA10

XA11

XRD

SMI

MIDI Port

X-Bus

XIORD

XIOWR

WATCHDOG WDO

CLKRUN

DR1

FIR

IRSL2

X-Bus

XIORD

XIOWR

FDC

MTR1

FDC

DRATE0

Wake-Up

Control

PWUREQ

DRATE0

FIR

IRSL3

2.10.11

2.10.6

FDC

IRSL2

BADDR

XCNF0

TEST

Serial Port DTR1_BOUT1 Strap

Serial Port SOUT1

Serial Port RTS1

Strap

X-Bus

XWR

XCNF1

XRDY

Parallel Port PNF

2.10.6

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16

1.0 Signal/Pin Connection and Description (Continued)

1.4 PARALLEL PORT MULTIPLEXER (PPM)

The Floppy Disk Controller (FDC) signals in Table 3 are directed to the associated Parallel Port (PP) pins either when the

PNF signal is low and bits 6-5 of the SuperI/O Configuration 5 register (SIOCF5) are set to 01, or when the PNF signal is

high and bits 6-5 are set to 10.

Table 3. FDC Signals on Parallel Port Pins

Parallel Port Pin

FDC Signal

INDEX

PD0

PD1

TRK0

PD2

WP

PD3

RDATA

DSKCHG

MSEN0

DRATE0

MSEN1

STEP

PD4

PD5

PD6

PD7

SLIN_ASTRB

AFD_DSTRB

INIT

DENSEL/DRATE1

DIR

ACK

DR1

ERR

HDSEL

WGATE

WDATA

MTR1

SLCT

PE

BUSY_WAIT

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17

1.0 Signal/Pin Connection and Description (Continued)

1.5 DETAILED SIGNAL/PIN DESCRIPTIONS

This section describes all the signals used in the PC8739x family. Some members of the PC8739x family implement

a subset of these signals. Refer to the table on page 3 to identify the functions relevant to a specific device.

1.5.1

Bus Interface

Pin(s) I/O Buffer Type Power Well

Signal

Description

LAD3-0

18-15

I/O IN_PCI/O_PCI

V_DD

LPC Address-Data. Multiplexed command, address bi-

directional data and cycle status.

LCLK

8

I

O

I

IN_PCI

O_PCI

IN_PCI

V_DD

LPC Clock. Same 33 MHz clock as the PCI clock.

LDRQ

11

12

LPC DMA Request. Encoded DMA request for LPC interface.

LFRAME

LPC Frame. Low pulse indicates the beginning of new LPC

cycle or termination of a broken cycle.

LRESET

SERIRQ

9

I

IN_PCI

V_DD

LPC Reset. Practically the PCI system reset.

10

I/O IN_PCI/O_PCI

Serial IRQ. The interrupt requests are serialized over a single

pin, where each IRQ level is delivered during a designated time

slot.

SMI

19

7

OD

I

OD₁₂

IN_PCI

V_DD

System Management Interrupt

LPCPD

Power Down. Indicates that power is going to be shut on the

LPC interface.

CLKRUN

6

I/OD IN_PCI/OD₁₂

V_DD

Clock Run. Indicates that LCLK is going to be stopped, and

requests full-speed LCK (same as PCI CLKRUN).

1.5.2

Clock

Signal

Pin(s) I/O Buffer Type Power Well

Description

CLKIN

20

I

IN_T

V_DD

Clock In. Active clock input signal of 32.768 KHz, 14.318 MHz or

48 MHz.

1.5.3

Infrared (IR)

Signal

IRRX1

Pin/s I/O Buffer Type Power Well

Description

69

I

IN_TS

V_DD

IR Receive 1. Primary input to receive serial data from the IR

transceiver. Monitored during power-off for wake-up event

detection.

IRRX2_IRSL0 68

I/O

IN_TS/O_3/6

IN_T/O_3/6

IN_T

V_DD

IRRX2 - IR Receive 2. Auxiliary IR receiver input to support a

second transceiver. Monitored during power-off for wake-up event

detection.

IRSL1

IRSL2

IRSL3

67

IRSL3-0 IR Select. Outputs are used to control the IR transceivers.

Input for PnP identiﬁcation of plug-in IR transceiver (dongle).

71, 34 I/O

66

I

After reset, the dual function IRSLX pins wake up in input mode.

After the ID is read by the IR driver, these pins can be put into

output mode. The output mode is controlled by Serial Port 2.

IRTX

70

O

O_6/12

V_DD

IR Transmit. IR serial output data.

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18

1.0 Signal/Pin Connection and Description (Continued)

1.5.4

Floppy Disk Controller (FDC)

Pin(s) I/O Buffer Type Power Well

Signal

Description

DENSEL

33, 53

O

O_2/12

OD₁₂, O_2/12

O_3/6

V_DD

Density Select. Indicates that a high FDC density data rate (500

Kbps, 1 Mbps or 2 Mbps) or a low density data rate (250 or 300

Kbps) is selected.

DIR

29, 49

Direction. Determines the direction of the Floppy Disk Drive

(FDD) head movement (active = step in, inactive = step out)

during a seek operation.

DR1

41, 71,

72

30

Drive Select. Decoded output signals in 2-drive mode, or

encoded signals in 4-drive mode. Controlled by bits 1 and 0 of the

Digital Output register (DOR).

DR0

DRATE0

34, 73

Data Rate 0. Reflects the value of bit 0 of the Configuration Control

register (CCR) or the Data Rate Select register (DSR), whichever

was written to last.

DRATE1

53

O_3/6

Data Rate 1. Reflects the value of bit 1 of the Configuration Control

register (CCR) or the Data Rate Select register (DSR), whichever

was written to last. Available on the PPM pins only.

DSKCHG

HDSEL

21, 45

22, 51

I

IN_T

V_DD

Disk Change. Indicates if the drive door has been opened.

O

OD₁₂, O_2/12

Head Select. Determines which side of the FDD is accessed.

Active low selects side 1, inactive selects side 0.

INDEX

32, 52

I

IN_T

V_DD

Index. Indicates the beginning of an FDD track.

MSEN1, 0 42, 44

Automatic Media Sense. Identiﬁes the media type of the ﬂoppy

disk in drive 1 and 0, if the drive supports this protocol.

MTR1

84, 73,

40

31

O

OD₁₂, O_2/12

V_DD

Motor Select. Active low, motor enable lines for drive 1 and 0,

controlled by bits D7-4 of the Digital Output register (DOR). MTR0 is

used to decode DR1 and DR0 in 4-drive mode.

MTR0

RDATA

23, 46

28, 47

I

IN_T

V_DD

Read Data. Raw serial input data stream read from the FDD.

STEP

O

OD₁₂, O_2/12

Step. Issues pulses to the FDD at a software programmable rate

to move the head during a seek operation.

TRK0

25, 50

27, 37

26, 36

I

IN_T

V_DD

Track 0. Indicates to the controller that the head of the selected

FDD is at track 0.

WDATA

WGATE

O

OD₁₂, O_2/12

Write Data. Carries out the pre-compensated serial data that is

written to the FDD. Pre-compensation is software selectable.

Write Gate. Enables the write circuitry of the selected FDD.

WGATE is designed to prevent glitches during power-up and

power-down. This prevents writing to the disk when power is

cycled.

WP

24, 48

I

IN_T

V_DD

Write Protected. Indicates that the disk in the selected drive is

write protected.

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19

1.0 Signal/Pin Connection and Description (Continued)

1.5.5

Game Port (PC87393 and PC87393F)

Pin(s) I/O Buffer Type Power Well

Signal

Description

JOYAX

JOYAY

98, 76 I/O IN_TS/OD₁₂

1, 79 I/O IN_TS/OD₁₂

V_DD

Joystick A X-Axis. Indicates X-axis position of joystick .

Joystick A Y-Axis. Indicates Y-axis position of joystick A

Joystick A Button 0. Indicates button 0 status of joystick A

Joystick A Button 1. Indicates button 1 status of joystick A

Joystick B X-Axis. Indicates X-axis position of joystick B

Joystick BY-Axis. Indicates Y-axis position of joystick B

Joystick B Button 0. Indicates button 0 status of joystick B

Joystick B Button 1. Indicates button 1 status of joystick B

JOYABTN0 96, 74

JOYABTN1 3, 81

I

IN_TS

JOYBX

JOYBY

99, 77 I/O IN_TS/OD₁₂

100, 78 I/O IN_TS/OD₁₂

JOYBBTN0 97, 75

JOYBBTN1 2, 80

I

IN_TS

1.5.6

General-Purpose Input/Output (GPIO) Ports (PC87392, PC87393 and PC87393F)

Signal

Pin/s I/O Buffer Type Power Well

Description

GPIO00-07 3, 2, 1, I/O

IN_TS

OD₆, O_3/6

/

V_DD

General-Purpose I/O Port 0, bits 0-7. Each pin is configured in-

dependently as input or I/O, with or without static pull-up, and with

either open-drain or totem-pole output type. The port support inter-

rupt assertion and each pin can be enabled or masked as an inter-

rupt source.

100, 99,

98, 97,

96

GPIO10-17 81, 80, I/O

IN_TS

OD₆, O_3/6

/

V_DD

79, 78,

77, 76,

75, 74

General-Purpose I/O Port 1, bits 0-7. Same as Port 0.

GPIO20-27 95, 94, I/O

IN_TS

/

93, 92,

91, 72,

87, 86

General-Purpose I/O Port 2, bits 0-7. Same as Port 0, without

interrupt support.

OD₆, O_3/6

GPIO30-37 85, 84, I/O

IN_TS

/

83, 82,

5, 19, 6,

71

General-Purpose I/O Port 3, bits 0-7. Same as Port 0, without

interrupt support.

OD₆, O_3/6

1.5.7

Musical Instrument Digital Interface (MIDI) Port (PC87393 and PC87393F)

Pin(s) I/O Buffer Type Power Well Description

Signal

MDTX

MDRX

82

83

O

I

O_3/6

IN_TS

V_DD

MIDI Transmit. MIDI serial data output

MIDI Receive. MIDI serial data input

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20

1.0 Signal/Pin Connection and Description (Continued)

1.5.8

Parallel Port

Signal

Pin/s

41

I/O Buffer Type Power Well

Description

ACK

I

IN_T

V_DD

Acknowledge. Pulsed low by the printer to indicate that it has

received data from the Parallel Port.

AFD_DSTRB 53

O

OD₁₄, O_14/14

AFD - Automatic Feed. When low, instructs the printer to

automatically feed a line after printing each line. This pin is in

TRI-STATE after a 0 is loaded into the corresponding control

register bit. An external 4.7 KΩ pull-up resistor should be

attached to this pin.

DSTRB - Data Strobe (EPP). Active low, used in EPP mode

to denote a data cycle. When the cycle is aborted, DSTRB

becomes inactive (high).

BUSY_WAIT 40

I

IN_T

V_DD

Busy. Set high by the printer when it cannot accept another

character.

Wait. In EPP mode, the Parallel Port device uses this active

low signal to extend its access cycle.

ERR

INIT

51

49

I

IN_T

V_DD

Error. Set active low by the printer when it detects an error.

O

OD₁₄, O_14/14

Initialize. When low, initializes the printer. This signal is in

TRI-STATE after a 1 is loaded into the corresponding control

register bit. Use an external 4.7 KΩ pull-up resistor.

PD7-3,

PD2, PD1

PD0

42-46,

48, 50,

52

I/O

IN_T

O_14/14

V_DD

Parallel Port Data. Transfer data to and from the peripheral

data bus and the appropriate Parallel Port data register. These

signals have a high current drive capability.

PE

37

I

IN_T

V_DD

Paper End. Set high by the printer when it is out of paper. This

pin has an internal weak pull-up or pull-down resistor.

SLCT

36

Select. Set active high by the printer when the printer is

selected.

SLIN_ASTRB 47

STB_WRITE 54

O

OD₁₄, O_14/14

SLIN - Select Input. When low, selects the printer. This signal

is in TRI-STATE after a 0 is loaded into the corresponding

control register bit. Uses an external 4.7 KΩ pull-up resistor.

ASTRB - Address Strobe (EPP). Active low, used in EPP

mode to denote an address or data cycle. When the cycle is

aborted, ASTRB becomes inactive (high).

O

OD₁₄, O_14/14

V_DD

STB - Data Strobe. When low, Indicates to the printer that

valid data is available at the printer port. This signal is in TRI-

STATE after a 0 is loaded into the corresponding control

register bit. An external 4.7 KΩ pull-up resistor should be

employed.

WRITE - Write Strobe. Active low, used in EPP mode to

denote an address or data cycle. When the cycle is aborted,

WRITE becomes inactive (high).

PNF

35

I

IN_T

V_DD

Printer Not Floppy. This signal selects the internal logical

device that is connected to the PPM pins. For details on

setting PNF polarity, see Section 2.10.6.

1.5.9

Power and Ground

Signal

V_DD

Pin/s I/O Buffer Type Power Well

Description

14, 39,

63, 88

I

PWR

GND

-

Main 3.3V Power Supply

V_SS

13, 38,

64, 89

Ground

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1.0 Signal/Pin Connection and Description (Continued)

1.5.10 Serial Port 1 and Serial Port 2 (SP1 and SP2)

Signal

CTS1

Pin/s I/O Buffer Type Power Well

Description

60

79

I

IN_TS

O_3/6

V_DD

Clear to Send. When low, indicate that the modem or other data

transfer device is ready to exchange data.

CTS2

DCD1

DCD2

55

74

Data Carrier Detected. When low, indicate that the modem or

other data transfer device has detected the data carrier.

DSR1

DSR2

56

75

I

Data Set Ready. When low, indicate that the data transfer device,

e.g., modem, is ready to establish a communications link.

DTR1_

BOUT1

61

O

Data Terminal Ready. When low, indicate to the modem or other

data transfer device that the UART is ready to establish a

communications link. After a system reset, these pins provide the

DTR function and set these signals to inactive high. Loopback

operation holds them inactive.

DTR2_

BOUT2

80

Baud Output. Provides the associated serial channel baud rate

generator output signal if test mode is selected, i.e., bit 7 of the

EXCR1 register is set.

DTR1_BOUT1 is used also as BADDR.

RI1

RI2

62

81

I

IN_TS

V_DD

Ring Indicator. When low, indicate that a telephone ring signal

has been received by the modem. They are monitored during

power-off for wake-up event detection.

RTS1

RTS2

58

77

O

O_3/6

V_DD

Request to Send. When low, indicate to the modem or other data

transfer device that the corresponding UART is ready to exchange

data. A system reset sets these signals to inactive high, and

loopback operation holds them inactive.

RTS1 is used also as TEST.

SIN1

SIN2

57

76

I

IN_TS

V_DD

Serial Input. Receive composite serial data from the

communications link (peripheral device, modem or other data

transfer device).

SOUT1

SOUT2

59

78

O

O_3/6

V_DD

Serial Output. Send composite serial data to the communications

link (peripheral device, modem or other data transfer device).

These signals are set active high after a system reset.

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1.0 Signal/Pin Connection and Description (Continued)

1.5.11 Strap Configuration

Signal

BADDR

Pin/s I/O Buffer Type Power Well

Description

61

I

IN_STRP

V_DD

Base Address. Sampled at Reset to determine the base

address of the conﬁguration Index-Data register pair, as follows.

No pull-up resistor:

2Eh-2Fh

10K external pull-up resistor: 4Eh-4Fh

TEST

58

I

IN_STRP

V_DD

Test. Forces the device into test mode if an external pull-up

resistor is connected. Otherwise, the pin is pulled to ‘0’ (zero) by

the internal resistor.

XCNF2-0

90, 4,

59

IN_STRP

V_DD

X-Bus Reset Conﬁguration Mode. Forces the X-Bus

transaction to be in one of the following modes: no BIOS, normal

or latch. For details, see Chapter 7.

Pins

2 1 0

Functionality

x 0 0 No BIOS¹

x 0 1 Normal Mode, XRDY disabled

0 1 0 Latch Mode, XA12-19, XRDY enabled

1 1 0 Latch Mode, GPIO10-17, XRDY enabled

0 1 1 Latch Mode, XA12-19, XRDY disabled

1 1 1 Latch Mode, GPIO10-17, XRDY disabled

Pulled to 0 by internal resistor, or set to 1 by external 10K pull-up

resistor.

1.

In the PC87391 and PC87392, the XCNFi signals must be set to this value. This is value is guaranteed by

the internal pull-down resistors, as long as the pins are not connected, or the load is small enough.

1.5.12 Wake-Up Control

Signal

Pin/s I/O Buffer Type Power Well

Description

PWUREQ 66

O

OD₆

V_DD

Power-Up Request. Active (low) level indicates that wake-up

event has occurred, and causes the chipset to turn the power

supply on, or to exit its current sleep state.

1.5.13 WATCHDOG Timer

Signal

WDO

Pin/s I/O Buffer Type Power Well

OD₆, O_3/6V_DD

Description

5

O

WATCHDOG Out. Low level indicates that the WATCHDOG Timer

has reached its time-out period without being retriggered.

The output type and an optional pull-up are conﬁgurable.

1.5.14 X-Bus Extension (PC87393 and PC87393F)

Signal

XRD

Pin/s I/O Buffer Type Power Well

Description

5

O

O_3/6

V_DD

Read. Active (low) level indicates read cycle on the X-Bus

Extension.

XWR

4

Write. Active (low) level indicates write cycle on the X-Bus

Extension.

XIORD

83, 71

I/O Read. Active (low) level indicates I/O read cycle on the X-Bus

Extension. This signal is for devices that require separate

read/write inputs for memory and I/O.

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1.0 Signal/Pin Connection and Description (Continued)

Signal

XIOWR

Pin/s I/O Buffer Type Power Well

Description

82, 73

O

O_3/6

V_DD

I/O Write. Active (low) level indicates I/O write cycle on the X-Bus

Extension. This signal is for devices that require separate

read/write inputs for memory and I/O.

XD7-0

96, 97, I/O

98, 99,

100, 1,

2, 3

IN_TS/O_3/6

V_DD

Data Bus

XA19-0

XCS1-0

74-95

O

O_3/6

V_DD

Address Bus

73, 72

Chip Select. These signals control the selection of up to two

chips residing on the X-Bus Extension.

XSTB2-0

87, 90,

91

O

O_3/6

V_DD

Assert Strobe. These signals control the selection of up to three

external latch devices for X-Bus Latched Address Mode

transactions.

XRDY

72, 35

87-84

I

IN_TS

V_DD

I/O Ready. This signal indicates to the PC87393 to extend the

access cycles.

PIRQA-D

Parallel Interrupt. Convert parallel interrupts into serial interrupts

by means of the Interrupt Serializer (The interrupt number

associated with each signal is a part of the system conﬁguration.)

1.6 INTERNAL PULL-UP AND PULL-DOWN RESISTORS

The signals listed in Table 4 can optionally support internal pull-up (PU) and/or pull-down (PD) resistors. See Section 9.3 for

the values of each resistor type.

Table 4. Internal Pull-Up and Pull-Down Resistors

Signal

Pin/s

Type

Comments

Game Port (GMP) (PC87393 and PC87393F)

PU₂₅

JOYABTN0

JOYABTN1

JOYBBTN0

JOYBBTN1

Programmable

General-Purpose Input/Output (GPIO) Ports

(PC87392, PC87393 and PC87393F)

PU₂₅

GPIO00-07

GPIO10-17

GPIO20-27

GPIO30-37

Programmable

Musical Instrument Digital Interface (MIDI) Port

(PC87393 and PC87393F)

PU₂₅

MDRX

Programmable

Strap Conﬁguration

PD₄₀

PD₁₅

BADDR

TEST

Strap

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1.0 Signal/Pin Connection and Description (Continued)

Signal

XCNF0

Pin/s

Type

PD₄₀

Comments

Strap

XCNF1

XCNF2

Parallel Port

PU₂₂₀

ACK

PU₂₂₀

AFD_DSTRB

BUSY_WAIT

ERR

PD₁₂₀

PU₂₂₀

INIT

PU₂₂₀

/

PE

Programmable

PD₁₂₀

PU₂₂₀

SLCT

SLIN_ASTRB

STB_WRITE

WATCHDOG Timer (WDT)

PU₃₀

WDO

Programmable

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2.0 Device Architecture and Conﬁguration

The PC8739x SuperI/O device comprises a collection of legacy and proprietary functional blocks. Each functional block is

described in a separate chapter in this document. However, some parameters in the implementation of each functional block

may vary per SuperI/O device. This chapter describes the PC8739x structure and provides all logical device specific infor-

mation, including special implementation of generic blocks, system interface and device configuration.

2.1 OVERVIEW

The PC8739x consists of 9 logical devices, the host interface, and a central set of configuration registers, all built around a

central, internal bus. The internal bus is similar to an 8-bit ISA bus protocol. See Figure 1, which illustrates the blocks and

related logic.

The system interface serves as a bridge between the external LPC interface and the internal bus. It supports 8-bit Read and

Write transactions for I/O, memory, DMA, and FWH, as defined in Intel’s LPC Interface Speciﬁcation, Revision 1.01.

The central configuration register set is ACPI compliant and supports a PnP configuration. The configuration registers are struc-

tured as a subset of the Plug and Play Standard registers, defined in Appendix A of the Plug and Play ISA Specification, Re-

vision 1.0a by Intel and Microsoft. All system resources assigned to the functional blocks (I/O address space, DMA channels

and IRQ lines) are configured in, and managed by, the central configuration register set. In addition, some function-specific

parameters are configurable through the configuration registers and distributed to the functional blocks through special control

signals.

2.2 CONFIGURATION STRUCTURE AND ACCESS

The configuration structure is comprised of a set of banked registers which are accessed via a pair of specialized registers.

2.2.1

The Index-Data Register Pair

Access to the SuperI/O configuration registers is via an Index-Data register pair, using only two system I/O byte locations.

The base address of this register pair is determined during reset, according to the state of the hardware strapping option on

the BADDR pin. Table 5 shows the selected base addresses as a function of BADDR.

Table 5. BADDR Strapping Options

I/O Address

BADDR

Index Register Data Register

0

1

2Eh

4Eh

2Fh

4Fh

The Index register is an 8-bit read/write register located at the selected base address (Base+0). It is used as a pointer to the

configuration register file, and holds the index of the configuration register that is currently accessible via the Data register.

Reading the Index register returns the last value written to it (or the default of 00h after reset).

The Data register is an 8-bit register (Base+1) used as a data path to any configuration register. Accessing the Data register

actually accesses the configuration register that is currently pointed to by the Index register.

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2.0 Device Architecture and Configuration (Continued)

SIN1

SOUT1

RTS1

GPIO37-30

GPIO

Ports

GPIO27-20

DTR1_BOUT1

CTS1

DSR1

DCD1

Serial

Port 1

GPIO17-10

GPIO07-00

RI1

WDO

WATCHDOG

Timer

SIN2

SOUT2

RTS2

DTR2_BOUT2

CTS2

DSR2

DCD2

RI2

SLCT

PE

BUSY_WAIT

ACK

SLIN_ASTRB

INIT

PD7-0

ERR

AFD_DSTRB

STB_WRITE

Serial

Port 2

Parallel

Port

IRRX1,IRRX2

IRTX

IRSL2-0

IRSL3

FIR

PNF

PPM

FDC

CLKIN

LRESET

LCLK

RDATA

WDATA

WGATE

HDSEL

DIR

STEP

TRK0

INDEX

DSKCHG

WP

SERIRQ

Bus

Interface

LDRQ

LFRAME

LAD3-0

SMI

CLKRUN

LPCPD

MTR1,0

DR1,0

DENSEL

DRATE0

XRD

XWR

XIORD

XIOWR

X-Bus

Extension

XD7-0

XA19-0

BADDR

TEST

Strap

Conﬁg

XCS1-0

XSTB2-0

PIRQA-D

XCNF2-0

JOYAX

JOYAY

JOYABTN0

JOYABTN1

JOYBX

MDTX

MDRX

MIDI

Port

Game

Port

JOYBY

Wake-Up

Control

JOYBBTN0

JOYBBTN1

PWUREQ

Conﬁg

& Control

Registers

Note: Not all members of the PC8739x family contain all these blocks. For device-specific information,

see the Block Diagrams on Page 4.

Figure 1. PC8739x Detailed Block Diagram

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2.0 Device Architecture and Configuration (Continued)

2.2.2

Banked Logical Device Registers Structure

Each functional block is associated with a Logical Device Number (LDN). The configuration registers are grouped into banks,

where each bank holds the standard configuration registers of the corresponding logical device. Table 6 shows the LDN

values of the PC8739x functional blocks. Any value not listed is reserved.

Figure 2 shows the structure of the standard configuration register file. The SuperI/O control and configuration registers are

not banked and are accessed by the Index-Data register pair only, as described above. However, the device control and

device configuration registers are duplicated over 9 banks for 9 logical devices. Therefore, accessing a specific register in

a specific bank is performed by two dimensional indexing, where the LDN register selects the bank (or logical device) and

the Index register selects the register within the bank. Accessing the Data register while the Index register holds a value of

30h or higher physically accesses the logical device configuration registers currently pointed to by the Index register, within

the logical device currently selected by the LDN register.

07h

Logical Device Number Register

SuperI/O Configuration Registers

20h

2Fh

Logical Device Control Register

30h

60h

63h

70h

71h

74h

75h

Standard Logical Device

Configuration Registers

Bank Select

Special (Vendor-defined)

Logical Device

F0h

FEh

Configuration Registers

Banks

(One per Logical Device)

Figure 2. Structure of Standard Conﬁguration Register File

Table 6. Logical Device Number (LDN) Assignments

Functional Block

LDN

00h

01h

02h

03h

07h

0Ah

0Bh

0Ch

0Fh

Floppy Disk Controller (FDC)

Parallel Port (PP)

Serial Port 2 with IR (SP2)

Serial Port 1 (SP1)

General-Purpose I/O (GPIO) Ports (PC87392, PC87393 and PC87393F only)

WATCHDOG Timer (WDT)

Game Port (GMP) (PC87393 and PC87393F only)

Musical Instrument Digital Interface (MIDI) Port (PC87393 and PC87393F only)

X-Bus Extension (PC87393 and PC87393F only)

Write accesses to unimplemented registers (i.e. accessing the Data register while the Index register points to a non-existing

register), are ignored and read returns 00h on all addresses, except for 74h and 75h (DMA configuration registers) which

returns 04h (indicating no DMA channel is active). The configuration registers are accessible immediately after reset.

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2.0 Device Architecture and Configuration (Continued)

2.2.3 Standard Logical Device Configuration Register Definitions

In the registers below, any undefined bit is reserved. Unless otherwise noted, the following definitions also hold true:

●

All registers are read/write.

●

All reserved bits return 0 on reads, except where noted otherwise. To prevent unpredictable results, do not modify

these bits. Use read-modify-write to prevent the values of reserved bits from being changed during write.

●

Write only registers should not use read-modify-write during updates.

Table 7. Standard Control Registers

Index

Register Name

Description

07h

Logical Device This register selects the current logical device. See Table 6 for valid numbers. All

Number

other values are reserved.

20h - 2Fh

SuperI/O

Conﬁguration

SuperI/O conﬁguration registers and ID registers

Table 8. Logical Device Activate Register

Description

Index

Register Name

30h

Activate

Bit 0 - Logical device activation control

0: Disabled

1: Enabled

Bits 7-1 - Reserved

Note: When the X-Bus Extension is disabled, access to its registers (not the PnP registers) is disabled, but all bridging func-

tions continue to operate according to its register settings.

Table 9. I/O Space Conﬁguration Registers

Index

Register Name

Description

60h

I/O Port Base

Address Bits (15-8)

Descriptor 0

Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 0.

61h

I/O Port Base

Address Bits (7-0)

Descriptor 0

Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 0.

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2.0 Device Architecture and Configuration (Continued)

Table 10. Interrupt Conﬁguration Registers

Index

Register Name

Description

70h

Interrupt Number Indicates selected interrupt number.

and Wake-Up on

Bits 7-5 - Reserved.

IRQ Enable

Bit 4 - Enables wake-up on the IRQ of the logical device. When enabled, IRQ

assertion triggers a wake-up event.

0: Disabled (default)

1: Enabled

Bits 3–0 select the interrupt number. A value of 1 selects IRQL1. A value of 15

selects IRQL15. IRQL0 is not a valid interrupt selection and represents no interrupt

selection.

71h

Interrupt Request Indicates the type and level of the interrupt request number selected in the previous

Type Select

register.

If a logical device supports only one type of interrupt, this register is read only.

Bits 7–2 - Reserved.

Bit 0 - Type of interrupt request selected in the previous register.

0: Edge

1: Level

Bit 1 - Level of the interrupt request selected in the previous register.

0: Low polarity

1: High polarity

Table 11. DMA Conﬁguration Registers

Description

Index

Register Name

74h

DMA Channel

Select 0

Indicates selected DMA channel for DMA 0 of the logical device (0 - The ﬁrst DMA

channel in case of using more than one DMA channel).

Bits 7-3 - Reserved.

Bits 2-0 select the DMA channel for DMA 0. The valid choices are 0-3, where a

value of 0 selects DMA channel 0, 1 selects channel 1, etc.

A value of 4 indicates that no DMA channel is active.

The values 5-7 are reserved.

75h

DMA Channel

Select 1

Indicates selected DMA channel for DMA 1 of the logical device (1 - The second

DMA channel in case of using more than one DMA channel).

Bits 7-3 - Reserved.

Bits 2-0 select the DMA channel for DMA 1. The valid choices are 0-3, where a

value of 0 selects DMA channel 0, 1 selects channel 1, etc.

A value of 4 indicates that no DMA channel is active.

The values 5-7 are reserved.

Table 12. Special Logical Device Conﬁguration Registers

Index

Register Name

Description

F0h-FEh

Logical Device Special (vendor-deﬁned) conﬁguration options

Conﬁguration

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2.0 Device Architecture and Configuration (Continued)

2.2.4

Standard Configuration Registers

Index

Register Name

Logical Device Number

07h

20h

SuperI/O ID

21h

SuperI/O Conﬁguration 1

22h

SuperI/O Conﬁguration 2

23h

SuperI/O Conﬁguration 3

24h

SuperI/O Conﬁguration 4

SuperI/O Control and

Conﬁguration Registers

25h

SuperI/O Conﬁguration 5

26h

SuperI/O Conﬁguration 6

27h

SuperI/O Revision ID

28h

SuperI/O Conﬁguration 8

29h

SuperI/O Conﬁguration 9

2Ah

SuperI/O Conﬁguration A

2Bh - 2Eh

30h

Reserved exclusively for National use

Logical Device Control (Activate)

I/O Base Address Descriptor 0 Bits 15-8

I/O Base Address Descriptor 0 Bits 7-0

Interrupt Number and Wake-Up on IRQ Enable

IRQ Type Select

60h

61h

Logical Device Control and

Conﬁguration Registers -

one per Logical Device

(some are optional)

70h

71h

74h

DMA Channel Select 0

75h

DMA Channel Select 1

F0h - F9h

Device Speciﬁc Logical Device Conﬁguration 1 to 10

Figure 3. Conﬁguration Register Map

SuperI/O Control and Conﬁguration Registers

The SuperI/O configuration registers at indexes 20h and 27h are mainly used for part identification, global power manage-

ment and the selection of pin multiplexing options. For details, see Section 2.10.

Logical Device Control and Conﬁguration Registers

A subset of these registers is implemented for each logical device. See functional block descriptions in the following sections.

Control

The only implemented control register for each logical device is the Activate register at index 30h. Bit 0 of the Activate reg-

ister controls the activation of the associated functional block. Activation enables access to the functional block’s registers,

and attaches its system resources, which are unassigned as long as it is not activated. Other effects may apply, on a func-

tion-specific basis (such as clock enable and active pinout signaling).

Standard Conﬁguration

The standard configuration registers manage the PnP resource allocation to the functional blocks. The I/O port base address

descriptor 0 is a pair of registers at Index 60-61h, holding the first 16-bit base address for the register set of the functional

block. An optional 16-bit second base-address (descriptor 1) at index 62-63h is used for logical devices with more than one

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2.0 Device Architecture and Configuration (Continued)

continuous register set. Interrupt Number and Wake-Up on IRQ Enable (index 70h) and IRQ Type Select (index 71h) allocate

an IRQ line to the block and control its type. DMA Channel Select 0 (index 74h) allocates a DMA channel to the block, where

applicable. DMA Channel Select 1 (index 75h) allocates a second DMA channel, where applicable.

Special Conﬁguration

The vendor-defined registers, starting at index F0h, control function-specific parameters such as operation modes, power

saving modes, pin TRI-STATE, clock rate selection, and non-standard extensions to generic functions.

2.2.5

Default Configuration Setup

The default configuration setup of the PC8739x can include two reset types, described below. See specific register descrip-

tions for the bits affected by each reset type.

• Software Reset

This reset is enabled by bit 1 of the SIOCF1 register, which resets all logical devices. A software reset also resets most

bits in the SuperI/O control and configuration registers (see Section 2.10 for the bits not affected). This reset does not

affect register bits that are locked for write access.

• Hardware Reset

This reset is activated by the assertion of the LRESET input. It resets all logical devices. It also resets all SuperI/O control

and configuration registers.

In event of a hardware reset, the PC8739x wakes up with the following default configuration setup:

— The conﬁguration base address is 2Eh or 4Eh, according to the BADDR strap pin value, as shown in Table 5.

— All logical devices are disabled, with the exception of the X-Bus which remains functional but whose registers cannot

be accessed.

— All multiplexed GPIO pins are conﬁgured according to the strap pins. When conﬁgured as GPIO, they have an internal

static pull-up (default direction is input) except GPIO36.

In event of either a hardware or a software reset, the PC8739x wakes up with the following default configuration setup:

— The legacy devices are assigned with their legacy system resource allocation.

— The National proprietary functions are not assigned with any default resources and the default values of their base

addresses are all 00h.

2.2.6

Power States

The following terminology is used in this document to describe the various possible power states:

• Power On

V_DDis active.

• Power Off

V_DDis inactive.

2.2.7

Address Decoding

A full 16-bit address decoding is applied when accessing the configuration I/O space as well as the registers of the functional

blocks. However, the number of configurable bits in the base address registers varies for each logical device.

The lower 1, 2, 3, 4 or 5 address bits are decoded within the functional block to determine the offset of the accessed register,

within the logical device’s I/O range of 2, 4, 8, 16 or 32 bytes, respectively. The rest of the bits are matched with the base

address register to decode the entire I/O range allocated to the logical device. Therefore the lower bits of the base address

register are forced to 0 (read only), and the base address is forced to be 2, 4, 8, 16 or 32 byte-aligned, according to the size

of the I/O range.

The base address of the FDC, Serial Port 1, Serial Port 2 with FIR are limited to the I/O address range of 00h to 7FXh only

(bits 11-15 are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to 3F8h. The addresses

of the non-legacy logical devices, including the GMP, MIDI and X-Bus, are configurable within the full 16-bit address range

(up to FFFXh).

In some special cases, other address bits are used for internal decoding (such as bit 10 in the Parallel Port). For more details,

see the description of the base address register for each logical device.

The X-Bus extension serves as a bridge from the LPC to the X-Bus. For module control and security function registers, the

16-bit base address is applied through the configuration address space. The lower 4 address bits are decoded within the X-

Bus for accessing each register. The address ranges in the LPC I/O space, LPC memory space and FWH memory space

that are bridged to the X-Bus are defined in the SuperI/O configuration section for the X-Bus bridge. The number of address

bits used for this decoding varies according to the specified zones and their sizes. See Section 2.19.2 and Section 2.19.3

for details of the address range specifications.

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2.0 Device Architecture and Configuration (Continued)

2.3 THE CLOCK MULTIPLIER

The source of all internal clocks in the chip is either an external 48 MHz clock on the CLKIN pin, or the on-chip clock multi-

plier. The clock multiplier is fed by applying a clock source at one of two frequencies on the CLKIN pin: 32.768 KHz or

14.31818 MHz. The clock multiplier generates two internal clocks, 24 MHz and 48 MHz. These clocks are needed for all the

modules in the PC8739x with the exception of the X-Bus module. After power-up or reset, the clock (clock multiplier or ex-

ternal clock) is disabled.

2.3.1

Functionality

The on-chip clock multiplier starts working when it is enabled by bit 2 of the SIOCF9 register, index 29h, i.e., when its value

changes from 0 to 1 (only for source clocks 32.768 KHz or 14.31818 MHz). This bit can also disable the clock multiplier and

its output clock after the multiplier is enabled. Once enabled, the output clock is frozen to a steady logic level until the mul-

tiplier provides a stable output clock that meets all requirements. Then the clock starts toggling.

On power-up when V_DDis applied, the chip wakes up with the on-chip clock multiplier disabled. The input and output clocks

of the clock multiplier may toggle regardless of the state of the Master Reset (MR) pin. The clock multiplier waits for a toggling

input clock.

Bit 3 of the SIOCF9 register, a read only bit, is the Valid Clock Multiplier status bit. While stabilizing, the output clock is frozen

to a steady logic level, and the status bit is cleared to 0 to indicate a frozen clock. When the clock multiplier is stable, the

output clock starts toggling and the status bit is set to 1. It tells the software when the clock multiplier is ready. The software

should poll this status bit until it is set (1), and only then activate (enable) the FDC, Parallel Port, UARTs and infrared inter-

face. When the multiplier is enabled for the first time after power-up, more time is required until this status bit is set to 1.

The clock multiplier and its output clock do not consume power when they are disabled.

2.3.2

Chip Power-Up

To ensure proper operation, proceed as follows after power-up:

1. Set bits 2, 1 and 0 of the Clock Control Configuration register (SIOCF9) at index 29h according to the clock source used

(even if the external clock is the default frequency setting). See Table 13. Bits 2, 1 and 0 may be written in a single write

cycle. From this point on, bits 1 and 0 of the SIOCF9 register are read only. The value of the clock source cannot be

changed, except by a total power-down and power-up cycle. However, the clock can be disabled at any time.

Table 13. Clock Multiplier Encoding Options

SIOCF9 Register (Index 29h)

Valid Clock

Chip Clock

External Source on CLKIN Pin

Multiplier

Status

Clock Enable

Source

Bit 3

Bit 2

Bit 1 Bit 0

External 48 MHz clock

32.768 KHz clock multiplier

14.31818 MHz clock multiplier

No clock

Always 1

1

0

1

0

1

0

0 = Frozen

1 = Stable

0

10, 01, 00

2. Enable the clock.

If the clock source is 32.768 kHz or 14.31818 MHz:

— Poll bit 3 of the SIOCF9 register while the clock multiplier is stabilizing.

— When bit 3 of SIOCF9 is set to 1, go to step 3.

3. Enable any module in the chip, as needed.

2.3.3

Disabling the Clock

Before disabling the clock multiplier (by clearing bit 2 of SIOCF9 Register) or the external clock (for 48 MHz), make sure that

all PC8739x modules are disabled. This is done by polling bit 4 of the SIOCF9 register (Module Enable Status) for 0.

2.3.4

Specifications

Wake-up time is 33 msec (maximum). This is measured from valid V_DDtoggling of the input clock and multiplier enabled

until the clock is stable. Tolerance (long term deviation) of the multiplier output clock, relative to the input clock, is ±110 ppm.

Total tolerance is therefore ± (input clock tolerance + 110 ppm). Cycle by cycle variance is 0.4 nsec (maximum).

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2.0 Device Architecture and Configuration (Continued)

2.4 INTERRUPT SERIALIZER

The Interrupt Serializer translates parallel interrupt request (PIRQ) signals received from external devices, via the PIRQn (n

can be A, B, C or D) pins and from internal IRQ sources, into serial interrupt request data transmitted over the SERIRQ bus.

This enables the integration of devices that support only parallel IRQs in a system which supports only serial IRQs.

PIRQ signals that enter the device or internal IRQs are fed into an IRQ Mapping, Enable, and Polarity Control block. This

block maps them to their associated IRQ slots. The IRQs are then fed into the Interrupt Serializer, where they are translated

into serial data and transmitted over the SERIRQ bus.

The PIRQn input value is routed to the Interrupt Serializer as the IRQ value to be driven onto IRQ slot n.

The same slot cannot be shared among different interrupt sources in this device.

When a transition is sensed on an IRQ source,the new value of the IRQ source is transmitted over the SERIRQ bus during

the corresponding IRQ slot. For example, when a transition on PIRQA is sensed, the new value of PIRQA is transmitted

during slot n of the SERIRQ bus.

Figure 4 shows the mechanism for both interrupt serialization and wake-up.

Bus Interface

Internal

IRQ1

IRQ

Sources

IRQ Mapping

and Polarity

Control

Interrupt

Serializer

SERIRQ

PIRQn

Pins

IRQ15

Wake-Up

Enable

Control

Signals

PWUREQ

Figure 4. Interrupt Serialization and Wake-Up Mechanism

2.5 WAKE-UP CONTROL

The Wake-Up Control module receives the parallel interrupt request (PIRQn) signals from external devices and the IRQ sig-

nals from internal sources. It generates the PWUREQ system wake-up signal. All mapped IRQ signals, both internal and

external, enter the Wake-Up Enable Control block. If one of them becomes active and is enabled for wake-up, an active

PWUREQ signal is generated.

2.6 THE PARALLEL PORT MULTIPLEXER (PPM)

The Parallel Port Multiplexer (PPM) allows connection of an external Floppy Disk Drive (FDD) through the Parallel Port con-

nector (25-pin DIN) instead of, or in addition to, the internal FDD on the normal FDC header. This is done by turning the

Parallel Port pins into an additional set of FDC pins, while isolating them from Parallel Port functionality (see Section 1.4 for

a signal multiplexing description).

A printer, or any other parallel device, may be exchanged with an external FDD without turning the system off. The PPM

logic automatically detects whether a parallel device or the FDD is connected, and routes the Parallel Port pins to either the

Parallel Port or the FDC functional blocks accordingly. See Figure 5.

To enable PPM mode, set bits 6-5 (Pin 35 Function Select) of the SIOCF5 register to the values that represent the desired

configuration (see Section 2.10.6). The control of the connection, after enabling PPM mode, is done by bit SIOCF5[7] (PNF

status) of this register as follows:

●

PNF status = 1, PPM is inactive and the Parallel Port pins are assigned Parallel Port functionality

●

PNF status = 0, PPM is active and the Parallel Port pins are assigned FDC functionality.

The value of bit SIOCF5[7] is determine by the PNF pin signal and the PNF polarity setting (bits SIOCF5[6:5]).

When PPM mode is disabled (both bits 6-5 of the SIOCF5 register = 0), the Parallel Port pins are assigned Parallel Port

functionality, regardless of the value of PNF.

The internal FDD on the normal FDC pins, and the external FDD on the Parallel Port pins can be assigned as Drive A and

Drive B, respectively, or the drive assignment can be switched between them.

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2.0 Device Architecture and Configuration (Continued)

The Parallel Port pins function as an FDD interface for either drive 1 or drive 3. See Figure 5 for the internal routing between

the PPM and FDC, and the Parallel Port and FDC pin-sets when PPM mode is active. The FDC output signals are driven

simultaneously both on the normal FDC pins and on the corresponding Parallel Port pins. The FDC inputs are received from

the FDC pins when either drive 0 or drive 2 is selected, and from the corresponding Parallel Port pins when either drive 1 or

drive 3 is selected.

The Parallel Port output signals are isolated from the Parallel Port pins. The Parallel Port input signals, as reflected by the

STR register, assume one of two possible values ([BUSY, PE, SLCT, ACK] = 1001 or 1111), indicating that nothing is con-

nected to the Parallel Port. The default values are controlled by bit 2 of the Parallel Port Configuration register (see Section

2.12.3 for details).

PPM is in power save mode when PPM is active and the PPM power save mode bit is enabled.See Section 2.6.1 for details.

PPM in Power Save Mode

and Drive 1 Selected

FDC Outputs

Outputs Frozen

FDC Pins

at Inactive Levels

FDC

FDC Inputs

0

1

PPM in Power Save Mode

and Drive 0 Selected

PPM Active and

Drive 1 or 3 Selected

FDC Outputs

Outputs Frozen

at Inactive Levels

FDC Inputs

PPM Power Save

PPM Active

and bit 7 of SIOCF5 is ’0’ (PNF=0)

Parallel Port Pins

Parallel Port

Outputs

Parallel Port Inputs

Parallel

Port

0

1

Default “Non-Connect”

Parallel Port Input Values

Figure 5. PPM Routing

2.6.1

PPM Power Save Mode

PPM power save mode helps avoid the additional power consumption associated with driving two sets of FDD outputs by

limiting the activity to the selected drive only. PPM power save mode is enabled by bit 2 of the SIOCF5 register, and is in

effect only when the PPM is active. Assuming that the internal FDD (on the normal FDC pins) is drive 0, while the external

FDD (on the Parallel Port pins) is drive 1, the outputs of the non-selected drive do not toggle, but rather are frozen at their

inactive levels. Table 14 shows the behavior of the FDC outputs on both the FDC and Parallel Port pins when the PPM is

active and PPM power save mode is enabled.

Table 14. FDC Output Status in PPM Power Save Mode

FDC Outputs

DR0

DR1

Signal

FDC Pins

Functional

Parallel Port Pins

0

1

0

1

Frozen at inactive levels

Functional

Frozen at inactive levels

Functional

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2.0 Device Architecture and Configuration (Continued)

2.7 PROTECTION

The PC8739x provides features to protect the PC at software levels. It can be locked to protect configuration bits or alteration

of the device hardware configuration, as well as internal GPIO settings and several types of configuration settings.

All protection mechanisms can be used optionally.

2.7.1

Pin Configuration Lock

To lock the pin configuration of the PC8739x in order to prevent unwanted changes to hardware configuration, set bit 7 of

the SIOCF1 register to 1. This causes all function select configuration bits to become read only bits. This bit can only be

cleared by a hardware reset.

2.7.2

GPIO Pin Function Lock

The PC8739x is capable of locking the attributes of each GPIO pin. The following attributes can be locked:

●

Output enable

●

Output type

●

Static pull-up

●

Driven data.

GPIO pins are locked per pin by setting the Lock bit in the appropriate GPIO Pin Configuration register. When the Lock bit

is set, the configuration of the associated GPIO pin can be cleared only by a hardware reset.

2.8 LPC INTERFACE

2.8.1

LPC Transactions Supported

The PC8739x LPC interface can respond to the following LPC transactions as part of the standard SuperI/O implementation:

—

I/O read and write cycles

8-bit DMA read and write cycles

DMA request cycles.

In addition, the X-Bus bridge uses the following transaction:

—

8-bit memory read and write (PC87393 and PC87393F only)

8-bit FWH read and write (PC87393F only)

LPC transactions conform with Intel’s LPC Interface Specification, Revision 1.00.

The LPC-FWH read and write cycles are similar to memory read and write cycles. The specifications of these cycles are

listed below. The Address, Data, TAR and SYNC cycles are as specified for LPC memory read and write cycles. The START

and ID fields are similar to the equivalent cycle in LPC memory read and write cycles but differ in the data placed on the LAD

signals (see details in the cycle description).

FWH Read Cycle (PC87393F only)

1. START: 1101 (0xD)

2. ID field:

FWH ID nibble (compared with bits 7-4 of X-Bus Memory Configuration Register, Section 2.19.8)

3. Address: 8 address nibbles (MS nibble first; see usage below)

4. TAR (two cycles)

5. SYNC

6. DATA:

2 data nibbles (LS nibble first; D3-D0, D7-D4)

7. TAR (two cycles)

FWH Write Cycle (PC87393F only)

1. START: 1110 (0xE)

2. ID field:

FWH ID nibble (compared with bits 7-4 of X-Bus Memory Configuration Register, Section 2.19.8)

3. Address: 8 address nibbles (MS nibble first; see usage below)

4. DATA:

2 data nibbles (LS nibble first; D3-D0, D7-D4)

5. TAR (two cycles)

6. SYNC

7. TAR (two cycles)

The ID field is compared with bits 7-4 of the X-Bus Memory Configuration register, described in Section 2.19.8. If the two

match, the PC8739x continues handling the transaction; if not, the current LPC-FWH transaction is ignored.

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2.0 Device Architecture and Configuration (Continued)

LPC-FWH Address Translation: The address field in the LPC-FWH transaction is constructed of eight nibbles. The first

seven nibbles correspond to the first LS seven address nibbles (A27-A0), as follows: the first incoming nibble corresponds

to addresses A27 - A24, the second to A23 - A20, and so forth until the seventh nibble, which corresponds to A3 - A0. In-

coming nibble eight is ignored. The MS bits of the 32-bit addresses are ’1111’ (A31 - A28).

2.8.2

CLKRUN Functionality

The PC8739x supports the CLKRUN I/O signal, whose use is highly recommended in portable systems. This signal is im-

plemented according to the specification in PCI Mobile Design Guide, Revision 1.1, December 18, 1998. The PC8739x sup-

ports operation with both a slow and stopped clock in ACPI state S0 (the system is active but is not being accessed). The

PC8739x drives the CLKRUN signal low to force the LPC bus clock into full speed operation in the following cases:

●

An IRQ is pending internally, waiting to be sent through the serial IRQ.

●

A DMA request or abort is pending internally, waiting to be sent through the serial DMA.

Note: When the CLKRUN signal is not in use, the PC8739x assumes valid clock on the CLKIN pin.

2.8.3

LPCPD Functionality

The PC8739x supports the LPCPD input. This signal is used in case the V_DDchip supply is not shared by all residents of

the LPC bus. The LPCPD signal conforms with Intel’s LPC Interface Specification, Revision 1.00. Note that if the PC8739x

power supply exists while LPCPD is active, it is not mandatory to reset the PC8739x when LPCPD is de-asserted.

2.9 REGISTER TYPE ABBREVIATIONS

The following abbreviations are used to indicate the Register Type:

●

R/W = Read/Write

●

R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different

register.

●

W = Write

●

RO = Read Only

●

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

2.10 SUPERI/O CONFIGURATION REGISTERS

This section describes the SuperI/O configuration and ID registers (those registers with first level indexes in the range of 20h

- 2Eh). See Table 15 for a summary and directory of these registers.

Note: Set the configuration registers to enable functions or signals that are relevant to the specific device. The val-

ues of fields that select functions, or signals, that are excluded from a specific device are treated as reserved and

should not be selected.

Table 15. SuperI/O Conﬁguration Registers

Index

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

Mnemonic

SID

Register Name

SuperI/O ID

Power Well

V_DD

Type

RO

Section

2.10.1

2.10.2

2.10.3

2.10.4

2.10.5

2.10.6

2.10.7

2.10.8

2.10.9

2.10.10

2.10.11

SIOCF1

SIOCF2

SIOCF3

SIOCF4

SIOCF5

SIOCF6

SRID

SuperI/O Conﬁguration 1

SuperI/O Conﬁguration 2

SuperI/O Conﬁguration 3

SuperI/O Conﬁguration 4

SuperI/O Conﬁguration 5

SuperI/O Conﬁguration 6

SuperI/O Revision ID

V_DD

R/W

RO

V_DD

SIOCF8

SIOCF9

SIOCFA

SuperI/O Conﬁguration 8

SuperI/O Conﬁguration 9

SuperI/O Conﬁguration A

V_DD

R/W

V_DD

2Bh - 2Fh Reserved exclusively for National use

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2.0 Device Architecture and Configuration (Continued)

2.10.1 SuperI/O ID Register (SID)

This register contains the identity number of the chip. Members of the PC8739x family are identified by the value EAh.

Location:

Type:

Index 20h

RO

Bit

7

6

5

4

3

2

1

0

Name

Chip ID

Reset

EAh

2.10.2 SuperI/O Configuration 1 Register (SIOCF1)

Location:

Type:

Index 21h

Varies per bit

Bit

7

6

Reserved

0

5

4

3

2

1

0

Name

Function

Select Lock

Global

Device

Enable

Number of DMA Wait

States

Number of I/O Wait

States

Software

Reset

Bit

0

1

0

1

Description

7

Pin Function Select Lock. This bit determines if the bits that select pin functions (located in the SIOCF1, 2, 3,

4, 5, 8 and A registers) are read only or read/write. When set to 1, this bit can only be cleared by a hardware

reset.

0: Bits are R/W

1: Bits are RO.

6

Reserved

5-4 Number of DMA Wait States. These are R/W bits.

Bits

5 4

Number

0 0

0 1

1 0

1 1

Reserved

Two (default)

Six

Twelve

3-2 Number of I/O Wait States. These are R/W bits.

Bits

3 2

Number

0 0

0 1

1 0

1 1

Zero (default)

Two

Six

Twelve

1

0

Software Reset. Read always returns 0. This is a R/W bit.

0: Ignored (default)

1: Resets all the logical devices that are affected by hardware reset (with the exception of Lock bits)

Global Device Enable. This bit controls the function enable of all the PC8739x logical devices, except X-Bus .

With the exception of X-Bus, it allows all logical devices to be disabled simultaneously by writing to a single bit.

This is a R/W bit.

0: All logical devices in the PC8739x are disabled (except X-Bus)

1: Each logical device is enabled according to its Activate register (Index 30h) (default)

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2.0 Device Architecture and Configuration (Continued)

2.10.3 SuperI/O Configuration 2 Register (SIOCF2)

Location:

Type:

Index 22h

R/W

Bit

7

6

5

4

3

2

1

0

Name

Pin 87

Function

Select

Pins 95-90

Function

Select

Pins 81-74

Function

Select

Pins 3-1 and 100-96

Function

Select

Reset

Strap

Bit

Description

7-6 Pin 87 Function Select

Bits

7 6

Function

0 0

0 1

1 0

1 1

GPIO26 (default for all XCNF2-0 values, except x01)

XA6 (default when XCNF2-0 is x01)

PIRQA

XSTB2

5-4 Pins 95-90 Function Select

Bits

5 4

Function

0 0

0 1

1 0

1 1

GPIO20-24, XSTB1 (default when XCNF2-0 is x00)

XA5-0 (default when XCNF2-0 is x01)

XA3-0, XSTB0, XSTB1 (default for all XCNF2-0 values, except x00 and x01)

Reserved

Pins 81-74 Function Select¹

3-2

Bits

3 2

Function

0 0

0 1

1 0

1 1

GPIO10-17 (default when XCNF2-0 is x00, 110 or 111)

XA12-19 (default when XCNF2-0 is x01, 010 or 011)

JOYABTN1, JOYBBTN1, JOYAY, JOYBY, JOYAX, JOYBX, JOYABTN0, JOYBBTN0

RI2, DTR2_BOUT2, CTS2, SOUT2, RTS2, SIN2, DSR2, DCD2

1-0 Pins 3-1 and 100-96 Function Select

Bits

1 0

Function

0 0

0 1

1 0

1 1

GPIO00-07 (default when XCNF2-0 is x00)

XD0-7 (default for all XCNF2-0 values, except x00)

JOYABTN1, JOYBBTN1, JOYAY, JOYBY, JOYAX, JOYBX, JOYABTN0, JOYBBTN0

Reserved

1. In the PC87391, these pins are pulled up after reset by an internal pull-up resistor. Software should set this

ﬁeld to 11 to enable the UART 2 function.

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2.0 Device Architecture and Configuration (Continued)

2.10.4 SuperI/O Configuration 3 Register (SIOCF3)

Location:

Type:

Index 23h

R/W

Bit

7

6

5

4

3

2

1

0

Name

Pins 83 and 82

Function Select

Pin 84

Function Select

Pin 85

Function Select

Pin 86

Function Select1

Reset

Strap

Bit

Description

7-6 Pins 83 and 82 Function Select

Bits

7 6

Function

0 0

0 1

1 0

1 1

GPIO32-33 (default for all XCNF2-0 values except x01)

XA10-11 (default when XCNF2-0 is x01)

MDRX, MDTX

XIORD, XIOWR

Pin 84 Function Select¹

5-4

Bits

5 4

Function

0 0

0 1

1 0

1 1

GPIO31 (default for all XCNF2-0 values except x01)

XA9 (default when XCNF2-0 is x01)

PIRQD

MTR1 (signal output is floated when PPM mode is enabled)

3-2 Pin 85 Function Select

Bits

3 2

Function

0 0

0 1

1 0

1 1

GPIO30 (default for all XCNF2-0 values except x01)

XA8 (default when XCNF2-0 is x01)

PIRQC

Reserved

1-0 Pin 86 Function Select

Bits

1 0

Function

0 0

0 1

1 0

1 1

GPIO27 (default for all XCNF2-0 values except x01

XA7 (default when XCNF2-0 is x01)

PIRQB

Reserved

1. In the PC87391, this pin is pulled up after reset by an internal pull-up resistor. Software should set this ﬁeld to

11 to enable the FDC function.

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2.0 Device Architecture and Configuration (Continued)

2.10.5 SuperI/O Configuration 4 Register (SIOCF4)

Location:

Type:

Index 24h

R/W

Bit

7

6

5

4

0

3

1

2

1

0

Name

Pin 5

Function

Select

Pin 19

Function

Select

Pin 73

Function

Select

Pin 72

Function

Select

Pin 6

Function

Select

Reset

Strap

0

Strap

0

Bit

Description

Pin 5 Function Select¹

7-6

Bits

Function

7 6

0 0

0 1

1 0

1 1

GPIO34 (default when XCNF2-0 is x00)

XRD (default for all XCNF2-0 values except x00)

WDO

Reserved

5

Pin 19 Function Select¹

0: GPIO35 (default)

1: SMI

Pin 73 Function Select¹

4-3

Bits

4 3

Function

0 0

0 1

1 0

1 1

XIOWR

XCS1 (default)

MTR1 (signal output is inactive, 1, when PPM mode is enabled)

DRATE0

Pin 72 Function Select¹

2-1

Bits

2 1

Function

0 0

0 1

1 0

1 1

GPIO25 (default when XCNF2-0 is x00)

XCS0 (default for all XCNF2-0 values except x00, 010 and 110)

XRDY (default when XCNF2-0 is 010 or 110)

DR1 (signal output is inactive, 1, when PPM mode is enabled)

0

Pin 6 Function Select¹

0: GPIO36 (default)

1: CLKRUN

1. In the PC87391, this pin is pulled up after reset by an internal pull-up resistor. Software should set this ﬁeld as

appropriate to enable the required Legacy function.

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2.0 Device Architecture and Configuration (Continued)

2.10.6 SuperI/O Configuration 5 Register (SIOCF5)

Location:

Type:

Index 25h

Varies per bit

Bit

7

6

0

5

0

4

3

2

1

0

Name

Pin 35

Function

Select

Pin 34

Function

Select

Pin 71

Function

Select

SMI to IRQ2

Enable

PPM Power

Save Enable

PNF Status

Reset

1

0

Bit

Description

7

PNF Status. This bit describes the status of the PNF signal, which determines if Parallel Port of external FDD sig-

nals are selected by PPM mode. This is a RO bit.

0: Floppy Disk

1: Parallel Port (default)

6-5 Pin 35 Function Select. These are R/W bits.

Bits

6 5

Function

0 0

0 1

1 0

1 1

PPM disabled (default)

PNF signal selected as active low (high selects printer, low selects floppy)

PNF signal selected as active high (low selects printer, high selects floppy)

XRDY signal selected

4

3

2

SMI to IRQ2 Enable. This is a R/W bit.

0: Disabled (default)

1: Enabled

Pin 34 Function Select. This is a R/W bit.

0: DRATE0 (default)

1: IRSL2

PPM Power Save Enable

0: Disabled (default).

1: When PPM is active and PNF is 0 (bit 7 of this register), the FDC output pins and the Parallel Port output

pins are masked when the corresponding drive is not used.

Pin 71 Function Select.¹This is a R/W bit.

1-0

Bits

1 0

Function

0 0

0 1

1 0

1 1

GPIO37 (default)

DR1

IRSL2

XIORD

1. In the PC87391, this pin is pulled up after reset by an internal pull-up resistor. Software should set this ﬁeld as

appropriate to enable the required Legacy function.

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2.0 Device Architecture and Configuration (Continued)

2.10.7 SuperI/O Configuration 6 Register (SIOCF6)

Write access to this register can be inhibited by setting bit 7. Activation of each logical device (bits 0-4) is also affected by

bit 0 of the logical device Activate register, index 30h and bit 0 of the SIOCF1 register.

Location:

Type:

Index 26h

R/W

Bit

7

6

5

4

Reserved

0

3

2

1

0

Name

SIOCF6

Software

Lock

General-Purpose

Scratch

Serial Port 1 Serial Port 2 Parallel Port

Disable

FDC

Disable

Reset

0

Bit

Description

7

SIOCF6 Software Lock. When this bit is set to 1 by software, it can be cleared only by hardware reset.

0: Write access to bits 0-6 of this register enabled (default)

1: Bits 6-0 of this register are RO

6-5 General-Purpose Scratch

4

3

Reserved

Serial Port 1 Disable

0: Enabled (default)

1: Disabled

2

1

0

Serial Port 2 Disable

0: Enabled (default)

1: Disabled

Parallel Port Disable

0: Enabled (default)

1: Disabled

FDC Disable

0: Enabled (default)

1: Disabled

2.10.8 SuperI/O Revision ID Register (SRID)

This register contains the ID number of the specific family member (Chip ID) and the chip revision number (Chip Rev). The

Chip Rev field identity number the chip revision.

Location:

Type:

Index 27h

RO

Bit

7

6

Chip ID

0

5

0

4

3

2

Chip Rev

X

1

0

Name

Reset

0

X

Bit

Description

7-5 Chip ID.

4-0 Chip Rev. These bits identify the device revision.

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2.0 Device Architecture and Configuration (Continued)

2.10.9 SuperI/O Configuration 8 Register (SIOCF8)

Location:

Type:

Index 28h

R/W

Bit

7

6

0

5

0

4

0

3

0

2

0

1

0

Name

GPIO to WDO to SMI

SMI Enable

Reserved

Enable

Reset

0

Bit

Description

7-2 Reserved

GPIO to SMI Enable¹

0: Disabled (default)

1: Enabled

1

0

WDO to SMI Enable

0: Disabled (default)

1: Enabled

1. PC87392, PC87393 and PC87393F only.

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44

2.0 Device Architecture and Configuration (Continued)

2.10.10 SuperI/O Configuration 9 Register (SIOCF9)

Location:

Type:

Index 29h

Varies per bit

Bit

7

0

6

Reserved

0

5

4

3

2

1

0

Name

Module

Enable

Status

Valid Multi-

plier Clock

Status

Clock

SuperI/O Chip Clock

Source

Enable

Reset

0

1

0

Bit

Description

7-5 Reserved

4

Module Enable Status. This bit defines the status of all the PC8739x modules with exception of the X-Bus. This

bit is read only.

0: All modules disabled

1: At least one module enabled

3

2

Valid Multiplier Clock Status. This bit is read only.

0: On-chip clock frozen

1: On-chip clock stable and toggling

Clock Enable. This bit enables the 48 and 24 MHz clock to the SuperI/O modules. When the SuperI/O chip

clock source is set to 48 MHz, this bit enables the path from the input CLKIN pin. When the clock source is set

to 32.768 KHz or 14.31818 MHz, this bit enables the clock multiplier.This is a read/write bit that is reset by

hardware reset only.

0: Clock disabled (default)

1: Clock enabled

1-0 SuperI/O Chip Clock Source. These bits define the clock source for the SuperI/O chip that is fed via the CLKIN

pin. On power-up (only), these bits are read or write and assume their default value. Once they are written, they

become read only bits.

Bits

1 0

Function

0 0

0 1

1 0

1 1

Clock source is 48 MHz

Clock source is the on-chip clock multiplier fed by 32.768 KHz

Clock source is the on-chip clock multiplier fed by 14.31818 MHz (default)

Reserved

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2.0 Device Architecture and Configuration (Continued)

2.10.11 SuperI/O Configuration A Register (SIOCFA)

Location:

Type:

Index 2Ah

R/W

Bit

7

6

0

5

1

4

3

0

2

1

0

1

Name

Pin 53 PPM

FDC Func-

tion Select

Pin 66

Function

Select

Reserved

Reset

0

1

Bit

Description

7

Pin 53 PPM FDC Function Select. This bit deﬁnes which of the following two FDC signals will appear on the PPM.

0: DENSEL (default)

1: DRATE1

6-5 Pin 66 Function Select

Bits

6 5

Function

0 0

0 1

1 0

1 1

Reserved

PWUREQ (default)

Reserved

IRSL3

4-0 Reserved

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46

2.0 Device Architecture and Configuration (Continued)

2.11 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION

2.11.1 General Description

The generic FDC is a standard FDC with a digital data separator, and is DP8473 and N82077 software compatible. The PC8739x

FDC supports 14 of the 17 standard FDC signals described in the generic Floppy Disk Controller (FDC) chapter, including:

●

FM and MFM modes are supported. To select either mode, set bit 6 of the ﬁrst command byte when writing to/read-

ing from a diskette, where:

0 = FM mode

1 = MFM mode

●

A logic 1 is returned for all ﬂoating (TRI-STATE) FDC register bits upon LPC I/O read cycles.

Exceptions to standard FDC support include:

●

Automatic media sense is supported by MSEN1-0 pins only on FDC signals routed to the PPM functional block (on

the Parallel Port)

●

DRATE1 is supported only on FDC signals routed to the PPM functional block (on the Parallel Port).

Table 16 lists the FDC functional block registers.

Table 16. FDC Registers

Offset¹

Mnemonic

Register Name

Status A

Type

00h

01h

02h

03h

04h

SRA

SRB

DOR

TDR

MSR

DSR

FIFO

RO

R/W

R

Status B

Digital Output

Tape Drive

Main Status

Data Rate Select

Data (FIFO)

N/A

W

05h

06h

07h

R/W

X

DIR

Digital Input

Conﬁguration Control

R

CCR

W

1. From the 8-byte aligned FDC base address.

2.11.2 Logical Device 0 (FDC) Configuration

Table 17 lists the configuration registers which affect the FDC. Only the last two registers (F0h and F1h) are described here.

See Sections 2.2.3 and 2.2.4 for descriptions of the others.

Table 17. FDC Conﬁguration Registers

Index

Conﬁguration Register or Action

Type

Reset

30h Activate. See also bit 0 of the SIOCF1 register and bit 0 of the SIOCF6 register. R/W

00h

03h

F2h

06h

03h

02h

04h

24h

00h

60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b.

61h Base Address LSB register. Bits 2 and 0 (for A2 and A0) are read only, 00b.

70h Interrupt Number and Wake-Up on IRQ Enable register

71h Interrupt Type. Bit 1 is read/write; other bits are read only.

74h DMA Channel Select

R/W

RO

75h Report no second DMA assignment

F0h FDC Conﬁguration register

R/W

F1h Drive ID register

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2.0 Device Architecture and Configuration (Continued)

2.11.3 FDC Configuration Register

This register is reset by hardware to 24h.

Location:

Type:

Index F0h

R/W

Bit

7

6

5

4

3

2

1

0

Name

Four-Drive

Encode

Enable

TDR

Register

Mode

DENSEL

Polarity

Control

PC-AT or

PS/2 Drive Reserved

Mode Select

FDC 2Mbps

Enable

Write

Protect

TRI-STATE

Control

Reset

0

1

0

1

0

Bit

Description

7

Four-Drive Encode Enable

0: Two ﬂoppy drives are directly controlled by DR1-0, MTR1-0.

1: Four ﬂoppy drives are controlled with the aid of an external decoder.

6

5

4

3

TDR Register Mode

0: PC-AT compatible drive mode; i.e., bits 7-2 of the TDR are 111111b (default)

1: Enhanced drive mode

DENSEL Polarity Control

0: Active low for 500 Kbps, or 1 or 2 Mbps data rates

1: Active high for 500 Kbps, or 1 or 2 Mbps data rates (default)

FDC 2Mbps Enable. This bit is set only when a 2Mbps drive is used.

0: 2Mbps disabled and the FDC clock is 24 MHz (default)

1: 2Mbps enabled and the FDC clock is 48 MHz

Write Protect. This bit allows forcing of write protect functionality by software. When set, writes to the floppy

disk drive are disabled. This effect is identical to WP when it is active.

0: Write protected according to WP signal (default)

1: Write protected regardless of value of WP signal

2

PC-AT or PS/2 Drive Mode Select

0: PS/2 drive mode

1: PC-AT drive mode (default)

1

0

Reserved

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

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2.0 Device Architecture and Configuration (Continued)

2.11.4 Drive ID Register

This read/write register is reset by hardware to 00h. This register controls bits 5 and 4 of the TDR register in the Enhanced

mode.

Location:

Type:

Index F1h

R/W

Bit

7

6

0

5

0

4

0

3

0

2

0

1

0

Name

Reset

Reserved

Drive 1 ID

Drive 0 ID

0

Bit

Description

7-4 Reserved

3-2 Drive 1 ID. When drive 1 is accessed, these bits are reﬂected on bits 5-4 of the TDR register, respectively.

1-0 Drive 0 ID. When drive 0 is accessed, these bits are reﬂected on bits 5-4 of the TDR register, respectively.

Usage Hints: Some BIOS implementations support automatic media sense FDDs, in which case bit 5 of the TDR register

in the Enhanced mode is interpreted as valid media sense when it is cleared to 0. If drive 0 and/or drive 1 do not support

automatic media sense, bits 1 and/or 3 of the Drive ID register should be set to 1 respectively (to indicate non-valid media

sense) when the corresponding drive is selected and the Drive ID bit is reflected on bit 5 of the TDR register in the Enhanced

mode.

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49

2.0 Device Architecture and Configuration (Continued)

2.12 PARALLEL PORT CONFIGURATION

2.12.1 General Description

The PC8739x Parallel Port supports all IEEE1284 standard communication modes: Compatibility (known also as Standard

or SPP), Bidirectional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ECP (with an optional Extended ECP

mode).

The Parallel Port includes two groups of runtime registers, as follows:

• A group of 21 registers at first level offset, sharing 14 entries. Three of this registers (at offsets 403h, 404h and 405h)

are used only in the Extended ECP mode.

• A group of four registers, used only in the Extended ECP mode, accessed by a second level offset.

The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime reg-

isters are used and which address bits are used for the base address. See Tables 18 and 19 for a listing of all registers, their

offset addresses, and the associated modes.

Table 18. Parallel Port Registers at First Level Offset

Offset

Mnemonic

Mode(s)

Type

Register Name

00h

DATAR

AFIFO

DTR

0,1

R/W

W

Data

3

ECP FIFO (Address)

Data (for EPP)

Status

4

R/W

RO

01h

02h

DSR

0,1,2,3

STR

4

RO

Status (for EPP)

Control

DCR

0,1,2,3

R/W

CTR

4

Control (for EPP)

EPP Address

03h

04h

05h

06h

07h

400h

ADDR

DATA0

DATA1

DATA2

DATA3

EPP Data Port 0

EPP Data Port 1

EPP Data Port 2

EPP Data Port 3

CFIFO

DFIFO

TFIFO

CNFGA

2

3

6

7

W

PP Data FIFO

ECP Data FIFO

Test FIFO

R/W

RO

Conﬁguration A

401h

402h

403h

CNFGB

ECR

7

RO

R/W

Conﬁguration B

Extended Control

Extended Index

0,1,2,3

EIR¹

EDR¹

EAR¹

404h

405h

0,1,2,3

R/W

Extended Data

Extended Auxiliary Status

1. These registers are extended to the standard IEEE1284 registers. They

are accessible only when enabled by bit 4 of the Parallel Port Conﬁgura-

tion register (see Section 2.12.3).

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2.0 Device Architecture and Configuration (Continued)

Table 19. Parallel Port Registers at Second Level Offset

Offset

Mnemonic

Type

Register Name

00h

02h

04h

05h

Control0

Control2

R/W

Extended Control 0

Extended Control 1

Extended Control 4

Conﬁguration 0

Control4

PP Confg0

2.12.2 Logical Device 1 (PP) Configuration

Table 20 lists the configuration registers which affect the Parallel Port. Only the last register (F0h) is described here. See

Sections 2.2.3 and 2.2.4 for descriptions of the others.

Table 20. Parallel Port Conﬁguration Registers

Index

Conﬁguration Register or Action

Type

Reset

30h Activate. See also bit 0 of the SIOCF1 register.

R/W

00h

02h

60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. Bit 2 (for

A10) should be 0b.

61h Base Address LSB register. Bits 1 and 0 (A1 and A0) are read only, 00b. For ECP

Mode 4 (EPP) or when using the Extended registers, bit 2 (A2) should also be 0b.

R/W

78h

70h Interrupt Number and Wake-Up on IRQ Enable register

R/W

07h

02h

71h Interrupt Type

Bits 7-2 are read only.

Bit 1 is a read/write bit.

Bit 0 is read only. It reﬂects the interrupt type dictated by the Parallel Port operation

mode. This bit is set to 1 (level interrupt) in Extended Mode and cleared (edge

interrupt) in all other modes.

74h DMA Channel Select

R/W

RO

04h

F2h

75h Report no second DMA assignment

F0h Parallel Port Conﬁguration register

R/W

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2.0 Device Architecture and Configuration (Continued)

2.12.3 Parallel Port Configuration Register

This register is reset by hardware to F2h.

Location:

Type:

Index F0h

R/W

Bit

7

6

5

4

3

Reserved

0

2

1

0

Name

Extended

Register

Access

PP Reflect-

ed Input

Signals

Power

Mode

Control

TRI-STATE

Control

Parallel Port Mode Select

Reset

1

0

1

0

Bit

Description

7-5 Parallel Port Mode Select

000: SPP Compatible mode. PD7-0 are always output signals.

001: SPP Extended mode. PD7-0 direction is controlled by software.

010: EPP 1.7 mode

011: EPP 1.9 mode

100: ECP mode (IEEE1284 register set), with no support for EPP mode.

101: Reserved

110: Reserved

111: ECP mode (IEEE1284 register set), with EPP mode selectable as mode 4.

Selection of EPP 1.7 or 1.9 in ECP mode 4 is controlled by bit 4 of the Control2 conﬁguration register of the

parallel port at offset 02h.

4

Extended Register Access

0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are ignored).

1: Registers at base (address) + 403h, base + 404h and base + 405h are accessible. This option supports run-

time conﬁguration within the Parallel Port address space.

3

2

Reserved

PP Reflected Input Signals. When the parallel port input signal is disconnected by the PPM, the input signals

reflected by the STR register assume one of the following values:

0: BUSY = 1, PE = 0, SLCT = 0, ACK = 1 (default)

1: BUSY = 1, PE = 1, SLCT = 1, ACK = 1.

1

0

Power Mode Control. When the logical device is active:

0: Parallel port clock disabled. ECP modes and EPP time-out are not functional when the logical device is active.

Registers are maintained.

1: Parallel port clock enabled. All operation modes are functional when the logical device is active (default).

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

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2.0 Device Architecture and Configuration (Continued)

2.13 SERIAL PORT 2 CONFIGURATION

2.13.1 General Description

Serial Port 2 includes IR functionality as described in the Serial Port 2 with IR chapter.

2.13.2 Logical Device 2 (SP2) Configuration

Table 21 lists the configuration registers which affect the Serial Port 2. Only the last register (F0h) is described here. See

Sections 2.2.3 and 2.2.4 for descriptions of the others.

Table 21. Serial Port 2 Conﬁguration Registers

Index

Conﬁguration Register or Action

Type

Reset

30h Activate. See also bit 0 of the SIOCF1 register and bit 2 of the SIOCF6 register. R/W

00h

02h

F8h

03h

04h

02h

60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b.

61h Base Address LSB register. Bit 2-0 (for A2-0) are read only, 000b.

70h Interrupt Number and Wake-Up on IRQ Enable register

71h Interrupt Type. Bit 1 is R/W; other bits are read only.

74h DMA Channel Select 0 (RX_DMA)

R/W

75h DMA Channel Select 1 (TX_DMA)

F0h Serial Port 2 Conﬁguration register

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2.0 Device Architecture and Configuration (Continued)

2.13.3 Serial Port 2 Configuration Register

This register is reset by hardware to 02h.

Location:

Type:

Index F0h

R/W

Bit

7

6

0

5

0

4

3

0

2

1

0

Name

Bank

Select

Enable

Power

Mode

Control

Busy

Indicator

TRI-STATE

Control

Reserved

Reset

0

1

0

Bit

Description

7

Bank Select Enable. Enables bank switching for Serial Port 2.

0: All attempts to access the extended registers in Serial Port 2 are ignored (default).

1: Enables bank switching for Serial Port 2.

6-3 Reserved

2

Busy Indicator. This read only bit can be used by power management software to decide when to power-down

the Serial Port 2 logical device.

0: No transfer in progress (default).

1: Transfer in progress.

1

Power Mode Control. When the logical device is active in:

0: Low power mode

Serial Port 2 clock disabled. The output signals are set to their default states. The RI input signal can be

programmed to generate an interrupt. Registers are maintained (unlike Active bit in index 30 that also

prevents access to Serial Port 2 registers).

1: Normal power mode

Serial Port 2 clock enabled. Serial Port 2 is functional when the logical device is active (default).

0

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

One exception is the IRTX pin, which is driven to 0 when Serial Port 2 is inactive and is not affected by this bit.

0: Disabled (default)

1: Enabled

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2.0 Device Architecture and Configuration (Continued)

2.14 SERIAL PORT 1 CONFIGURATION

2.14.1 Logical Device 3 (SP1) Configuration

Table 22 lists the configuration registers which affect the Serial Port 2. Only the last register (F0h) is described here. See

Sections 2.2.3 and 2.2.4 for descriptions of the others.

Table 22. Serial Port 1 Conﬁguration Registers

Index

Conﬁguration Register or Action

Type

Reset

30h Activate. See also bit 0 of the SIOCF1 register and bit 3 of the SIOCF6 register. R/W

00h

03h

F8h

04h

03h

04h

02h

60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b.

61h Base Address LSB register. Bit 2-0 (for A2-0) are read only, 000b.

70h Interrupt Number and Wake-Up on IRQ Enable register

71h Interrupt Type. Bit 1 is R/W; other bits are read only.

74h Report no DMA Assignment

R/W

RO

75h Report no DMA Assignment

RO

F0h Serial Port 1 Conﬁguration register

R/W

2.14.2 Serial Port 1 Configuration Register

This register is reset by hardware to 02h.

Location:

Type:

Index F0h

R/W

Bit

7

6

0

5

0

4

3

0

2

1

0

Name

Bank

Select

Enable

Power

Mode

Control

Busy

Indicator

TRI-STATE

Control

Reserved

Reset

0

1

0

Bit

Description

7

Bank Select Enable. Enables bank switching for Serial Port 1.

0: Disabled (default).

1: Enabled

6-3 Reserved

2

Busy Indicator. This read only bit can be used by power management software to decide when to power-down

the Serial Port 1 logical device.

0: No transfer in progress (default).

1: Transfer in progress.

1

Power Mode Control. When the logical device is active in:

0: Low power mode

Serial Port 1 clock disabled. The output signals are set to their default states. The RI input signal can be

programmed to generate an interrupt. Registers are maintained (unlike Active bit in Index 30 that also

prevents access to Serial Port 1 registers).

1: Normal power mode

Serial Port 1 clock enabled. Serial Port 1 is functional when the logical device is active (default).

0

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

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2.0 Device Architecture and Configuration (Continued)

2.15 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION

This section applies to the PC87392, PC87393 and PC87393F only.

2.15.1 General Description

The GPIO functional block includes 32 pins, arranged in four 8-bit ports (ports 0, 1, 2 and 3). All pins in ports 0 and 1 are

I/O, and have full event detection capability, enabling them to trigger the assertion of IRQ and SMI signals. Pins in ports 2

and 3 are I/O, but none of them has event detection capability. The twelve runtime registers associated with the four ports

are arranged in the GPIO address space as shown in Table 23. The GPIO base address is 16-byte aligned. Address bits 3-

0 are used to indicate the register offset.

Table 23. Runtime Registers in GPIO Address Space

Offset

Mnemonic

GPDO0 GPIO Data Out 0

GPDI0 GPIO Data In 0

Register Name

Port Type

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0

1

R/W

RO

GPEVEN0 GPIO Event Enable 0

GPEVST0 GPIO Event Status 0

GPDO1 GPIO Data Out 1

R/W

R/W1C

R/W

RO

GPDI1

GPIO Data In 1

GPEVEN1 GPIO Event Enable 1

GPEVST1 GPIO Event Status 1

GPDO2 Data Out 2

R/W

R/W1C

R/W

RO

2

3

GPDI2

GPDO3 Data Out 3

GPDI3 Data In 3

Data In 2

R/W

RO

2.15.2 Implementation

The standard GPIO port with event detection capability (such as ports 0 and 1) has four runtime registers. Each pin is asso-

ciated with a GPIO Pin Configuration register that includes seven configuration bits. Ports 2 and 3 are non-standard ports

that do not support event detection, and therefore differ from the generic model as follows:

●

They each have two runtime registers for basic functionality: GPDO2/3 and GPDI2/3. Event detection registers

GPEVEN2/3 and GPEVST2/3 are not available.

●

Only bits 3-0 are implemented in the GPIO Pin Conﬁguration registers of ports 2 and 3. Bits 6-4, associated with the

event detection functionality, are reserved.

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2.0 Device Architecture and Configuration (Continued)

2.15.3 Logical Device 7 (GPIO) Configuration

Table 24 lists the configuration registers which affect the GPIO. Only the last three registers (F0h - F2h) are described here.

See Sections 2.2.3 and 2.2.4 for a detailed description of the others.

Table 24. GPIO Conﬁguration Register

Index

Conﬁguration Register or Action

Type

Reset

30h Activate. See also bit 7 of the SIOCF1 register.

60h Base Address MSB register

R/W

RO

00h

03h

04h

00h

44h

01h

61h Base Address LSB register. Bits 3-0 (for A3-0) are read only, 0000b.

70h Interrupt Number and Wake-Up on IRQ Enable register

71h Interrupt Type. Bit 1 is read/write. Other bits are read only.

74h Report no DMA assignment

75h Report no DMA assignment

RO

F0h GPIO Pin Select register

R/W

F1h GPIO Pin Conﬁguration register

F2h GPIO Pin Event Routing register

Figure 6 shows the organization of these registers.

GPIO Pin Select Register

(Index F0h)

Port Select

Pin Select

Port 3, Pin 0

Port 2, Pin 0

Port 1, Pin 0

Port 0, Pin 0

Pin 0

Port 0

GPIO Pin

Conﬁguration Register

(Index F1h)

Conﬁguration Registers

Port 0, Pin 7

Port 3

Pin 7

Pin 0

Port 1, Pin 0

Port 0, Pin 0

Port 0

Port 1

GPIO Pin Event

Routing Register

(Index F2h)

Event Routing

Registers

Port 0, Pin 7

Pin 7

Figure 6. Organization of GPIO Pin Registers

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2.0 Device Architecture and Configuration (Continued)

2.15.4 GPIO Pin Select Register

This register selects the GPIO pin (port number and bit number) to be configured (i.e., which register is accessed via the

GPIO Pin Configuration register). It is reset by hardware to 00h.

Location:

Type:

Index F0h

R/W

Bit

7

6

0

5

0

4

0

3

Reserved

0

2

0

1

Pin Select

0

Name

Reset

Reserved

Port Select

0

Bit

Description

7-6 Reserved

5-4 Port Select. These bits select the GPIO port to be configured:

00: Port 0 (default)

01, 10, 11: Binary value of port numbers 1-3 respectively. All other values are reserved.

3

Reserved

2-0 Pin Select. These bits select the GPIO pin to be conﬁgured in the selected port:

000, 001,... 111: Binary value of the pin number, 0, 1,... 7 respectively (default=0)

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2.0 Device Architecture and Configuration (Continued)

2.15.5 GPIO Pin Configuration Register

This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register. All the GPIO

Pin registers that are accessed via this register have a common bit structure, as shown below. This register is reset by hard-

ware to 44h, except for ports 2 and 3, that are reset to 04h, and GPIO36 which resets to 00h.

Location:

Type:

Index F1h

R/W

Ports: 0 and 1 (with event detection capability)

Bit

7

6

5

4

3

Lock

0

2

1

0

Name

Event

Polarity

Pull-Up

Control

Output

Type

Output

Enable

Reserved Debounce

Enable

Event Type

Reset

0

1

0

1

0

Ports 2 and 3 (without event detection capability)

Bit

7

0

6

0

5

0

4

0

3

Lock

0

2

1

0

Name

Pull-Up

Control

Output

Type

Output

Enable

Reserved

Reset

1

0

Bit

Description

7

6

Reserved

Event Debounce Enable. (Ports 0 and 1 with event detection capability). Enables transferring the signal only

after a predetermined debouncing period of time.

0: Disabled

1: Enabled (default)

Reserved. (Ports 2 and 3). Always 0.

5

4

3

Event Polarity. (Ports 0 and 1 with event detection capability). This bit deﬁnes the polarity of the signal that

issues an interrupt from the corresponding GPIO pin (falling/low or rising/high).

0: Falling edge or low level input (default)

1: Rising edge or high level input

Reserved. (Ports 2 and 3). Always 0.

Event Type. (Ports 0 and 1 with event detection capability). This bit deﬁnes the type of the signal that issues an

interrupt from the corresponding GPIO pin (edge or level).

0: Edge input (default)

1: Level input

Reserved. (Ports 2 and 3). Always 0.

Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to

0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1 (bit 7 of SuperI/O

Conﬁguration 1 register, SIOCF1).

0: No effect (default)

1: Direction, output type, pull-up and output value locked

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2.0 Device Architecture and Configuration (Continued)

Bit

Description

2

Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin.

It supports open-drain output signals with internal pull-ups and TTL input signals.

0: Disabled

1: Enabled (default)

1

0

Output Type. This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin.

0: Open-drain (default)

1: Push-pull

Output Enable. This bit indicates the GPIO pin output state. It has no effect on the input path.

0: TRI-STATE (default)

1: Output enabled

2.15.6 GPIO Event Routing Register

This register enables the routing of the GPIO event to IRQ and/or SMI signals. It is implemented only for ports 0,1 which

have event detection capability. This register is reset by hardware to 00h.

Location:

Type:

Index F2h

R/W

Bit

7

6

0

5

0

4

0

3

0

2

0

1

0

Name

Enable SMI Enable IRQ

Routing

Reserved

Routing

Reset

0

1

Bit

Description

7-2 Reserved

1

Enable SMI Routing

0: Disabled (default)

1: Enabled

0

Enable IRQ Routing

0: Disabled

1: Enabled (default)

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2.0 Device Architecture and Configuration (Continued)

2.16 WATCHDOG TIMER (WDT) CONFIGURATION

2.16.1 Logical Device 10 (WDT) Configuration

Table 25 lists the configuration registers which affect the WATCHDOG Timer. Only the last register (F0h) is described here.

See Sections 2.2.3 and 2.2.4 for a detailed description of the others.

Table 25. WDT Conﬁguration Registers

Index

Conﬁguration Register or Action

Type

Reset

30h Activate. When bit 0 is cleared, the registers of this logical device are not

accessible.

R/W

00h

60h Base Address MSB register

R/W

00h

61h Base Address LSB register. Bits 1 and 0 (for A1 and A0) are read only, 00b. R/W

70h Interrupt Number (for routing the WDO signal) and Wake-Up on IRQ Enable R/W

register.

71h Interrupt Type. Bit 1 is read/write. Other bits are read only.

74h Report no DMA assignment

R/W

RO

03h

04h

02h

75h Report no DMA assignment

RO

F0h WATCHDOG Timer Conﬁguration register

R/W

2.16.2 WATCHDOG Timer Configuration Register

This register is reset by hardware to 02h.

Location:

Type:

Index F0h

R/W

Bit

7

0

6

0

5

0

4

0

3

2

1

0

Name

Internal

Pull-Up

Enable

Power

Mode

Control

Output

Type

TRI-STATE

Control

Reserved

Reset

0

1

0

Bit

Description

7-4 Reserved

3

2

1

Output Type. This bit controls the buffer type (open-drain or push-pull) of the WDO pin.

0: Open-drain (default)

1: Push-pull

Internal Pull-Up Enable. This bit controls the internal pull-up resistor on the WDO pin.

0: Disabled (default)

1: Enabled

Power Mode Control

0: Low power mode:

WATCHDOG Timer clock disabled. WDO output signal is set to 1. Registers are accessible and maintained

(unlike Active bit in Index 30h that also prevents access to WATCHDOG Timer registers).

1: Normal power mode:

WATCHDOG Timer clock enabled. WATCHDOG Timer is functional when the logical device is active (default).

0

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

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2.0 Device Architecture and Configuration (Continued)

2.17 GAME PORT (GMP) CONFIGURATION

This section applies to the PC87393 and PC87393F only.

2.17.1 Logical Device 11 (GMP) Configuration

Table 26 lists the configuration registers which affect the Game Port. Only the last register (F0h) is described here. See Sec-

tions 2.2.3 and 2.2.4 for a detailed description of the others.

Table 26. GMP Conﬁguration Registers

Index

Conﬁguration Register or Action

Type

Reset

30h Activate. When bit 0 is cleared, the registers of this logical device are not

accessible.

R/W

00h

60h Base Address MSB register

R/W

RO

02h

01h

00h

03h

04h

00h

61h Base Address LSB register.

70h Interrupt Number and Wake-Up on IRQ Enable register.

71h Interrupt Type. Bit 1 is read/write. Other bits are read only.

74h Report no DMA assignment

75h Report no DMA assignment

RO

F0h Game Port Conﬁguration register

R/W

2.17.2 Game Port Configuration Register

This register is reset by hardware to 00h.

Location:

Type:

Index F0h

R/W

Bit

7

0

6

0

5

0

4

3

2

1

0

Name

GMP

Enhanced

Mode Enable Enable

Internal

Pull-Up

TRI-STATE

Control

Reserved

Reset

0

Bit

Description

7-4 Reserved

3

GMP Enhanced Mode Enable. See Usage Hints below.

0: Disabled (default)

1: Enabled

2

Internal Pull-Up Enable. When the GMP functions are selected, this bit controls the internal pull-up resistor on

pins 96 (GPIO07/JOYABTN0), 3 (GPIO00/JOYABTN1), 97 (GPIO06/JOYBBTN0) and 2 (GPIO01/JOYBBTN1) or

pins 74 (GPIO17/JOYABTN0), 81 (GPIO10/JOYABTN1), 75 (GPIO16/JOYBBTN0), 80 (GPIO11/JOYBBTN1).

0: Disabled (default)

1: Enabled

1

0

Reserved

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

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2.0 Device Architecture and Configuration (Continued)

Usage Hints: To operate GMP enhanced features, make sure to locate its base address within the LPC Wide Generic ad-

dress range.

When bit 3 of the GMP configuration register is set to 0 (default), the GMP operates in Legacy mode. In this mode, only the

Game Port Legacy Status (GMPLST) register of the GMP is accessible, and is mapped to the base address of the GMP.

For example, if GMP configuration bit 3 is set to 0 and the base address is programmed to 203h, the GMPLST register is

mapped to address 203h, and is the only user-accessible GMP register.

The GMP is also forced to operate in Legacy mode if the programmed base address is not 16-byte aligned; i.e. bits 3-0 of

the base address are not all 0’s.

When bit 3 of the GMP register is set to 1 and the programmed GMP base address is 16-byte aligned; i.e., bits 3-0 of the

base address are all 0’s, the GMP can be operated in Enhanced mode. In this condtion, all the registers listed in the GMP

chapter are accessible.

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2.0 Device Architecture and Configuration (Continued)

2.18 MIDI PORT (MIDI) CONFIGURATION

This section applies to the PC87393 and PC87393F only.

2.18.1 Logical Device 12 (MIDI) Configuration

Table 26 lists the configuration registers which affect the MIDI Port. Only the last register (F0h) is described here. See Sec-

tions 2.2.3 and 2.2.4 for a detailed description of the others.

Table 27. MIDI Conﬁguration Registers

Index

Conﬁguration Register or Action

Type

Reset

30h Activate. When bit 0 is cleared, the registers of this logical device are not accessible.

60h Base Address MSB register

R/W

00h

03h

30h

00h

03h

04h

00h

61h Base Address LSB register. Bit 0 (for A0) is read only, 0b.

70h Interrupt Number and wake-up on IRQ enable.

71h Interrupt Type. Bit 1 is read/write. Other bits are read only.

74h Report no DMA assignment

Varies per bit

R/W

RO

75h Report no DMA assignment

RO

F0h MIDI Port Conﬁguration register

R/W

2.18.2 MIDI Port Configuration Register

This register is reset by hardware to 00h.

Location:

Type:

Index F0h

R/W

Bit

7

0

6

0

5

0

4

3

2

1

Reserved

0

Name

MIDI

Enhanced

Mode Enable Enable

Internal

Pull-Up

TRI-STATE

Control

Reserved

Reset

0

Bit

Description

7-4 Reserved

3

MIDI Enhanced Mode Enable. See Usage Hints below.

0: Disabled (default)

1: Enabled

2

Internal Pull-Up Enable. This bit controls the internal pull-up resistor on pin 83 (GPIO32/MDRX).

0: Disabled (default)

1: Enabled

1

0

Reserved

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

Usage Hints: To operate MIDI enhanced features, make sure to locate its base address within the LPC Wide Generic ad-

dress range.

When bit 3 of the MIDI configuration register is set to 0 (default), the MIDI operates in Legacy mode. In this mode, only the

MIDI IN, MIDI OUT, MIDI Status and MIDI Command registers of the MIDI are user-accessible.

When bit 3 of the MIDI configuration register is set to 1, the MIDI is operated in Enhanced mode. In this condition, all the

registers listed in the MIDI chapter are accessible.

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2.0 Device Architecture and Configuration (Continued)

2.19 X-BUS CONFIGURATION

This section applies to the PC87393 and PC87393F only. FWH-related descriptions apply to the PC87393F only.

2.19.1 Logical Device 15 (X-Bus) Configuration

Table 28 lists the configuration registers that affect the X-Bus functional block. The X-Bus base address registers point to

the X-Bus registers described in the X-Bus chapter. The memory space to which the X-Bus responds is defined by the con-

figuration registers in the following sections. See Sections 2.2.3 and 2.2.4 for a detailed description of the others.

Table 28. X-Bus Conﬁguration Registers

Index

Conﬁguration Register or Action

Type

Reset

30h Activate. When bit 0 is cleared, the registers of this logical device are not accessible.

60h Base Address MSB register

R/W

00h

61h Base Address LSB register. Bits 3-0 (for A3-A0) are read only, 0000b.

Varies per

bit

70h Interrupt Number and wake-up on IRQ enable.

71h Interrupt Type.

RO

00h

04h

00h

74h Report no DMA assignment

RO

75h Report no DMA assignment

RO

F0h X-Bus I/O Conﬁguration register

R/W

F1h X-Bus I/O Base Address High Byte register

F2h X-Bus I/O Base Address Low Byte register

F3h X-Bus I/O Size Conﬁguration register

F4h X-Bus Memory Conﬁguration register

F5h X-Bus Memory Base Address High Byte register

F6h X-Bus Memory Base Address Low Byte register

F7h X-Bus Memory Size Conﬁguration register

F8h X-Bus PIRQA and PIRQB Mapping register

F9h X-Bus PIRQC and PIRQD Mapping register

2.19.2 X-Bus I/O Range Programming

LPC I/O transactions can be forwarded to the PC8739x X-Bus. The X-Bus I/O configuration registers define the map of ad-

dresses to be forwarded. The PC8739x provides five, individually enabled I/O zones. Each zone generates an internal select

signal that is sent to the X-Bus functional block. The mapping of the internal select signals to the PC8739x XCS0-1 signals

is controlled by the X-Bus. See Section 7.3 for further details.

The supported I/O zones are:

●

Keyboard controller (KBC) - legacy 60h, 64h addresses and an alternate location

●

Power Management & Embedded Controller (PM) - legacy 62h, 66h and an alternate location

●

Real Time Clock (RTC) - legacy 70h, 71h and two alternate locations

User-Deﬁned I/O Zone (UDIZ) - speciﬁed using the zone size (2ⁿwhere n is 1 through 8) and start address (must be

●

aligned with the block size)

●

Debug Port Address Enable (TST) - This zone is for debug use only.

These decoded I/O zones are determined by the following four registers: X-Bus I/O Configuration, X-Bus I/O Zone Base

Address High and Low Byte, and X-Bus I/O Size Configuration. When a zone (e.g. KBC, PM or RTC) is enabled but is not

associated with any select signal in the X-Bus interface, a value of 00h is read and data written is ignored.

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2.0 Device Architecture and Configuration (Continued)

2.19.3 X-Bus Memory Range Programming

LPC memory transactions and/or LPC-FWH transactions can be forwarded to the PC8739x X-Bus. The X-Bus Memory Con-

figuration register defines the address space to which the PC8739x responds. The XCNF2-0 strap inputs impact the default

setting of the X-Bus Memory Configuration register enable boot process from memories connected on the X-Bus. Two mem-

ory areas may be individually enabled: a user-defined zone, and BIOS memory (BIOS-LPC and/or BIOS-FWH spaces).

To enable BIOS support, set the XCNF2-0 strap inputs to select any of the BIOS modes (see Section 1.5.11 for details). The

PC8739x responds to LPC memory read and write transactions to/from the BIOS address spaces, shown in Table 29, as

long as BIOS LPC Enable (bit 0) of the X-Bus Memory Configuration register is set.

Table 29. BIOS-LPC Memory Space Deﬁnition

Memory Address Range

Description

000E 0000h - 000E FFFFh

Extended BIOS Range (Legacy)

Only when Extended BIOS Enable bit in X-Bus Memory

Range Conﬁguration register is set

000F 0000h - 000F FFFFh

BIOS Range (Legacy)

FFC0 0000h - FFFFF FFFh 386 mode BIOS Range.

This is the upper 4 Mbyte of the memory space

The PC8739x responds to LPC-FWH read and write transactions from/to the high memory address range (’386’ mode BIOS

range), shown in Table 29, as long as BIOS FWH Enable (bit 3) of the X-Bus Memory Configuration register is set.

Table 30. BIOS-FWH Memory Space Deﬁnition

Memory Address Range

Description

FFC0 0000h - FFFFF FFFh 386 mode BIOS Range.

This is the upper 4 Mbyte of the memory space

Upon reset in BIOS enabled mode (XCNF≠000), the BIOS LPC Enable bit is set and the BIOS FWH Enable bit is set. The

PC8739x automatically detects the type of host boot protocol in use via the first completed BIOS read operation after reset.

If the first read is an LPC memory read, the BIOS FWH Enable bit is cleared. If the first read is an LPC-FWH read, the BIOS

LPC Enable bit is cleared. Any other LPC or LPC-FWH transactions are ignored. The bits are cleared only by the first read

operation, allowing software to enable response to these address ranges by setting the bit. Figure 7 illustrates this behavior.

XCNF[2-0] Disable BIOS

BIOS FWH Enable =0

BIOS LPC Enable = 0

RESET

BIOS FWH Enable =1

BIOS LPC Enable = 1

First LPC FWH Read

First LPC Memory Read

BIOS FWH Enable =0

BIOS LPC Enable = 1

BIOS FWH Enable =1

BIOS LPC Enable = 0

Note:

Only hardware-controlled transitions

are shown. Other transitions are

possible via software writes to the bits.

Figure 7. BIOS Mapping Enable Scheme

The User-Defined Memory Zone (UDMZ) is specified via a 32-bit start address. This address is formed by 8 bits of the X-

Bus Memory Base Address Low Byte register, 8 bits of the X-Bus Memory Base Address HIgh Byte register and 16 least

significant bits of 0. The size of the window is specified through the X-Bus Memory Size Configuration register. The zone

base address must be aligned to the block size.

The address used for the X-Bus transaction is the 28 least significant bits of the address bus. In read transactions, the data

read from the X-Bus is passed to the LPC bus. In write transactions, the data from the LPC is passed to the X-Bus.

2.19.4 X-Bus I/O Configuration Register

This register is reset by hardware to 00h.

Location:

Index F0h

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2.0 Device Architecture and Configuration (Continued)

Type:

R/W

Bit

7

6

5

4

3

2

1

0

Name

User-

TST

Defined I/O Address

RTC Address Enable

PM Address Enable

KBC Address Enable

Zone

Enable

Reset

0

Bit

Description

7

User-Deﬁned I/O Zone Enable. This bit enables the mapping of the User-Deﬁned I/O zone to the X-Bus space.

The zone base address and size are deﬁned by the X-Bus I/O Base Address High Byte register, X-Bus I/O Base

Address Low Byte register and the X-Bus I/O Size Conﬁguration register.

0: Disabled (default)

1: Enabled

6

TST (Debug Port) Address Enable. When set, enables the mapping of I/O address 80h to the X-Bus space.

0: Disabled (default)

1: Enabled

5-4 RTC Address Enable. This bit controls the mapping of the RTC I/O address to the X-Bus space.

Bits

5 4

Mapping (hex)

0 0

0 1

1 0

1 1

Disabled (default)

70, 71

370, 371

70, 71, 72, 73

3-2 PM Address Enable. This bit controls the mapping of the PM I/O address to the X-Bus space.

Bits

3 2

Mapping (hex)

0 0

0 1

1 0

1 1

Disabled (default)

62, 66

362, 366

Reserved

1-0 KBC Address Enable. This bit controls the mapping of the KBC I/O address to the X-Bus space.

Bits

1 0

Mapping (hex)

0 0

0 1

1 0

1 1

Disabled (default)

60, 64

360, 364

Reserved

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2.0 Device Architecture and Configuration (Continued)

2.19.5 X-Bus I/O Base Address High Byte Register

This register describes the high byte for the user-defined I/O zone mapped to the X-Bus. This register is reset by hardware

to 00h.

Location:

Type:

Index F1h

R/W

Bit

7

6

0

5

0

4

3

2

0

1

0

Name

Reset

User-Defined Zone Address High

0

Bit

Description

7-0 User-Deﬁned Zone Address High. Deﬁnes the higher 8 bits of the user-deﬁned I/O block base address. The

base address should be aligned on the selected block size.

2.19.6 X-Bus I/O Base Address Low Byte Register

This register describes the low byte for the user-defined I/O zone mapped to the X-Bus. This register is reset by hardware

to 00h.

Location:

Type:

Index F2h

R/W

Bit

7

6

0

5

0

4

3

2

0

1

0

Name

Reset

User-Defined Zone Address Low

0

Bit

Description

7-0 User-Deﬁned Zone Address Low. Deﬁnes the lower 8 bits of the user-deﬁned I/O block base address. The

base address should be aligned on the selected block size.

2.19.7 X-Bus I/O Size Configuration Register

This register defines the size of the user-defined I/O zone mapped to the X-Bus. This register is reset by hardware to 00h.

Location:

Type:

Index F3h

R/W

Bit

7

6

0

5

0

4

0

3

0

2

1

0

Name

Reset

Reserved

User-Defined I/O Zone Size

0

Bit

Description

7-4 Reserved

3-0 User-Deﬁned I/O Zone Size. Deﬁnes the size in bytes of the zone window. The size is deﬁned as a power of

two using the equation: NumOfBytes = 2ⁿ(User-Deﬁned I/O Zone size). The zone must always be aligned to the

window size (i.e., for a 128 byte window, the 7 LSBs of the address are zero).

Bits

Size (Bytes)

3 2 1 0

0 0 0 0 1 (default)

. . .

1 0 0 0 256

Other

Reserved

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2.0 Device Architecture and Configuration (Continued)

2.19.8 X-Bus Memory Configuration Register

This register is reset by hardware to 00h.

Location:

Type:

Index F4h

R/W

Bit

7

0

6

5

4

0

3

2

1

0

Name

User-

Defined

Memory

Space

BIOS

BIOS FWH

Enable

Extended BIOS LPC

Space

Enable

BIOS FWH ID

Enable

Reset

0

Depends on strap setting.

Bit

Description

7-4 BIOS FWH ID. The identiﬁcation nibble that is part of a FWH transaction (see Section 2.8.1 for details), which

identiﬁes the device addressed.

3

2

BIOS FWH Enable. When set, enables PC8739x response to LPC-FWH transactions to the BIOS-FWH space,

if the BIOS FWH ID matches the ID of the transaction.. The reset value of this register is deﬁned by the XCNF2-

0 conﬁguration inputs. The value of this bit is later updated, based on the detected host BIOS scheme, see

Section 2.19.3 for details.

0: Disabled (default when XCNF disable BIOS conﬁguration)

1: Enabled (default when XCNF enable BIOS conﬁguration)

User-Defined Memory Space Enable. When set, enables the PC8739x to respond to LPC memory read and

write accesses in the user-deﬁned memory area range. The base address and size of the user-deﬁned range is

speciﬁed by X-Bus Memory Base Address High and Low Byte registers and the X-Bus Memory Size

Conﬁguration register.

0: Disabled (default)

1: Enabled

1

0

BIOS Extended Space Enable. Expands the BIOS address space to which the PC8739x responds to include

the Extended BIOS address range.

0: Disabled (default)

1: Enabled

BIOS LPC Enable. Enables the PC8739x to respond to LPC memory accesses to the BIOS-LPC space. The

reset value of this register is deﬁned by the XCNF2-0 conﬁguration inputs. The value of this bit is later updated,

based on the detected host BIOS scheme (see Section 2.19.3 for details).

0: Disabled (default when XCNF disable BIOS conﬁguration)

1: Enabled (default when XCNF enable BIOS conﬁguration)

2.19.9 X-Bus Memory Base Address High Byte Register

This register describes the high byte for the user-defined memory zone mapped to the X-Bus (decoded as bits 31 to 24 of

the 32-bit address range, bits 15-0 are 0). This register is reset by hardware to 00h.

Location:

Type:

Index F5h

R/W

Bit

7

6

0

5

4

3

2

1

0

Name

Reset

User-Defined Memory Zone Address High

0

Bit

Description

7-0 User-Deﬁned Memory Zone Address High. Deﬁnes the higher 8 bits of the user-deﬁned memory block base

address. The base address should be aligned on the selected block size.

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2.0 Device Architecture and Configuration (Continued)

2.19.10 X-Bus Memory Base Address Low Byte Register

This register describes the low byte for the user-defined memory zone mapped to the X-Bus (decoded as bits 23 to 16 of

the 32-bit address range; bits 15 to 0 are 0). This register is reset by hardware to 00h.

Location:

Type:

Index F6h

R/W

Bit

7

6

0

5

4

3

2

1

0

Name

Reset

User-Defined Memory Zone Address Low

0

Bit

Description

7-0 User-Deﬁned Memory Zone Address Low. Deﬁnes the lower 8 bits of the user-deﬁned memory block base

address. The base address should be aligned on the selected block size.

2.19.11 X-Bus Memory Size Configuration Register

This register defines the size of the user-defined memory zone mapped to the X-Bus. This register is reset by hardware to

00h.

Location:

Type:

Index F7h

R/W

Bit

7

6

0

5

0

4

0

3

0

2

1

0

Name

Reset

Reserved

User-Defined Memory Zone Size

0

Bit

Description

7-4 Reserved

3-0 User-Deﬁned Memory Zone Size. Deﬁnes the size in bytes of the zone window. The size is deﬁned as a power

of two using the equation: NumOfBytes = 2ⁿ(User-Deﬁned Memory Zone size+16). The zone must always be

aligned to the window size (i.e., for a 128 Kbyte window, the 17 LSBs of the address should be zero.

Bits

Size (Bytes)

3 2 1 0

0 0 0 0 64K (default)

. . .

1 0 0 0 16M

Other

Reserved

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2.0 Device Architecture and Configuration (Continued)

2.19.12 X-Bus PIRQA and PIRQB Mapping Register

This set of registers defines the mapping of the PIRQA and PIRQB signals.

Location:

Type:

Index F8h

R/W

Bit

7

6

5

4

0

3

0

2

1

0

Name

PIRQB Mapping

PIRQA Mapping

0 0

Reset

0

Bit

Description

7-4 PIRQB Mapping. Deﬁnes to which host IRQ the PIRQB input is routed.

Bits

Function

3 2 1 0

0 0 0 0 IRQ Disabled (default)

0 0 0 1 IRQ1

. . .

1 1 1 1

IRQ 15

3-0 PIRQA Mapping. Deﬁnes to which host IRQ the PIRQA input is routed.

Bits

Function

3 2 1 0

0 0 0 0 IRQ Disabled (default)

0 0 0 1 IRQ1

. . .

1 1 1 1

IRQ 15

2.19.13 X-Bus PIRQC and PIRQD Mapping Register

This set of registers defines the mapping of the PIRQC and PIRQD signals.

Location:

Type:

Index F9h

R/W

Bit

7

6

5

4

3

0

2

1

0

Name

PIRQD Mapping

PIRQC Mapping

Reset

0

Bit

Description

7-4 PIRQD Mapping. Deﬁnes to which host IRQ the PIRQD input is routed.

Bits

Function

3 2 1 0

0 0 0 0 IRQ Disabled (default)

0 0 0 1 IRQ1

. . .

1 1 1 1

IRQ 15

3-0 PIRQC Mapping. Deﬁnes to which host IRQ the PIRQC input is routed.

Bits

Function

3 2 1 0

0 0 0 0 IRQ Disabled (default)

0 0 0 1 IRQ1

. . .

1 1 1 1

IRQ 15

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3.0 General-Purpose Input/Output (GPIO) Port

Note: This section applies to the PC87392, PC87393 and PC87393F only.

This chapter describes one 8-bit port. A device may include a combination of several ports with different implementations.

For the device specific implementation, see the Device Architecture and Configuration chapter.

3.1 OVERVIEW

The GPIO port is an 8-bit port, which is based on eight pins. It features:

●

Software capability to manipulate and read pin levels

●

Controllable system notiﬁcation by several means based on the pin level or level transition

●

Ability to capture and manipulate events and their associated status

●

Back-drive protected pins.

GPIO port operation is associated with two sets of registers:

●

Pin Conﬁguration registers, mapped in the Device Conﬁguration space. These registers are used to statically set up

the logical behavior of each pin. There are two 8-bit register for each GPIO pin.

●

Four 8-bit runtime registers: GPIO Data Out (GPDO), GPIO Data In (GPDI), GPIO Event Enable (GPEVEN) and

GPIO Event Status (GPEVST). These registers are mapped in the GPIO device IO space (which is determined by

the base address registers in the GPIO Device Conﬁguration). They are used to manipulate and/or read the pin val-

ues, and to control and handle system notiﬁcation. Each runtime register corresponds to the 8-pin port, such that bit

n in each one of the four registers is associated with GPIOXn pin, where X is the port number.

Each GPIO pin is associated with ten configuration bits and the corresponding bit slice of the four runtime registers, as

shown in Figure 8.

The functionality of the GPIO port is divided into basic functionality that includes the manipulation and reading of the GPIO

pins, and enhanced functionality. The basic functionality is described in Section 3.2. The enhanced functionality which in-

cludes the event detection and system notification is described in Section 3.3.

Bit n

GPDOX

GPIOX Base Address

GPDIX

Runtime

8 GPCFG

Registers

GPEVENX

GPEVSTX

Registers

X = port number

n = pin number, 0 to 7

GPIO Pin

Conﬁguration (GPCFG)

Register

GPIOXn

GPIOXn CNFG

GPIOXn

Port Logic

x8

Port and Pin

Select

GPIO Pin

Select (GPSEL)

Register

x8

8 GPEVR

Registers

Event

Pending

Indicator

Interrupt

Request

Event

Routing

Control

SMI

x8

GPIO Pin Event

Routing (GPEVR)

Register

GPIOXn ROUTE

Figure 8. GPIO Port Architecture

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3.0 General-Purpose Input/Output (GPIO) Port (Continued)

3.2 BASIC FUNCTIONALITY

The basic functionality of each GPIO pin is based on four configuration bits and a bit slice of runtime registers GPDO and

GPDI. The configuration and operation of a single pin GPIOXn (pin n in port X) is shown in Figure 9.

GPIO Device

Enable

Read Only

Data In

Static

Pull-Up

Push-Pull =1

Read/Write

Data Out

Internal

Bus

Pull-Up

Enable

Output

Enable

Output

Type

Pull-Up

Control

Lock

Bit 3

Bit 2

Bit 1

Bit 0

GPIO Pin Conﬁguration (GPCFG) Register

Figure 9. GPIO Basic Functionality

3.2.1

Configuration Options

The GPCFG register controls the following basic configuration options:

• Port Direction - Controlled by the Output Enable bit (bit 0)

• Output Type - Push-pull vs. open-drain. It is controlled by Output Buffer Type (bit 1) by enabling/disabling the pull-up

portion of the output buffer.

• Weak Static Pull-Up - May be added to any type of port (input, open-drain or push-pull). It is controlled by Pull-Up Control

(bit 2).

• Pin Lock - GPIO pin may be locked to prevent any changes in the output value and/or the output characteristics. The

lock is controlled by Lock (bit 3). It disables writes to the GPDO register bits, and to bits 0-3 of the GPCFG register (In-

cluding the Lock bit itself). Once locked, it can be released by hardware reset only.

3.2.2

Operation

The value that is written to the GPDO register is driven to the pin, if the output is enabled. Reading from the GPDO register

returns its contents, regardless of the pin value or the port configuration. The GPDI register is a read-only register. Reading

from the GPDI register returns the pin value, regardless of what is driving it (the port itself, configured as an output port, or

the external device when the port is configured as an input port). Writing to this register is ignored.

Activation of the GPIO port is controlled by external device specific configuration bit (or a combination of bits). When the port

is inactive, access to GPDI and GPDO registers is disabled, and the inputs are blocked. However, there is no change in the

port configuration and in the GPDO value, and hence there is no effect on the outputs of the pins.

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3.0 General-Purpose Input/Output (GPIO) Port (Continued)

3.3 EVENT HANDLING AND SYSTEM NOTIFICATION

The enhanced GPIO port supports system notification based on event detection. This functionality is based on six configu-

ration bits and a bit slice of runtime registers GPEVEN and GPEVST. The configuration and operation of the event detection

capability is shown in Figure 10. The operation of system notification is illustrated in Figure 11.

1

Event

Pending

Indicator

0

R/W

Event

Enable

0

1

Rising

Edge

Detector

R/W 1 to Clear

Input

Status

Debouncer

Detected

Enabled Events

from other

GPIO Pins

Rising Edge or

High Level =1

Level =1

Internal

Bus

Event

Event Type

Debounce

Event Polarity

Bit 5

Enable

Bit 6

Bit 4

GPIO Pin Conﬁguration Register

Figure 10. Event Detection

3.3.1

Event Configuration

Each pin in the GPIO port is a potential input event source. The event detection can trigger a system notification upon pre-

determined behavior of the source pin. The GPCFG register determines the event detection trigger type for the system no-

tification.

Event Type and Polarity

Two trigger types of event detection are supported: edge and level. An edge event may be detected upon a source pin tran-

sition either from high to low or low to high. A level event may be detected when the source pin is in active level. The trigger

type is determined by Event Type (bit 4 of the GPCFG register). The direction of the transition (for edge) or the polarity of

the active level (for level) is determined by Event Polarity (bit 5 of the GPCFG register).

Event Debounce Enable

The input signal can be debounced for about 15 msec before entering the detector. The signal state is transferred to the

detector only after a debouncing period during which the signal has no transitions, to ensure that the signal is stable. The

debouncer adds 15 msec delay to both assertion and de-assertion of the event pending indicator. Therefore, when working

with a level event and system notification by either SMI or IRQ, it is recommended to disable the debounce if the delay in

the SMI/IRQ de-assertion is not acceptable. The debounce is controlled by Event Debounce Enable (bit 6 of the GPCFG

register).

3.3.2

System Notification

System notification on GPIO-triggered events is by means of assertion of one or more of the following output pins:

●

Interrupt Request (via the device’s Bus Interface)

●

System Management Interrupt (SMI, via the device’s Bus Interface)

The system notiﬁcation for each GPIO pin is controlled by the corresponding bits in the GPEVEN and GPEVR registers.

System notification by a GPIO pin is enabled if the corresponding bit of the GPEVEN register is set to 1. The corresponding

bits in the GPEVR register select which means of system notification the detected event is routed to. The event routing

mechanism is described in Figure 11.

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3.0 General-Purpose Input/Output (GPIO) Port (Continued)

Event Pending Indicator

SMI

IRQ

Event

Routing

Logic

Enable

SMI

Routing

Enable

IRQ

Routing

Routed Events

from other GPIO Pins

Bit 1

Bit 0

GPIO Pin Event Routing Register

Figure 11. GPIO Event Routing Mechanism

The GPEVST register is a general-purpose edge detector which may be used to reflect the event source pending status for

edge-triggered events.

The term active edge refers to a change in a GPIO pin level that matches the Event Polarity bit (1 for rising edge and 0 for

falling edge). Active level refers to the GPIO pin level that matches the Event Polarity bit (1 for high level and 0 for low level).

The corresponding bit of the GPEVST register is set by hardware whenever an active edge is detected, regardless of any

other bit settings. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored.

A GPIO pin is in event pending state if the corresponding bit of the GPEVEN register is set and either:

●

The Event Type is level and the pin is in active level, or

●

The Event Type is edge and the corresponding bit of the GPEVST register is set.

The target means of system notification is asserted if at least one GPIO pin is in event pending state.

The selection of the target means of system notification is determined by the GPEVR register. If IRQ is selected as one of the

means for the system notification, the specific IRQ line is determined by the IRQ selection procedure of the device configura-

tion. The assertion of any means of system notification is blocked when the GPIO functional block is deactivated.

If the output of a GPIO pin is enabled, it may be put in event pending state by the software when writing to the GPDO register.

An pending edge event may be cleared by clearing the corresponding GPEVST bit. However, a level event source may not

be released by software (except for disabling the source), as long as the pin is in active level. When level event is used, it

is recommended to disable the input debouncer.

Upon de-activation of the GPIO port, the GPEVST register is cleared and access to both the GPEVST and GPEVEN regis-

ters is disabled. All system notification means including the target IRQ line are detached from the GPIO and de-asserted.

Before enabling any system notification, it is recommended to set the desired event configuration, and then verify that the

status registers are cleared.

3.4 GPIO PORT REGISTERS

The register maps in this chapter use the following abbreviations for Type:

●

R/W = Read/Write

●

R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different

register.

●

W = Write

●

RO = Read Only

●

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

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3.0 General-Purpose Input/Output (GPIO) Port (Continued)

3.4.1

GPIO Pin Configuration (GPCFG) Register

This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is

mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register that functions as an index

register, and the specific GPCFG register that reflects the configuration of the currently selected pin. For details on the

GPSEL register, refer to the Device Architecture and Configuration chapter.

Bits 4-6 are applicable only for the enhanced GPIO port with event detection support. In the basic port, these bits are re-

served, return 0 on read and have no effect on port functionality.

Location:

Type:

Device specific

R/W (bit 3 is set only)

Bit

7

6

5

4

3

Lock

0

2

1

0

Event

Polarity

Pull-Up

Control

Output

Type

Output

Enable

Name

Reset

Reserved Debounce

Enable

Event Type

0

1

0

1

0

Bit

Description

7

6

Reserved

Event Debounce Enable

0: Disabled

1: Enabled (default)

5

Event Polarity. This bit deﬁnes the polarity of the signal that causes a detection of an event from the

corresponding GPIO pin (falling/low or rising/high).

0: Falling edge or low level input (default)

1: Rising edge or high level input

4

3

Event Type. This bit deﬁnes the signal type that causes detection of an event from the corresponding GPIO pin.

0: Edge input (default)

1: Level input

Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to

0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1. (Refer to the

Device Architecture and Configuration chapter.)

0: No effect (default)

1: Direction, output type, pull-up and output value locked

2

Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin.

It supports open-drain output signals with internal pull-ups and TTL input signals

0: Disabled

1: Enabled (default)

1

0

Output Type. This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin.

0: Open-drain (default)

1: Push-pull

Output Enable. This bit indicates the GPIO pin output state. It has no effect on input.

0: TRI-STATE (default)

1: Output enabled

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3.0 General-Purpose Input/Output (GPIO) Port (Continued)

3.4.2

GPIO Pin Event Routing (GPEVR) Register

This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is

mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register that functions as an index

register, and the specific GPER register that reflects the routing configuration of the currently selected pin. For details on the

GPSEL register, refer to the Device Architecture and Configuration chapter.

This set of registers is applicable only for the enhanced GPIO port with event detection support. In the basic port this register

set is reserved, returns 0 on read and has no effect on port functionality.

Location:

Type:

Device specific

R/W

Bit

7

0

6

0

5

0

4

3

0

2

0

1

0

GPIO Event GPIO Event

Name

Reset

Reserved

to SMI

Enable

to IRQ

Enable

0

1

Bit

Description

7-2 Reserved

1

GPIO Event to SMI Enable

event to SMI.

. This bit is used to enable/disable the routing of the corresponding detected GPIO

0: Disabled (default)

1: Enabled

0

GPIO Event to IRQ Enable. This bit is used to enable/disable the routing of the corresponding detected GPIO

event to IRQ.

0: Disabled

1: Enabled (default)

3.4.3

GPIO Port Runtime Register Map

Offset

Mnemonic

GPDO

Register Name

GPIO Data Out

Type

R/W

Section

3.4.4

1

Device speciﬁc

GPDI

GPIO Data In

RO

3.4.5

GPEVEN

GPEVST

GPIO Event Enable

GPIO Event Status

R/W

3.4.6

R/W1C

3.4.7

1. The location of this register is deﬁned in the Device Architecture and Conﬁguration chap-

ter in Section 2.15.1.

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3.0 General-Purpose Input/Output (GPIO) Port (Continued)

3.4.4

GPIO Data Out Register (GPDO)

Location:

Type:

Device specific

R/W

Bit

7

6

1

5

1

4

1

3

1

2

1

0

1

Name

Reset

Data Out

1

Bit

Description

7

6

Data Out. Bits 7-0 correspond to pins 7-0 respectively. The value of each bit determines the value driven on the

corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the written data unless the

bit is locked by the GPCFG register Lock bit. Reading the bit returns its value, regardless of the pin value and

conﬁguration.

5

4

3

2

1

0

0: Corresponding pin driven to low when output enabled

1: Corresponding pin driven or released to high (according to buffer type and static pull-up selection) when

output enabled

3.4.5

GPIO Data In Register (GPDI)

Location:

Type:

Device specific

RO

Bit

7

6

5

4

3

2

1

0

Name

Reset

Data In

X

Bit

Description

7

6

5

Data In. Bits 7-0 correspond to pins 7-0 respectively. Reading each bit returns the value of the corresponding

4

3

2

1

0

GPIO pin, regardless of the pin conﬁguration and the GPDO register value. Write is ignored.

0: Corresponding pin level low

1: Corresponding pin level high

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3.0 General-Purpose Input/Output (GPIO) Port (Continued)

3.4.6

GPIO Event Enable Register (GPEVEN)

Location:

Type:

Device specific

R/W

Bit

7

6

0

5

0

4

3

2

0

1

0

Name

Reset

Event Enable

0

Bit

Description

7

6

5

Event Enable. Bits 7-0 correspond to pins 7-0 respectively. Each bit enables system notiﬁcation triggering by

4

3

2

1

0

the corresponding GPIO pin. The bit has no effect on the corresponding Status bit in the GPEVST register.

0: IRQ generation by corresponding GPIO pin masked

1: IRQ generation by corresponding GPIO pin enabled

3.4.7

GPIO Event Status Register (GPEVST)

Location:

Type:

Device specific

R/W1C

Bit

7

6

0

5

0

4

0

3

0

2

0

1

0

Name

Reset

Status

0

Bit

Description

7

6

Status. Bits 7-0 correspond to pins 7-0 respectively. Each bit is an edge detector that is set to 1 by the hardware

upon detection of an active edge (i.e. edge that matches the IRQ Polarity bit) on the corresponding GPIO pin.

This edge detection is independent of the Event Type or the Event Enable bit in the GPEVEN register. However,

the bit may reﬂect the event status for enabled, edge-trigger event sources. Writing 1 to the Status bit clears it

to 0.

5

4

3

2

1

0

0: No active edge detected since last cleared

1: Active edge detected

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4.0 WATCHDOG Timer (WDT)

4.1 OVERVIEW

The WATCHDOG Timer prompts the system via SMI or interrupt when no system activity is detected on a predefined selec-

tion of system events for a predefined period of time (1 to 255 minutes).

The WATCHDOG Timer monitors two maskable system events: the interrupt request lines of the two serial ports (UART1

and UART2). The system prompt is performed by asserting a special-purpose output pin (WDO), which can be attached to

external SMI. Alternatively, this indication can be routed to any arbitrary IRQ line and is also available on a status bit that

can be read by the host.

This chapter describes the generic WATCHDOG Timer functional block. A device may include a different implementation.

For device specific implementation, see the Device Architecture and Conﬁguration chapter.

4.2 FUNCTIONAL DESCRIPTION

The WATCHDOG Timer consists of an 8-bit counter and three registers: Timeout register (WDTO), Mask register (WDMSK)

and Status register (WDST). The counter is an 8-bit down counter that is clocked every minute and is used for the timeout

period countdown. The WDTO register holds the programmable timeout, which is the period of inactivity after which the

WATCHDOG Timer prompts the system (1 to 255 minutes). The WDMSK register determines which system events are en-

abled as WATCHDOG Timer trigger events to restart the countdown. The WDST register holds the WATCHDOG Timer sta-

tus bit that reflects the value of the WDO pin and indicates that the timeout period has expired.

Figure 12 shows the functionality of the WATCHDOG Timer.

Upon reset, the Timeout register (WDTO) is initialized to zero, the timer is deactivated, the WDO is inactive (high) and all

trigger events are masked.

Upon writing to the WDTO register, the timer is activated while the counter is loaded with the timeout value and starts count-

ing down every minute. If a trigger event (unmasked system event) occurs before the counter has expired (reached zero),

the counter is reloaded with the timeout period (from WDTO register) and restarts the countdown. If no trigger event occurs

before the timeout period expires, the counter reaches zero and stops counting. Consequently, the WDO pin is asserted

(pulled low) and the WDO Status bit is cleared to 0.~

Writing to the WDTO register de-asserts the WDO output (released high) and sets the WDO Status bit to 1. If a non-zero

value is written, a new countdown starts as described above. If 00h is written, the timer is deactivated.

To summarize, the WDO output is de-asserted (high) and the Status bit is set to 1 (inactive) upon:

●

Reset

●

Activating the WATCHDOG Timer or

●

Writing to the WDTO register.

The WDO output is asserted (low) and the WDO status is set to zero (active) when the counter reaches zero.

When an IRQ is assigned to the WATCHDOG Timer (through the WATCHDOG Timer device configuration), the selected

IRQ level is active as long as the WDO status bit is low (active).

Enable Bits

Data Bus 1 Minute Clock

Write

Register

3 2 1 0

WDMSK

WDTO Register

Timer

Reserved

Load

Reload

Serial Port 1 IRQ

Serial Port 2 IRQ

Zero Detector

Status Bit

Interrupt

WDO

Figure 12. WATCHDOG Timer Functional Diagram

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4.0 WATCHDOG Timer (WDT) (Continued)

4.3 WATCHDOG TIMER REGISTERS

The WATCHDOG Timer registers at offsets 00h-02h relative to the WATCHDOG base address, are shown in the following

register map. The base address is defined by designated registers in the WATCHDOG Timer device configuration register

set.

The following abbreviations are used to indicate the Register Type:

R/W

R

= Read/Write

= Read from a specific address returns the value of a specific register. Write to the same address is to a different register.

W

= Write

RO

= Read Only

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

4.3.1

WATCHDOG Timer Register Map

Offset Mnemonic

Register Name

Type

Section

00h

01h

02h

03h

WDTO

WDMSK

WDST

WATCHDOG Timeout

WATCHDOG Mask

WATCHDOG Status

Reserved

R/W

RO

4.3.2

4.3.3

4.3.4

4.3.2

WATCHDOG Timeout Register (WDTO)

This register holds the programmable timeout period, between 1 and 255 minutes. Writing to this register de-asserts the

WDO output and sets the WDO status bit to 1 (inactive). Additionally, writing to this register is interpreted as a command for

starting or stopping the WATCHDOG Timer, according to the data written. If a non-zero value is written, the timer is activated

(countdown starts). If a non-zero value is written when the counter is running, the timer is immediately reloaded with the new

value and starts counting down from the new value. If 00h is written, the timer and its outputs are de-activated.

Location:

Type:

Offset 00h

R/W

Bit

7

6

0

5

0

4

3

2

0

1

0

Name

Reset

Programmed Timeout Period

0

Bit

Description

7-0 Programmed Timeout Period. These bits hold the binary value of the timeout period in minutes (1 to 255). A

value of 00h halts the counter and forces the outputs to inactive levels. A device reset clears the register to 00h.

00h: Timer and WDO outputs inactive

01h-FFh: Programmed timeout period (in minutes)

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4.0 WATCHDOG Timer (WDT) (Continued)

4.3.3

WATCHDOG Mask Register (WDMSK)

This register is used to determine which system events (IRQ) are enabled as WATCHDOG Timer trigger events. An enabled

IRQ event becomes a trigger event that causes the timer to reload the WDTO and restart the countdown.

This register enables or masks the trigger events that restart the WATCHDOG timer.

Location:

Type:

Offset 01h

R/W

Bit

7

0

6

0

5

0

4

0

3

2

1

0

Serial Port 2 Serial Port 1

IRQ Trigger IRQ Trigger

Name

Reset

Reserved

Enable

0

Bit

Description

7-4 Reserved

3

Serial Port 2 IRQ Trigger Enable. This bit enables the IRQ assigned to Serial Port 2 to trigger WATCHDOG

Timer reloading.

0: Serial Port 2 IRQ not a trigger event

1: An active Serial Port 2 IRQ enabled as a trigger event

2

Serial Port 1 IRQ Trigger Enable. This bit enables the IRQ assigned to Serial Port 1 to trigger WATCHDOG

Timer reloading.

0: Serial Port 1 IRQ not a trigger event

1: An active Serial Port 1 IRQ enabled as a trigger event

1-0 Reserved

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4.0 WATCHDOG Timer (WDT) (Continued)

4.3.4

WATCHDOG Status Register (WDST)

This register holds the WATCHDOG Timer status, which reflects the value of the WDO pin and indicates that the timeout

period has expired.

On reset or on WATCHDOG Timer activation, this register is initialized to 01h.

Location:

Type:

Offset 02h

RO

Bit

7

6

0

5

0

4

Reserved

0

3

0

2

0

1

0

Name

WDO Value

Reset

0

1

Required

Bit

Description

7-1 Reserved

0

WDO Value. This bit reﬂects the value of the WDO signal (even if WDO is not configured for output).

0: WDO active

1: WDO inactive (default)

4.4 WATCHDOG TIMER REGISTER BITMAP

Register

Bits

Offset Mnemonic

7

6

5

4

3

2

1

0

00h

WDTO

Programmed Timeout Period

Serial Port 2 Serial Port 1

IRQ

Trigger

Enable

IRQ

Trigger

Enable

01h

WDMSK

Reserved

WDO

Value

02h

WDST

Reserved

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5.0 Game Port (GMP)

Note: This section applies to the PC87393 and PC87393F only.

5.1 OVERVIEW

This chapter describes a generic Game Port. For the implementation used in this device, see the Device Architecture and

Conﬁguration chapter.

The Game Port monitors the interface of up to two game devices, and provides data that can be used to determine the exact

momentary status of these game devices.

A game device is an instrument used for giving commands to a PC, usually to control a game executed on that PC. A Joystick

is a commonly used game device. These commands are given by the game device in a passive manner, by indicating sev-

eral status parameters that can be captured by the system via the Game Port.

The status of a game device includes the following parameters:

●

Button status (pressed/released) of up to two buttons per game device

●

Horizontal (X-axis) position indicated by the game device

●

Vertical (Y-axis) position indicated by the game device.

Figure 13 shows the basic system configuration of the Game Port.

X-Axis

Y-Axis

Game Device

Game

Port

Game

Interface

Button 1

Button 0

Button 1

Button 0

Device A

Device

Circuitry

Figure 13. Game Port System Conﬁguration

5.2 FUNCTIONAL DESCRIPTION

5.2.1

Game Device Axis Position Indication

A typical game device has the following interface pins:

●

an X-axis position indicator

●

a Y-axis position indicator

●

one or two button status indicator(s).

The X and Y axis indicators are fed into the Game Port via pins JOYnX and JOYnY, respectively, where ‘n’ indicates the

game device number. The status indicators of buttons 0 and 1 are fed into the Game Port via JOYnBTN0,1, respectively.

The X and Y axis position indication mechanism of each game device includes external components, as seen in Figure 14.

Such a mechanism is implemented per game device axis line.

X/Y-Axis

Indicators

Input

Path

R_VX

R_CX

Game

Port

JOYnX

JOYnY

Pins

C_X

X/Y-Axis

Circuit

Discharge

Control

Game Device

X/Y-Axis Varying

Resistor

Waveform Shaping Circuit

Figure 14. Game Device Axis Position Indication Mechanism

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5.0 Game Port (GMP) (Continued)

The varying resistors R_VXand R_VYare usually implemented in the game device. Their resistance values are determined

directly by the horizontal and vertical positions, respectively, indicated by the game device. The waveform shaping circuits

are usually implemented outside the game device using constant resistors (R_CX/Y) and constant capacitors (C_X/Y). Together

with R_VX/Y, these components implement two R-C structures, the varying parameters of which are used to determine the

exact momentary position indicated by the game device.

When the Game Port is enabled and not in the midst of a game device position reading process, it drives the JOYnX,Y pins

low. In this state, the capacitors C_X/Yare completely discharged.

5.2.2

Capturing the Position

The process of capturing the position indicated by the game device is initiated by a command given to the Game Port to

release the JOYnX,Y lines, thus allowing the capacitors C_X/Yto be charged. This command is given by performing a write

access to offset 1 from the Game Port base address, which is the offset of the Game Port Legacy Status Register (GMPLST,

see Section 5.3.3). Once JOYnX,Y pins are released, R_CX/Yand R_VX/Ystart charging C_X/Y, and the voltage level of the

JOYnX,Y pins increases until it reaches V_IH. This process is described in Figure 15.

V

_CX/Y[V]

Charge

Discharge

Idle

V_DD

V_IH

0

Drive

Low

Drive

Low

Release

Time

Time measured as

position indication

Figure 15. Position Reading Process Waveform (not drawn to scale)

The vertical and horizontal positions indicated by the game device are determined by measuring the time it takes for the

voltage level on the JOYnX,Y pins to reach the level of logic 1. Since the charging time is determined by the resistance val-

ues of R_VX/Y, measuring this time actually indicates the resistance values of R_VX/Y, and therefore also reflects the position

indicated by the game device.

Once an axis pin is sensed as logic 1, the axis circuit discharge control is activated in order to discharge C_X/Y. This causes

the corresponding axis pin to be driven low for approximately 1.5 µsec. After that, this axis line is held low until another po-

sition reading process is initiated.

During the charge time and the 1.5 µsec discharge time which follows, the corresponding axis line does not respond to any

reading process initiation. This prevents software from disturbing the position reading process and makes the position read-

ing processes of all axis lines independent of each other.

5.2.3

Button Status Indication

The button(s) status indication mechanism is described in Figure 16. Although this figure shows an active-low button

(R_BU0>>R_BD0), the polarity of the button can be either high or low, assuming that the Game Port software is aware of the

button’s polarity.

Buttons 0,1

Status

RBU0

Indicators

Input Path

Game

Port

JOYnBTN0

JOYnBTN1

Pins

RBD0

Game Device Button Status Circuit

Figure 16. Game Device Button Status Indication Mechanism

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5.0 Game Port (GMP) (Continued)

A simple push-button mechanism is usually used to implement the game device buttons. The status of each button is sensed

by the Game Port via the JOYnBTN0,1 pins as either high or low, and reflected by the GMPLST register. It is the responsi-

bility of the software to determine the actual status of the buttons according to their polarity, which depends on the specific

implementation of the system and the game device.

5.2.4

Operation Modes

The Game Port can be used to monitor the position and button status indicators in one of the following operation modes:

●

Legacy mode

●

Enhanced mode.

Legacy Mode

Legacy mode is enabled when bit 0 of the GMPCTL register is set to 0, which is its default state.

In this mode, the game device indicators are monitored by polling their momentary status via the Game Port Legacy Status

register (GMPLST, see Section 5.3.3).

The process of reading the position status of the game device(s) is initiated by performing a write access to offset 1 in the

Game Port address space. This write access causes the Game Port to release the JOYnX,Y pins. When a JOYnX,Y pin is

released, the corresponding bit in the GMPLST register is set to 1. To capture the position indicated by the game device,

the software must poll the GMPLST register and measure the time it takes for the JOYnX,Y to go high. This measurement

should be performed by measuring the time during which an axis bit is 1.

Reading the status of the buttons of the game device is done by polling the GMPLST register and looking for changes in the

bits reflecting the status of the JOYnBTN0,1 pins.

No debounce of the input signals is performed by the Game Port in Legacy mode. It is the responsibility of the software to

implement such debounce, if necessary.

Enhanced Mode

Enhanced mode is enabled when bit 0 of the GMPCTL register is set to 1.

In Enhanced mode, the Game Port hardware monitors the status indicators of the game device(s), and provides processed

data that can be easily used by software to determine the complete status of the game device.

The process of reading the position status of the game device(s) is initiated as in Legacy mode. However, in Enhanced mode

the Game Port hardware measures the C_X/Ycharging time using four 16-bit up-counters. Each one of the four axis status

lines (two lines per game device) has a dedicated counter.

Once the Game Port releases the JOYnX,Y to go high, each one of the counters starts counting until its associated axis

status line reaches the voltage level of logic 1.

When a position counter of a game device stops counting, its associated Position Counter Ready bit in the GMPXST register

is set. In this case, the software must wait until the counters associated with the game device are ready, and then read their

values. The least significant byte of a position counter should be read first. The full, 16-bit count value should be calculated

as follows:

X/Y Position Count = GMPnX/YL + (GMPnX/YH * 256)

where:

GMPnX/YL indicates the low byte of the position counter of device n (either X or Y axis)

GMPnY/HL indicates the high byte of the position counter of device n (either X or Y axis)

The software must calibrate itself according to the actual count values acquired when the game device was set to indicate

its extreme horizontal and vertical positions.

If a position counter has reached the full count of FFFFh, this counter has overflowed; i.e., it has reached its full count before

the corresponding axis indicator has reached the level of logic 1. In such a case, the software must decide what to do.

The Game Port supports the following clock frequencies for operating the position counters:

●

1 MHz clock (default)

●

500 KHz clock.

The clock frequency for the position counter of each game device is configured via the GMPCTL register and should be set

by the software to match the physical components of the external game device interface circuitry. The desired position of

the counter frequency should be set before initiating a position status reading process.

Reading the status of the buttons of the game device(s) is performed as in Legacy mode. In addition, an optional debouncer

of 16 msec is implemented on each button status input. The debouncers are disabled by default and may be enabled by

software via the GMPCTL register.

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5.0 Game Port (GMP) (Continued)

5.2.5

Operation Control

When the Game Port is operated in Legacy mode, it can only be operated by polling (see Section 5.2.4, Legacy Mode).

When the Game Port is operated in Enhanced mode, both kinds of status reading operations (position and button) can be

performed using polling or interrupt controlled operation.

If polling controlled operation is preferred, the software should poll either the GMPLST register for the direct status of the

buttons as in Legacy mode, or the GMPXST register which provides indications regarding button events detected by hard-

ware. The GMPXST register should also be polled for the status of the position counters. When the status is ready, the

counter values can be read. These values reflect the positions indicated by the game device.

If interrupt controlled operation is preferred, the software should first define the events on which an interrupt request is to be

issued. This is done by writing the required values to the GMPEPOL (see Section 5.3.14) and GMPIEN (see Section 5.3.5)

registers. The GMPEPOL register defines the events on which the buttons cause an interrupt request to be issued. These

events are all edge-triggered. The GMPIEN register determines what events are physically routed to the interrupt request

assigned to the Game Port. An independent interrupt enable bit is implemented in the GMPIEN register for each one of the

four buttons and two position counters of the two supported game devices.

5.3 GAME PORT REGISTERS

The following abbreviations are used to indicate the Register Type:

●

R/W = Read/Write

●

R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different

register.

●

W = Write

●

RO = Read Only

●

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

5.3.1

Game Port Register Map

The following table lists the Game Port registers. for the Game Port register bitmap, see Section 5.4.

Offset

Mnemonic

Register Name

Type

Section

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

GMPCTL Game Port Control

R/W

RO

5.3.2

5.3.3

GMPLST Game Port Legacy Status

GMPXST Game Port Extended Status

R/W1C

R/W

RO

5.3.4

GMPIEN Game Port Interrupt Enable

5.3.5

GMPAXL Game Device A X Position Low Byte

GMPAXH Game Device A X Position High Byte

GMPAYL Game Device A Y Position Low Byte

GMPAYH Game Device A Y Position High Byte

GMPBXL Game Device B X Position Low Byte

GMPBXH Game Device B X Position High Byte

GMPBYL Game Device B Y Position Low Byte

GMPBYH Game Device B Y Position High Byte

GMPEPOL Game Port Event Polarity

5.3.6

RO

5.3.7

RO

5.3.8

RO

5.3.9

RO

5.3.10

5.3.11

5.3.12

5.3.13

5.3.14

RO

R/W

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5.0 Game Port (GMP) (Continued)

5.3.2

Game Port Control Register (GMPCTL)

This register affects the functionality of the Game Port only when operated in Enhanced mode (bit 0 of this register is set

to 1). Bits 1,2 and 4-7 affect Game Port functionality, as described in the table below.

Location:

Type:

Offset 00h

R/W

Bit

7

6

5

4

3

2

1

0

Device B

Button 1

Device B

Button 0

Device A

Button 1

Device A

Button 0

GMP

Enhanced

Mode

Device B

Reserved Pre-Scale Pre-Scale

Device A

Name

Debounce Debounce Debounce Debounce

Enable

Reset

0

Required

Bit

Description

7

Device B Button 1 Debounce Enable. When set to 1, enables a 16 ms input debouncer on Device B Button 1

status input.

0: Disabled (default)

1: Enabled

6

5

4

Device B Button 0 Debounce Enable. Same as bit 7, but for Device B Button 0.

0: Disabled (default)

1: Enabled

Device A Button 1 Debounce Enable. Same as bit 7, but for Device A Button 1.

0: Disabled (default)

1: Enabled

Device A Button 0 Debounce Enable. Same as bit 7, but for Device A Button 0.

0: Disabled (default)

1: Enabled

3

2

Reserved

Device B Pre-Scale Enable. This bit determines the clock frequency used by Device B position counters.

0: 1 MHz (default)

1: 500 KHz

1

0

Device A Pre-Scale Enable. This bit determines the clock frequency used by Device A position counters.

0: 1 MHz (default)

1: 500 KHz

GMP Enhanced Mode Enable

0: Disabled (default)

1: Enabled

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5.0 Game Port (GMP) (Continued)

5.3.3

Game Port Legacy Status Register (GMPLST)

This register is functional in all Game Port operation modes. Reading this register returns the status and the state of Device

A and B button and Axis pins, as defined in the table below. Writing to the offset of this register initiates a game device po-

sition reading process by forcing a low pulse to be driven on the axis pins in Legacy and Enhanced modes, and by initializing

all position counters in Enhanced mode.

Location:

Type:

Offset 01h

RO

Bit

7

6

5

4

3

2

1

0

Device B

Button 1

Device B

Button 0

Device A

Button 1

Device A

Device B

Device A

Name

Reset

Button 0 Y-Axis Pin X-Axis Pin Y-Axis Pin X-Axis Pin

Pin Status Pin Status Pin Status Pin Status

Status

X

Bit

Description

7

6

5

4

3

2

1

0

Device B Button 1 Pin Status. This bit directly reﬂects the status of Device B Button 1 input pin.

0: Low

1: High

Device B Button 0 Pin Status. This bit directly reﬂects the status of Device B Button 0 input pin.

0: Low

1: High

Device A Button 1 Pin Status. This bit directly reﬂects the status of Device A Button 1 input pin.

0: Low

1: High

Device A Button 0 Pin Status. This bit directly reﬂects the status of Device A Button 0 input pin.

0: Low

1: High

Device B Y-Axis Pin Status. This bit reﬂects the state of Device B Y-axis input pin.

0: JOYBY pin is driven low

1: JOYBY pin is released for charging

Device B X-Axis Pin Status. This bit reﬂects the state of Device B X-axis input pin.

0: JOYBX pin is driven lowr

1: JOYBX pin is released for charging

Device A Y-Axis Pin Status. This bit reﬂects the state of Device A Y-axis input pin.

0: JOYAY pin is driven low

1: JOYAY pin is released for charging

Device A X-Axis Pin Status. This bit reﬂects the status of Device A X-axis input pin.

0: JOYAX pin is driven low

1: JOYAX pin is released for charging

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5.0 Game Port (GMP) (Continued)

5.3.4

Game Port Extended Status Register (GMPXST)

This register indicates which of the corresponding game device interface events have occurred. Writing 1 to a bit clears it.

Reading a position counter clears the corresponding Counter Ready bit. Writing to a bit 0 has no effect.

This register is functional only in Enhanced mode.

Location:

Type:

Offset 02h

R/W1C

Bit

7

6

5

4

3

2

1

0

Device B

Button 1

Event

Device B

Button 0

Event

Device A

Button 1

Event

Device A

Device B

Device A

Button 0 Y-Position X-Position Y-Position X-Position

Event

Status

Name

Reset

Bit

Counter

Ready

Counter

Ready

Counter

Ready

Counter

Ready

Status

0

Description

7

6

5

4

3

2

1

0

Device B Button 1 Event Status. When set to 1, it indicates that a Device B Button 1 event has occurred. The

event itself is deﬁned by the GMPEPOL register, see Section 5.3.14.

0: Event not active (default)

1: Event active

Device B Button 0 Event Status. When set to 1, it indicates that a Device B Button 0 event has occurred. The

event itself is deﬁned by the GMPEPOL register, see Section 5.3.14.

0: Event not active (default)

1: Event active

Device A Button 1 Event Status. When set to 1, it indicates that a Device A Button 1 event has occurred. The

event itself is deﬁned by the GMPEPOL register, see Section 5.3.14.

0: Event not active (default)

1: Event active

Device A Button 0 Event Status. When set to 1, it indicates that a Device A Button 0 event has occurred. The

event itself is deﬁned by the GMPEPOL register, see Section 5.3.14.

0: Event not active (default)

1: Event active

Device B Y-Position Counter Ready. When set to 1, it indicates that the value of the Y-position counter of

Device B can now be read.

0: Event not active (default)

1: Event active

Device B X-Position Counter Ready. When set to 1, it indicates that value of the X-position counter of Device

B can now be read.

0: Event not active (default)

1: Event active

Device A X-Position Counter Ready. When set to 1, it indicates that the value of the Y-position counter of

Device A can now be read.

0: Event not active (default)

1: Event active

Device A X-Position Counter Ready. When set to 1, it indicates that the value of the X-position counter of

Device A can now be read.

0: Event not active (default)

1: Event active

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5.0 Game Port (GMP) (Continued)

5.3.5

Game Port Interrupt Enable Register (GMPIEN)

This register defines the conditions on which the Game Port asserts its interrupt request signal.

This register is functional only in Enhanced mode.

Location:

Type:

Offset 03h

R/W

Bit

7

6

5

4

3

2

1

0

Device B

Button 1

Device B

Button 0

Device A

Button 1

Device A

Button 0

Position

Reserved IRQ Event

Device B

Position

Device A

Position

Name

Reset

IRQ Enable IRQ Enable IRQ Enable IRQ Enable

Deﬁnition IRQ Enable IRQ Enable

0

Bit

Description

7

Device B Button 1 IRQ Enable. When set to 1, the Game Port issues an interrupt request in response to an

event triggered by Button 1 of Device B. When set to 0, Button 1 of Device B cannot cause interrupt requests to

be issued.

0: Disabled (default)

1: Enabled

6

5

4

Device B Button 0 IRQ Enable. Same as bit 7 of this register, but for Device B Button 0.

0: Disabled (default)

1: Enabled

Device A Button 1 IRQ Enable. Same as bit 7 of this register, but for Device A Button 1.

0: Disabled (default)

1: Enabled

Device A Button 0 IRQ Enable. Same as bit 7 of this register, but for Device A Button 0.

0: Disabled (default)

1: Enabled

3

2

Reserved

Position IRQ Event Deﬁnition Deﬁnes the event on which the position IRQ is asserted for both game devices.

0: Both X-Position Counter and Y-Position Counter are ready

1: Either X-Position Counter or Y-Position Counter is ready

1

0

Device B Position IRQ Enable. When set to 1, the Game Port issues an interrupt request when the position

reading of Device B is completed and the position counters can be read. When set to 0, no interrupt request is

issued in response to any change in the status of Device B position counters.

0: Disabled (default)

1: Enabled

Device A Position IRQ Enable. Same as bit 2 of this register, but for Device A.

0: Disabled (default)

1: Enabled

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5.0 Game Port (GMP) (Continued)

5.3.6

Game Device A X-Axis Position Low Byte (GMPAXL)

Reading this register returns the value of the low byte of the X-axis position counter of game Device A. Before reading this

register verify that bit 0 of GMPXST (Device A Position Counter Ready) is set to 1. Writing to the offset of this register is

ignored.

This register is functional only in Enhanced mode.

Location:

Type:

Offset 04h

RO

Bit

7

6

0

5

4

3

2

1

0

Name

Reset

Device A X-Axis Position Counter Low Byte

0

5.3.7

Game Device A X-Axis Position High Byte (GMPAXH)

Reading this register returns the value of the high byte of the X-axis position counter of game Device A. Read this register

after reading the GMPAXL register, and verifying that bit 0 of GMPXST (Device A Position Counter Ready) is set to 1. Writing

to the offset of this register is ignored.

This register is functional only in Enhanced mode.

Location:

Type:

Offset 05h

RO

Bit

7

6

0

5

4

3

2

1

0

Name

Reset

Device A X-Axis Position Counter High Byte

0

5.3.8

Game Device A Y-Axis Position Low Byte (GMPAYL)

Reading this register returns the value of the low byte of the Y-axis position counter of game Device A. Before reading this

register verify that bit 1 of GMPXST (Device A Position Counter Ready) is set to 1. Writing to the offset of this register is

ignored.

This register is functional only in Enhanced mode.

Location:

Type:

Offset 06h

RO

Bit

7

6

0

5

4

3

2

1

0

Name

Reset

Device A Y-Axis Position Counter Low Byte

0

5.3.9

Game Device A Y-Axis Position High Byte (GMPAYH)

Reading this register returns the value of the high byte of the Y-axis position counter of game Device A. Read this register

after reading the GMPAYL register and verifying that bit 1 of GMPXST (Device A Position Counter Ready) is set to 1. Writing

to the offset of this register is ignored.

This register is functional only in Enhanced mode.

Location:

Type:

Offset 07h

RO

Bit

7

6

0

5

4

3

2

1

0

Name

Reset

Device A Y-Axis Position Counter High Byte

0

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5.0 Game Port (GMP) (Continued)

5.3.10 Game Device B X-Axis Position Low Byte (GMPBXL)

Reading this register returns the value of the low byte of the X-axis position counter of game Device B. Before reading this

register verify that bit 2 of GMPXST (Device B Position Counter Ready) is set to 1. Writing to the offset of this register is

ignored.

This register is functional only in Enhanced mode.

Location:

Type:

Offset 08h

RO

Bit

7

6

0

5

4

3

2

1

0

Name

Reset

Device B X-Axis Position Counter Low Byte

0

5.3.11 Game Device B X-Axis Position High Byte (GMPBXH)

Reading this register returns the value of the high byte of the X-axis position counter of game Device B. Before reading this

register verify that bit 2 of GMPXST (Device B Position Counter Ready) is set to 1. Writing to the offset of this register is

ignored.

This register is functional only in Enhanced mode.

Location:

Type:

Offset 09h

RO

Bit

7

6

0

5

4

3

2

1

0

Name

Reset

Device B X-Axis Position Counter High Byte

0

5.3.12 Game Device B Y-Axis Position Low Byte (GMPBYL)

Reading this register returns the value of the low byte of the Y-axis position counter of game Device B. Before reading this

register verify that bit 3 of GMPXST (Device B Position Counter Ready) is set to 1. Writing to the offset of this register is

ignored.

This register is functional only in Enhanced mode.

Location:Offset 0Ah

Type:

RO

Bit

7

0

6

0

5

4

3

2

1

0

Name

Reset

Device B Y-Axis Position Counter Low Byte

0

5.3.13 Game Device B Y-Axis Position High Byte (GMPBYH)

Reading this register returns the value of the high byte of the Y-axis position counter of game Device B. Before reading this

register verify that bit 3 of GMPXST (Device B Position Counter Ready) is set to 1. Writing to the offset of this register is

ignored.

This register is functional only in Enhanced mode.

Location:Offset 0Bh

Type:

RO

Bit

7

0

6

0

5

4

3

2

1

0

Name

Reset

Device B Y-Axis Position Counter High Byte

0

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5.0 Game Port (GMP) (Continued)

5.3.14 Game Port Event Polarity Register (GMPEPOL)

This register defines the polarity of button events on which the Game Port issues an interrupt request.

This register is functional only in Enhanced mode.

Location:

Type:

Offset 0Ch

R/W

Bit

7

6

5

4

3

2

1

0

Device B Button 1 Event Device B Button 0 Event Device A Button 1 Event Device A Button 0 Event

Polarity Polarity Polarity Polarity

Name

Reset

0

Bit

Description

7-6 Device B Button 1 Event Polarity. This bit deﬁnes the event polarity on which Device B Button 1 issues an

interrupt request.

Bits

7 6

Number

0 0

0 1

1 0

1 1

None (default)

Rising edge

Falling edge

Rising and falling edge

5-4 Device B Button 0 Event Polarity. Same as bits 7-6 of this register, but for Device B Button 0.

Bits

5 4

Number

0 0

0 1

1 0

1 1

None (default)

Rising edge

Falling edge

Rising and falling edge

3-2 Device A Button 1 Event Polarity. Same as bits 7-6 of this register, but for Device A Button 1.

Bits

3 2

Number

0 0

0 1

1 0

1 1

None (default)

Rising edge

Falling edge

Rising and falling edge

1-0 Device A Button 0 Event Polarity. Same as bits 7-6 of this register, but for Device A Button 0.

Bits

1 0

Number

0 0

0 1

1 0

1 1

None (default)

Rising edge

Falling edge

Rising and falling edge

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5.0 Game Port (GMP) (Continued)

5.4 GAME PORT BITMAP

Register

Bits

Offset

Mnemonic

7

6

5

4

3

2

1

0

Device B Device B Device A Device A

Button 1 Button 0 Button 1 Button 0

Debounce Debounce Debounce Debounce

GMP

Enhanced

Mode

Device B Device A

Reserved Pre-Scale Pre-Scale

00h

GMPCTL

Enable

Device B Device B Device A Device A

Button 1 Button 0 Button 1 Button 0

Device B

X-Axis

Device A

X-Axis

Device B

Y-AxisPin

Status

Device A

Y-Axis Pin

Status

01h

02h

03h

GMPLST

GMPXST

GMPIEN

Status

Device B Device B Device A Device A Device B Device B Device A Device A

Button 1 Button 0 Button 1 Button 0 Y-Position X-Position Y-Position X-Position

Event

Status

Event

Status

Event

Status

Event

Status

Counter

Ready

Counter

Ready

Counter

Ready

Counter

Ready

Device B Device B Device A Device A

Button 1 Button 0 Button 1 Button 0

Position Device B Device A

IRQ

Event

Position

IRQ

Position

IRQ

Reserved

IRQ

Enable

Deﬁnition

Enable

04h

05h

06h

07h

08h

09h

0Ah

0Bh

GMPAXL

GMPAXH

GMPAYL

GMPAYH

GMPBXL

GMPBXH

GMPBYL

GMPBYH

Device A X-Axis Position Counter Low Byte

Device A X-Axis Position Counter High Byte

Device A Y-Axis Position Counter Low Byte

Device A Y-Axis Position Counter High Byte

Device B X-Axis Position Counter Low Byte

Device B X-Axis Position Counter High Byte

Device B Y-Axis Position Counter Low Byte

Device B Y-Axis Position Counter High Byte

Device B Button 1

Event Polarity

Device B Button 0

Event Polarity

Device A Button 1

Event Polarity

Device A Button 0

Event Polarity

0Ch

GMPEPOL

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6.0 Musical Instrument Digital Interface (MIDI) Port

Note: This section applies to the PC87393 and PC87393F only.

6.1 OVERVIEW

This chapter describes a generic MIDI Port. For the implementation used in this device, see the Device Architecture and

Conﬁguration chapter.

The MIDI Port is an asynchronous receiver/transmitter that uses a two-wire, bi-directional, relatively slow communication

channel to transmit and receive data bytes to or from MIDI-compliant devices, according to a predefined communication pro-

tocol. The MIDI Port is compatible with MPU-401 UART mode.

The MIDI was originally defined to establish a standard interface between computers and digital musical instruments such

as synthesizers, and has become the de facto standard for this purpose. However, the MIDI is also commonly used for other

purposes, such as communicating with advanced game devices.

The MIDI Port serves as a communication pipe between software and a MIDI device. The software and the MIDI device must

interpret the data they exchange, and act accordingly.

The MIDI Port supports the following two feature types:

●

Legacy (MPU-401)

●

Enhanced.

Legacy. These include all features supported by MPU-401 UART mode. They can all be operated via the Legacy I/O ad-

dress space of 2 bytes, traditionally allocated for the MIDI Port.

Enhanced. These features extend the capabilities of the MIDI Port. They can only be operated if the MIDI is allocated with

an address space of at least 3 bytes.

The basic system configuration of the MIDI Port consists of the port itself, a single pull-up resistor for the MDRX pin, and a

MIDI compliant device. This system configuration is shown in Figure 17. The purpose of the pull-up resistor is to make sure

that the MIDI Port senses an inactive (high) MIDI receive signal in the absence of a MIDI device.

R

MDRX Pin

MIDI Receive

MIDI Transmit

MIDI Receive

MIDI

Port

MIDI

Game

Device

MDTX Pin

Figure 17. MIDI System Conﬁguration

6.2 FUNCTIONAL DESCRIPTION

The MIDI Port consists of five major functional blocks:

●

Internal Bus Interface Unit

●

Port Control and Status Registers

●

Data Buffers and FIFOs

●

MIDI Communication Engine

●

MIDI Signals Routing Control Logic.

See Figure 18 for a block diagram of the MIDI Port.

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6.0 Musical Instrument Digital Interface (MIDI) Port (Continued)

Asynchronous

Interface

Synchronous

Interface

SuperI/O

Internal

Bus

Tx Data

8

Tx Data

8

MIDI

Transmit

Signal

MIDI

Communication

Engine

Data

Buffers

and

MIDI

MDTX Pin

MDRX Pin

Internal

Rx Data

8

Rx Data

8

Signals

Routing

Control

Bus

Interface

Unit

MIDI

Receive

Signal

(Data Serializer)

FIFOs

Control

Data Buffer

Status and Control

Communication

Status and Control

Read/Write

Routing

Control

Interface

MIDI Port

Control and Status

Registers

Figure 18. MIDI Port Block Diagram

6.2.1

Internal Bus Interface Unit

The Internal Bus Interface Unit handles all read and write transactions between the host and the registers of the MIDI Port.

It also controls the MIDI Port interrupt request logic (see Section 6.2.8).

6.2.2

Port Control and Status Registers

A Control register (MCNTL, see Section 6.3.6) and a Status register (MSTAT, see Section 6.3.4) allow the user to control

the operation of the MIDI, and provide status information regarding its various functional units. A Command register (MCOM,

see Section 6.3.5) allows the user to control the operation mode of the MIDI Port by serving as a port via which the host can

issue commands to the MIDI. A MIDI Port command is defined as a write access to the MIDI Command register. The mean-

ing of each command is determined by the data byte written during this write access.

6.2.3

Data Buffers and FIFOs

The Data Buffers and FIFOs function as a mechanism for synchronizing between the Internal Bus Interface Unit and the

MIDI Communication Engine. This synchronization allows each of these units to handle its own tasks without having to

pause to send/receive data to/from the other unit. Synchronization also bridges the gap in the data transfer rate between

these two units. Data transfer rate matching is done when the FIFOs of the MIDI Port are enabled. It allows the MIDI Port to

interface a bus at a relatively high data transfer rate, while maintaining communication with a MIDI device over a communi-

cation channel that supports a relatively low data transfer rate.

6.2.4

MIDI Communication Engine

The MIDI Communication Engine handles the serializing of outgoing data and the de-serializing of incoming data transferred

between the MIDI Port and the MIDI device. During transmit (serial data transfer from the MIDI Port to the MIDI device), the

Communication Engine receives data bytes from the output data buffer or FIFO, serializes them into a stream of data bits,

and transmits them as a sequence of high and low pulses over the MDTX pin according to the MIDI communication protocol.

During receive (serial data transfer from the MIDI device to the MIDI Port), the Communication Engine receives a sequence

of high and low pulses via the MDRX pin, converts them into a stream of data bits and de-serializes them into data bytes

that it sends to the input data buffer or FIFO.

Both transmit and receive are performed at a fixed serial data rate of 31.25 Kbits per second. The serial data format is also

fixed, and consists of 1 Start bit, 8 Data bits and 1 Stop bit. See the waveform illustrating a MIDI byte transfer in Figure 19.

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6.0 Musical Instrument Digital Interface (MIDI) Port (Continued)

LSB

MSB

0

MIDI Signal

Start

Stop

Bit

1

0

1

0

1

0

1

Data Bits

Bit

32µsec

Figure 19. MIDI Byte Transfer Waveform

MIDI Signals Routing Control Logic

6.2.5

The MIDI Signals Routing Control Logic controls the various routing options available for the MIDI transmit and receive sig-

nals. It is controlled by the MIDI Control register (MCNTL, see Section 6.3.6). These routing options are not part of the Leg-

acy definition of the MIDI Port.

6.2.6

Operation Modes

The MIDI Port can be operated in one of the following modes:

●

Pass-Thru (Non-UART) Mode (default)

●

UART Mode.

Pass-Thru (Non-UART) Mode

After a hardware reset, the MIDI Port is in Pass-Thru mode.

In this mode, transmission is disabled by default, and all writes to the MIDI Data Out register (MDO, see Section 6.3.3) are

ignored. Transmission in this mode may be enabled by setting bit 4 of the MIDI Control register (MCNTL, see Section 6.3.6).

Receive in Pass-Thru mode is enabled, and a 16-byte Receive FIFO is available. Reading the MIDI Data In register (MDI,

see Section 6.3.2) in this mode returns the oldest data stored in the Receive FIFO. If serial data is received while the Receive

FIFO is full with data that has not yet been read, the last received data is lost, thus maintaining the data that was previously

stored in the Receive Buffer.

When in Pass-Thru mode, the MIDI Port responds to commands issued by the host, as follows:

●

3Fh puts the MIDI Port in UART mode. Also, in response to this command, the MIDI Port puts an acknowledge byte

of FEh in the Receive Buffer.

●

A0h-A7h or ABh causes the MIDI Port to put an acknowledge byte of FEh followed by a data byte of 00h in the Re-

ceive Buffer.

●

ACh causes the MIDI Port to put an acknowledge byte of FEh, followed by a data byte of 15h, in the Receive Buffer.

●

ADh causes the MIDI Port to put an acknowledge byte of FEh, followed by a data byte of 01h, in the Receive Buffer.

●

AFh causes the MIDI Port to put an acknowledge byte of FEh, followed by a data byte of 64h, in the Receive Buffer.

●

FFh resets the MIDI Port to its initial state, including all the bits of the MSTAT register. In response, the MIDI Port

puts an acknowledge of FEh in the Receive Buffer. This command is usually referred to as the MIDI Reset Command.

●

The MIDI Port responds to all other commands by putting an acknowledge byte of FEh in the Receive Buffer.

Putting the acknowledge byte of FEh is equivalent to receiving a data byte. Therefore, once an acknowledge byte is put in

the Receive Buffer, it causes the Receive Buffer Empty status flag (see Section 6.2.7) to be cleared, which may also cause

a MIDI Port interrupt request to be issued.

When the Receive FIFO is disabled, switching from Pass-Thru mode to UART mode causes data stored in the Receive Buff-

er to be lost. After switching to UART mode, the MIDI Port is blocked for receive until the acknowledge byte is read from the

Receive Buffer.

If a command is issued to the MIDI Port while the MIDI Communication Engine is in the middle of a byte transfer (the Start

bit has been transmitted or received), the execution of the command and the response are postponed until the ongoing byte

transfer is completed.

After each MIDI Port operation in Pass-Thru mode, the MIDI Status register (MSTAT, see Section 6.3.4) is updated accord-

ingly.

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6.0 Musical Instrument Digital Interface (MIDI) Port (Continued)

UART Mode

Entering UART mode is done by software, by giving the MIDI Port command of 3Fh. Once in UART mode, both transmit and

receive are enabled. In addition, the two 16-byte Receive and Transmit FIFOs are automatically enabled.

In UART mode, data written to the MDO register is placed in the Transmit FIFO, from which it is taken by the MIDI Commu-

nication Engine and transmitted via the MDTX pin to the MIDI device. Likewise, whenever the Transmit FIFO is not empty,

the next byte is taken out by the Communication Engine and transmitted via the MDTX pin to the MIDI device.

Whenever serial data is received by the Communication Engine via the MDRX pin, it is de-serialized and put in the Receive

FIFO. Reading the MDI register returns the next byte in the Receive FIFO. The MDI register should not be read while the

Receive FIFO is empty. If serial data is received while the Receive FIFO is full, this data is lost and not stored in the Receive

FIFO, thus keeping the data that was previously stored in the Receive FIFO.

When in UART mode, the MIDI Port responds to commands given by the host as follows:

●

A command of FFh returns the MIDI Port to Pass-Thru mode, and resets it to its initial state.

●

All other commands, issued while the MIDI Port is in UART mode, are ignored.

When switching from UART mode to Pass-Thru mode, any data previously stored in the Receive FIFO is lost, unless the

FIFO is enabled for Pass-Thru mode.

As in Pass-Thru mode, if a command is issued to the MIDI Port while the MIDI Communication Engine is in the middle of a

byte transfer, the execution of the command and the response are postponed until the ongoing byte transfer is completed.

The MIDI commands supported by the MIDI Port and their respective responses are listed in Table 31.

After each MIDI Port operation in UART mode, the MSTAT register is updated accordingly.

Table 31. MIDI Commands Supported by the MIDI Port

MIDI Port Response

Command

Pass-Thru Mode

UART Mode

Enter UART mode

FEh (Acknowledge)

3Fh

A0h-A7h, ABh

ACh

Ignored

FEh (Acknowledge)

00h

Ignored

FEh (Acknowledge)

15h

FEh (Acknowledge)

01h

ADh

FEh (Acknowledge)

64h

AFh

MIDI Port Reset

FEh (Acknowledge)

Enter Pass-Thru Mode

MIDI Port Reset

FFh

Others

FEh (Acknowledge)

Ignored

6.2.7

MIDI Port Status Flags

The status of the various functional units of the MIDI Port is reflected by the MSTAT register. This register is functional in

both Pass-Thru and UART modes. Some of the status indications provided by the MSTAT register are not included in the

Legacy definition of the MIDI Port. These indications can be ignored, if not required by the software.

The following status flags are included in the Legacy definition of the MIDI Port:

●

Receive Buffer Empty

●

Transmit Buffer Full

The Receive Buffer Empty flag is reflected by bit 7 of the MSTAT register. The Transmit Buffer Full flag is reflected by bit 6

of the MSTAT register. When operating in UART mode, these bits reflect the status of the Receive and Transmit FIFOs.

The Receive Buffer Empty status flag is cleared to 0 also when an acknowledge byte is put by the MIDI Port itself following

a MIDI command.

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6.0 Musical Instrument Digital Interface (MIDI) Port (Continued)

The values of these bits are set by the MIDI Port hardware and are not affected by reading the MSTAT register.

The following status indications are provided by the MIDI Port, although they are not included in the Legacy definition of the

MIDI Port:

●

Receive FIFO Full

●

Transmit FIFO Empty

●

Receive Overrun Error

●

MIDI Port Operation Mode

The Receive FIFO Full and Transmit FIFO Empty status flags are reflected by MSTAT register bits 5 and 2, respectively.

These bits are updated only when the MIDI Port operates in UART mode or when in Pass-Thru mode with the Receive FIFO

enabled. Otherwise, these bits are constantly cleared. The values of these bits are set by the MIDI Port hardware and are

not affected by reading the MSTAT register.

The Receive Overrun Error flag indicates that serial data has been received by the MIDI Communication Engine while the

Receive Buffer of FIFO was full. This flag is reflected by bit 3 of the MSTAT register. It is updated in both Pass-Thru and

UART modes. When a Receive Overrun Event occurs, the data in the Receive Buffer/FIFO is kept and all incoming data is

lost. Incoming data will keep getting lost until there is room in the Receive Buffer/FIFO to accept it. The Receive Overrun

Error status flag is cleared when the MSTAT register is read.

The MIDI Port Operation Mode flag indicates whether the MIDI Port currently operates in Pass-Thru or UART mode. This

status flag is reflected by bit 4 of the MSTAT register. It can be used by software to keep track of the currently selected MIDI

Port operation mode.

6.2.8

MIDI Port Interrupts

The MIDI Port supports interrupt assertion in both Pass-Thru and UART modes, in response to one of the following events,

or both:

●

Receive Data Ready

●

Transmit Buffer Empty

The Receive Data Ready event refers to the case in which there is data to be read in the Receive Buffer/FIFO. An interrupt

request is asserted by the MIDI Port to indicate a Receive Data Ready event in one of the following cases:

• The MIDI Port is in Pass-Thru mode, and the Receive Buffer contains a data or acknowledge byte which has not been

read yet. In this case, the interrupt request is deasserted once the Receive Buffer is read.

• The MIDI Port is in UART mode, and the Receive FIFO contains eight, or more, data bytes which have not been read

yet, or it is in Pass-Thru mode with the Receive FIFO enabled. In this case, the interrupt request is deasserted once the

Receive FIFO level drops below eight bytes.

• The MIDI Port is in UART mode, the Receive FIFO contains less than eight data bytes which have not been read yet,

and no data was received by the Communication Engine, the MIDI Port is in Pass-Thru mode with the Receive FIFO

enabled, or a read occurs from the Receive FIFO during a timeout period of approximately 1.28 msec (the time it takes

to transfer 4 bytes over the MIDI communication channel). In this case, the interrupt request is deasserted when either

new data is received by the Communication Engine, or data is read from the Receive FIFO.

The Transmit Buffer Empty event refers to the case in which the Transmit Buffer/FIFO of the MIDI Port can still accept data

to transmit. An interrupt request is asserted by the MIDI Port to indicate a Transmit Buffer Empty event in one of the following

cases:

• The MIDI Port is in Pass-Thru mode, and the Transmit Buffer is empty. In this case, the interrupt request is deasserted

once a byte is written to the Transmit Buffer.

• The MIDI Port is in UART mode, and the Transmit FIFO is empty. In this case, the interrupt request is deasserted once

the Transmit FIFO is filled with at least 3 bytes.

After hardware reset, interrupts are asserted by the MIDI Port only in response to a Receive Data Ready event. Interrupt

assertion in response to Transmit Buffer Empty events can be enabled by setting writing 1 to bit 1 of the MCNTL register.

Interrupt assertion in response to Receive Data Ready events can be disabled by writing 0 to bit 3 of the MCNTL register.

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6.0 Musical Instrument Digital Interface (MIDI) Port (Continued)

6.2.9

Enhanced MIDI Port Features

The MIDI Port supports the following modes/operations, which are not part of the Legacy definition of the MIDI Port:

●

Transmit in Pass-Thru

●

Loopback mode

●

MIDI Thru

●

MDTX pin masking

Transmit in Pass-Thru. When the MIDI Port is operated in Pass-Thru mode, transmit is disabled by default. To enable it,

write 1 to bit 4 of the MCNTL register.

Loopback Mode. The MIDI serial data transmit signal is routed internally to the MIDI serial data receive signal. This causes

all the data transmitted by the MIDI Port to also be received. Loopback mode can be used as a mode for testing the MIDI

Port or its software. To enable it, write 1 to bit 7 of the MCNTL register.

MIDI Thru. The MIDI serial data receive signal is routed internally to the MIDI serial data transmit signal. This causes any

incoming stream of pulses received via the MDRX pin to be driven immediately on the MDTX pin. This feature allows the

MIDI Port to be connected as a link in a chain of several MIDI devices. In parallel to routing the MIDI receive signal to the

MIDI transmit signals, the incoming serial data is also received by the MIDI Port itself. To enable it, write 1 to bit 6 of the

MCNTL register.

MDTX Pin Masking. MDTX pin masking forces this pin to remain at a high level. This causes all transmit processes to occur

without physically driving the serial data via the MDTX pin. Writing 1 to bit 2 of the MCNTL register enables MDTX pin mask-

ing.

The above three features are handled by the MIDI Signals Routing Control Logic, which is illustrated in Figure 20.

Loopback

Mode

Enable

MIDI Thru

Enable

MDTX Pin

Masking

Enable

MIDI

Transmit

Signal

0

1

MDTX Pin

MDRX Pin

MIDI

Receive

Signal

1

0

Figure 20. MIDI Signals Routing Control Logic

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6.0 Musical Instrument Digital Interface (MIDI) Port (Continued)

6.3 MIDI PORT REGISTERS

The following abbreviations are used to indicate the Register Type:

●

R/W = Read/Write

●

R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different

register.

●

W = Write

●

RO = Read Only

●

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

6.3.1

MIDI Port Register Map

The following table lists the MIDI Port registers. For the MIDI Port register bitmap, see Section 6.4.

Offset

Mnemonic

Register Name

Type

Section

00h

01h

02h

MDI

MIDI Data In

MIDI Data Out

R

W

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

MDO

MSTAT MIDI Status

MCOM MIDI Command

MCNTL MIDI Control

R

W

R/W

6.3.2

MIDI Data In Register (MDI)

This read register is used for reading data received by the MIDI Port, and status information returned by the MIDI Port in

response to a previously issued command. When the FIFOs of the MIDI Port are enabled, reading from this offset returns

the next byte taken out of the Receive FIFO.

Location:

Type:

Offset 00h

R

Bit

7

6

5

4

3

2

1

0

Name

Reset

Data In

X

6.3.3

MIDI Data Out Register (MDO)

This write register is used for writing data to be transmitted by the MIDI Port. When the FIFOs of the MIDI Port are enabled,

writing to this offset puts the data byte into the Transmit FIFO.

Location:

Type:

Offset 00h

W

Bit

7

6

5

4

3

2

1

0

Name

Reset

Data Out

X

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6.0 Musical Instrument Digital Interface (MIDI) Port (Continued)

6.3.4

MIDI Status Register (MSTAT)

This read register provides status information regarding the functional blocks of the MIDI Port.

Location:

Type:

Offset 01h

R

Bit

7

6

5

4

3

2

1

0

MIDI Port

Operation

Mode

Rx Buffer Tx Buffer

Empty

Rx FIFO

Full

Rx Overrun Tx FIFO Not

Name

Reset

Reserved

Full

Error

Empty

1

0

Bit

Description

7

Rx Buffer Empty. When set to 1, it indicates that the Receive Buffer in Pass-Thru mode, or the FIFO in UART

mode, is empty. When set to 0, it indicates that the Receive Buffer or FIFO contain data that can be read via the

MDI register.

0: Not empty

1: Empty (default)

6

5

Tx Buffer Full. When set to 1, it indicates that the Transmit Buffer or FIFO cannot accept any more data. When

set to 0, it indicates that the Transmit Buffer or FIFO can accept more data written to the MDO register.

0: Not full (default)

1: Full

Rx FIFO Full. When set to 1, it indicates that the Receive FIFO cannot accept any more received data bytes.

When set to 0, it indicates that the Receive FIFO can accept more received data bytes. This bit is forced to 0

when the FIFOs are disabled.

0: Not full or disabled (default)

1: Full

4

3

MIDI Port Operation Mode. When set to 1, it indicates that the MIDI Port is currently operating in UART mode.

When set to 0, it indicates that the MIDI Port is currently operating in Pass-Thru (non-UART) mode.

0: Pass-Thru mode (default)

1: UART mode

Rx Overrun Error. This bit is cleared to 0 when the MSTAT register is read. An overrun error is deﬁned as the

state in which one or more data bytes have been received by the MIDI Port while the Receive Buffer, or FIFO,

was full.

0: No overrun error (default)

1: Overrun error

2

Tx FIFO Not Empty. This bit is forced to 0 when the FIFOs are disabled.

0: Empty or disabled (default)

1: Not empty

1-0 Reserved

6.3.5

MIDI Command Register (MCOM)

This write register is a port via which commands are issued by the host to the MIDI Port.

Location:

Type:

Offset 01h

W

Bit

7

6

5

4

3

2

1

0

Name

Reset

Command Byte

X

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6.0 Musical Instrument Digital Interface (MIDI) Port (Continued)

6.3.6

MIDI Control Register (MCNTL)

This register controls enhanced MIDI functions.

Location:

Type:

Offset 02h

R/W

Bit

7

6

5

4

3

2

1

0

Rx Data

Ready

Interrupt

Enable

Tx Buffer

Empty

Interrupt

Enable

Rx FIFO

Enable for

Pass-Thru

Mode

Loopback

Mode

Enable

Pass-Thru

Transmit

Enable

MDTX Pin

Masking

Enable

MIDI Thru

Enable

Name

Reserved

Reset

0

1

0

1

Required

Bit

Description

7

6

Loopback Mode Enable. When enabled, the MIDI receive signal is internally connected to the MIDI transmit

signal.

0: Disabled (default)

1: Enabled

MIDI Thru Enable. When enabled, the MDRX pin is internally connected to the MDTX pin, which then reﬂects

the MIDI receive signal. When disabled, the MDTX pin is driven with data coming from the MIDI Port transmit

engine.

0: Disabled (default)

1: Enabled

5

4

Reserved. Must be 0.

Pass-Thru Transmit Enable. When enabled, data is transmitted in Pass-Thru (non-UART) mode.

0: Disabled (default)

1: Enabled

3

2

1

0

Rx Data Ready Interrupt Enable. When enabled, an interrupt request is asserted in response to a Receive

Data Ready event.

0: Disabled

1: Enabled (default)

MDTX Pin Masking Enable. When enabled, the MDTX pin is constantly driven high by the MIDI Port. When

disabled, MDTX serves as the MIDI Port transmit line.

0: Disabled (default)

1: Enabled

Tx Buffer Empty Interrupt Enable. When enabled, an interrupt request is asserted in response to a Transmit

Buffer Empty event.

0: Disabled (default)

1: Enabled

Rx FIFO Enable for Pass-Thru Mode. When this bit is set to 1, the Receive FIFO is enabled in Pass-Thru

mode. This bit is ignored in UART mode.

0: Disabled

1: Enabled (default)

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6.0 Musical Instrument Digital Interface (MIDI) Port (Continued)

6.4 MIDI PORT BITMAP

Register

Bits

Offset

Mnemonic

MDI

7

6

5

4

3

2

1

0

00h

Data In

MDO

Data Out

MIDI Port

Operation Overrun

Mode Error

Rx

Rx Buffer Tx Buffer Rx Buffer

Tx FIFO

Empty

01h

MSTAT

MCOM

Reserved

Empty

Full

Command Byte

Rx FIFO

Enablefor

Pass-

Thru

Mode

Pass-

Thru

Rx Data

Ready

MDTX

Tx Buffer

Empty

Loopback

Mode

Enable

MIDIThru

Enable

02h

MCNTL

Reserved

Transmit Interrupt Masking Interrupt

Enable Enable Enable Enable

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7.0 X-Bus Extension

Notes: This section applies to the PC87393 and PC87393F only.

FWH-related descriptions apply to the PC87393F only.

7.1 OVERVIEW

The PC8739x provides an X-Bus extension to the LPC bus to enable the ISA-like interface to external 8-bit peripherals. De-

code logic, described in the Device Architecture and Configuration chapter, defines the addresses for which the X-Bus gen-

erates transactions. These transactions may be in the I/O address space and the memory address space or in the FWH

memory address space. Using the X-Bus interface, the PC8739x serves as a bridge for such transactions into the X-Bus.

Figure 21 is a schematics block diagram of the X-Bus bridging function. For details on the decoder functions, see the Device

Architecture and Configuration chapter. All other functions are described in detail in this chapter.

IRQ

Serializer

PIRQ(A-D)

IRQ Router

XA19-0

XD7-0

Bus

XIORD XIOWR

XRD XWR

XSTB2-0

X-Bus

Configuration

Cycle

Generator

XRDY

LPC

Bus

Memory

Address

Decoder

XCS0

I/O

Address

Decoder

XCS1

XCNF2-0

Device Architecture Component

X-Bus Interface

Figure 21. X-Bus Block Diagram

7.2 IRQ ROUTING

The PC8739x supports up to four IRQ inputs, PIRQA through PIRQD. These pins may be used to support legacy devices

that are connected on the X-Bus. The PC8739x enables any of these interrupts to be routed to any one of fifteen host IRQs.

The IRQ inputs are mapped by X-Bus PIRQA-D Mapping registers at F8h and F9h. XIRQCA through XIRQCD registers en-

able the user to define the interrupt as active high or low, and to route it to a wake-up event.

7.3 X-BUS TRANSACTIONS

The X-Bus extension supports 8-bit I/O or memory read/write cycles.

The zone mapping of the chip select signals determines how X-Bus read and write cycles correspond to memory and I/O

bus cycles. The zone mapping to a select signal, XCS1-0, must be enabled regardless of whether the I/O device is using

the chip select signal. Signal mapping to a pin may be disabled when the select signal is not required for an off-chip interface.

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7.0 X-Bus Extension (Continued)

The X-Bus interface outputs the address in one of two modes:

●

Normal Address mode - A pin is assigned for each address line, and a non-multiplexed address data bus is used.

●

Latched Address mode - The number of pins used for outputting the address is reduced. The address lines are mul-

tiplexed with the data bus. External latches should be used to enable the memory or I/O device access to the multi-

plexed address signals. When the memory conﬁguration uses more than 1 Mbyte of memory, this mode must be

used to generate address signals 20 through 27.

X-Bus access timing is driven by an internal version of the LPC clock (i.e., it has the same frequency but may have some

phase delay), referred to in this section simply as "the clock". The transactions are described in reference to the clock, and

the AC speciﬁcations are relative to it. This provides an easy way for calculating the timing for the system design. However,

the system interface is optimized for an asynchronous interface. For hints on how to use it, refer to the usage hints in Section

7.5.

7.3.1

Programmable I/O Range Chip Select

The PC8739x has two chip select signals, XCS1-0, to indicate X-Bus accesses. The PC8739x X-Bus functional block en-

ables flexible association of these chip selects with I/O and memory address ranges in the LPC address space. The Chip

Select Mapping field of the X-Bus Zone Configuration registers defines to which of the decoded address ranges the respec-

tive XCS signal responds. In addition, the X-Bus Configuration register enables specifying the access time for the respective

select signal via bits that control the fixed wait cycles and variable wait cycles, using the XRDY input.

If the chip select signal setting results in a conflict in which both selects are configured for the same transaction, XCS0 has

priority. XCS1 remains inactive and its Configuration register setting is ignored. For zones that are not associated with one

of the chip select signals, the X-Bus does not respond to LPC transactions.

7.3.2

LPC and FWH Address to X-Bus Address Translation

The BIOS memory on the LPC bus can occupy one of three regions in the memory space (specified in Table 29 and Table

31). Address translation between the LPC bus address and the X-Bus is performed as follows:

I/O Transactions. The 16-bit address of the LPC bus is padded with zeroes (bits 16 through 27) to create the 28-bit input

address to the X-Bus functional block.

Memory Transactions. The 32-bit address received from the LPC bus is used to decode the different zones described in

Section 2.19. The address is then translated to the X-Bus address using the following rules:

●

User-Deﬁned Zone (UDZ) and 386 Mode-Compatible BIOS Range (LPC or LPC-FWH) - The 28 least signiﬁcant bits

of the LPC address are used as the X-Bus input address. Figure 22 illustrates the mapping for this zone. (Note: See

Section 2.8.1 for the way addresses are built for FWH transactions.)

●

Legacy and Extended Legacy BIOS Range - The 17 least signiﬁcant bits (A16-0) of the LPC address are routed as

the 17 least signiﬁcant signals address lines of the X-Bus (XA16-0). The upper 11 X-Bus address lines are driven to

1. This shifts the addresses to the end of the X-Bus memory space (see Figure 23).

X-Bus Address

LPC Bus Address

FFFFFFFFh

xFFFFFFFh

xFC00000h

FFC00000h

00000000h

Figure 22. LPC to X-Bus Address Translation: 386 Mode-Compatible BIOS Range

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7.0 X-Bus Extension (Continued)

X-Bus Address

LPC Bus Address

FFFFFFFFh

xFFFFFFFh

xFFE0000h

000FFFFFh

Legacy BIOS

000F0000h

000EFFFFh

Extended

Legacy BIOS

000E0000h

00000000h

Figure 23. LPC to X-Bus Address Translation: Legacy and Extended Legacy BIOS Ranges

Extended Read/Write Signal Mode

7.3.3

This mode is essential for devices that have separate read and write signals for memory transactions and for I/O transac-

tions. While in this mode, the PC8739x routes I/O read and write signals to XIORD and XIOWR pins, and memory or FWH

read and write signals to XRD and XWR.

If the PC8739x is set to wake-up with the X-Bus signals configured to output pins (using strap pins XCNF2-0), the extended

mode is disabled, and must be re-enabled by the user.

7.3.4

Indirect Memory Read and Write Transaction

I/O mapped registers may be used through an LPC I/O transaction to perform an X-Bus memory transaction. This mecha-

nism uses the following X-Bus module registers:

●

Four Indirect Memory Address registers, XIMA3-XIMA0, representing address bits 31 to 0

●

One Indirect Memory Data register (XIMD), representing data bits 7 to 0

●

Two enable bits, one for each Select Conﬁguration register, XZCNF0[5] and XZCNF1[5].

Following a write to the XIMD register, a memory write cycle appears on the X-Bus using the addresses and data from the

XIMA3-XIMA0 and XIMD registers. Following a read from the XIMD register, a memory read cycle appears on the X-Bus

using the addresses from these same registers. The returned data from the X-Bus cycle is used to finish the LPC I/O read

cycle from XIMD register.

The read or write cycles appear only if one of the Indirect Memory Cycle Enable bits (XZCNF0[5] or XZCNF1[5]) is set. If

both of these bits are set, select 1 is ignored and the transaction takes place according to select 0 settings. All X-Bus cycle

configurations are the same as defined in the X-Bus Select Configuration registers (XZCNF0 and XZCNF1).

7.3.5

Normal Address Mode X-Bus Transactions

The read and write transactions in Normal address mode are similar to those used in the X-Bus or ISA bus. At least two idle

cycles are inserted at the end of each X-Bus transaction cycle (there may be more idle cycles due to the LPC transactions).

Once a read cycle on the LPC falls within the range of any of the enabled decoded address ranges of the X-Bus functional

block, a read cycle begins. A read cycle (Figure 24) starts by outputting the address signals on address signals XA19-0 on

the rising edge of the clock. During this time, the PC8739x does not drive the data bus signals XD7-0. One LPC clock cycle

later, a chip select signal XCS1 or 0 is asserted, based on the address accessed and the select signal mapping. Three clock

cycles later, on the next rising edge of the clock, the XRD signal is asserted (set to 0) indicating that this is a read cycle and

enabling the device being accessed to drive the data bus within 16 clock cycles plus the internally programmed wait state

period. If XRDY use is enabled for this zone, XRDY input value is then checked on the rising edge of the clock, and the trans-

action is extended until XRDY is detected to be high. Four clock cycles later, the input data XD7-0 is sampled on the rising

edge of the clock. One LPC clock cycle later, XRD is de-asserted (set to 1) and one clock cycle later, the transaction is com-

pleted by de-asserting XCS1-0. The address is retained for the duration of two more cycles, after which the address lines

change their values to 0.

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108

7.0 X-Bus Extension (Continued)

Once a write cycle on the LPC falls within the range of any of the enabled decoded address ranges of the X-Bus functional

block, a write cycle begins. A write cycle (Figure 25) starts by outputting the address signals on address signals XA19-0,

and the data signals on data pins XD7-0, on the rising edge of the clock. One LPC clock cycle later, a chip select signals

XCS1 or 0 is asserted, based on the address accessed and the select signal mapping. Three clock cycles later, on the next

rising edge of the clock, the XWR signal is asserted (set to 0) indicating that this is a write cycle and enabling the device to

be written for 16 clock cycles plus the internally programmed wait state period. If XRDY use is enabled for this zone, XRDY

input value is then checked on the rising edge of the clock, and the transaction is extended until XRDY is detected to be high.

Five LPC clock cycles later, XWR is de-asserted (set to 1) and one clock cycle later, the transaction is completed by de-

asserting XCS1-0. Two clock cycle later, the address lines change their values to 0.

CLK

(Internal for

Reference)

XD7-0

XD[7:0] (Data In)

(Data Read)

XA19-0

XCS1-0

XWR

XRD

XRDY

Insert 12+”Programmed Wait States” of 33 MHz clocks here.

All non-clock signals remain the same during this inserted time.

Figure 24. Read Access Cycle - Normal Address Mode

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109

7.0 X-Bus Extension (Continued)

CLK

(Internal for Reference)

XD7-0

XA19-0

XCS1-0

XWR

XRD

XRDY

Insert 12+”Programmed Wait States” of 33 MHz clocks here.

All non-clock signals remain the same during this inserted time.

Figure 25. Write Access Cycle - Normal Address Mode

Latched Address Mode X-Bus Transactions

7.3.6

The read and write transactions in Latched address mode are similar to those used in Normal address mode, except for how

the addresses are placed on the X-Bus. In this mode, address signals 27-0 are output using the XA signals and via multi-

plexing over the data bus (XD7-0). Latch control signals XSTB2-0 help a system capture these signals. The XSTB2-0 signals

are placed as long as the address signal are valid (until the end of a transaction).

Once a read cycle on the LPC falls within the range of any of the enabled X-Bus decoded address ranges, a read cycle

begins. A read cycle starts by outputting the lower twenty address signals on address signals XA19-0, and address signals

27-20 on data signals XD7-0, on the rising edge of the clock. Two clock cycles later, a strobe signal (XSTB2) is asserted to

latch the information on an external latch. Two clock cycles later, a second set of address signals, 19-12, is placed on data

pins XD7-0. These may be latched using the strobe signal XSTRB1 output two cycles later on the rising edge of the clock.

Two clock cycles later, the last group of address signals, 11-4, is output on data signals XD7-0. The XSTRB0 output two

cycles later, on the rising edge of the clock, may be used to latch this part of the address. Two cycles later on the rising edge

of the clock, the PC8739x stops driving the data bus. At this point, all addresses are available either on the address outputs

of the PC8739x (XA19-0) or in one of the three latches. The system may require only part of these addresses, depending

on the size of the address memory or peripheral space. One clock cycle later, a chip select signal XCS1 or 0 is asserted,

based on the address accessed and the select signal mapping. From this point, the read continues as described for the Nor-

mal address mode. XSTRB2-0 are deasserted when the address becomes invalid.

Once a write cycle on the LPC falls within the range of any of the enabled decoded address ranges of the X-Bus functional

block, a read cycle is started. A write cycle starts by outputting the lower twenty address signals on address signals XA19-

0] and address signals 27- 20 on data signals XD7-0, on the rising edge of the clock. Two clock cycles later, a strobe signal

(XSTB2) is asserted to latch the information on an external latch. Two clock cycles later, a second set of address signals,

19-12, is placed on data pins XD7-0. These may be latched using the strobe signal XSTRB1 output two cycles later on the

rising edge of the clock. Two clock cycles later, the last group of address signals, 11-4, is output on the data signals XD7-0.

The XSTRB0 output, two cycles later on the rising edge of the clock, may be used to latch this part of the address. Two

cycles later on the rising edge of the clock, the PC8739x outputs the data signals on data pins XD7-0 on the rising edge of

the clock. At this point, all the address is available either on the address outputs of the PC8739x (XA[19:0]) or in one of the

three latches. The system may require only part of these addresses, depending on the size of the address memory or pe-

ripheral space. One clock cycle later, chip select signal XCS1 or 0 is asserted, based on the address accessed and the select

signal mapping. From this point, the write continues as described for the Normal address mode. XSTRB2-0 are deasserted

when the address becomes invalid.

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110

7.0 X-Bus Extension (Continued)

CLK

(Internal for Reference)

A

[11-4]

XD7-0

[19-12]

[27-20]

XSTB2

XSTB1

XSTB0

XA19-0

(Some May Not be

Available Due to Multiplexing)

XA27-0

(Externally Available Address)

XCS

XRD

XWR

XRDY

Transaction Continues as for Normal Address Mode Read

Figure 26. X-Bus Read Access Cycle - Latched Address Mode

CLK

(Internal for Reference)

D

[7-0]

A

[11-4]

XD7-0

[19-12]

[27-20]

XSTB2

XSTB1

XSTB0

XA19-0

(Some May Not be

Available Due to Multiplexing)

A27-0

(Externally Available Address)

XCS

XRD

XWR

XRDY

Transaction Continues as for Normal Address Mode Write

Figure 27. X-Bus Write Access Cycle - Latched Address Mode

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111

7.0 X-Bus Extension (Continued)

7.4 X-BUS CONFIGURATION REGISTERS

The following abbreviations are used to indicate the Register Type:

●

R/W = Read/Write

●

R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different

register.

●

W = Write

●

RO = Read Only

●

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

7.4.1

X-Bus Register Map

The following table lists the X-Bus registers.

Offset

Mnemonic

Register Name

Type

Section

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

XBCNF X-Bus Conﬁguration

R/W

7.4.2

7.4.3

7.4.4

XZCNF0 X-Bus Select 0 Conﬁguration

XZCNF1 X-Bus Select 1 Conﬁguration

Reserved exclusively for National use

XIRQCA X-Bus IRQ A Conﬁguration

R/W

7.4.5

7.4.6

7.4.7

7.4.8

7.4.9

7.4.10

XIRQCB X-Bus IRQ B Conﬁguration

XIRQCC X-Bus IRQ C Conﬁguration

XIRQCD X-Bus IRQ D Conﬁguration

XIMA0 X-Bus Indirect Memory Address Register 0

XIMA1 X-Bus Indirect Memory Address Register 1

XIMA2 X-Bus Indirect Memory Address Register 2

XIMA3 X-Bus Indirect Memory Address Register 3

XIMD

X-Bus Indirect Memory Data Register

7.4.2

X-Bus Configuration Register (XBCNF)

This register affects the functionality mode of the X-Bus.

Location:

Type:

Offset 00h

R/W

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W

Extended

Mode

Latch

Address

Mode

Name

Reset

Reserved

Enable

0

Strap

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7.0 X-Bus Extension (Continued)

Bit

Description

7-2 Reserved

1

Read/Write Extended Mode Enable. When set to 1, enables the separation of the I/O read and write

transactions from pins XRD & XWR to pins XIORD & XIOWR, leaving the memory and FWH transactions to be

routed to XRD and XWR.

0: Disabled (default)

1: Enabled

0

Latch Address Mode Enabled. When set to 1, enables three phases of addresses to be latched on the data

pins. Reset value of this bit is set by the XCNF2-0 strap inputs. See Section 1.5.11 for the deﬁnition of this

setting.

0: Disabled

1: Enabled

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7.0 X-Bus Extension (Continued)

7.4.3

X-Bus Select 0 Configuration Register (XZCNF0)

This register affects the mapping of modules associated with Chip Select 0, XCS0.

Location:

Type:

Offset 01h

R/W

Bit

7

6

5

4

3

2

1

0

Indirect

XRDY

Enable

Wait States Memory

Name

Reset

Select 0 Mapping

Strap

Enable

Cycle

Enable

Strap

1

0

Bit

Description

7

XRDY Enable. Enables the use of XRDY input for devices mapped to XCS0. Reset value of this bit is deﬁned

by the XCNF2-0 strap inputs.

0: Disabled (default for all XCNF2-0 values, except 010 or 110)

1: Enabled (default if XCNF2-0 is set to 010 or 110)

6

5

Wait States Enable

0: Wait states disabled

1: 8 clock cycles of wait enabled (default)

Indirect Memory Cycle Enable. Enable indirect memory access mechanism to generate memory transaction

on XCS0.

0: Disabled (default)

1: Enabled

4-0 Select 0 Mapping

UDIZ = User-Deﬁned I/O Zone

-

= XCS0 does not respond to this zone decode

+

= XCS0 responds to this zone decode and is inﬂuenced by its setting

Bits

Function

4 3 2 1 0 KBC PM RTC TST UDIZ BIOS MEM

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

0 0 1 1 0

0 0 1 1 1

0 1 0 0 0

0 1 0 0 1

0 1 0 1 0

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1

1 0 0 0 0

1 0 0 0 1

1 0 0 1 0

1 0 0 1 1

1 0 1 0 0

1 0 1 0 1

1 0 1 1 0

1 0 1 1 1

Others

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

- (default if XCNF2-0 No BIOS mode is set)

- (default if XCNF2-0 selects any of the BIOS modes)

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

Reserved

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7.0 X-Bus Extension (Continued)

7.4.4

X-Bus Select 1 Configuration Register (XZCNF1)

This register affects the mapping of modules associated with Chip Select 1, XCS1.

Location:

Type:

Offset 02h

R/W

Bit

7

6

5

4

3

0

2

1

0

Indirect

XRDY

Enable

Wait States Memory

Enable

Name

Reset

Select 1 Mapping

Cycle

Enable

0

1

0

Bit

Description

7

XRDY Enable. Enables the use of XRDY input for devices mapped to XCS1.

0: Disabled (default)

1: Enabled

6

5

Wait States Enable

0: Wait states disabled

1: 8 clock cycles of wait enabled (default)

Indirect Memory Cycle Enable. Enable indirect memory access mechanism to generate memory transaction

on XCS1.

0: Disabled (default)

1: Enabled

4-0 Select 1 Mapping

UDIZ = User-Deﬁned I/O Zone

-

= XCS1 does not respond to this zone decode

+

= XCS1 responds to this zone decode and is inﬂuenced by its setting

Bits

Function

4 3 2 1 0 KBC PM RTC TST UDIZ BIOS MEM

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

0 0 1 1 0

0 0 1 1 1

0 1 0 0 0

0 1 0 0 1

0 1 0 1 0

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1

1 0 0 0 0

1 0 0 0 1

1 0 0 1 0

1 0 0 1 1

1 0 1 0 0

1 0 1 0 1

1 0 1 1 0

1 0 1 1 1

Others

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

- (default)

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

Reserved

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7.0 X-Bus Extension (Continued)

7.4.5

X-Bus PIRQx Input Registers (XIRQCA to XIRQCD)

This set of four registers defines the mapping of the four PIRQ signals. Each registers is associated with one of the four

PIRQ inputs, as follows:

Location:

Type:

Offset 04h (XIRQCA)

Offset 05h (XIRQCB)

Offset 06h (XIRQCC)

Offset 07h (XIRQCD)

R/W

Bit

7

6

5

0

4

0

3

2

1

0

PIRQ

Polarity

Inversion

PIRQ

Enable

PIRQ

Polarity

PWUREQ

Enable

Name

Reset

Reserved

0

Bit

Description

7-4 Reserved

3

PIRQ Polarity Inversion. This bit controls the polarity of the IRQ signal sent through the IRQ Serializer (see

Table 32). This bit is reset to ’0’.

2

PIRQ Enable. When this bit is set, it enables the interrupt. Ignored when the IRQ is mapped to zero (see

Section 2.2.3).

0: Disabled (default).

1: Enabled.

1

0

PIRQ Polarity. This bit speciﬁes the active level of the incoming IRQ signal.

0: Active low (default).

1: Active high.

Power-Up Request Enable. An IRQ event is routed to the PWUREQ output.

0: Disabled (default).

1: Enabled.

Table 32. IRQ Polarity Control

PIRQ Polarity

Serial IRQ Polarity

Inversion

0

1

0

1

0

1

PIRQx

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7.0 X-Bus Extension (Continued)

Bit

1

2

3

0

PIRQ

Polarity

Inversion

Name

PWUREQ

Enable

PIRQ

Polarity Enable

0

1

IRQ

Serializer

0

1

PIRQx

PWUREQ

Figure 28. Functional Illustration of X-Bus PIRQx Input Registers

7.4.6

X-Bus Indirect Memory Address Register 0 (XIMA0)

This register describes the addresses 7-0 for read or write transaction to the memory.

Location:

Type:

Offset 08h

R/W

Bit

7

6

0

5

0

4

3

2

0

1

0

Name

Reset

X-Bus Indirect Memory Address 7-0

0

Bit

Description

7-0 X-Bus Indirect Memory Address 7-0

7.4.7

X-Bus Indirect Memory Address Register 1 (XIMA1)

This register describes the addresses 15-8 for read or write transaction to the memory.

Location:

Type:

Offset 09h

R/W

Bit

7

6

0

5

4

3

2

1

0

Name

Reset

X-Bus Indirect Memory Address 15-8

0

Bit

Description

7-0 X-Bus Indirect Memory Address 15-8

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7.0 X-Bus Extension (Continued)

7.4.8

X-Bus Indirect Memory Address Register 2 (XIMA2)

This register describes the addresses 23-16 for read or write transaction to the memory.

Location:

Type:

Offset 0Ah

R/W

Bit

7

6

0

5

4

3

2

1

0

Name

Reset

X-Bus Indirect Memory Address 23-16

0

Bit

Description

7-0 X-Bus Indirect Memory Address 23-16

7.4.9

X-Bus Indirect Memory Address Register 3 (XIMA3)

This register describes the addresses 31-24 for read or write transaction to the memory.

Location:

Type:

Offset 0Bh

R/W

Bit

7

6

0

5

4

3

2

1

0

Name

Reset

X-Bus Indirect Memory Address 31-24

0

Bit

Description

7-0 X-Bus Indirect Memory Address 31-24

7.4.10 X-Bus Indirect Memory Data Register (XIMD)

This register describes data bits 7-0 for read or write transaction to the memory.

Location:

Type:

Offset 0Ch

R/W

Bit

7

6

0

5

0

4

3

2

0

1

0

Name

Reset

X-Bus Indirect Memory Data 7-0

0

Bit

Description

7-0 X-Bus Indirect Memory Data 7-0

7.5 USAGE HINTS

1. To use the PC8739x with the National Semiconductor PC87570 Keyboard and Power Management Controller, connect

the X-Bus as follows:

PC8739x

Signals

PC87570

Signals

XRD

HMEMRD

HMEMWR

HIOR

XWR

XIORD

XIOWR

XD7-0

HIOW

HD7-0

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7.0 X-Bus Extension (Continued)

XA3-0

HA3-0

XD7-0

HA11-4

XA18-12

XSTB0

XRDY

HA18-12

FXASTB

HIOCHRDY

PIRQA-D

GND

IRQ11, IRQ8, IRQ12, and IRQ1 respectively

HMEMCS

If any of the functions multiplexed on XA18-12 (Game Port or Serial Port 2) are needed, use an external latch for these

signals.

Use the XRDY signal that is enabled upon reset. Either of the XIORD and XIOWR signals may be used. Set proper sys-

tem configuration before accessing a PC87570 or any I/O device with separate read and write signals for I/O and mem-

ory transactions.

2. Bear in mind the following system design hints for asynchronous X-Bus use:

●

The chip select signal should be used as a qualiﬁer with the address when partial address decoding is in use for mul-

tiple device access control.

●

In read cycles, the system may drive the data until the read signal XRD is de-asserted to guarantee the proper

PC8739x sampling.

●

In write cycles, use either the falling or rising edge of the write control signal (XWR) to latch the data in the device.

3. Address multiplexing on XDT7-0 and the XSTB2-0 is designed for glueless interface with off-chip latch components. See

the example using 74HCT373 latches in Figure 29.

XDT7-0

XSTB2

D7-0

Latch

A27-20

(74HCT373)

PC8739

Latch

A19-12

(74HCT373)

XSTB1

Latch

A11-4

A3-0

(74HCT373)

XSTB0

XA3-0

Figure 29. Latched Mode X-Bus Transactions External Logic

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119

7.0 X-Bus Extension (Continued)

7.6 X-BUS EXTENSION BITMAP

Register

Bits

Offset

Mnemonic

7

6

5

4

3

2

1

0

R/W

Extended

Mode

Latch

Address

Mode

00h

XBCNF

Reserved

Enable

XRDY

Enable

WaitStates

Enable

01h

XZCNF0

Reserved

Select 0 Mapping

Select 1 Mapping

XRDY

Enable

WaitStates

Enable

02h

03h

XZCNF1

Reserved

PIRQ

Polarity

Inversion

PIRQ

Enable

PIRQ

Polarity

PWUREQ

Enable

04h

05h

06h

07h

XIRQCA

XIRQCB

XIRQCC

XIRQCD

Reserved

PIRQ

Polarity

Inversion

PIRQ

Enable

PIRQ

Polarity

PWUREQ

Enable

Reserved

PIRQ

Polarity

Inversion

PIRQ

Enable

PIRQ

Polarity

PWUREQ

Enable

PIRQ

Polarity

Inversion

PIRQ

Enable

PIRQ

Polarity

PWUREQ

Enable

XIMA0

XIMA1

XIMA2

XIMA3

XIMD

08h

09h

0Ah

0Bh

0Ch

X-Bus Indirect Memory Address 7-0

X-Bus Indirect Memory Address 15-8

X-Bus Indirect Memory Address 23-16

X-Bus Indirect Memory Address 31-24

X-Bus Indirect Memory Data 7-0

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8.0 Legacy Functional Blocks

This chapter briefly describes the following blocks that provide legacy device functions:

●

Floppy Disk Controller (FDC)

●

Parallel Port

●

Serial Port 1 (SP1), UART Functionality for both Serial Port 1 and Serial Port 2

●

Serial Port 2 (SP2), Infrared Functionality

The description of each Legacy block includes the sections listed below. For details on the general implementation of each

legacy block, see the SuperI/O Legacy Functional Blocks datasheet.

●

General Description

●

Register Map table(s)

●

Bitmap table(s).

The register maps in this chapter use the following abbreviations for Type:

●

R/W = Read/Write

●

R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different

register.

●

W = Write

●

RO = Read Only

●

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

8.1 FLOPPY DISK CONTROLLER (FDC)

8.1.1

General Description

The generic FDC is a standard FDC with a digital data separator, and is DP8473 and N82077 software compatible.

The FDC is implemented in this device as follows:

●

FM and MFM modes are supported. To select either mode, set bit 6 of the ﬁrst command byte when writing to/read-

ing from a diskette, where:

0 = FM mode

1 = MFM mode

●

Automatic media sense is supported by MSEN1-0 pins only on FDC signals routed to the PPM functional block (on

the Parallel Port).

●

DRATE1 is not supported.

●

A logic 1 is returned for all ﬂoating (TRI-STATE) FDC register bits upon LPC I/O read cycles.

8.1.2

FDC Register Map

Offset

Mnemonic

Register Name

Status A

Type

00h

01h

02h

03h

SRA

SRB

DOR

TDR

MSR

DSR

FIFO

RO

R/W

R

Status B

Digital Output

Tape Drive

Main Status

Data Rate Select

Data (FIFO)

Reserved

04h

W

05h

06h

R/W

DIR

Digital Input

Conﬁguration Control

R

07h

CCR

W

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8.0 Legacy Functional Blocks (Continued)

8.1.3

FDC Bitmap Summary

The FDC supports two system operation modes: PC-AT mode and PS/2 mode (MicroChannel systems). Unless specifically

indicated otherwise, all fields in all registers are valid in both drive modes.

Register

Bits

Offset Mnemonic

7

6

5

4

3

2

1

0

IRQ

Pending

Head Se-

lect

Head

Direction

SRA¹

00h

Reserved

Step

TRK0

INDEX

WP

Drive

Select 0

Status

SRB¹

01h

Reserved

WDATA

RDATA

WGATE

MTR1

MTR0

Motor

Enable 3

Motor

Enable 2

Motor

Enable 1

Motor

Enable 0

Reset

Controller

02h

03h

DOR

TDR

DMAEN

Drive Select

Reserved

Tape Drive Select 1,0

Logical Drive

Exchange

TDR²

Reserved

Drive ID Information

Command

Data I/O

Direction Execution

Non-DMA

in

Drive 3

Busy

Drive 2

Busy

Drive 1

Busy

Drive 0

Busy

MSR

DSR

RQM

Progress

04h

Data Transfer Rate

Select

Software

Reset

Low Power Reserved

Precompensation Delay Select

05h

07h

FIFO

DIR³

Data Bits

Reserved

DSKCHG

High

Density

DIR¹

CCR

Reserved

DRATE 1,0 Status

DRATE1,0

1. Applicable only in PS/2 Mode

2. Applicable only in Enhanced TDR Mode

3. Applicable only in PC-AT Compatible Mode

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122

8.0 Legacy Functional Blocks (Continued)

8.2 PARALLEL PORT

8.2.1

General Description

The Parallel Port supports all IEEE1284 standard communication modes: Compatibility (known also as Standard or SPP),

Bidirectional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ECP (with an optional Extended ECP mode).

8.2.2

Parallel Port Register Map

The Parallel Port functional block register maps are grouped according to first and second level offsets. EPP and second

level offset registers are available only when base address is 8-byte aligned.

Table 33. Parallel Port Register Map for First Level Offset

First Level

Offset

Modes (ECR Bits)

7 6 5

Mnemonic

Register Name

Type

0 0 0

0 0 1

000h

DATAR PP Data

R/W

000h

001h

002h

003h

004h

005h

006h

007h

400h

401h

402h

403h

404h

405h

AFIFO ECP Address FIFO

0 1 1

All Modes

1 0 0

W

DSR

DCR

Status

RO

Control

R/W

W

ADDR EPP Address

DATA0 EPP Data Port 0

DATA1 EPP Data Port 1

DATA2 EPP Data Port 2

DATA3 EPP Data Port 3

CFIFO PP Data FIFO

DFIFO ECP Data FIFO

TFIFO Test FIFO

1 0 0

0 1 0

0 1 1

R/W

RO

1 1 0

CNFGA Conﬁguration A

CNFGB Conﬁguration B

1 1 1

RO

ECR

EIR

Extended Control

Extended Index

All Modes

R/W

EDR

EAR

Extended Data

Extended Auxiliary Status

Table 34. Parallel Port Register Map for Second Level Offset

Second Level

Register Name Type

Offset

00h

02h

04h

05h

Control0

Control2

R/W

Control4

PP Confg0

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123

8.0 Legacy Functional Blocks (Continued)

8.2.3

Parallel Port Bitmap Summary

The Parallel Port functional block bitmaps are grouped according to first and second level offsets.

Table 35. Parallel Port Bitmap Summary for First Level Offset

Register

Bits

Offset Mnemonic

7

6

5

4

3

2

1

0

DATAR

000h

Data Bits

AFIFO

Address Bits

Printer

Status

ACK

Status

SLCT

Status

ERR

Status

EPP Time-

out Status

001h

002h

DSR

DCR

PE Status

Reserved

Printer

Automatic

Data

Strobe

Control

Direction

Control

Interrupt

Enable

PP Input

Control

Reserved

Initialization Line Feed

Control

003h

004h

005h

006h

007h

400h

ADDR

DATA0

DATA1

DATA2

DATA3

CFIFO

DFIFO

TFIFO

EPP Device or Register Selection Address Bits

EPP Device or R/W Data

Data Bits

Bit 7 of PP

Confg0

400h

401h

CNFGA

CNFGB

Reserved

Interrupt

Request

Value

Reserved

Interrupt Select

Reserved

DMA Channel Select

ECP

Interrupt

Mask

ECP

Interrupt

Service

ECP DMA

Enable

FIFO

FIFO Full

402h

ECR

ECP Mode Control

Empty

403h

404h

405h

EIR

EDR

EAR

Reserved

Second Level Offset

Data Bits

Reserved

FIFO Tag

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124

8.0 Legacy Functional Blocks (Continued)

Table 36. Parallel Port Bitmap Summary for Second Level Offset

Bits

Register

Second

Level Mnemonic

Offset

7

6

5

4

3

2

1

0

EPP Time-

out

Interrupt

Mask

DCR

00h

Control0

Control2

Reserved

Register Freeze Bit

Live

Reserved

Channel

Address

Enable

Revision

Reserved 1.7 or 1.9

Select

SPP Com-

patibility

02h

04h

Reserved

Control4 Reserved

PP DMA Request Inactive Time

Reserved

PP DMA Request Active Time

PE

Demand

DMA

Enable

PP

Confg0

Bit 3 of

CNFGA

Internal

Pull-up or

Pull-down

ECP DMA Channel

Number

05h

ECP IRQ Channel Number

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125

8.0 Legacy Functional Blocks (Continued)

8.3 UART FUNCTIONALITY (SP1 AND SP2)

8.3.1

General Description

Both SP1 and SP2 provide UART functionality. The generic SP1 and SP2 support serial data communication with remote

peripheral device or modem using a wired interface. The functional blocks can function as a standard 16450, 16550, or as

an Extended UART.

8.3.2

UART Mode Register Bank Overview

Four register banks, each containing eight registers, control UART operation. All registers use the same 8-byte address

space to indicate offsets 00h through 07h. The BSR register selects the active bank and is common to all banks. See Figure

30.

BANK 3

BANK 2

BANK 1

Common

Register

Throughout

All Banks

BANK 0

Offset 07h

Offset 06h

Offset 05h

Offset 04h

LCR/BSR

Offset 02h

Offset 01h

Offset 00h

16550 Banks

Figure 30. UART Mode Register Bank Architecture

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126

8.0 Legacy Functional Blocks (Continued)

8.3.3

SP1 and SP2 Register Maps for UART Functionality

Table 37. Bank 0 Register Map

Offset

Mnemonic

Register Name

Receiver Data Port

Type

00h

01h

RXD

TXD

IER

RO

W

Transmitter Data Port

Interrupt Enable

R/W

RO

W

EIR

Event Identiﬁcation (Read Cycles)

FIFO Control (Write Cycles)

Line Control

02h

03h

FCR

LCR¹

R/W

BSR¹

MCR

LSR

Bank Select

04h

05h

06h

07h

Modem/Mode Control

Link Status

R/W

RO

MSR

Modem Status

RO

SPR/ASCR Scratchpad/Auxiliary Status and Control

R/W

1. When bit 7 of this Register is set to 1, bits 6-0 of BSR select the bank, as

shown in Table 38.

Table 38. Bank Selection Encoding

BSR Bits

Bank

Functionality

Selected

7

6

5

4

3

2

1

0

1

x

0

1

x

1

x

0

1

x

0

1

0

x

0

1

0

1

0

1

x

1

x

0

x

1

0

1

2

3

4

5

6

7

UART + IR

(SP1 + SP2)

IR Only

(SP2)

Table 39. Bank 1 Register Map

Register Name

Offset

Mnemonic

Type

00h

01h

LBGD(L) Legacy Baud Generator Divisor Port (Low Byte)

LBGD(H) Legacy Baud Generator Divisor Port (High Byte)

Reserved

R/W

02h

03h

LCR/BSR Line Control/Bank Select

Reserved

R/W

04h - 07h

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127

8.0 Legacy Functional Blocks (Continued)

Table 40. Bank 2 Register Map

Register Name

Offset

Mnemonic

Type

00h

01h

02h

03h

04h

05h

06h

07h

BGD(L) Baud Generator Divisor Port (Low Byte)

BGD(H) Baud Generator Divisor Port (High Byte)

R/W

EXCR1

Extended Control1

LCR/BSR Line Control/Bank Select

EXCR2

Extended Control 2

Reserved

TXFLV

RXFLV

TX_FIFO Level

RX_FIFO Level

R/W

Table 41. Bank 3 Register Map

Offset

Mnemonic

Register Name

Type

00h

01h

MRID

Module Revision ID

RO

SH_LCR Shadow of LCR (Read Only)

SH_FCR Shadow of FIFO Control (Read Only)

LCR/BSR Line Control/Bank Select

Reserved

02h

RO

03h

R/W

04h-07h

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128

8.0 Legacy Functional Blocks (Continued)

8.3.4

SP1 and SP2 Bitmap Summary for UART Functionality

Table 42. Bank 0 Bitmap

Bits

Register

Offset Mnemonic

7

6

5

4

3

2

1

0

RXD

Receiver Data Bits

Transmitter Data Bits

MS_IE

00h

TXD

IER¹

Reserved

LS_IE

IPR1

TXLDL_IE RXHDL_IE

01h

Reserved³/

MS_IE

IER²

Reserved

TXEMP_IE

DMA_IE⁴

EIR¹

FEN1

FEN0

Reserved

RXFT

IPR0

IPF

3

Reserved /

LS_EV or

TXHLT_EV

EIR²

02h

Reserved

TXEMP_EV

MS_EV

TXLDL_EV RXHDL_EV

4

DMA_EV

FCR

RXFTH1

BKSE

RXFTH0

SBRK

TXFTH1

STKP

TXFTH0

EPS

Reserved

PEN

TXSR

STB

RXSR

WLS1

FIFO_EN

WLS0

LCR⁵

03h

BSR⁵

BKSE

Bank Select

ISEN or

DCDLP

MCR¹

04h

Reserved

LOOP

RILP

RTS

DTR

MCR²

Reserved

TX_DFR

FE

Reserved

PE

RTS

OE

DTR

RXDA

DCTS

05h

06h

LSR

ER_INF

DCD

TXEMP

RI

TXRDY

DSR

BRK

CTS

MSR

DDCD

TERI

DDSR

SPR¹

Scratch Data

07h

ASCR

RXACT

RXWDG

S_OET

TXUR⁴

Reserved

Reserved RXF_TOUT

2

4

1. Non-Extended Mode

2. Extended Mode

3. In SP1 only

4. In SP2 only

5. When bit 7 of this register is set to 1, bits 6-0 of BSR select the bank, as shown in Table 38.

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129

8.0 Legacy Functional Blocks (Continued)

Table 43. Bank 1 Bitmap

Bits

Register

Offset Mnemonic

7

6

5

4

3

2

1

0

00h

01h

02h

03h

LBGD(L)

LBGD(H)

Legacy Baud Generator Divisor (Least Signiﬁcant Bits)

Legacy Baud Generator Divisor (Most Signiﬁcant Bits)

Reserved

LCR/BSR

Same as Bank 0

04h-

07h

Reserved

Table 44. Bank 2 Bitmap

Bits

Register

Offset Mnemonic

7

6

5

4

3

2

1

0

00h

01h

02h

03h

04h

BGD(L)

BGD(H)

EXCR1

Baud Generator Divisor Low (Least Signiﬁcant Bits)

Baud Generator Divisor High (Most Signiﬁcant Bits)

BTEST

LOCK

Reserved

ETDLBK

LOOP

Reserved

EXT_SL

LCR/BSR

EXCR2

Same as Bank 0

PRESL0

PRESL1

Reserved

05h Reserved

06h

07h

TXFLV

RXFLV

Reserved

TFL4

RFL4

TFL3

RFL3

TFL2

RFL2

TFL1

RFL1

TFL0

RFL0

Table 45. Bank 3 Bitmap

Bits

Register

Offset Mnemonic

7

6

5

4

3

2

1

0

00h

01h

02h

03h

MRID

Module ID (MID 7-4)

Revision ID(RID 3-0)

SH_LCR

SH_FCR

LCR/BSR

BKSE

SBRK

STKP

EPS

PEN

STB

WLS1

RXSR

WLS0

RXFTH1

RXFTH0

TXFHT1

TXFTH0

Reserved

TXSR

FIFO_EN

Same as Bank 0

Reserved

04h-

07h

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8.0 Legacy Functional Blocks (Continued)

8.4 IR FUNCTIONALITY (SP2)

8.4.1

General Description

This section describes the IR support registers of Serial Port 2 (SP2). The UART support registers for both SP1 and SP2

are described in Section 8.3.

The IR functional block provides advanced, versatile serial communications features with IR capabilities.

SP2 supports also two DMA channels; the functional block can use either one or both of them. One channel is required for

IR-based applications, since IR communication works in half duplex fashion. Two channels would normally be needed to

handle high-speed full duplex UART based applications.

8.4.2

IR Mode Register Bank Overview

Eight register banks, each containing eight registers, control SP2 operation. Banks 0-3 are used to control both UART and

IR modes of operation; banks 4-7 are used to control and configure the IR modes of operation only. All registers use the

same 8-byte address space to indicate offsets 00h through 07h. The BSR register selects the active bank and is common

to all banks. See Figure 31.

BANK 7

BANK 6

Common

Register

Throughout

BANK 5

BANK 4

BANK 3

BANK 2

BANK 1

BANK 0

All Banks

Offset 07h

Offset 06h

Offset 05h

Offset 04h

LCR/BSR

IR Special Banks

(Banks 4-7)

Offset 02h

Offset 01h

Offset 00h

Figure 31. SP2 Register Bank Architecture

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131

8.0 Legacy Functional Blocks (Continued)

8.4.3

SP2 Register Map for IR Functionality

.

Table 46. Bank 4 Register Map

Offset

Mnemonic

Register Name

Type

00h-01h

02h

Reserved

IRCR1

IR Control 1

R/W

03h

LCR/BSR Line Control/Bank Select

Reserved

04h - 07h

Table 47. Bank 5 Register Map

Offset

Mnemonic

Register Name

Type

00h-02h

03h

Reserved

LCR/BSR Line Control/Bank Select

R/W

04h

IRCR2

IR Control 2

05h - 07h Reserved

Table 48. Bank 6 Register Map

Register Name

Offset

Mnemonic

Type

00h

01h

IRCR3

IR Control 3

Reserved

R/W

02h

SIR_PW SIR Pulse Width Control (≤ 115 Kbps)

LCR/BSR Line Control/Bank Select

Reserved

R/W

03h

04h-07h

Table 49. Bank 7 Register Map

Offset

Mnemonic

Register Name

Type

00h

01h

02h

03h

04h

05h

06h

07h

IRRXDC IR Receiver Demodulator Control

IRTXMC IR Transmitter Modulator Control

RCCFG CEIR Conﬁguration

RO

LCR/BSR Line Control/Bank Select

IRCFG1 IR Interface Conﬁguration 1

Reserved

R/W

IRCFG3 IR Interface Conﬁguration 3

IRCFG4 IR Interface Conﬁguration 4

R/W

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8.0 Legacy Functional Blocks (Continued)

8.4.4

SP2 Bitmap Summary for IR Functionality

Table 50. Bank 4 Bitmap

Bits

Register

Offset Mnemonic

7

6

5

4

3

2

1

0

00h-

01h

Reserved

02h

03h

EIR

Reserved

IR_SL1

IR_SL0

Reserved

LCR/BSR

Same as Bank 0

Reserved

04h-

07h

Table 51. Bank 5 Bitmap

Bits

Register

Offset Mnemonic

6

5

4

3

2

1

0

00h-

02h

Reserved

03h

04h

LCR/BSR

IRCR2

Same as Bank 0

AUX_IRRX Reserved

Reserved

IRMSSL IR_FDPLX

05h-

07h

Table 52. Bank 6 Bitmap

Bits

Register

Offset Mnemonic

6

5

4

3

2

1

0

00h

01h

02h

03h

IRCR3

SHDM_DS SHMD_DS

Reserved

SIR_PW

Reserved

SPW (3-0)

LCR/BSR

Same as Bank 0

Reserved

04h-

07h

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8.0 Legacy Functional Blocks (Continued)

Table 53. Bank 7 Bitmap

Bits

Register

Offset Mnemonic

7

6

5

4

3

2

1

0

IRRXDC

00h

01h

02h

03h

04h

05h

06h

07h

DBW (2-0)

MCPW (2-0)

T_OV

DFR (4-0)

MCFR (4-0)

IRTXMC

RCCFG

RCDM_DS

RC_MMD0

R_LEN

RXHSC

SIRC (2-0)

RCH (2-0)

Reserved

TXHSC RC_MND1

LCR/BSR

Same as Bank 0

IRCFG1 STRV_MS

IRID3

IRIC (2-0)

Reserved

RXINV

IRCFG3

IRCFG4

Reserved

AMCFG

Reserved

IRSL21_DS

RCLC (2-0)

Reserved

Reserved IRSL0_DS

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134

9.0 Device Characteristics

9.1 GENERAL DC ELECTRICAL CHARACTERISTICS

9.1.1

Recommended Operating Conditions

Symbol

V_DD

Parameter

Min

3.0

0

Typ

Max Unit

3.6

V

Supply Voltage

3.3

T_A

+70

°C

Operating Temperature

9.1.2

Absolute Maximum Ratings

Absolute maximum ratings are values beyond which damage to the device may occur. Unless otherwise specified, all volt-

ages are relative to ground.

Symbol

V_DD

V_I

Parameter

Conditions

Min

−0.5

−65

Max

+6.5

Unit

V

Supply Voltage

Input Voltage

Output Voltage

V_DD+ 0.5

+165

V

V_O

V

T_STG

P_D

°C

W

°C

Storage Temperature

1

Power Dissipation

T_L

Lead Temperature Soldering (10 s)

+260

C_ZAP= 100 pF

R_ZAP= 1.5 KΩ¹

ESD Tolerance

2000

V

1. Value based on test complying with RAI-5-048-RA human body model ESD testing.

9.1.3

Capacitance

Symbol

C_IN

Parameter

Input Pin Capacitance

Min

Typ

5

Max Unit

7

12

8

pF

C_IN1

C_IO

5

8

Clock Input Capacitance

I/O Pin Capacitance

10

6

C_O

Output Pin Capacitance

T_A= 25°C, f = 1 MHz

Power Consumption under Recommended Operating Conditions

9.1.4

Symbol

Parameter

Conditions

Typ

Max

Unit

V_IL= 0.5 V, V_IH= 2.4 V

No Load

I_CC

V_DDAverage Main Supply Current

32

50

mA

V_DDQuiescent Main Supply Current V_IL= V_SS, V_IH= V_DD

in Low Power Mode No Load

I_CCLP

1.3

1.7

mA

9.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES

The following tables summarize the DC characteristics of all device pins described in the Signal/Pin Connection and De-

scription chapter. The characteristics describe the general I/O buffer types defined in Table 1. For exceptions, refer to Sec-

tion 9.2.9. The DC characteristics of the system interface meet the PCI2.1 3.3V DC signaling.

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9.0 Device Characteristics (Continued)

9.2.1

Input, CMOS Compatible

Symbol: IN_C

Symbol

V_IH

Parameter

Input High Voltage

Conditions

Min

Max

Unit

V

5.5¹

0.7 V_DD

V_IL

−0.5

1

0.3 V_DD

V

Input Low Voltage

V_IN= V_DD

V_IN= V_SS

50

nA

I_IL

Input Leakage Current

−50

1. Not tested. Guaranteed by design.

9.2.2

Input, PCI 3.3V

Symbol: IN_PCI

Symbol

V_IH

Parameter

Input High Voltage

Conditions

Min

Max

Unit

V

0.5V_DDV_DD+ 0.5

V_IL

-0.5

0.3V_DD

V

Input Low Voltage

1

0 < V_in< V_DD

±10

µA

Input Leakage Current

l_IL

1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with TRI-STATE outputs.

9.2.3

Input, Strap Pin

Symbol: IN_STRP

Symbol

Parameter

Input High Voltage

Conditions

Min

Max

5.5¹

Unit

1

V_IH

V

0.6V_DD

1

-0.5¹

16.5

0.5V_DD

V_IL

V

Input Low Voltage

R_IH

R_IL

During Reset: V_IN=0.6V_DD

During Reset: V_IN=0.4V_DD

KΩ

Input High Resistance

Input Low Resistance

20

1. Not tested. Guaranteed by design.

9.2.4

Input, TTL Compatible

Symbol: IN_T

Symbol

V_IH

Parameter

Input High Voltage

Conditions

Min

Max

Unit

V

5.5¹

0.8

2.0

−0.5¹

V_IL

V

Input Low Voltage

V_IN= V_DD

V_IN= V_SS

10

µA

I_IL

Input Leakage Current

−10

1. Not tested. Guaranteed by design.

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136

9.0 Device Characteristics (Continued)

9.2.5

Input, TTL Compatible with Schmitt Trigger

Symbol: IN_TS

Symbol

V_IH

Parameter

Input High Voltage

Conditions

Min

Max

Unit

V

5.5¹

0.8

2.0

1

V_IL

V

Input Low Voltage

Input Leakage Current

Input Hysteresis

−0.5

V_IN= V_DD

V_IN= V_SS

10

µA

mV

I_IL

−10

V_H

250

1. Not tested. Guaranteed by design.

9.2.6

Output, PCI 3.3V

Symbol: O_PCI

Symbol

V_OH

Parameter

Conditions

l_out= -500 µA

l_out=1500 µA

Min

Max

Unit

0.9V_DD

V

Output High Voltage

Output Low Voltage

V_OL

0.1 V_DD

9.2.7

Symbol: O_p/n

Output, Totem-Pole buffer that is capable of sourcing p mA and sinking n mA

Output, Totem-Pole Buffer

Symbol

V_OH

Parameter

Conditions

I_OH= −p mA

I_OL= n mA

Min

Max

Unit

V

2.4

Output High Voltage

Output Low Voltage

V_OL

0.4

V

9.2.8

Symbol: OD_n

Output, Open-Drain output buffer, capable of sinking n mA. Output from these signals is open-drain and cannot be forced high.

Output, Open-Drain Buffer

Symbol

Parameter

Output Low Voltage

Conditions

Min

Max

Unit

V_OL

I_OL= n mA

0.4

V

9.2.9

Exceptions

1. All pins are back-drive protected, except for the output pins with PCI Buffer Type.

2. The following pins have a PU₂₂₀internal pull-up resistor and therefore have input leakage current to V_DD: ACK,

AFD_DSTRB, ERR, INIT, PE, SLIN_ASTRB, STB_WRITE.

3. The following pins have a PU₂₅internal pull-up resistor and therefore have input leakage current to V_DD: GPIO40-47,

GPIO30-37, GPIO20-27, GPIO10-17, GPIO00-07.

4. The following pins have a PD₁₂₀internal pull-down resistor and therefore have input leakage current to GND:

BUSY_WAIT, PE, SLCT.

5. Output from SLCT, BUSY_WAIT (and PE if bit 2 of PP Confg0 Register is 0) is open-drain in all SPP modes, except in

SPP Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1.

Otherwise, output from these signals is level 2. External 4.7 KΩ pull-up resistors should be used.

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137

9.0 Device Characteristics (Continued)

6. Output from ACK, ERR (and PE if bit 2 of PP Confg0 Register is set to 1) is open-drain in all SPP modes, except in SPP

Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is set to 1.

Otherwise, output from these signals is level 2. External 4.7 KΩ pull-up resistors should be used.

7. Output from STB, AFD, INIT, SLIN is open-drain in all SPP modes, except in SPP Compatible mode when the setup

mode is ECP-based (FIFO). Otherwise, output from these signals is level 2. External 4.7 KΩ pull-up resistors should be

used.

8. I_OHis valid for a GPIO pin only when it is not configured as open-drain.

9.3 INTERNAL RESISTORS

9.3.1

Pull-Up Resistor

Symbol: PU_nn

.

Symbol

Parameter

Pull-up equivalent resistance

Conditions

Min Typical Max

Unit

R_PU

V_PIN= V_DD= 3.3V

nn-30%

nn nn+30%

KΩ

9.3.2

Pull-Down Resistor

Symbol: PD_nn

.

Symbol

Parameter

Pull-down equivalent resistance

Conditions

Min Typical Max

Unit

R_PD

V_PIN= 0V, V_DD= 3.3V nn-30%

nn nn+30%

KΩ

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138

9.0 Device Characteristics (Continued)

9.4 AC ELECTRICAL CHARACTERISTICS

9.4.1

AC Test Conditions

Load Circuit (Notes 1, 2, 3)

AC Testing Input, Output Waveform

V_DD

S₁

2.4

2.0

0.8

2.0

0.8

0.1 µf

Test Points

0.4

R_L

Device

Input

Output

Under

Test

C_L

Figure 32. AC Test Conditions, T_A= 0 °C to 70 °C, V_DD= 3.3 V ±10%

Notes:

1. C_L= 100 pF for all output pins (except O_PCI);

C_L= 50 pF for O_PCIoutput pins;

These values include both jig and oscilloscope capacitance.

2. S₁= Open for push-pull output pins.

S₁= V_DDfor high impedance to active low and active low to high impedance measurements.

S₁= GND for high impedance to active high and active high to high impedance measurements.

R_L= 1.0KΩ for µP interface pins.

3. For the FDC open-drive interface pins, S₁= V_DDand R_L= 150Ω.

9.4.2

Clock Timing

48 MHz

Symbol

Parameter

Min

Max

Unit

ns

Clock High Pulse Width¹

Clock Low Pulse Width¹

8.4

20

t_CH

t_CL

t_CP

ns

1 2

21.5

ns

Clock Period

1. Not tested. Guaranteed by design.

2. For the 14.31818 MHz clock, required tolerance is 200

ppm (max).

.

t_CP

t_CH

CLKIN

t_CL

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139

9.0 Device Characteristics (Continued)

9.4.3

LCLK and LRESET

Symbol

Parameter

LCLK Cycle Time

Min

Max

Units

1

30

ns

t_CYC

t_HIGH

11

1

ns

LCLK High Time

LCLK Low Time

t_LOW

LCLK Slew Rate²

-

4

V/ns

mV/ns

LRESET Slew Rate³

50

1. The PCI may have any clock frequency between nominal DC and 33

MHz. Device operational parameters at frequencies under 16 MHz

may be guaranteed by design rather than by testing. The clock fre-

quency may be changed at any time during the operation of the sys-

tem as long as the clock edges remain “clean” (monotonic) and the

minimum cycle and high and low times are not violated. The clock

may only be stopped in a low state.

2. Rise and fall times are speciﬁed in terms of the edge rate measured in

V/ns. This slew rate must be met across the minimum peak-to-peak

portion of the clock wavering as shown below.

3. The minimum LRESET slew rate applies only to the rising (de-assertion)

edge of the reset signal, and ensures that system noise cannot ren-

der an otherwise a monotonic signal to appear to bounce in the

switching range.

3.3 V Clock

t_HIGH

t_LOW

0.6 V_DD

0.5 V_DD

0.4 V_DD

0.3 V_DD

0.4 V_DDp-to-p

(minimum)

0.2 V_DD

t_CYC

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140

9.0 Device Characteristics (Continued)

9.4.4

LPC and SERIRQ Signals

Symbol

t_VAL

t_ON

Figure

Output

Input

Description

Output Valid Delay

Float to Active Delay

Active to Float Delay

Input Setup Time

Input Hold Time

Reference Conditions

After RE CLK

Min

Max

Unit

ns

11

2

After RE CLK

Before RE CLK

After RE CLK

ns

t_OFF

t_SU

t_HI

28

ns

7

0

ns

Input

ns

Output

LCLK

t_VAL

t_ON

LPC Signals/

SERIRQ

t_OFF

Input

LCLK

t_SU

t_HI

LPC Signals/

SERIRQ

Input

Valid

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141

9.0 Device Characteristics (Continued)

9.4.5

Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing

Symbol

Parameter

Conditions

Min

Max

Unit

1

t_BTN+ 25

Transmitter

Receiver

ns

t_BTN− 25

t_BT

Single Bit Time in Serial Port and Sharp-IR

t_BTN− 2%

t_BTN+ 2%

t_CWN+ 25

2

Transmitter

Receiver

t_CWN− 25

500

Modulation Signal Pulse Width in Sharp-IR

and Consumer Remote Control

t_CMW

3

t_CPN+ 25

Transmitter

t_CPN− 25

Modulation Signal Period in Sharp-IR and

Consumer Remote Control

t_CMP

4

Receiver

ns

t_MMIN

t_MMAX

(³/₁₆) x t_BTN− 15

(³/₁₆) x t_BTN+ 15

1

Transmitter,

Variable

t_SPW

SIR Signal Pulse Width

Transmitter,

Fixed

1.48

1.78

µs

Receiver

Transmitter

Receiver

1

± 0.87%

± 2.0%

± 2.5%

± 6.5%

SIR Data Rate Tolerance.

% of Nominal Data Rate.

S_DRT

Transmitter

Receiver

SIR Leading Edge Jitter.

% of Nominal Bit Duration.

t_SJT

1. t_BTNis the nominal bit time in Serial Port, Sharp-IR, SIR and Consumer Remote Control modes. It is deter-

mined by the setting of the Baud Generator Divisor registers

2. t_CWNis the nominal pulse width of the modulation signal for Sharp-IR and Consumer Remote Control modes. It

is determined by the MCPW ﬁeld (bits 7-5) of the IRTXMC registerand the TXHSC bit (bit 2) of the

RCCFG register

3. t_CPNis the nominal period of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is

determined by the MCFR ﬁeld (bits 4-0) of the IRTXMC registerand the TXHSC bit (bit 2) of the RCCFG

register.

4. t_MMINand t_MMAXdeﬁne the time range within which the period of the incoming subcarrier signal has to fall in

order for the signal to be accepted by the receiver. These time values are determined by the contents of

the IRRXDC register and the setting of the RXHSC bit (bit 5) of the RCCFG register

t

BT

Serial Port

t

CMP

CMW

Sharp-IR

Consumer Remote Control

t

SPW

SIR

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142

9.0 Device Characteristics (Continued)

9.4.6

Modem Control Timing

Symbol

Parameter

Min

10

Max

Unit

ns

t_L

RI2,1 Low Time

RI2,1 High Time

t_H

10

ns

t_SIM

Delay to Set IRQ from Modem Input

40

ns

CTS, DSR, DCD

t_SIM

INTERRUPT

t_SIM

(Read MSR)

RI

t_L

t_H

9.4.7

FDC Write Data Timing

Parameter

Symbol

t_HDH

Min

Max

Unit

µs

HDSEL Hold from WGATE Inactive¹

100

HDSEL Setup to WGATE Active¹

Write Data Pulse Width

µs

t_HDS

t_WDW

See t_DRP, t_ICPand t_WDWvalues in table below

1. Not tested. Guaranteed by design.

HDSEL

WGATE

t_HDS

t_HDH

t_WDW

WDATA

t_DRPt_ICPt_WDWValues

t_DRP

t_ICP

t_ICPNominal

t_WDW

t_WDWMinimum

Data Rate

1 Mbps

Unit

1

125

208

250

2 x t_ICP

1000

2000

3333

4000

250

375

500

ns

6 x t_CP

500 Kbps

300 Kbps

250 Kbps

6 x t_CP

1

10 x t_CP

12 x t_CP

1. t_CPis the clock period defined in the Clock Timing section of this chapter.

143

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9.0 Device Characteristics (Continued)

9.4.8

FDC Drive Control Timing

Symbol

Parameter

Min

6

Max

Unit

µs

DIR Setup to STEP Active¹

Index Pulse Width

t_DST

t_IW

100

t_STR

8

ns

t_STD

t_STP

t_STR

ms

µs

DIR Hold from STEP Inactive

STEP Active High Pulse Width¹

STEP Rate Time¹

0.5

ms

1. Not tested. Guaranteed by design.

DIR

t_STD

t_DST

STEP

t_STP

t_STR

INDEX

t_IW

9.4.9

FDC Read Data Timing

Symbol

Parameter

Min

Max

Unit

t_RDW

50

ns

Read Data Pulse Width

t_RDW

RDATA

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144

9.0 Device Characteristics (Continued)

9.4.10 Standard Parallel Port Timing

Symbol

Parameter

Conditions

Typ

Max

Unit

These times are system dependent

and are therefore not tested.

500

ns

t_PDH

Port Data Hold

Port Data Setup

Strobe Width

These times are system dependent

and are therefore not tested.

500

ns

t_PDS

t_SW

These times are system dependent

and are therefore not tested.

Typical Data Exchange

BUSY

ACK

t_PDH

t_PDS

PD7-0

t_SW

STB

9.4.11 Enhanced Parallel Port Timing

Symbol

t_WW19a

t_WW19ia

t_WST19a

t_WEST

Parameter

WRITE Active from WAIT Low

WRITE Inactive from WAIT Low

Min

Max EPP 1.7 EPP 1.9 Unit

45

65

✔

ns

DSTRB or ASTRB Active from WAIT Low

DSTRB or ASTRB Active after WRITE Active

PD7-0 Hold after WRITE Inactive

PD7-0 Valid after WRITE Active

2

0

✔

t_WPDH

t_WPDS

15

t_EPDW

80

0

PD7-0 Valid Width

t_EPDH

PD7-0 Hold after DSTRB or ASTRB Inactive

t_WW19a

WRITE

DSTRB

or

ASTRB

t_WST19a

t_WPDH

t_WEST

t_EPDH

t_WST19a

Valid

t_EPDW

PD7-0

WAIT

t_WPDS

t_WW19ia

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145

9.0 Device Characteristics (Continued)

9.4.12 Extended Capabilities Port (ECP) Timing

Forward Mode

Parameter

Data Setup before STB Active

Symbol

t_ECDSF

Min

0

Max

Unit

ns

s

t_ECDHF

t_ECLHF

t_ECHHF

t_ECHLF

t_ECLLF

0

Data Hold after BUSY Inactive

BUSY Active after STB Active

STB Inactive after BUSY Active

BUSY Inactive after STB Active

STB Active after BUSY Inactive

75

0

1

0

35

ms

ns

0

t_ECDHF

PD7-0

AFD

t_ECDSF

t_ECLLF

STB

t_ECHLF

t_ECLHF

BUSY

t_ECHHF

Reverse Mode

Parameter

Symbol

Min

0

Max

Unit

ns

ms

s

t_ECDSR

t_ECDHR

t_ECLHR

t_ECHHR

t_ECHLR

t_ECLLR

Data Setup before ACK Active

Data Hold after AFD Active

AFD Inactive after ACK Active

ACK Inactive after AFD Inactive

AFD Active after ACK Inactive

ACK Active after AFD Active

0

75

0

35

1

0

ns

t_ECDHR

PD7-0

BUSY

t_ECDSR

ACK

AFD

t_ECLLR

t_ECHLR

t_ECHHR

t_ECLHR

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146

9.0 Device Characteristics (Continued)

9.4.13 X-Bus Signals (PC87393 and PC87393F only)

Symbol

t_VAL

t_ON

Figure

Output

Input

Description

Output Valid Delay

Float to Active Delay

Output Hold time

Active to Float Delay

Input Setup Time

Input Hold Time

Reference Conditions

After RE CLK

Min

Max

Unit

ns

20

0

After RE CLK

Before RE CLK

After RE CLK

ns

t_OH

ns

t_OFF

t_SU

30

ns

15

0

ns

t_HI

Input

ns

Output

Internal CLK

(for reference only not available off chip)

t_VAL

t_OH

t_ON

X-Bus Outputs

XA[0:19], XD[0:7],

t_OFF

XRD, XWR, XCS[0:1]

Input

Internal CLK

(for reference only not available off chip)

t_SU

t_HI

XD[0:7]

XRDY

Input

Valid

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147

Physical Dimensions

All dimensions are in millimeters.

Thin Quad Flatpack (TQFP), JEDEC

Order Number PC8739x-VJG

NS Package Number VJG100A

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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and whose

failure to perform, when properly used in accordance

with instructions for use provided in the labeling, can

be reasonably expected to result in a signiﬁcant injury

to the user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

National Semiconductor

Corporation, Americas

Fax: 1-800-737-7018

Email: support@nsc.com

Tel: 1-800-272-9959

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型号：	PC87391-VJG
厂家：	National Semiconductor
描述：	100-Pin LPC SuperI/O Devices for Portable Applications 100引脚LPC SuperI / O设备，用于便携式应用便携式 PC 时钟
文件：	总148页 (文件大小：1605K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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