TMS427409A [NSC]
4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES; 4194304 4位扩展数据输出动态随机存取存储器
| 型号： | TMS427409A |
| 厂家： | 
National Semiconductor |
| 描述： | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
| 文件： | 总37页 (文件大小：518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
DJ/DGA PACKAGES
This data sheet is applicable to all
(TOP VIEW)
TMS41x409As and TMS42x409As symbolized
by Revision “B”, Revision “E”, and subsequent
revisions as described in the device
symbolization section.
V
1
2
3
4
5
6
26
25
24
23
22
21
V
SS
CC
DQ1
DQ2
W
RAS
A11
DQ4
DQ3
CAS
OE
Organization . . . 4194304 × 4
Single Power Supply (5 V or 3.3 V)
Performance Ranges:
†
A9
ACCESS ACCESS ACCESS
TIME TIME TIME
EDO
CYCLE
A10
A0
A1
A2
A3
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
t
t
t
t
RAC
CAC
AA
HPC
9
MAX
50 ns
60 ns
70 ns
50 ns
60 ns
70 ns
MAX
13 ns
15 ns
18 ns
13 ns
15 ns
18 ns
MAX
25 ns
30 ns
35 ns
25 ns
30 ns
35 ns
MIN
10
11
12
13
’41x409A-50
’41x409A-60
’41x409A-70
’42x409A-50
’42x409A-60
’42x409A-70
20 ns
25 ns
30 ns
20 ns
25 ns
30 ns
V
V
CC
SS
Extended-Data-Out (EDO) Operation
CAS-Before-RAS (CBR) Refresh
Low Power Dissipation
PIN NOMENCLATURE
†
A0–A11
Address Inputs
DQ1–DQ4
CAS
Data In/Data Out
Column-Address Strobe
No Internal Connection
Output Enable
3-State Unlatched Output
NC
OE
High-Reliability Plastic 24/26-Lead
300-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package (DJ Suffix) and
24/26-Lead 300-Mil-Wide Surface-Mount
Thin Small-Outline Package (TSOP)
(DGA Suffix)
RAS
Row-Address Strobe
5-V or 3.3-V Supply
Ground
Write Enable
‡
V
V
W
CC
SS
†
‡
A11 is NC for TMS417409A and TMS427409A.
See Available Options Table
Operating Free-Air Temperature Range
0°C to 70°C
AVAILABLE OPTIONS
SELF
description
POWER
SUPPLY
REFRESH
CYCLES
REFRESH,
BATTERY
BACKUP
DEVICE
The TMS41x409A and TMS42x409A series are
16777216-bit dynamic random-access memory
(DRAM) devices organized as 4194304 words of
four bits each.
TMS416409A
TMS417409A
TMS426409A
TMS427409A
5 V
5 V
–
–
–
–
4096 in 64 ms
2048 in 32 ms
4096 in 64 ms
2048 in 32 ms
3.3 V
3.3 V
These devices feature maximum RAS access
times of 50, 60, and 70 ns. All address and data-in
lines are latched on chip to simplify system
design. Data out is unlatched to allow greater
system flexibility.
The TMS416409A and TMS417409A are offered in a 24/26-lead plastic surface-mount SOJ package
(DJ suffix). The TMS426409A and TMS427409A are offered in a 24/26-lead plastic surface-mount SOJ
package (DJ suffix) and a 24/26-lead plastic surface-mount TSOP (DGA suffix). These packages are designed
for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
†
logic symbol (TMS416409A and TMS426409A)
RAM 4096 K × 4
9
A0
A1
20D10/21D0
10
11
12
15
16
17
18
19
21
8
A2
A3
A4
0
A5
A
4194303
A6
A7
A8
A9
20D19/21D9
20D20
A10
A11
6
20D21
C20 [ROW]
G23/[REFRESH ROW]
5
RAS
CAS
24 [PWR DWN]
C21[COLUMN]
G24
&
23
23C22
24,25 EN
4
W
23,21D
G25
22
OE
2
DQ1
A,22D
26
A,Z26
3
DQ2
DQ3
24
25
DQ4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
†
logic symbol (TMS417409A and TMS427409A)
RAM 4096 K × 4
20D11/21D0
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
10
11
12
15
16
17
18
19
21
8
0
A
4194303
20D21/21D10
C20 [ROW]
G23/[REFRESH ROW]
5
RAS
CAS
24 [PWR DWN]
C21[COLUMN]
G24
&
23
23C22
24,25 EN
4
W
23,21D
G25
22
OE
2
DQ1
A,22D
26
A,Z26
3
DQ2
DQ3
24
25
DQ4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
functional block diagram
TMS416409A, TMS426409A
RAS CAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
256K Array
4
Column-
Address
Buffers
R
o
w
Data-
In
†
4
256K Array
A11
4
Reg.
I/O
Buffers
4
D
e
c
o
d
e
64
Data-
Out
Reg.
Row-
Address
Buffers
12
256K Array
DQ1–DQ4
12
Column addresses A10 and A11 are not used.
†
TMS417409A, TMS427409A
RAS CAS
W
OE
Timing and Control
A0
A1
11
Column Decode
Sense Amplifiers
4
Column-
Address
Buffers
256K Array
256K Array
R
o
w
256K Array
256K Array
Data-
In
4
A10
4
Reg.
I/O
Buffers
4
D
e
c
o
d
e
32
32
Data-
Out
Reg.
Row-
Address
Buffers
11
256K Array
11
256K Array
DQ1–DQ4
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
operation
extended data out
Extended data out (EDO) allows data output rates of up to 50 MHz for 50-ns devices. When keeping the same
rowaddresswhileselectingrandomcolumnaddresses, thetimeforrow-addresssetupandholdandforaddress
multiplex is eliminated. The maximum number of columns that can be accessed is determined by t
maximum RAS low time.
, the
RASP
Extended data out does not place the data in/data out pins (DQ pins) into the high-impedance state with the
rising edge of CAS. The output remains valid for the system to latch the data. After CAS goes high, the DRAM
decodes the next address. OE and W can control the output impedance. Descriptions of OE and W further
explain EDO operation benefit.
address: A0–A11 (TMS416409A and TMS426409A) and A0–A10 (TMS417409A and TMS427409A)
Twenty-two address bits are required to decode each of the 4194304 storage cell locations. For the
TMS416409A and TMS426409A,12 row-address bits are set up on A0 through A11 and latched onto the chip
by the row-address strobe (RAS). Ten column-address bits are set up on A0 through A9. For the TMS417409A
and TMS427409A, 11 row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS.
Eleven column-address bits are set up on A0 through A10. All addresses must be stable on or before the falling
edge of RAS and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the
row decoder. CAS is used as a chip select, activating the output buffers and latching the address bits into the
column-address buffers.
output enable (OE)
OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance (see Figure 8). There are two
methods for placing the DQs into the high-impedance state and maintaining that state during CAS high time.
The first method is to transition OE high before CAS transitions high and keep OE high for t
(hold time, OE
CHO
fromCAS) past the CAS transition. This disables the DQs and they remain disabled, regardless of OE, until CAS
falls again. The second method is to have OE low as CAS transitions high. Then OE can pulse high for a
minimum of t
(precharge time, OE) anytime during CAS high time, disabling the DQs regardless of further
OEP
transitions on OE until CAS falls again (see Figure 8).
write enable (W)
The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled so long as CAS is high
(see Figure 9).
data in/data out (DQ1–DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the later falling
edge of CAS or W strobes data into the on-chip data latch with setup and hold times referenced to the later edge.
The DQs drive valid data after all access times are met and remain valid except in cases described in the W
and OE sections.
5
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
RAS-only refresh
TMS416409A, TMS426409A
Arefreshoperationmustbeperformedatleastonceevery64mstoretaindata. Thiscanbeachievedbystrobing
each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh.
TMS417409A, TMS427409A
Arefreshoperationmustbeperformedatleastonceevery32mstoretaindata. Thiscanbeachievedbystrobing
each of the 2048 rows (A0–A10). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh.
hidden refresh
A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by
holding CAS at V after a read operation and cycling RAS after a specified precharge period, similar to a
IL
RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally.
CAS-before-RAS (CBR) refresh
CBR refresh is performed by bringing CAS low earlier than RAS (see parameter t
) and holding it low after
CSR
RAS falls (see parameter t
). For successive CBR refresh cycles, CAS can remain low while cycling RAS.
CHR
The external address is ignored, and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full V level. These eight initialization cycles must include at least one refresh
CC
(RAS-only or CBR) cycle.
test mode
The test mode (see Figure 1) is initiated with a CBR-refresh cycle while simultaneously holding the W input low.
The entry cycle performs an internal refresh cycle while internally setting the device to perform parallel read or
write on subsequent cycles. While in the test mode, any data sequence can be performed. The device exits test
mode if a CBR refresh cycle with W held high or a RAS-only refresh cycle is performed.
In the test mode, the device is configured as 1024K bits × 4 bits for each DQ. Each DQ pin has a separate 4-bit
parallel read and write data bus that ignores column addresses A0 and A1. During a read cycle, the four internal
bits are compared for each DQ pin. If the four bits agree, DQ goes high; if not, DQ goes low. Test time is reduced
by a factor of four for this series.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
test mode (continued)
Exit Cycle
Normal
Entry Cycle
RAS
Test Mode Cycle
Mode
CAS
W
NOTE A: The states of W, data in, and address are defined by the type of cycle used during test mode.
Figure 1. Test-Mode Cycle
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Supply voltage range, V
(TMS41x409A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
(TMS42x409A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
CC
CC
Voltage range on any pin (TMS41x409A) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on any pin (TMS42x409A) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
TMS41x409A
MIN NOM MAX
TMS42x409A
MIN NOM MAX
3.6
UNIT
V
V
V
V
T
Supply voltage
4.5
5
0
5.5
3
3.3
0
V
V
V
V
CC
SS
IH
Supply voltage
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
2.4
– 1
0
6.5
0.8
70
2
– 0.3
0
V
+ 0.3
CC
0.8
70
IL
°C
A
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TMS416409A
’416409A-50 ’416409A-60 ’416409A-70
†
PARAMETER
UNIT
TEST CONDITIONS
= – 5 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
2.4
2.4
2.4
V
V
OH
OH
Low-level output voltage
Input current (leakage)
= 4.2 mA
= 5.5 V,
0.4
0.4
0.4
OL
OL
V
V = 0 V to 6.5 V,
I
CC
All others = 0 V to V
I
I
I
± 10
± 10
± 10
µA
I
CC
Output current
(leakage)
V
= 5.5 V,
V
= 0 V to V ,
CC
CC
CAS high
O
± 10
± 10
± 10
µA
O
Average read- or
write-cycle current
‡§
V
V
= 5.5 V,
Minimum cycle
100
80
70
mA
CC1
CC
= 2.4 V (TTL),
IH
After one memory cycle,
RAS and CAS high
2
1
2
1
2
1
mA
mA
Average standby
current
I
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After one memory cycle,
RAS and CAS high
V
= 5.5 V,
Minimum cycle,
CC
RAS cycling,
Average refresh current
(RAS-only refresh or
CBR)
‡§
‡¶
I
I
100
100
80
90
70
80
mA
mA
CC3
CAS high (RAS only),
RAS low after CAS low (CBR)
V
= 5.5 V,
t
= MIN,
CC
RAS low,
HPC
CAS cycling
Average EDO current
CC4
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS = V
IL
Measured with a maximum of one address change during each EDO cycle, t
HPC
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TMS417409A
’417409A-50 ’417409A-60 ’417409A-70
†
PARAMETER
UNIT
TEST CONDITIONS
= – 5 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
2.4
2.4
2.4
V
V
OH
OH
Low-level output voltage
Input current (leakage)
= 4.2 mA
= 5.5 V,
0.4
0.4
0.4
OL
OL
V
V = 0 V to 6.5 V,
I
CC
All others = 0 V to V
I
I
I
± 10
± 10
± 10
µA
I
CC
Output current
(leakage)
V
= 5.5 V,
V
= 0 V to V
,
CC
CC
CAS high
O
± 10
± 10
± 10
µA
O
Average read- or
write-cycle current
‡§
V
V
= 5.5 V,
Minimum cycle
130
110
100
mA
CC1
CC
= 2.4 V (TTL),
IH
After one memory cycle,
RAS and CAS high
2
1
2
1
2
1
mA
mA
Average standby
current
I
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After one memory cycle,
RAS and CAS high
Average refresh current
(RAS-only refresh or
CBR)
V
= 5.5 V,
Minimum cycle,
CAS high (RAS only),
RAS low after CAS low (CBR)
CC
RAS cycling,
‡§
‡¶
I
I
130
110
110
90
100
80
mA
mA
CC3
V
= 5.5 V, = MIN,
t
CC
RAS low,
HPC
CAS cycling
Average EDO current
CC4
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS = V
IL
Measured with a maximum of one address change during each EDO cycle, t
HPC
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TMS426409A
’426409A-50
’426409A-60
’426409A-70
†
PARAMETER
UNIT
TEST CONDITIONS
= – 2 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level
output
voltage
I
I
I
I
LVTTL
2.4
2.4
2.4
OH
OH
OL
OL
V
V
V
OH
= – 100 µA
= 2 mA
LVCMOS
LVTTL
V
–0.2
V
–0.2
V
–0.2
CC
CC
CC
Low-level
output
voltage
0.4
0.2
0.4
0.2
0.4
0.2
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
CC
All others = 0 V to V
I
I
I
± 10
± 10
± 10
± 10
± 10
± 10
µA
µA
I
CC
Output
current
(leakage)
V
= 3.6 V,
V
= 0 V to V ,
CC
CC
CAS high
O
O
Average
read- or
write- cycle
current
‡§
I
V = 3.6 V,
CC
Minimum cycle
90
70
60
mA
CC1
V
IH
= 2 V (LVTTL)
After one memory cycle, RAS and CAS
high
2
1
2
1
2
1
mA
mA
Average
standby
current
I
CC2
V
IH
= V
– 0.2 V (LVCMOS),
CC
After one memory cycle, RAS and CAS
high
Average
refresh
current
V
= 3.6 V,
Minimum cycle,
CC
RAS cycling,
‡§
I
I
90
70
90
60
80
mA
mA
CC3
(RAS-only
refresh
or CBR)
CAS high (RAS-only refresh),
RAS low after CAS low (CBR)
Average
‡¶
V
= 3.6 V,
t
= MIN,
CC
RAS low,
HPC
CAS cycling
100
CC4
EDO current
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS = V
IL
Measured with a maximum of one address change during each EDO cycle, t
HPC
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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TMS427409A
’427409A-50
’427409A-60
’427409A-70
†
PARAMETER
UNIT
TEST CONDITIONS
= – 2 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level
output
voltage
I
I
I
I
LVTTL
2.4
2.4
2.4
OH
OH
OL
OL
V
V
V
OH
= – 100 µA
= 2 mA
LVCMOS
LVTTL
V
–0.2
V
–0.2
V
–0.2
CC
CC
CC
Low-level
output
voltage
0.4
0.2
0.4
0.2
0.4
0.2
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
CC
All others = 0 V to V
I
I
I
± 10
± 10
± 10
± 10
± 10
± 10
µA
µA
I
CC
Output
current
(leakage)
V
= 3.6 V,
V
= 0 V to V ,
CC
CC
CAS high
O
O
Average
read- or
write- cycle
current
‡§
I
V = 3.6 V,
CC
Minimum cycle
120
100
90
mA
CC1
V
IH
= 2 V (LVTTL)
After one memory cycle, RAS and CAS
high
2
1
2
1
2
1
mA
mA
Average
standby
current
I
CC2
V
IH
= V
– 0.2 V (LVCMOS),
CC
After one memory cycle, RAS and CAS
high
Average
refresh
current
V
= 3.6 V,
Minimum cycle,
CC
RAS cycling,
‡§
I
I
120
110
100
90
90
80
mA
mA
CC3
(RAS-only
refresh
or CBR)
CAS high (RAS-only refresh),
RAS low after CAS low (CBR)
Average
‡¶
V
= 3.6 V,
t
= MIN,
CC
RAS low,
HPC
CAS cycling
CC4
EDO current
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS = V
IL
Measured with a maximum of one address change during each EDO cycle, t
HPC
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capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
pF
†
C
C
C
C
C
Input capacitance, A0–A11
5
7
7
7
7
i(A)
Input capacitance, OE
pF
i(OE)
i(RC)
i(W)
o
Input capacitance, CAS and RAS
Input capacitance, W
pF
pF
‡
Output capacitance
pF
†
‡
A11 is NC (no internal connection) for TMS417409A and TMS427409A.
CAS and OE = V to disable outputs
IH
= NOM supply voltage ±10%, and the bias on pins under test is 0 V.
NOTE 3:
V
CC
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x409A-50
’42x409A-50
’41x409A-60
’42x409A-60
’41x409A-70
’42x409A-70
PARAMETER
UNIT
MIN
MAX
25
MIN MAX
MIN MAX
t
t
t
t
t
t
t
t
t
t
Access time from column address (see Note 5)
Access time from CAS (see Note 5)
30
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
13
15
18
CAC
CPA
RAC
OEA
CLZ
REZ
CEZ
OEZ
WEZ
Access time from CAS precharge (see Note 5)
Access time from RAS (see Note 5)
28
35
40
50
60
70
Access time from OE (see Note 5)
13
15
18
Delay time, CAS to output in low impedance
Output buffer turn off delay from RAS (see Note 6)
Output buffer turn off delay from CAS (see Note 6)
Output buffer turn off delay from OE (see Note 6)
Output buffer turn off delay from W (see Note 6)
0
3
3
3
3
0
0
13
13
13
13
3
3
3
3
15
15
15
15
3
3
3
3
18
18
18
18
NOTES: 4. With ac parameters, it is assumed that t = 2 ns.
T
5. For TMS42x409A, access times are measured with output reference levels of V
= 2 V and V
= 0.8 V.
OH
OL
6. The maximum values of t
, t
, t
, and t
are specified when the output is no longer driven. Data in should not be driven
WEZ
REZ CEZ OEZ
until one of the applicable maximum specifications is satisfied.
13
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EDO timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x409A-50
’42x409A-50
’41x409A-60
’42x409A-60
’41x409A-70
’42x409A-70
UNIT
MIN
20
57
40
7
MAX
MIN
25
68
48
10
5
MAX
MIN
30
78
58
10
5
MAX
t
t
t
t
t
t
t
t
t
t
Cycle time, EDO page mode, read-write
Cycle time, EDO read-write
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HPC
PRWC
CSH
CHO
DOH
CAS
WPE
OCH
CP
Delay time, RAS active to CAS precharge
Hold time, OE from CAS
Hold time, output from CAS
5
Pulse duration, CAS active (see Note 7)
Pulse duration, W active (output disable only)
Setup time, OE before CAS
8
10000
10 10000
12 10000
7
7
10
10
5
7
10
10
5
8
Pulse duration, CAS precharge
Precharge time, OE
8
5
OEP
NOTES: 4: With ac parameters, it is assumed that t = 2 ns.
T
7. In a read-write cycle, t
CWD
and t must be observed.
CWL
14
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timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x409A-50
’42x409A-50
’41x409A-60
’42x409A-60
’41x409A-70
’42x409A-70
UNIT
MIN
84
MAX
MIN
104
135
MAX
MIN
124
160
MAX
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Cycle time, read-write
111
RWC
RASP
RAS
RP
Pulse duration, RAS active, fast page mode (see Note 8)
Pulse duration, RAS active, non-page mode (see Note 8)
Pulse duration, RAS precharge
50 100 000
60 100 000
70 100 000
50
30
8
10 000
60
40
10
0
10 000
70
50
10
0
10 000
Pulse duration, write command
WP
Setup time, column address
0
ASC
ASR
DS
Setup time, row address
0
0
0
Setup time, data in (see Note 9)
0
0
0
Setup time, read command
0
0
0
RCS
CWL
RWL
Setup time, write command before CAS precharge
Setup time, write command before RAS precharge
8
10
10
12
12
8
Setup time, write command before CAS active
(early-write only)
t
0
0
0
ns
WCS
t
t
t
t
t
t
t
t
Setup time, W high before RAS low (CBR refresh only)
Setup time, W low before RAS low (test mode only)
Setup time, CAS referenced to RAS (CBR refresh only)
Hold time, column address
10
10
5
10
10
5
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
WRP
WTS
CSR
CAH
DH
8
10
10
10
0
12
12
10
0
Hold time, data in (see Note 9)
8
Hold time, row address
8
RAH
RCH
RRH
Hold time, read command referenced to CAS (see Note 10)
Hold time, read command referenced to RAS (see Note 10)
0
0
0
0
Hold time, write command during CAS active
(early-write only)
t
8
10
12
ns
WCH
t
t
t
t
t
t
Hold time, RAS referenced to OE
8
10
10
10
13
28
10
10
10
10
15
35
10
10
10
10
18
40
ns
ns
ns
ns
ns
ns
ROH
WRH
WTH
CHR
OEH
RHCP
Hold time, W high after RAS low (CBR refresh)
Hold time, W low after RAS low (test mode only)
Hold time, CAS referenced to RAS (CBR refresh only)
Hold time, OE command
Hold time, RAS active from CAS precharge
NOTES: 4. With ac parameters, it is assumed that t = 2 ns.
T
8. In a read-write cycle, t
RWD
and t must be observed.
RWL
9. Referenced to the later of CAS or W in write operations
10. Either t or t must be satisfied for a read cycle.
RRH
RCH
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timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4) (continued)
’41x409A-50
’42x409A-50
’41x409A-60
’42x409A-60
’41x409A-70
’42x409A-70
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Delay time, column address to write command
(read-write only)
t
42
49
57
ns
AWD
t
t
t
t
t
t
t
t
t
Delay time, W low after xCAS precharge (read-write only)
Delay time, CAS precharge to RAS
45
5
54
5
62
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
CPW
CRP
CWD
OED
RAD
RAL
Delay time, CAS to write command (read-write only)
Delay time, OE to data in
30
13
10
25
18
12
5
34
15
12
30
20
14
5
40
18
12
35
25
14
5
Delay time, RAS to column address (see Note 11)
Delay time, column address to RAS precharge
Delay time, column address to CAS precharge
Delay time, RAS to CAS (see Note 11)
25
37
30
45
35
52
CAL
RCD
RPC
Delay time, RAS precharge to CAS
t
t
t
t
t
t
Delay time, CAS active to RAS precharge
Delay time, RAS to write command (read-write only)
Access time from address (test mode)
Access time, from column precharge (test mode)
Access time, from RAS (test mode)
Transition time
8
67
30
35
55
2
10
79
35
40
65
2
12
92
40
45
75
2
ns
ns
ns
ns
ns
ns
ms
ms
RSH
RWD
TAA
TCPA
TRAC
T
30
64
32
30
64
32
30
64
32
’4x6409A
’4x7409A
t
Refresh time interval
REF
NOTES: 4. With ac parameters, it is assumed that t = 2 ns.
T
11. The maximum value is specified only to ensure access time.
16
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PARAMETER MEASUREMENT INFORMATION
V
TH
V
CC
R
R
R
L
1
2
Output Under Test
= 100 pF
Output Under Test
= 100 pF
C
C
L
L
(see Note A)
(see Note A)
(a) LOAD CIRCUIT
NOTE A: C includes probe and fixture capacitance.
(b) ALTERNATE LOAD CIRCUIT
L
DEVICE
’41x409A
’42x409A
V
(V)
R
( )
R
( )
V
(V)
R ( )
L
CC
1
2
TH
5
828
295
868
1.31
1.4
218
500
3.3
1178
Figure 2. Load Circuits for Timing Parameters
17
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PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
RP
t
T
t
CSH
t
RCD
t
RSH
t
CRP
t
CAS
t
CAS
ASR
t
t
CP
RAD
t
ASC
t
RAH
t
CAL
t
RAL
Don’t Care
Row
Column
Address
t
RCS
t
t
RRH
RCH
t
CAH
Don’t Care
Don’t Care
W
t
CAC
t
CEZ
REZ
t
t
AA
Valid Data Out
Hi-Z
DQ1–DQ4
See Note A
CLZ
t
t
WEZ
t
RAC
t
WPE
t
OEA
t
OEZ
t
ROH
Don’t Care
Don’t Care
OE
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 3. Read-Cycle Timing
18
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PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
CAS
t
RP
t
T
t
RSH
t
RCD
t
CRP
t
CSH
t
t
CAS
ASR
t
CP
t
ASC
t
CAL
t
RAL
t
RAH
t
CAH
Row
Column
Don’t Care
Address
t
CWL
t
RAD
t
RWL
t
WCH
t
WCS
Don’t Care
Don’t Care
W
t
DH
t
DS
Don’t Care
Valid Data
DQ1–DQ4
Don’t Care
OE
Figure 4. Early-Write-Cycle Timing
19
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SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
RP
t
T
t
RSH
t
RCD
t
CRP
t
CAS
t
CSH
t
CAS
ASR
t
t
CP
ASC
t
RAL
t
CAL
t
RAH
t
CAH
Don’t Care
Row
Column
Address
t
CWL
t
RAD
t
DS
t
RWL
Don’t Care
Don’t Care
Don’t Care
W
t
WP
t
CLZ
t
DH
Valid Data In
DQ1–DQ4
Invalid Data Out
t
OED
t
OEH
Don’t Care
Don’t Care
OE
Figure 5. Write-Cycle Timing
20
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PARAMETER MEASUREMENT INFORMATION
t
RWC
t
RAS
RAS
CAS
t
RP
t
T
t
t
CRP
RCD
t
CAS
t
ASR
t
t
CP
RAH
t
CAH
t
RAD
t
T
t
ASC
Row
Column
Don’t Care
Address
t
t
CWL
RCS
t
RWL
t
RWD
t
WP
Don’t Care
W
t
AWD
t
CWD
t
CAC
t
DS
t
AA
t
t
DH
CLZ
Data
Out
Data
In
Don’t Care
Hi-Z
DQ1–DQ4
See Note A
t
RAC
t
OEZ
t
OEA
t
OEH
t
OED
Don’t Care
Don’t Care
OE
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Read-Write-Cycle Timing
21
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PARAMETER MEASUREMENT INFORMATION
t
RASP
RAS
t
RP
t
t
T
RHCP
t
t
RCD
RSH
t
CSH
t
t
CRP
HPC
t
CAS
t
CP
CAS
t
RAH
t
ASC
t
CAL
t
ASR
t
RAL
t
CAH
Row
Column #1
Column #2
Column #3
Address
t
RAD
t
RCH
t
OEA
OE
t
RCS
t
CAC
t
RRH
t
DOH
W
t
CAC
t
AA
t
t
CEZ
AA
t
See Note C
CPA
t
RAC
t
REZ
t
CLZ
Data #1
Data #2
Data #3
DQ1–DQ4
See Note A
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. Access time is t -, t -, or t -dependent.
CPA AA
C. Output is turned off by t
CAC
if RAS goes high during CAS low.
CEZ
Figure 7. EDO Read Cycle
22
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PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
CAS
t
CSH
t
RHCP
t
HPC
t
CP
t
CAS
t
RSH
t
ASR
t
RAH
t
ASC
t
CAL
t
CAH
t
RAL
Row
Column #1
Column #2
Column #3
Address
t
RAD
t
OCH
t
t
CHO
OEP
t
OEP
OE
t
OEA
t
RRH
t
RCS
t
RCH
t
OEA
t
CAC
W
t
DOH
t
CLZ
t
OEZ
See Note A
t
CAC
t
t
CEZ
CPA
t
AA
t
REZ
t
OEZ
t
RAC
t
AA
Data #1
if RAS goes high during CAS low.
Data #1
Data #2
Data #3
DQ1–DQ4
NOTE A: Output is turned off by t
CEZ
Figure 8. EDO Read-Cycle With OE Control
23
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PARAMETER MEASUREMENT INFORMATION
t
RASP
RAS
CAS
t
RP
t
t
RHCP
CSH
t
CRP
t
HPC
t
RSH
t
CP
t
CAS
t
ASR
t
RAH
t
RAL
t
CAH
t
CAL
t
ASC
Row
Column #1
Column #2
Column #3
Address
OE
t
RAD
t
OEA
t
CAC
t
RCS
t
CAC
t
WPE
t
RCH
t
RRH
W
t
DOH
t
CAC
t
WEZ
t
CPA
t
CEZ
t
AA
CLZ
RAC
t
CPA
t
t
AA
t
AA
t
REZ
t
Data #1
Data #2
Data #3
DQ1–DQ4
Figure 9. EDO Read-Cycle With W Control
24
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PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
t
RHCP
t
HPC
RAS
CAS
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASC
t
RAH
t
CP
t
CAH
t
RAL
t
t
CAL
ASR
Row
Column
Column
Don’t Care
Address
t
CWL
t
CWL
t
RAD
t
t
RWL
WCH
t
WCS
Don’t Care
Don’t Care
Don’t Care
W
t
DH
t
DS
Data In
Data In
DQ1–DQ4
OE
Don’t Care
Don’t Care
NOTE A: Areadcycleoraread-writecyclecanbeintermixedwithwritecyclesaslongasreadandread-writetimingspecificationsarenotviolated.
Figure 10. EDO Early-Write-Cycle Timing
25
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SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
t
RAS
RHCP
t
t
CSH
HPC
t
CRP
t
RSH
t
RCD
t
CAL
t
CAS
t
ASC
CAS
t
RAH
t
CP
t
RAL
t
t
CAH
ASR
Address
Row
Column
Column
Don’t Care
t
RAD
t
CWL
t
t
CWL
t
RWL
WP
t
DS
W
Don’t Care
Don’t Care
Don’t Care
t
OEH
t
DH
t
CLZ
Valid
In
Don’t Care
Valid Data In
Don’t Care
DQ1–DQ4
Invalid Data out
t
OEH
t
OED
Don’t Care
Don’t Care
OE
NOTE A: Areadcycleoraread-writecyclecanbeintermixedwithwritecyclesaslongasreadandread-writetimingspecificationsarenotviolated.
Figure 11. EDO Write-Cycle Timing
26
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
CAS
t
t
CSH
t
RSH
t
PRWC
t
CRP
t
RCD
CP
t
t
CAS
ASR
ASC
t
t
CAL
t
CAH
t
RAL
t
RAD
Row
Column 1
Column 2
Don’t Care
Address
t
RAH
t
CWL
t
CWD
t
CPW
t
AWD
t
RWL
t
WP
t
RWD
W
t
RCS
t
CPA
t
OEH
t
AA
t
DH
t
t
Valid Out 2
(see Note A)
RAC
t
DS
t
CAC
Valid
In 1
Valid
In 2
DQ1–DQ4
Valid
Out 1
t
CLZ
t
OED
OEA
t
t
OEH
OEZ
OE
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read- and write-timing specifications are not violated.
Figure 12. EDO Read-Write-Cycle Timing
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
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SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
t
CRP
RP
t
T
t
RPC
Don’t Care
Don’t Care
CAS
t
RAH
t
ASR
Address
Row
Don’t Care
Row
Don’t Care
W
DQ1–DQ4
OE
Hi Z
Don’t Care
Figure 13. RAS-Only Refresh-Cycle Timing
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RP
t
RAS
RAS
CAS
t
CSR
t
t
CHR
RPC
t
T
t
WRP
t
WRH
W
Address
OE
Don’t Care
Don’t Care
DQ1–DQ4
Hi-Z
Figure 14. Automatic-CBR-Refresh-Cycle Timing
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
RP
Memory Cycle
t
RP
t
t
RAS
t
RAS
RAS
CAS
t
CHR
t
CAS
t
CAH
t
ASC
t
RAH
t
ASR
Row
Col
Don’t Care
Address
t
WRH
t
t
WRP
WRH
t
RRH
t
WRP
t
WRH
t
WRP
t
RCS
t
W
RAC
t
CAC
t
REZ
t
WEZ
t
CEZ
t
AA
Valid Data Out
OEA
DQ1–DQ4
OE
t
CLZ
t
OEZ
t
Figure 15. Hidden-Refresh-Cycle (Read) Timing
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
RAS
Refresh Cycle
t
t
RP
RP
t
t
RAS
RAS
CAS
t
CHR
t
CAS
t
CAH
t
ASC
t
RAH
t
ASR
Don’t Care
Row
Col
Address
t
WRH
t
t
WRP
WCS
t
WP
W
t
WCH
t
DH
t
DS
Don’t Care
Valid Data
DQ1–DQ4
OE
Don’t Care
Figure 16. Hidden-Refresh-Cycle (Write) Timing
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RP
t
RAS
RAS
CAS
t
CSR
t
CHR
t
RPC
t
T
t
WTH
t
WTS
Don’t Care
W
Don’t Care
Address
OE
Don’t Care
Hi-Z
DQ1–DQ4
Figure 17. Test-Mode-Entry-Cycle Timing
t
RC
t
RP
t
RAS
RAS
t
CSR
t
RPC
t
CHR
t
T
CAS
t
WRP
W
Don’t Care
Don’t Care
t
WRH
Address
Don’t Care
t
REZ
CEZ
t
Hi-Z
Don’t Care
DQ1–DQ4
Figure 18. Test-Mode-Exit-Cycle CBR-Refresh-Cycle Timing
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
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MECHANICAL DATA
DJ (R-PDSO-J24/26)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
0.680 (17,27)
0.670 (17,02)
26
21
19
14
0.340 (8,64)
0.330 (8,38)
0.305 (7,75)
0.295 (7,49)
1
6
8
13
0.032 (0,81)
0.026 (0,66)
0.106 (2,69) TYP
0.008 (0,20) NOM
0.148 (3,76)
0.128 (3,25)
Seating Plane
0.004 (0,10)
0.275 (6,99)
0.260 (6,60)
0.020 (0,51)
0.016 (0,41)
0.007 (0,18)
M
0.050 (1,27)
4040092-3/B 02/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
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SMKS893B – AUGUST 1996 – REVISED APRIL 1997
MECHANICAL DATA
DGA (R-PDSO-G24/26)
PLASTIC SMALL-OUTLINE PACKAGE
0.020 (0,50)
0.008 (0,21)
0.050 (1,27)
M
0.012 (0,30)
26
14
0.371 (9,42)
0.355 (9,02)
0.304 (7,72)
0.296 (7,52)
0.006 (0,15) NOM
1
13
0.679 (17,24)
0.671 (17,04)
Gage Plane
0.010 (0,25)
0°–5°
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.047 (1,19) MAX
0.002 (0,05) MIN
4040265-3/C 11/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
device symbolization (TMS416409A illustrated)
TI
-SS
Speed ( -50, - 60, -70)
Package Code
TMS416409A DJ
W
E
Y
M LLLL
P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright 1998, Texas Instruments Incorporated
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