TP3064 [NSC]
``Enhanced' Serial Interface CMOS CODEC/Filter COMBO; ``增强型'串行接口CMOS编解码器/滤波器COMBO
| 型号： | TP3064 |
| 厂家： | 
National Semiconductor |
| 描述： | ``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
| 文件： | 总18页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1991
TP3064, TP3067
‘‘Enhanced’’ Serial Interface
CMOS CODEC/Filter COMBO
General Description
The TP3064 (m-law) and TP3067 (A-law) are monolithic
PCM CODEC/Filters utilizing the A/D and D/A conversion
architecture shown in Figure 1, and a serial PCM interface.
The devices are fabricated using National’s advanced dou-
ble-poly CMOS process (microCMOS).
É
Features
Y
Complete CODEC and filtering system including:
Ð Transmit high-pass and low-pass filtering
Ð Receive low-pass filter with sin x/x correction
Ð Active RC noise filters
Ð m-law or A-law compatible COder and DECoder
Ð Internal precision voltage reference
Ð Serial I/O interface
Ð Internal auto-zero circuitry
Ð Receive push-pull power amplifiers
m-lawÐTP3064
Similar to the TP305X family, these devices feature an addi-
tional Receive Power Amplifier to provide push-pull bal-
anced output drive capability. The receive gain can be ad-
justed by means of two external resistors for an output level
Y
Y
Y
Y
Y
Y
Y
Y
Y
g
of up to 6.6V across a balanced 600X load.
A-lawÐTP3067
Also included is an Analog Loopback switch and a TS out-
X
put.
Designed for D3/D4 and CCITT applications
g
5V operation
See also AN-370, ‘‘Techniques for Designing with CODEC/
Filter COMBO Circuits.’’
Low operating powerÐtypically 70 mW
Power-down standby modeÐtypically 3 mW
Automatic power-down
TTL or CMOS compatible digital interfaces
Maximizes line interface card circuit density
COMBOÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corpora-
tion.
Block Diagram
TL/H/5070–1
FIGURE 1
C
1995 National Semiconductor Corporation
TL/H/5070
RRD-B30M115/Printed in U. S. A.
Connection Diagrams
Plastic Chip Carrier
Dual-In-Line Package
TL/H/5070–6
Top View
Order Number TP3064J or TP3067J
See NS Package J20A
Order Number TP3064WM or TP3067WM
See NS Package M20B
Order Number TP3064N or TP3067N
See NS Package N20A
TL/H/5070–2
Top View
Order Number TP3064V or TP3067V
See NS Package V20A
Pin Description
Symbol
MCLK
Function
Symbol
Function
Transmit master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be
X
VPOa
GNDA
VPOb
VPI
The non-inverted output of the receive power
amplifier.
asynchronous with MCLK . Best
R
performance is realized from synchronous
operation.
Analog ground. All signals are referenced to
this pin.
The inverted output of the receive power
amplifier.
BCLK
The bit clock which shifts out the PCM data
on D . May vary from 64 kHz to 2.048 MHz,
X
X
Inverting input to the receive power amplifier.
Analog output of the receive filter.
ea
but must be synchronous with MCLK .
X
VF O
R
V
D
X
The TRI-STATE PCM data output which is
É
enabled by FS .
X
g
5V 5%.
Positive power supply pin. V
CC
CC
FS
X
Transmit frame sync pulse input which
FS
Receive frame sync pulse which enables
BCLK to shift PCM data into D . FS is an
8 kHz pulse train. SeeFigures 2 and3 for
timing details.
R
enables BCLK to shift out the PCM data on
X
D . FS is an 8 kHz pulse train, seeFigures 2
R
R
R
X
X
and3 for timing details.
TS
X
Open drain output which pulses low during
the encoder time slot.
D
Receive data input. PCM data is shifted into
following the FS leading edge.
R
R
D
R
ANLB
Analog Loopback control input. Must be set
to logic ‘0’ for normal operation. When pulled
to logic ‘1’, the transmit filter input is
disconnected from the output of the transmit
preamplifier and connected to the VPOa
output of the receive power amplifier.
Analog output of the transmit input amplifier.
Used to externally set gain.
BCLK
/
The bit clock which shifts data into D after
R
the FS leading edge. May vary from 64 kHz
R
to 2.048 MHz. Alternatively, may be a logic
input which selects either
1.536 MHz/1.544 MHz or 2.048 MHz for
master clock in synchronous mode and
R
CLKSEL
BCLK is used for both transmit and receive
X
directions (see Table I).
GS
X
VF Ib
X
Inverting input of the transmit input amplifier.
Non-inverting input of the transmit input
amplifier.
MCLK /
R
PDN
Receive master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be
VF Ia
X
asynchronous with MCLK , but should be
X
synchronous with MCLK for best
X
performance. When MCLK is connected
eb
g
5V 5%.
V
BB
Negative power supply pin. V
BB
R
continuously low, MCLK is selected for all
X
internal timing. When MCLK is connected
R
continuously high, the device is powered
down.
2
Functional Description
POWER-UP
sion performance, however, MCLK should be synchronous
R
with MCLK , which is easily achieved by applying only static
X
logic levels to the MCLK /PDN pin. This will automatically
When power is first applied, power-on reset circuitry initializ-
es the COMBOTM and places it into a power-down state. All
non-essential circuits are deactivated and the D , VF O,
R
connect MCLK to all internal MCLK functions (see Pin
X
R
X
R
Description). For 1.544 MHz operation, the device automati-
cally compensates for the 193rd clock pulse each frame.
FS starts each encoding cycle and must be synchronous
VPOb and VPOa outputs are put in high impedance states.
To power-up the device, a logical low level or clock must be
applied to the MCLK /PDN pin and FS and/or FS pulses
X
R
X
R
with MCLK and BCLK . FS starts each decoding cycle
X
X
R
and must be synchronous with BCLK . BCLK must be a
must be present. Thus, 2 power-down control modes are
available. The first is to pull the MCLK /PDN pin high; the
alternative is to hold both FS and FS inputs continuously
R
R
R
clock, the logic levels shown in Table I are not valid in asyn-
chronous mode. BCLK and BCLK may operate from 64
kHz to 2.048 MHz.
X
R
X
R
lowÐthe device will power-down approximately 2 ms after
the last FS or FS pulse. Power-up will occur on the first
FS or FS pulse. The TRI-STATE PCM data output, D ,
X
R
SHORT FRAME SYNC OPERATION
X
R
X
will remain in the high impedance state until the second FS
pulse.
X
The COMBO can utilize either a short frame sync pulse (the
same as the TP3020/21 CODECs) or a long frame sync
pulse. Upon power initialization, the device assumes a short
SYNCHRONOUS OPERATION
frame mode. In this mode, both frame sync pulses, FS and
X
FS , must be one bit clock period long, with timing relation-
For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive di-
rections. In this mode, a clock must be applied to MCLK
R
ships specified in Figure 2. With FS high during a falling
X
edge of BCLK , the next rising edge of BCLK enables the
X
X
X
TRI-STATE output buffer, which will output the sign bit.
and the MCLK /PDN pin can be used as a power-down
R
control. A low level on MCLK /PDN powers up the device
R
and a high level powers down the device. In either case,
D
X
The following seven rising edges clock out the remaining
seven bits, and the next falling edge disables the D output.
With FS high during a falling edge of BCLK (BCLK in
X
MCLK will be selected as the master clock for both the
X
transmit and receive circuits. A bit clock must also be ap-
R
R
X
synchronous mode), the next falling edge of BCLK latches
R
plied to BCLK and the BCLK /CLKSEL can be used to
R
X
in the sign bit. The following seven falling edges latch in the
seven remaining bits. All devices may utilize the short frame
sync pulse in synchronous or asynchronous operating
mode.
select the proper internal divider for a master clock of 1.536
MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation,
the device automatically compensates for the 193rd clock
pulse each frame.
LONG FRAME SYNC OPERATION
With a fixed level on the BCLK /CLKSEL pin, BLCK will be
X
R
selected as the bit clock for both the transmit and receive
directions. Table I indicates the frequencies of operation
To use the long (TP5116A/56 CODECs) frame mode, both
the frame sync pulses, FS and FS , must be three or more
X
R
bit clock periods long, with timing relationships specified in
which can be selected, depending on the state of BCLK
/
R
CLKSEL. In this synchronous mode, the bit clock, BCLK ,
X
may be from 64 kHz to 2.048 MHz, but must be synchro-
Figure 3. Based on the transmit frame sync, FS , the COM-
X
BO will sense whether short or long frame sync pulses are
being used. For 64 kHz operation, the frame sync pulse
must be kept low for a minimum of 160 ns. The D TRI-
nous with MCLK .
X
X
Each FS pulse begins the encoding cycle and the PCM
X
data from the previous encode cycle is shifted out of the
STATE output buffer is enabled with the rising edge of FS
X
or the rising edge of BCLK , whichever comes later, and the
X
first bit clocked out is the sign bit. The following seven
enabled D output on the positive edge of BCLK . After 8
X
X
bit clock periods, the TRI-STATE D output is returned to a
X
high impedance state. With an FS pulse, PCM data is
BCLK rising edges clock out the remaining seven bits. The
X
R
latched via the D input on the negative edge of BCLK (or
D
X
output is disabled by the falling BCLK edge following
X
R
X
BCLK if running). FS and FS must be synchronous with
the eighth rising edge, or by FS going low, whichever
X
comes later. A rising edge on the receive frame sync pulse,
R
X
R
MCLK
.
X/R
FS , will cause the PCM data at D to be latched in on the
R
R
next eight falling edges of BCLK (BCLK in synchronous
TABLE I. Selection of Master Clock Frequencies
R
X
mode). All devices may utilize the long frame sync pulse in
synchronous or asynchronous mode.
Master Clock
Frequency Selected
BCLK /CLKSEL
R
TRANSMIT SECTION
TP3067
TP3064
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
see Figure 4. The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be real-
ized. The op amp drives a unity-gain filter consisting of RC
active pre-filter, followed by an eighth order switched-ca-
pacitor bandpass filter clocked at 256 kHz. The output of
this filter directly drives the encoder sample-and-hold circuit.
The A/D is of companding type according to m-law
(TP3064) or A-law (TP3067) coding conventions. A preci-
sion voltage reference is trimmed in manufacturing to pro-
Clocked
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
0
1
1.536 MHz or
1.544 MHz
2.048 MHz
1.536 MHz or
1.544 MHz
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive
clocks may be applied. MCLK and MCLK must be 2.048
MHz for the TP3067, or 1.536 MHZ, 1.544 MHz for the
TP3064, and need not be synchronous. For best transmis-
X
R
vide an input overload (t
) of nominally 2.5V peak (see
MAX
3
Functional Description (Continued)
table of Transmission Characteristics). The FS frame sync
ods. At the end of the decoder time slot, the decoding cycle
begins, and 10 ms later the decoder DAC output is updated.
X
pulse controls the sampling of the filter output, and then the
successive-approximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out through D
E
The total decoder delay is
10 ms (decoder update) plus
110 ms (filter delay) plus 62.5 ms ((/2 frame), which gives
approximately 180 ms.
X
at the next FS pulse. The total encoding delay will be ap-
X
proximately 165 ms (due to the transmit filter) plus 125 ms
(due to encoding delay), which totals 290 ms. Any offset
voltage due to the filters or comparator is cancelled by sign
bit integration.
RECEIVE POWER AMPLIFIERS
Two inverting mode power amplifiers are provided for direct-
ly driving a matched line interface transformer. The gain of
g
the first power amplifier can be adjusted to boost the 2.5V
peak output signal from the receive filter up to 3.3V peak
RECEIVE SECTION
g
g
The receive section consists of an expanding DAC which
fifth order switched-capacitor low pass filter
clocked at 256 kHz. The decoder is A-law (TP3067) or
m-law (TP3064) and the 5th order low pass filter corrects for
the sin x/x attenuation due to the 8 kHz sample/hold. The
filter is then followed by a 2nd order RC active post-filter
into an unbalanced 300X load, or 4.0V into an unbal-
drives
a
anced 15 kX load. The second power amplifier is internally
connected in unity-gain inverting mode to give 6 dB of signal
gain for balanced loads.
Maximum power transfer to a 600X subscriber line termina-
tion is obtained by differentially driving a balanced trans-
with its output at VF O. The receive section is unity-gain,
R
but gain can be added by using the power amplifiers. Upon
former with a
S
2:1 turns ratio, as shown in Figure 4. A total
peak power of 15.6 dBm can be delivered to the load plus
termination.
the occurrence of FS , the data at the D input is clocked in
R
R
on the falling edge of the next eight BCLK (BCLK ) peri-
R
X
ENCODING FORMAT AT D OUTPUT
X
TP3067
A-Law
TP3064
m-Law
(Includes Even Bit Inversion)
e a
V
V
Full-Scale
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
IN
e
0V
IN
Ð
0
e b
V
Full-Scale
0
IN
4
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at any Digital Input
or Output
a
b
0.3V to GNDA 0.3V
V
CC
b
b
a
25 C to 125 C
Operating Temperature Range
Storage Temperature Range
Lead Temp. (Soldering, 10 sec.)
ESD (Human Body Model) J
ESD (Human Body Model) N
Latch-Up Immunity
§
§
V
V
to GNDA
to GNDA
7V
7V
a
65 C to 150 C
CC
§
§
b
BB
300 C
§
Voltage at any Analog Input
or Output
1000V
1500V
a
b
0.3V
V
CC
0.3V to V
BB
100 mA on Any Pin
e
25 C. All other limits
Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
CC
a
e b
e
e
0 C to 70 C by correlation with 100% electrical testing at T
A
g
g
5.0V 5%, V
5.0V 5%; T
§
§
§
BB
A
are assured by correlation with other production tests and/or product design and characterization. All signals referenced to
e a
e b
e
5.0V, T 25 C.
A
GNDA. Typicals specified at V
5.0V, V
§
CC
BB
Symbol
Parameter
Conditions
Min
Typ
Max
Units
POWER DISSIPATION (ALL DEVICES)
I
I
I
I
0
Power-Down Current
Power-Down Current
Active Current
(Note)
(Note)
0.5
0.05
7.0
1.5
0.3
mA
mA
mA
mA
CC
0
1
BB
VPI 0V; VF O, VPOa and VPOb unloaded
10.0
10.0
e
CC
R
VPI 0V; VF O, VPOa and VPOb unloaded
7.0
e
1
Active Current
BB
R
DIGITAL INTERFACE
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
0.6
V
V
IL
2.2
2.4
IH
OL
e
D , I
X
3.2 mA
0.4
0.4
V
V
L
e
TS , I
X
3.2 mA, Open Drain
L
eb
s
V
OH
Output High Voltage
Input Low Current
Input High Current
D , I
X H
3.2 mA
V
s
b
I
I
I
GNDA
V
IN
V
, All Digital Inputs
IL
10
10
10
10
10
10
mA
mA
mA
IL
s
s
b
b
V
IH
V
IN
V
CC
IH
s
s
V
CC
Output Current in High Impedance
State (TRI-STATE)
D , GNDA
X
V
O
OZ
Note: I
and I
are measured after first achieving a power-up state.
BB0
CC0
5
Electrical Characteristics (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
e a
e b
e
5.0V 5%; T
A
g
g
5.0V 5%, V
CC
BB
e
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V
0 C to 70 C by correlation with 100% electrical testing at T
25 C. All other limits are assured by correlation with other
e
§
§
§
A
CC
a
e b
e
5.0V, T 25 C.
A
5.0V, V
§
BB
Symbol
Parameter
Conditions
Min
Typ
Max
200
3
Units
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)
a
2.5V, VF I or VF Ib
nA
MX
X
s
s
s
s
b
b
a
a
b
200
I XA
I
Input Leakage Current
Input Resistance
2.5V
2.5V
V
V
X
X
a
R XA
I
2.5V, VF I or VF Ib
10
X
X
R
XA
O
Output Resistance
Closed Loop, Unity Gain
1
R XA
L
Load Resistance
GS
X
GS
X
10
kX
pF
C XA
L
Load Capacitance
50
t
L
b
a
2.8
V
XA
Output Dynamic Range
Voltage Gain
GS , R 10 kX
2.8
5000
1
V
O
X
A XA
V
VF Ia to GS
X
V/V
MHz
mV
V
X
F XA
U
Unity-Gain Bandwidth
Offset Voltage
2
b
V
XA
20
20
OS
CM
l
CMRRXA 60 dB
b
V
XA
Common-Mode Voltage
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
2.5
2.5
CMRRXA
PSRRXA
DC Test
60
60
dB
dB
DC Test
ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)
R
RF
Output Resistance
Load Resistance
Pin VF
O
1
3
X
O
R
e
VF O
R
g
R RF
L
2.5V
10
kX
pF
mV
C RF
L
Load Capacitance
Output DC Offset Voltage
Connect from VF O to GNDA
R
25
b
VOS
O
R
Measure from VF O to GNDA
R
200
200
ANALOG INTERFACE WITH POWER AMPLIFIERS (ALL DEVICES)
s
s
1.0V VPI 1.0V
b
b
b
100
IPI
Input Leakage Current
Input Resistance
100
25
nA
MX
mV
X
s
s
1.0V VPI 1.0V
RIPI
VIOS
ROP
10
b
Input Offset Voltage
Output Resistance
25
Inverting Unity-Gain at
VPOa or VPOb
1
F
C
Unity-Gain Bandwidth
Load Capacitance
Open Loop (VPOb
)
400
kHz
pF
C P
L
100
a
a
GA
Gain from VPOb to VPOa
600X VPO to VPOb
V/V
e
R
L
b
1
P
Level at VPOb 1.77 Vrms
e
PSRR
Power Supply Rejection of
VPOb Connected to VPI
P
b
V
or V
BB
0 kHz 4 kHz
60
36
dB
dB
CC
b
4 kHz 50 kHz
R P
L
Load Resistance
Connect from VPOa to VPOb
600
X
6
Timing Specifications
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
e a
e b
25 C. All other limits are assured by correlation with other
e
5.0V 5%, T
g
5.0V 5%, V
g
CC
BB
A
e
production tests and/or product design and characterization. All signals are referenced to GNDA. Typicals specified at V
0 C to 70 C by correlation with 100% electrical testing at T
§
§
§
A
e
CC
a
e b
e
e
e
0.7V.
OL
5.0V, V
5.0V, T
25 C. All timing parameters are measured at V
2.0V and V
§
See Definitions and Timing Conventions section for test methods information.
BB
A
OH
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1/t
Frequency of Master Clock
1.536
1.544
MHz
MHz
MHz
PM
MCLK and MCLK
X
2.048
R
R
R
t
t
t
t
t
t
t
t
Rise Time of Master Clock
Fall Time of Master Clock
Period Bit of Clock
MCLK and MCLK
X
50
50
ns
ns
ns
ns
ns
ns
ns
ns
RM
FM
PB
RB
FB
MCLK and MCLK
X
485
488
15725
50
Rise Time of Bit Clock
Fall Time of Bit Clock
BCLK and BCLK
X R
BCLK and BCLK
X
50
R
Width of Master Clock High
Width of Master Clock Low
MCLK and MCLK
X
160
160
100
WMH
WML
SBFM
R
MCLK and MCLK
X
R
Set-Up Time from BCLK High
X
to MCLK Falling Edge
X
t
Set-Up Time from FS High
X
Long Frame Only
100
ns
SFFM
to MCLK Falling Edge
X
t
t
t
Width of Bit Clock High
Width of Bit Clock Low
160
160
0
ns
ns
ns
WBH
WBL
HBFL
Holding Time from Bit Clock
Low to Frame Sync
Long Frame Only
Short Frame Only
Long Frame Only
t
t
t
Holding Time from Bit Clock
High to Frame Sync
0
80
0
ns
ns
ns
HBFS
SFB
Set-Up Time for Frame Sync
to Bit Clock Low
e
Load 150 pF plus 2 LSTTL Loads
Delay Time from BCLK High
X
180
DBD
to Data Valid
e
Load 150 pF plus 2 LSTTL Loads
t
t
Delay Time to TS Low
X
140
165
ns
ns
DBTS
Delay Time from BCLK Low to
X
50
20
DZC
Data Output Disabled
e
C
L
t
Delay Time to Valid Data from
0 pF to 150 pF
165
ns
DZF
FS or BCLK , Whichever
X X
Comes Later
t
t
t
t
t
Set-Up Time from D Valid to
R
50
50
ns
ns
ns
ns
ns
SDB
HBD
SF
BCLK
R/X
Low
Hold Time from BCLK
R/X
Low to
D
R
Invalid
Set-Up Time from FS
X/R
to
Short Frame Sync Pulse (1 Bit Clock
Period Long)
50
BCLK
X/R
Low
Hold Time from BCLK
X/R
Low
Short Frame Sync Pulse (1 Bit Clock
Period Long)
100
100
HF
to FS
X/R
Low
Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
Long Frame Sync Pulse (from 3 to 8 Bit
Clock Periods Long)
HBFI
(FS or FS
X
)
R
t
Minimum Width of the Frame
Sync Pulse (Low Level)
64k Bit/s Operating Mode
160
ns
WFL
7
Timing Diagrams
8
Timing Diagrams (Continued)
9
Transmission Characteristics
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
e a
e b
25 C. All other limits are assured by correlation with other
e
5.0V 5%; T
g
5.0V 5%, V
g
CC
BB
A
e
production tests and/or product design and characterization. GNDA
0 C to 70 C by correlation with 100% electrical testing at T
§
§
§
A
e
e
0V, f
5.0V, V
e
0 dbm0, transmit input amplifier
1.02 kHz, V
IN
5.0V, T
A
e a
e b
e
connected for unity gain non-inverting. Typicals specified at V
25 C.
§
CC
BB
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AMPLITUDE RESPONSE
Absolute Levels
(Definition of
Nominal 0 dBm0 Level is 4 dBm
(600X)
0 dBm0
nominal gain)
1.2276
Vrms
t
Virtual Decision Value Defined
per CCITT Rec. G711
Max Transmit Overload Level
TP3064 (3.17 dBm0)
MAX
2.501
2.492
V
V
PK
TP3067 (3.14 dBm0)
PK
e
e
25 C, V
CC
eb
b
0.15
G
G
Transmit Gain, Absolute
T
5V, V
BB
5V
0.15
dB
§
XA
XR
A
e
e
e
e
e
e
e
e
e
b
b
Transmit Gain, Relative to G
XA
f
f
f
f
f
f
f
f
f
16 Hz
50 Hz
60 Hz
200 Hz
40
30
dB
dB
dB
dB
dB
dB
dB
dB
dB
b
26
0.1
b
b
1.8
b
b
300 Hz-3000 Hz
3300 Hz
0.15
0.35
0.15
0.05
0
b
3400 Hz
0.7
b
b
4000 Hz
14
32
4600 Hz and Up, Measure
Response from 0 Hz to 4000 Hz
b
G
G
G
Absolute Transmit Gain Variation
with Temperature
Relative to G
0.1
0.1
dB
dB
XAT
XAV
XRL
XA
XA
b
Absolute Transmit Gain Variation
with Supply Voltage
Relative to G
0.05
0.05
Transmit Gain Variations with
Level
Sinusoidal Test Method
eb
40 dBm0 to 3 dBm0
Reference Level
10 dBm0
a
b
VF Ia
0.2
0.4
1.2
0.2
0.4
1.2
dB
dB
dB
eb
eb
eb
b
b
b
X
VF Ia
X
50 dBm0 to 40 dBm0
b
55 dBm0 to 50 dBm0
VF Ia
X
e
e
eb
b
G
G
Receive Gain, Absolute
T
25 C, V
§
5V, V
BB
5V
0.15
0.15
dB
RA
RR
A
CC
e
Input Digital Code Sequence
for 0 dBm0 Signal
e
e
e
e
b
b
b
Receive Gain, Relative to G
RA
f
f
f
f
0 Hz to 3000 Hz
3300 Hz
0.15
0.35
0.15
0.05
0
dB
dB
dB
dB
3400 Hz
0.7
b
4000 Hz
14
b
G
G
G
Absolute Receive Gain Variation
with Temperature
Relative to G
0.1
0.1
dB
RAT
RAV
RRL
RA
RA
b
Absolute Receive Gain Variation
with Supply Voltage
Relative to G
0.05
0.05
dB
Receive Gain Variations with
Level
Sinusoidal Test Method; Reference
Input PCM Code Corresponds to an
b
Ideally Encoded 10 dBm0 Signal
eb
eb
eb
a
b
b
b
PCM Level
PCM Level
PCM Level
40 dBm0 to 3 dBm0
0.2
0.4
1.2
0.2
0.4
1.2
dB
dB
dB
b
50 dBm0 to 40 dBm0
b
55 dBm0 to 50 dBm0
e
b
2.5
V
RO
Receive Filter Output at VF
O
R
RL 10 kX
2.5
V
10
Transmission Characteristics (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
e a
e b
e
5.0V 5%; T
A
g
g
5.0V 5%, V
CC
BB
e
production tests and/or product design and characterization. GNDA
0 C to 70 C by correlation with 100% electrical testing at T
25 C. All other limits are assured by correlation with other
§
§
§
A
e
e
0V, f
5.0V, V
e
1.02 kHz, V 0 dbm0, transmit input amplifier
IN
e a
e b
e
5.0V, T
A
connected for unity gain non-inverting. Typicals specified at V
25 C.
§
CC
BB
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ENVELOPE DELAY DISTORTION WITH FREQUENCY
e
D
D
Transmit Delay, Absolute
f
1600 Hz
290
315
ms
XA
e
e
e
e
e
e
e
b
Transmit Delay, Relative to D
f
f
f
f
f
f
f
500 Hz 600 Hz
195
120
50
220
145
75
ms
ms
ms
ms
ms
ms
ms
XR
XA
b
600 Hz 800 Hz
b
800 Hz 1000 Hz
b
b
b
1000 Hz 1600 Hz
20
40
1600 Hz 2600 Hz
55
75
2600 Hz 2800 Hz
b
2800 Hz 3000 Hz
80
105
155
130
e
D
D
Receive Delay, Absolute
f
1600 Hz
180
200
ms
RA
e
e
e
e
e
b
b
b
b
b
Receive Delay, Relative to D
f
f
f
f
f
500 Hz 1000 Hz
40
30
25
20
ms
ms
ms
ms
ms
RR
RA
b
b
b
1000 Hz 1600 Hz
1600 Hz 2600 Hz
70
90
2600 Hz 2800 Hz
b
2800 Hz 3000 Hz
100
145
125
175
NOISE
N
XC
N
XP
N
RC
Transmit Noise, C Message
Weighted
TP3064 (Note 1)
TP3067 (Note 1)
12
15
dBrnC0
dBm0p
b
b
67
Transmit Noise, Psophometric
Weighted
74
Receive Noise, C Message
Weighted
PCM Code Equals Alternating
Positive and Negative Zero
TP3064
8
11
dBrnCO
N
RP
N
RS
Receive Noise, Psophometric
Weighted
PCM Code Equals Positive
Zero
b
b
79
TP3067
82
dBm0p
dBm0
e
b
53
Noise, Single Frequency
f
0 kHz to 100 kHz, Loop Around
e
Measurement, VF Ia 0 Vrms
X
e
CC
a
PPSR
Positive Power Supply Rejection,
Transmit
V
5.0 V
100 mVrms
0 kHz 50 kHz (Note 2)
eb a
100 mVrms
X
DC
e
b
f
40
dBC
dBC
NPSR
Negative Power Supply Rejection,
Transmit
V
BB
5.0 V
DC
X
e
b
0 kHz 50 kHz (Note 2)
f
40
PPSR
Positive Power Supply Rejection,
Receive
PCM Code Equals Positive Zero
a
100 mVrms
R
e
V
5.0 V
DC
CC
Measure VF
O
R
0 Hz 4000 Hz
b
4 kHz 50 kHz
e
e
b
f
f
38
25
dBC
dB
NPSR
Negative Power Supply Rejection,
Receive
PCM Code Equals Positive Zero
R
eb
a
100 mVrms
V
5.0 V
BB
Measure VF
DC
O
R
e
e
e
b
f
f
f
0 Hz 4000 Hz
40
40
36
dBC
dB
b
4 kHz 25 kHz
b
25 kHz 50 kHz
dB
b
0 dBm0, 300 Hz 3400 Hz Input
PCM Code Applied at DR
SOS
Spurious Out-of-Band Signals
at the Channel Output
Measure Individual Image Signals at
VF O
R
b
b
b
4600 Hz–7600 Hz
7600 Hz–8400 Hz
8400 Hz–100,000 Hz
32
40
dB
dB
dB
32
11
Transmission Characteristics (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
e a
e b
e
5.0V 5%; T
A
g
g
5.0V 5%, V
CC
BB
e
production tests and/or product design and characterization. GNDA
0 C to 70 C by correlation with 100% electrical testing at T
25 C. All other limits are assured by correlation with other
§
§
§
A
e
e
0V, f
5.0V, V
e
1.02 kHz, V
0 dbm0, transmit input amplifier
e
IN
5.0V, T
A
e a
e b
connected for unity gain non-inverting. Typicals specified at V
25 C.
§
CC
BB
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DISTORTION
STD
STD
Signal to Total Distortion
Transmit or Receive
Half-Channel
Sinusoidal Test Method (Note 3)
e
X,
Level 3.0 dBm0
e
33
36
29
30
14
15
dBC
dBC
dBC
dBC
dBC
dBC
R
b
0 dBm0 to 30 dBm0
eb
40 dBm0
XMT
RCV
XMT
RCV
eb
55 dBm0
b
b
SFD
SFD
IMD
Single Frequency Distortion,
Transmit
46
46
dB
dB
dB
X
Single Frequency Distortion,
Receive
R
b
Intermodulation Distortion
Loop Around Measurement,
eb
41
VF Ia
4 dBm0 to 21 dBm0, Two
Frequencies in the Range
b
X
b
300 Hz 3400 Hz
CROSSTALK
e b
300 Hz 3000 Hz
CT
X-R
Transmit to Receive Crosstalk
f
e
b
b
b
b
D
Quiet PCM Code
90
90
75
70
dB
dB
R
e
b
e
300 Hz 3000 Hz, VF I 0V
X
CT
R-X
Receive to Transmit Crosstalk
f
(Note 2)
POWER AMPLIFIERS
PA Maximum 0 dBm0 Level
V
O
Balanced Load, R Connected Between
L
(Better than 0.1 dB Linearity over
VPOa and VPOb
.
g
b
a
the Range 10 dBm0 to 3 dBm0)
e
e
R
R
600X
3.3
Vrms
Vrms
L
1200X
3.5
L
e
S/D
Signal/Distortion
R
L
600X
50
dB
P
b
Note 1: Measured by extrapolation from the distortion test result at 50 dBm0.
Note 2: PPSR , NPSR , and CT
X
are measured with a 50 dBm0 activation signal applied to VF Ia
.
b
X
b
X
R
X
Note 3: TP3064 is measured using C message weighted filter. TP3067 is measured using psophometric weighted filter.
12
Applications Information
POWER SUPPLIES
While the pins of the TP3060 family are well protected
against electrical misuse, it is recommended that the stan-
dard CMOS practice be followed, ensuring that ground is
connected to the device before any other connections are
made. In applications where the printed circuit board may be
plugged into a ‘‘hot’’ socket with power and clocks already
present, an extra long ground pin in the connector should
be used.
minimizes the interaction of ground return currents flowing
through a common bus impedance. 0.1 mF supply decou-
pling capacitors should be connected from this common
ground point to V
possible.
and V , as close to the device as
BB
CC
For best performance, the ground point of each CODEC/
FILTER on a card should be connected to a common card
ground in ‘‘STAR’’ formation, rather than via a ground bus.
All ground connections to each device should meet at a
common point as close as possible to the GNDA pin. This
This common ground point should be decoupled to V and
CC
V
with 10 mF capacitors.
BB
Note: See Application Note 370 for further details
Typical Asynchronous Application
TL/H/5070–5
a
R1
R2
t
10 kX
e
c
a
,(R1 R2)
Note 1: Transmit gain
Note 2: Receive gain
20
20
log
log
R2
#
J
c
2
R3
t
e
c
,R4
10 kX
R4
#
J
FIGURE 4
13
Definitions and Timing Conventions
DEFINITIONS
TIMING CONVENTIONS
V
IH
V
is the d.c. input level above which
For the purposes of this timing specification, the following
conventions apply:
IH
an input level is guaranteed to appear
as a logical one. This parameter is to
be measured by performing a
Input Signals
All input signals may be characterized
k
e
e
2.4V, t
as: V
0.4V, V
10 ns,
L
H
R
functional test at reduced clock
speeds and nominal timing, (i.e. not
minimum setup and hold times or
output strobes), with the high level of
k
t
10 ns.
The period of clock signal is
designated as t where xx
F
Period
Pxx
represents the mnemonic of the clock
signal being specified.
all driving signals set to V and
IH
maximum supply voltages applied to
the device
Rise Time
Fall Time
Rise times are designated as t ,
Ryy
where yy represents a mnemonic of
the signal whose rise time is being
V
V is the d.c. input level below which
IL
IL
an input level is guaranteed to appear
as a logical zero to the device. This
parameter is measured in the same
specified. t
Ryy
is measured from V to
IL
V
.
IH
Fall times are designated as t
,
Fyy
manner as V but with all driving
IH
signal low levels set to V and
IL
minimum supply voltages applied to
the device.
where yy represents a mnemonic of
the signal whose fall time is being
specified. t
is measured from V to
IH
Fyy
V
.
IL
Pulse Width High The high pulse width is designated as
, where zz represents the
V
V
V
OH
is the minimum d.c. output level
OH
OL
to which an output placed in a logical
one state will converge when loaded
at the maximum specified load current.
t
WzzH
mnemonic of the input or output signal
whose pulse width is being specified.
High pulse widths are measured from
V
OL
is the maximum d.c. output level
to which an output placed in a logical
zero state will converge when loaded
at the maximum specified load current.
V
to V .
IH
IH
Pulse Width Low The low pulse width is designated as
, where zz represents the
t
WzzL
Threshold Region The threshold region is the range of
.
mnemonic of the input or output signal
whose pulse width is being specified.
Low pulse widths are measured from
input voltages between V and V
IL IH
Valid Signal
A signal is Valid if it is in one of the
valid logic states, (i.e. above V or
IH
V
to V .
IL
IL
below V ). In timing specifiations, a
IL
signal is deemed valid at the instant it
enters a valid state.
Setup Time
Hold Time
Delay Time
Setup times are designated as t ,
Swwxx
where ww represents the mnemonic of
the input signal whose setup time is
being specified relative to a clock or
strobe input represented by mnemonic
xx. Setup times are measured from the
ww Valid to xx Invalid.
Invalid Signal
A signal is Invalid if it is not in a valid
logic state, i.e. when it is in in the
threshold region between V and V
IL
.
IH
In timing specifications, a signal is
deemed Invalid at the instant it enters
the threshold region.
Hold times are designated as t
,
Hxxww
where ww represents the mnemonic of
the input signal whose hold time is
being specified relative to a clock or
strobe input represented by mnemonic
xx. Hold times are measured from xx
Valid to ww Invalid.
Delay times are designated as t
Dxxyy
Hi to Low, where xx represents the
mnemonic of the input reference
signal and yy represents the
mnemonic of the output signal whose
timing is being specified relative to xx.
The mnemonic may optionally be
terminated by an H or L to specify the
high going or low going transition of
the output signal. Maximum delay
times are measured from xx Valid to yy
Valid. Minimum delay times are
measured from xx Valid to yy Invalid.
This parameter is tested under the
load conditions specified in the
Conditions column of the Timing
Specifications section of this data
sheet.
14
15
Physical Dimensions inches (millimeters)
Cavity Dual-In-Line Package (J)
Order Number TP3064J or TP3067J
NS Package Number J20A
Molded Small Outline Package (WM)
Order Number TP3064WM or TP3067WM
NS Package Number M20B
16
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number TP3064N or TP3067N
NS Package Number N20A
17
Ý
Lit. 113975
Physical Dimensions inches (millimeters) (Continued)
Plastic Chip Carrier (V)
Order Number TP3064V or TP3067V
NS Package Number V20A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
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