TP5088WM [NSC]
TP5088 DTMF Generator for Binary Data; TP5088 DTMF生成的二进制数据
| 型号： | TP5088WM |
| 厂家： | 
National Semiconductor |
| 描述： | TP5088 DTMF Generator for Binary Data |
| 文件： | 总6页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1991
TP5088 DTMF Generator for Binary Data
General Description
Features
Y
Direct microprocessor interface
This CMOS device provides low cost tone-dialing capability
in microprocessor-controlled telephone applications. 4-bit
binary data is decoded directly, without the need for conver-
sion to simulated keyboard inputs required by standard
DTMF generators. With the TONE ENABLE input low, the
oscillator is inhibited and the device is in a low power idle
mode. On the low-to-high transition of TONE ENABLE, data
is latched into the device and the selected tone pair from
the standard DTMF frequencies is generated. An open-drain
N-channel transistor provides a MUTE output during tone
generation.
Y
Binary data inputs with latches
Y
Generates 16 standard tone pairs
Y
On-chip 3.579545 MHz crystal-controlled oscillator
Better than 0.64% frequency accuracy
High group pre-emphasis
Y
Y
Y
Y
Y
Y
Low harmonic distortion
MUTE output interfaces to speech network
Low power idle mode
3.5V–8V operation
Block Diagram
TL/H/5004–1
s
e
e
e
5 pF, C 0.02 pF.
1
*Crystal Specification: Parallel Resonant 3.579545 MHz, R
150X, L
100 mH, C
S
0
C
1995 National Semiconductor Corporation
TL/H/5004
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b a
30 C to 70 C
Operating Temperature, T
Storage Temperature
§
55 C to 150 C
§
A
b
a
§
500 mW
§
Maximum Power Dissipation
b
Supply Voltage (V
MUTE Voltage
V
SS
)
12V
12V
DD
Maximum Voltage at
Any Other Pin
a
b
0.3V
V
DD
0.3V to V
SS
Electrical Characteristics
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
e
25 C. All other limits are assured by correlation with other production tests and/
e a
0 C to 70 C by
3.5V to 8V, T
§
§
DD
A
e
correlation with 100% electrical testing at T
or product design and characterization.
§
A
Parameter
Conditions
Min
Typ
Max
Units
Minimum Supply Voltage, V (min)
DD
Generating Tones
3.5
V
Minimum Supply Voltage for Data Input,
TONE ENABLE and MUTE Logic Functions
2
V
Operating Current
Idle
e %
R
, D0–D3 Open
55
350
2.5
mA
L
e
Generating Tones
V
3.5V, Mute Open
1.5
mA
DD
Input Pull-Up Resistance
D0–D3
100
50
kX
kX
TONE ENABLE
Input Low Level
TONE ENABLE, D0–D3
0.2 V
DD
V
Input High Level
TONE ENABLE, D0–D3
0.8 V
DD
V
e
MUTE OUT Sink Current
(TONE ENABLE LOW)
V
V
3.5V
DD
0.4
mA
e
0.5V
o
e
MUTE OUT Leakage Current
(TONE ENABLE HIGH)
V
V
3.5V
DD
DD
1
mA
e
V
o
e
240 X
Output Amplitudes
Low Group
R
L
130
180
170
230
220
310
mVrms
mVrms
e
V
T
3.5V
DD
e
High Group
25 C
§
A
e
e
Mean Output DC Offset
V
3.5V
8V
1.2
3.6
V
V
DD
V
DD
High Group Pre-Emphasis
2.2
2.7
3.2
dB
dB
e
5V
Dual Tone/Total Harmonic Distortion Ratio
1 MHz Bandwidth, V
DD
b
20
e
R
L
240X
Start-Up Time (to 90% Amplitude), t
OSC
4
ms
ns
ns
ns
e
Data Set-Up Time, t (Figure 2)
S
V
DD
V
DD
V
DD
5V
5V
5V
100
e
e
Data Hold Time, t
280
600
H
Data Duration t
W
Note 1: R is the external load resistor connected from TONE OUT to V
L
.
SS
2
Connection Diagram
Dual-In-Line Package
TL/H/5004–2
Top View
Order Number TP5088WM or TP5088N
See NS Package M14B or N14A
3.579545 MHz A-cut crystal (NTSC TV color-burst) is need-
ed between pins 6 and 7. Load capacitors and a feedback
resistor are included on-chip for good start-up and stability.
The oscillator is stopped when the TONE ENABLE input is
pulled to logic low.
Functional Description
With the TONE ENABLE pin pulled low, the device is in a
low power idle mode, with the oscillator inhibited and the
output transistor turned off. Data on inputs D0–D3 is ig-
nored until a rising transition on TONE ENABLE. Data meet-
ing the timing specifications is latched in, the oscillator and
output stage are enabled, and tone generation begins. The
decoded data sets the high group and low group program-
mable counters to the appropriate divide ratios. These
counters sequence two ratioed-capacitor D/A converters
through a series of 28 equal duration steps per sine wave
cycle. On-chip regulators ensure good stability of tone am-
plitudes with variations in supply voltage and temperature.
The two tones are summed by a mixer amplifier, with pre-
emphasis applied to the high group tone. The output is an
NPN emitter-follower requiring the addition of an external
TONE ENABLE Input (Pin 2): This input has an internal
pull-up resistor. When TONE ENABLE is pulled to logic low,
the oscillator is inhibited and the tone generators and output
transistor are turned off. A low to high transition on TONE
ENABLE latches in data from D0–D3. The oscillator starts,
and tone generation continues until TONE ENABLE is
pulled low again.
MUTE (Pin 8): This output is an open-drain N-channel de-
vice that sinks current to V when TONE ENABLE is low
SS
and no tones are being generated. The device turns off
when TONE ENABLE is high.
D0, D1, D2, D3 (Pins 9, 10, 11, 12): These are the inputs for
binary-coded data, which is latched in on the rising edge of
TONE ENABLE. Data must meet the timing specifications of
Figure 2. At all other times these inputs are ignored and may
be multiplexed with other system functions.
load resistor to V
.
SS
Table I shows the accuracies of the tone output frequencies
and Table II is the Functional Truth Table.
TABLE I. Output Frequency Accuracy
TONE OUT (Pin 14): This output is the open emitter of an
NPN transistor, the collector of which is connected internal-
Tone
Standard
Tone Output
Frequency
% Deviation
Group DTMF (Hz)
from Standard
ly to V . When an external load resistor is connected from
DD
TONE OUT to V , the output voltage on this pin is the sum
SS
b
a
a
b
Low
697
770
852
941
694.8
770.1
852.4
940.0
0.32
0.02
0.03
0.11
of the high and low group tones superimposed on a DC
offset. When not generating tones, this output transistor is
turned off to minimize the device idle current.
Group
f
L
SINGLE TONE ENABLE (Pin 3): This input has an internal
pull-up resistor. When pulled to V , the device is in single
SS
tone mode and only a single tone will be generated at pin 14
(for testing purposes). For normal operation, leave this pin
b
b
a
a
High
1209
1336
1477
1633
1206.0
1331.7
1486.5
1639.0
0.24
0.32
0.64
0.37
Group
f
H
open-circuit or pull to V
.
DD
GROUP SELECT (Pin 4): This pin is used to select the high
group or low group frequency when the device is in single
tone mode. It has an internal pull-up resistor. Leaving this
Pin Descriptions
(Pin 1): This is the positive supply to the device, refer-
V
DD
pin open-circuit or pulling it to V
will generate the high
DD
enced to V . The collector of the TONE OUT transistor is
SS
also connected to this pin.
group, while pulling to V will generate the low group fre-
SS
quency at the TONE OUT pin.
V
(Pin 5): This is the negative voltage supply. All voltages
are referenced to this pin.
SS
OSC IN, OSC OUT (Pins 6 and 7): All tone generation tim-
ing is derived from the on-chip oscillator circuit. A low-cost
3
TABLE II. Functional Truth Table
Keyboard
Equivalent
Data Inputs
TONE
TONES OUT
MUTE
ENABLE
D3
D2
D1
D0
f
L
(Hz)
f (Hz)
H
X
1
2
3
4
5
6
7
8
9
0
*
X
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
X
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
X
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0V
0V
0V
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
O/C
Ý
A
B
C
D
Timing Diagram
Typical Application
TL/H/5004–4
*Adjust R for desired tone amplitude.
TL/H/5004–3
E
FIGURE 2
FIGURE 3
4
Physical Dimensions inches (millimeters)
Order Number TP5088WM
NS Package Number M14B
5
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line (N)
Order Number TP5088N
NS Package Number N14A
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