NTE27C256-15D [NTE]
UVPROM, 32KX8, 150ns, CMOS, PDIP28, DIP-28;
| 型号： | NTE27C256-15D |
| 厂家： | 
NTE ELECTRONICS |
| 描述： | UVPROM, 32KX8, 150ns, CMOS, PDIP28, DIP-28 可编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总7页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTE27C256−12D, NTE27C256−15D, NTE27C256−70D
Integrated Circuit
256 Kbit (32Kb x 8) UV−EPROM
28−Lead DIP Type Package
NTE27C256−15P
Integrated Circuit
256 Kbit (32Kb x 8) OTP−EPROM
28−Lead DIP Type Packag
Description:
The NTE27C256 is a 256Kbit EPROM in a 28−Lead DIP type package ideally suited for microproces-
sor systems requiring large programs and is organized as 32,768 by 8 bits. The NTE27C256−12D,
NTE27C256−15D, and NTE27C256−70D have a transparent lid which allows the user to expose the
chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by follow-
ing the programming procedure. The NTE27C256−15P is suitable for applications where the content
is programmed only one time and erasure is not required.
Features:
D 5V 10% Supply Voltage in Read Operation
D Access Time: 45ns
D Low Power “CMOS” Consumption:
− Active Current 30mA at 5MHz
− Standby Current 100A
D Programming Voltage: 12.75V 0.25V
D Programming Time: 100s/Word
Absolute Maximum Ratings: (Note 1)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −2 to +7V
Input or Output Voltage (Except A9, Note 2), VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −2 to +7V
A9 Voltage (Note 2), VA9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −2 to +13.5V
Program Supply Voltage, VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −2 to +14V
Ambient Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 to +125C
Temperature Under Bias Range, TBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 to +125C
Storage Temperature Range, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to +150C
Note 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the
table “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only and operation of the device at these or any other conditions above those
indicated in the Operating sections of this specification is not implied. Exposure to Absolute
Maximum Rating conditions for extended periods may affect device reliability.
Note 2. Minimum DC voltage on the input or output is −0.5V with possible undershoot to −2.0V for
a period less than 20ns. Maximum DC voltage on output is VCC +0.5V with possible over-
shoot to VCC +2V for a period less than 20ns.
Rev. 10−18
Device Operation:
The modes of operation of the NTE27C256 are listed in the Operating Modes table. A single power
supply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9.
Read Mode:
The NTE27C256 has two control functions, both of which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power control and should be used for device selection.
Output Enable (G) is the output control and should be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the addresses are stable, the address access time (tAVQV
)
is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from
the falling edge of G, assuming that E has been low and the addresses have been stable for at least
tAVQV−tGLQV
.
Operating Modes:
Mode
E
VIL
G
A9
X
VPP
VCC
VCC
VPP
VPP
VPP
VCC
Q7−Q0
Data Out
Hi−Z
Read
VIL
VIH
VIH
VIL
VIH
X
Output Disable
VIL
X
Program
VIL Pulse
VIH
X
Data Input
Data Output
Hi−Z
Verify
X
Program Inhibit
VIH
X
Standby
VIH
X
Hi−Z
Note: X = VIH or VIL, VID = 12V 0.5V.
Capacitance: (TA = +25C, f = 1MHz, Note 3 unless otherwise specified)
Parameter
Input Capacitance
Output Capacitance
Symbol
Test Conditions
VIN = 0V
Min Typ Max Unit
CIN
−
−
−
−
6
pF
pF
COUT VOUT = 0V
12
Note 3. Sampled only, not 100% tested.
Standby Mode:
The NTE27C256has a standby mode which reduces the supply current from 30mA to 100A. The
NTE27C256 is placed in the standby mode by applying a CMOS high signal to the E input. When in
the standby mode, the outputs are in a high impedance state, independent of the G input.
Two Line Output Control:
Because EPROMs are usually used in larger memory arrays, this product features a 2 line control
function which accommodates the use of multiple memory connection. The two line control function
allows:
a. The lowest possible memory power dissipation,
b. Complete assurance that output bus connection will not occur.
For the most efficient use of these two control lines, E should be decoded and used as the primary
device selecting function, while G should be made a common connection to all devices in the array
and connected to the READ line from the system control bus. This ensures that all deselected memory
devices are in their low power standby mode and that the output pins are only active when data is
required from a particular memory device.
Read Mode DC Characteristics: (TA = 0 to +70C, VCC = 5V 10%, VPP = VCC, Note 4 unless
otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Symbol
ILI
Test Conditions
Min
−
Typ Max Unit
0V VIN VCC
−
−
−
10
10
30
A
A
ILO
0V VOUT VCC
−
ICC
E = VIL, G = VIL, IOUT = 0mA,
f = 5MHz
−
mA
Supply Surrent (Standby)
TTL
ICC1
ICC2
IPP
E = VIH
−
−
−
−
−
−
−
−
1
100
100
0.8
mA
A
A
V
CMOS
E > VCC −0.2V
VPP = VCC
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
−
VIL
−0.3
2
VIH
VOL
Note 5
VCC+1
0.4
V
IOL = 2.1mA
−
V
Output High Voltage
TTL
VOH
IOH = −400A
IOH = −100A
2.4
−
−
−
−
V
V
CMOS
VCC−0.7
Note 4. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Note 5. Maximum DC voltage on output is VCC +0.5V.
System Considerations:
The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three segments that are of interest to the system designer: the
standby current level, the active current level, and transient current peaks that are produced by the
falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capaci-
tive and inductive loading of the device at the output. The associated transient voltage peaks can be
suppressed by complying with the two line output control and by properly selected decoupling capaci-
tors. It is recommended that a 0.1F ceramic capacitor be used on every device between VCC and
VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as
close to the device as possible. In addition, a 4.7F bulk electrolytic capacitor should be used between
VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply
connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the
inductive effects of PCB traces.
Read Mode AC Characteristics: (TA = 0 to +70C, VCC = 5V 10%, VPP = VCC, Note 4 unless
otherwise specified)
Parameter
Symbol Alt.
Test Conditions
Min Typ Max Unit
Address Valid To Output Valid
NTE27C256−70D
tAVQV tACC E = VIL , G = VIL
−
−
−
−
−
−
70
ns
ns
ns
NTE27C256−12D
120
150
NTE27C256−15D, NTE27C256−15P
Chip Enable Low To Output Valid
NTE27C256−70D
tELQV
tCE G = VIL
−
−
−
−
−
−
70
ns
ns
ns
NTE27C256−12D
120
150
NTE27C256−15D, NTE27C256−15P
Note 4. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Read Mode AC Characteristics (Cont’d): (TA = 0 to +70C, VCC = 5V 10%, VPP = VCC, Note 4
unless otherwise specified)
Parameter
Symbol Alt.
tGLQV
Test Conditions
Min Typ Max Unit
Output Enable Low To Output Valid
NTE27C256−70D
tOE E = VIL
−
−
−
−
−
−
35
60
65
ns
ns
ns
NTE27C256−12D
NTE27C256−15D, NTE27C256−15P
Chip Enable High To Output Hi−Z
NTE27C256−70D
tEHQZ
tDF G = VIL, Note 3
0
0
0
−
−
−
30
40
50
ns
ns
ns
NTE27C256−12D
NTE27C256−15D, NTE27C256−15P
Output Enable High To Output Hi−Z
NTE27C256−70D
tGHQZ
tDF E = VIL, Note 3
0
0
0
0
−
−
−
−
30
40
50
−
ns
ns
ns
ns
NTE27C256−12D
NTE27C256−15D, NTE27C256−15P
Address Transition To Output Transition
tAXQX
tOH E = VIL , G = VIL
Note 3. Sampled only, not 100% tested.
Note 4. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Programming Mode DC Characteristics: (TA = +25C, VCC = 6.25V 0.25V, VPP = 12.75V 0.25V,
Note 4 unless otherwise specified)
Parameter
Input Leakage Current
Supply Current
Symbol
ILI
Test Conditions
VIL VIN VIH
Min Typ
Max
10
50
Unit
A
mA
mA
V
−
−
−
−
−
−
−
−
−
−
ICC
Program Current
IPP
E = VIL
−
50
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage, TTL
A9 Voltage
VIL
−0.3
2
0.8
VIH
VCC+0.5
0.4
V
VOL
VOH
VID
IOL = 2.1mA
−
V
IOH = −1mA
3.6
11.5
−
V
12.5
V
Note 4. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Programming Mode AC Characteristics: (TA = +25C, VCC = 6.25V 0.25V, VPP = 12.75V 0.25V,
Note 4 unless otherwise specified)
Parameter
Symbol Alt.
tAVEL tAS
tQVEL tDS
tVPHEL tVPS
tVCHEL tVCS
tELEH tPW
Test Conditions Min Typ Max Unit
Address Valid To Chip Enable Low
Input Valid To Chip Enable Low
VPP High To Chip Enable Low
VCC High To Chip Enable Low
Chip Enable Program Pulse Width
2
2
−
−
−
−
−
−
−
s
s
s
s
s
2
−
2
−
95
105
Note 4. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Programming Mode AC Characteristics (Cont’d): (TA = +25C, VCC = 6.25V 0.25V,
PP = 12.75V 0.25V, Note 4 unless otherwise specified)
V
Parameter
Symbol Alt.
Test Conditions Min Typ Max Unit
Chip Enable High To Input Transition
Input Transition To Output Enable Low
Output Enable Low To Output Valid
Output Enable High To Output Hi−Z
tEHQX
tQXGL
tGLQV
tGHQZ
tDH
tOES
tOE
2
2
−
0
0
−
−
−
−
−
−
−
s
s
ns
ns
ns
100
130
−
tDFP
tAH
Output Enable High To Address Transition tGHAX
Note 4. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Programming:
When delivered (and after each erasure for UV EPROM), all bits of the NTE27C256 are in the “1”
state. Data is introduced by selectively programming “0”s into the desired bit locations. Although only
“0”s will be programmed, both “1”s and “0”s can be present in the data word. The only way to change
a “0” to a “1” is by die exposure to ultraviolet light (UV EPROM). The NTE27C256 is in the program-
ming mode when VPP input is at 12.75V, G is at VIL and E is pulsed to VIL. The data to be programmed
is applied to 8 bits in parallel to the data output pins. The levels required for the address and data
inputs are TTL. VCC is specified to be 6.25V 0.25V.
Program Inhibit:
Programming of multiple NTE27C256s in parallel with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel NTE27C256 may be common. A TTL low level pulse
applied to an NTE27C256’s E input, with VPP at 12.75V, will program that NTE27C256. A high level
E input inhibits the other NTE27C256s from being programmed.
Program Verify:
A verify (read) should be performed on the programmed bits to determine that they were correctly
programmed. The verify is accomplished with G at VIL, E at VIH, VPP at 12.75V and VCC at 6.25V.
Erasure Operation:
The erasure characteristics of the NTE27C256 is such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than approximately 4000Å. It should be noted that sunlight
and some type of fluorescent lamps have wavelengths in the 3000−4000Å range. Research shows
that constant exposure to room level fluorescent lighting could erase a typical NTE27C256 in about
3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight.
If the NTE27C256 is to be exposed to these types of lighting conditions for extended periods of time,
it is suggested that opaque labels be put over the NTE27C256 window to prevent unintentional era-
sure. The recommended erasure procedure for the NTE27C256 is exposure to short wave ultraviolet
light which has a wavelength of 2537Å. The integrated dose (i.e. UV intensity x exposure time) for
erasure should be a minimum of 15W−sec/cm2. The erasure time with this dosage is approximately
15 to 20 minutes using an ultraviolet lamp with 12000W/cm2 power rating. The NTE27C256 should
be placed within 2.5cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their
tubes which should be removed before erasure.
Pin Connection Diagram
VPP
A12
A7
1
2
3
28
VCC
27 A14
26
A13
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
25 A8
24 A9
23
22
A11
G
21 A10
20
E
19 Q7
18 Q6
17 Q5
16 Q4
11
Q0
Q1 12
13
Q2
VSS 14
15
Q3
NTE27C256−12D
NTE27C256−15D
NTE27C256−70D
1.470 (37.34) Max
28
1
15
.526
(13.36)
Max
14
.225 (5.72) Max
.125 (3.18) Min
.100 (2.54)
NTE27C256−15P
28
1
15
14
.570 (14.48)
Max
1.4598 (37.08) Max
.175
(4.45)
.100 (2.54)
1.300 (33.02)
.130
(3.3)
Min
.523 (14.8)
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