NTE6664 [NTE]
Integrated Circuit 64K-Bit Dynamic RAM; 集成电路64K位动态随机存储器
| 型号： | NTE6664 |
| 厂家： | 
NTE ELECTRONICS |
| 描述： | Integrated Circuit 64K-Bit Dynamic RAM |
| 文件： | 总5页 (文件大小：42K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTE6664
Integrated Circuit
64K–Bit Dynamic RAM
Description:
The NTE6664 is a 65,536 Bit, high–speed, dynamic Random Access Memory. Organized as 65,536
one–bit words and fabricated using HMOS high–performance N–Channel silicon–gate technology,
this 5V only dynamic RAM combines high performance with low cost and improved reliability.
By multiplying row– and column– address inputs, the NTE6664 requires only eight address lines and
permits packaging in a standard 16–Lead DIP package. Complete address decoding is done on chip
with address latches incorporated. Data out is controlled by CAS allowing for greater system flexibility.
All inputs and outputs, including clocks, are fully TTL compatible. The NTE6664 incorporates a one–
transistor cell design and dynamic storage techniques. In addition to the RAS–only refresh mode,
the refresh control function available on Pin1 provides two additional modes of refresh, automatic and
self refresh.
Features:
D Single +5V Operation (±10%)
D 128 Cycle, 2ms Refresh
D Control on Pin1 for Automatic or Self Refresh
D RAS–Only Refresh Mode
D Maximum Access Time: 150ns
D Low Power Dissipation:
302.5mW Max (Active)
22mW Max (Standby)
D CAS Controlled Output
D Fast Page Mode Cycle Time
D Low Soft Error Rate: < 0.1% per 1000 Hrs
D Three State Data Output
D Early–Write Common I/O Capability
Absolute Maximum Ratings: (Note 1)
Voltage on VCC Supply Relative to VSS, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2 to +7V
Voltage Relative to VSS for Any Pin Except VCC, Vin, Vout . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 to +7V
Data Out Current (Short Circuit), Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70°C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C
Note 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS.
Exposure to higher than recommended voltages for extended periods of time could affect
the device reliability.
Recommended Operating Conditions: (Note 2, TA = 0 to +70°C unless otherwise specified)
Parameter
Symbol
Min Typ Max Unit
Supply Voltage (Operating Voltage Range)
V
4.5
0
5.0
0
5.5
0
V
V
V
V
CC
V
SS
Logic 1 Voltage, All Inputs
V
2.4
–1.0
–
6.5
0.8
IH
Logic 0 Voltage, All Inputs (Note 3)
V
–
IL
Note 2. All voltages referenced to VSS.
Note 3. The device will withstand undershoots to the –2V level with a maximum pulse width 0f 20ns
at the –1.5V level. This is periodically sampled rather than 100% tested.
DC Characteristics: (VCC = 5V ±10%, TA = 0 to +70°C unless otherwise specified)
Parameter
Symbol
Test Conditions
t = 270ns, Note 4
RC
Min Typ Max Unit
V
CC
V
CC
V
CC
Power Supply Current
I
I
I
–
–
–
–
–
–
55
4
mA
mA
mA
CC1
CC2
CC3
Power Supply Current (Standby)
RAS = CAS = V
IH
Power Supply Current During
RAS only Refresh Cycles
t
= 270ns, Note 4
45
RC
Input Leakage Current
I
V
V
< V < V
–
–
10
µA
lkg(L)
SS
in
CC
Any Input Except REFRESH
REFRESH Input Current
Output Leakage Current
Output Logic 1 Voltage
Output Logic 0 Voltage
I
< V < V
–
–
–
–
–
–
20
10
–
µA
µA
V
lkg(F)
SS
in
CC
I
CAS at Logic 1, 0 ≤ V ≤ 5.5V
out
lkg(O)
V
I
out
I
out
= –4mA
2.4
–
OH
V
= 4mA
0.4
V
OL
Note 4. Current is a function of cycle rate and output loading; maximum current is measured at the
fastest cycle rate with the output open.
Capacitance: (VCC = 5V ±10%, f = 1MHz, TA = +25°C, Note 5, Periodically Sampled Rather
Than 100% Tested)
Parameter
Input Capacitance
RAS, CAS, WRITE, REFRESH
Output Capacitance
Symbol
Test Conditions
Min Typ Max Unit
A0 – A7, D
C
in
–
–
3
6
5
8
pF
Q
C
out
CAS = V to Disable Output
–
5
7
pF
IH
Note 5. Capacitance measured with a Boonton Meter or effective capacitance calculated from the
equation: C = I∆t/∆V.
Read, Write, and Read–Modify–Write Cycles: (VCC = 5V ±10%, TA = 0 to +70°C unless other–
wise specified, Notes 6, 7, and 8)
Parameter
Random Read or Write Cycle Time
Read–Write Cycle Time
Access Time from RAS
Access Time from CAS
Output Buffer and Turn–Off Delay
RAS Precharge Time
Symbol
Test Conditions
Note 9, Note 10
Note 9, Note 10
Note 11, Note 13
Note 12, Note 13
Note 19
Min Typ
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
t
270
280
–
–
–
–
–
–
–
–
–
RC
t
–
RWC
t
150
75
RAC
CAC
t
–
t
0
30
OFF
t
100
150
75
–
RP
RAS Pulse Width
t
t
10000
10000
RAS
CAS
CAS Pulse Width
Read, Write, and Read–Modify–Write Cycles (Cont’d): (VCC = 5V ±10%, TA = 0 to +70°C
unless otherwise specified, Notes 6, 7, and 8)
Parameter
RAS to CAS Delay Time
Symbol
Test Conditions
Min Typ
Max
75
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Note 14
25
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
RCD
Row Address Setup Time
t
ASR
RAH
Row Address Hold Time
t
20
0
–
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time Referenced to RAS
Transition Time (Rise and Fall)
Read Command Setup Time
Read Command Hold Time Referenced to CAS
Read Command Hold Time Referenced to RAS
Write Command Hold Time
t
–
ASC
CAH
t
35
95
3
–
t
AR
Note 18
–
t
T
50
–
t
0
RCS
RCH
RRH
t
t
Note 15
Note 15
0
–
0
–
t
35
95
35
45
45
0
–
WCH
WCR
Write Command Hold Time Referenced to RAS
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data in Setup Time
t
Note 18
–
t
–
WP
t
–
RWL
CWL
t
–
t
Note 16
Note 16
Note 18
–
DS
DH
Data in Hold Time
t
35
95
–10
75
–
–
Data in Hold Time Referenced to RAS
CAS to RAS Precharge Time
RAS Hold Time
t
–
DHR
t
t
–
CRP
–
RSH
Refresh Period
t
2
RFSH
Write Command Setup Time
CAS to Write Delay
t
Note 17
Note 17
Note 17
–10
45
120
150
60
145
–10
2000
320
–
WCS
CWD
RWD
t
t
–
RAS to Write Delay
–
CAS Hold Time
t
–
CSH
CAS Precharge Time (Page Mode Cycle Only)
Page Mode Cycle Time
t
t
–
CP
–
PC
RAS to REFRESH Delay
t
–
RFD
REFRESH Period (Battery Backup Mode)
t
–
FBP
REFRESH to RAS Precharge Time
(Battery Backup Mode)
t
–
FBR
REFRESH Cycle Time (Auto Pulse Mode)
REFRESH Pulse Period (Auto Period Mode)
REFRESH to RAS Setup Time (Auto Pulse Mode)
REFRESH to RAS Delay Time (Auto Pulse Mode)
REFRESH Inactive Time
t
270
60
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
FC
t
2000
FP
t
–30
320
60
–
–
–
–
–
FSR
FRD
t
t
t
FI
FRL
RAS to REFRESH Lead Time
370
370
RAS Inactive Time During REFRESH
t
FRI
Note 6. VIH min and VIL max are reference levels for measuring timing of input signals. Transition
times are measured between VIH and VIL.
Note 7. An initial pause of 100µs is required after power–up followed by 8 RAS cycles before proper
device operation is guaranteed.
Note 8. The transition time specification applies for all input signals. In addition to meeting the transi-
tion rate specification, all input signals must transmit between VIH and VIL (or between VIL
and VIH) in a monotonic manner.
Note 9. The specification for tRC(min) and tRMW(min) are used only to indicate cycle time at which
proper operation over the full temperature range (0°C ≤ TA ≤ +70°C) is assured.
Note10. AC measurements tT = 5ns.
Note11. Assumes that tRCD ≤ tRCD(max).
Note12. Assumes that tRCD ≥ tRCD(max).
Note13. Measured with a current load equivalent to 2 TTL (–200µA, +4mA) loads and 100pF with the
data output trip points set at VOH = 2V and VOL = 0.8V.
Note14. Operation within the tRCD(max) limit ensures that tRAC(max) can be met, tRCD(max) is speci-
fied as a reference point only; if tRCD is greater than the specified tRCD(max) limit, then ac-
cess time is controlled exclusively by tCAC
.
Note15. Either tRRH or tRCH must be satisfied for a read cycle.
Note16. These parameters are referenced to CAS leading edge in random write cycles and to WRITE
leading edge in delayed write or read–modify–write cycles.
Note17. tWCS, tCWD, and tRWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if tWCS ≥ tWCS(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle;
if tCWD ≥ tCWD(min) and tRWD ≥ tRWD(min), the cycle is read–write cycle and the data out will
contain data read from the selected cell; if neither of the above sets of conditions is satisfied,
the condition of the data out (at access time) is indeterminate.
Note19. tOFF(max) defines the time at which the output achieves the open circuit condition and is not
referenced to output voltage levels.
Block Diagram
V
V
CC
SS
Precharge
Clock
Memory
Array
Memory
Array
RAS
A0
A1
A2
A3
A4
A5
A6
A7
Row Decoder
Row Decoder
CAS
Memory
Array
Memory
Array
Write, W
REFRESH
Data In, D
Output Data, Q
Memory
Array
Memory
Array
Row Decoder
Row Decoder
Memory
Array
Memory
Array
Precharge
Clock
Pin Connection Diagram
1
16
15
* REFRESH
VSS
D 2
CAS
3
4
14 Q
W
13 A6
RAS
A0 5
12
A3
A1 6
A2 7
11 A4
10 A5
8
9 A7
VCC
* If pin is not used, it should be connected to VCC through a 10k resistor.
16
1
9
8
.260 (6.6)
Max
.870 (22.0) Max
.200
(5.08)
Max
.100 (2.54)
.099 (2.5) Min
.700 (17.78)
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