NTE8542 [NTE]
Integrated Circuit Tri−State Quad I/O Register; 集成电路三州四I / O寄存器
| 型号： | NTE8542 |
| 厂家： | 
NTE ELECTRONICS |
| 描述： | Integrated Circuit Tri−State Quad I/O Register |
| 文件： | 总4页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTE8542
Integrated Circuit
Tri−State Quad I/O Register
General Description:
The NTE8542 is a 4−bit storage register with two terminals per bit which may be used as either inputs
or outputs when tied to two bus lines. Storage capability is obtained with positive edge triggered flip−
flops having common clock and asynchronous clear. Each I/O terminal can be forced to a high imped-
ance state (Hi−z state) using the Output Disable controls.
Features:
D Series 54/74 compatible
D Input clamp diodes
D Propagation delays . . . . . . . 25ns
D Power dissipation . . . . . . 400mW
D Operation . . . . . . . . . . . . . 40MHz
Absolute Maximum Ratings: (Note 1)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Input Voltage, Vi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
Recommended Operating Conditions:
Parameter
Symbol Min Max Unit
Supply Voltage
Temperature
VCC
TA
4.75 5.25
+70
V
0
°C
Note 1. “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot
be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that
the devices should be operated at these limits. The table of “Electrical Characteristics” pro-
vides conditions for actual device operation.
Electrical Characteristics: (Notes 2 and 3)
Parameter
Logical “1” Input Voltage
Logical “1” Input Current
Symbol
VIH
Test Conditions
VCC = Min
Min Typ Max Unit
2.0
−
−
V
IIH
VCC = Max, VIN = 2.4V
VCC = Max, VIN = 5.5V
−
−
−
−
40
1.0
μA
Logical “0” Input Voltage
Logical “0” Input Current
Input Clamp Voltage
VIL
IIL
VCC = Min
−
−
−
−
0.8
V
VCC = Max, VIN = 0.4V
VCC = Min, IIN = −12mA
−1.0 −1.6 mA
VCD
VOH
IOS
−
−
−
−1.5
V
V
Logical “1” Output Voltage
Output Short Circuit Current
VCC = Min, IOUT = −800μ 2.4
−
VCC = Max, VOUT = 0V,
Note 4
−25
−70 mA
Logical “0” Output Voltage
Supply Current
VOL
ICC
VCC = Min, IOUT = 16mA
VCC = Max
−
−
−
−
0.4
V
120 mA
TRI−STATE I/O Current with
VCC = Max, VIN = 2.4V
VCC = Max, VIN = 0.4V
−
−
−
−
40
−40
μA
ns
ns
ns
ns
Inputs and Outputs Disabled
Propagation Delay to a Logical “0”
from Clock to Output
tpd0
tpd0
tpd1
t1H
RL = 400Ω, CL = 50pF
TA = 25°C
−
−
−
−
23
24
25
35
36
38
Propagation Delay to a Logical “0”
from Clear to Output
RL = 400Ω, CL = 50pF
TA = 25°C
Propagation Delay to a Logical “1”
from Clock to Output
RL = 400Ω, CL = 50pF
TA = 25°C
Delay from Disable to High
Impedance State
RL = 400Ω, CL = 5.0pF
TA = 25°C
6.0 15
(from Logical “1” Level)
Delay from Disable to High
Impedance State
t0H
tH1
tH0
RL = 400Ω, CL = 5.0pF
TA = 25°C
−
−
−
15
20
17
25
30
25
ns
ns
ns
(from Logical “0” Level)
Delay from Disable to Logical
“1” Level
RL = 400Ω, CL = 50pF
TA = 25°C
(from High Impedance State)
Delay from Disable to Logical
“0” Level
RL = 400Ω, CL = 50pF
TA = 25°C
(from High Impedance State)
Maximum Clock Frequency
Enable to Clock Set−Up Time
Enable to Clock Set−Up Time
fMAX
tSO
tSI
RL = 400Ω, CL = 50pF
TA = 25°C
30
20
20
40
13
12
−
−
−
MHz
ns
RL = 400Ω, CL = 50pF
TA = 25°C
RL = 400Ω, CL = 50pF
TA = 25°C
ns
Electrical Characteristics (Cont’d): (Notes 2 and 3)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Date to Clock Set−Up Time
tSO
RL = 400Ω, CL = 50pF
TA = 25°C
10 4.5
5.0 −4.0
10 4.5
5.0 −3.5
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
Date to Clock Set−Up Time
Data to Clock Hold Time
Data to Clock Hold Time
Minimum Clock Pulse Width
Minimum Clear Pulse Width
tSI
tHO
tHI
RL = 400Ω, CL = 50pF
TA = 25°C
RL = 400Ω, CL = 50pF
TA = 25°
RL = 400Ω, CL = 50pF
TA = 25°C
PWMIN RL = 400Ω, CL = 50pF
TA = 25°C
20
20
−
−
PWMIN RL = 400Ω, CL = 50pF
TA = 25°C
Note 2. Unless otherwise specified min/max limits apply across the 0°C to +70°C range for the
NTE8542. All typicals are given for VCC = 5.0V and TA = 25°C.
Note 3. All currents into device pins shown as positive, out of device pins as negative, all voltages
referenced to GND unless otherwise noted. All values shown as max or min on absolute
value basis.
MODE OF OPERATION:
CLEAR
DIS1
DIS2
E1
1
E2
1
A1 − 4
Q
B1 − 4
Hi−z
Q
Comments
0
0
0
0
0
1
0
1
1
0
0
1
Output Data to Bus A
Output Data to Bus B
Output Data to Both Buses
1
1
Hi−z
Q
1
1
Q
1
1
Hi−z
Hi−z
Store Data With Outputs
in Hi−z State
0
0
0
X
X
X
X
X
X
0
1
0
1
0
0
Data
QN
QN
Enter Data From Bus A
Data Enter Data From Bus B
Data
Data Enter Data From Both
Buses (Logic “1” on Either
Will Dominate)
1
X
X
X
X
X
X
Clear
X
= Don’t Care State
QN = Data After Clock Transition
Pin Connection Diagram
DIS
1
2
3
16 V
CC
2
DIS
A1
B1
15
1
14 A4
B2
A2
4
5
13
B4
12 B3
11 A3
E2
E1
6
7
10 Clock
Clear
GND
8
9
16
9
1
8
.870 (22.0)
.260
(6.6)
Max
Max
.200 (5.08)
Max
.100 (2.54)
.099 (2.5) Min
.700 (17.78)
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