M25PX32-VMP6EB [NUMONYX]
Flash, 4MX8, PDSO8,;
| 型号： | M25PX32-VMP6EB |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 4MX8, PDSO8, 光电二极管 |
| 文件： | 总68页 (文件大小：1496K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M25PX32
32-Mbit, dual I/O, 4-Kbyte subsector erase,
serial Flash memory with 75 MHz SPI bus interface
Features
SPI bus compatible serial interface
75 MHz (maximum) clock frequency
2.7 V to 3.6 V single supply voltage
Dual input/output instructions resulting in an
VFQFPN8 (MP)
6 × 5 mm
equivalent clock frequency of 150 MHz:
– Dual Output Fast Read instruction
– Dual Input Fast Program instruction
32 Mbit Flash memory
– Uniform 4-Kbyte subsectors
– Uniform 64-Kbyte sectors
SO8W (MW)
208 mils
Additional 64-byte user-lockable, one-time
programmable (OTP) area
Erase capability
– Subsector (4-Kbyte) granularity
– Sector (64-Kbyte) granularity
– Bulk Erase (32 Mbit) in 34 s (typical)
Write protections
– Software write protection applicable to
every 64-Kbyte sector (volatile lock bit)
SO16 (MF)
300 mils
– Hardware write protection: protected area
size defined by three non-volatile bits (BP0,
BP1 and BP2)
Deep Power-down mode: 5 μA (typical)
Electronic signature
– JEDEC standard two-byte signature
(7116h)
– Unique ID code (UID) with16 bytes read-
only, available upon customer request
TBGA24 (ZM) 6x8 mm
More than 100 000 write cycles per sector
More than 20 year data retention
Packages
– RoHS compliant
Automotive Certified Parts Available
March 2009
Rev 10
1/68
www.numonyx.com
1
Contents
M25PX32
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Serial Data output (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Data input (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Protect/Enhanced Program supply voltage (W/VPP) . . . . . . . . . . . . 10
V
V
CC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Dual Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . 13
Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13
Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 14
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7.1
4.7.2
Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . 16
4.8
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1
6.2
6.3
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/68
M25PX32
Contents
6.4
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.5
6.6
6.7
6.8
6.9
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Read Data Bytes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . 34
Dual Output Fast Read (DOFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.10 Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.11 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.12 Dual Input Fast Program (DIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.13 Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.14 Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.15 Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.16 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.17 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.18 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.19 Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . 49
7
Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8
9
10
11
12
13
3/68
List of tables
M25PX32
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Software protection truth table (Sectors 0 to 63, 64 Kbyte granularity) . . . . . . . . . . . . . . . 16
Protected area sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Lock Register out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Lock Register in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Data Retention and Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
VFQFPN8 (MLP8) 8-lead very thin fine pitch dual flat package no lead,
6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SO8W 8-lead plastic small outline, 208 mils body width, package
Table 20.
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SO16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data . . . . . . . 62
TBGA 6x8 mm 24-ball package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 21.
Table 22.
Table 23.
Table 24.
4/68
M25PX32
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VFQFPN and SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
BGA 6x8 24 ball ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write Enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 28
Figure 12. Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 30
Figure 13. Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 33
Figure 15. Read Data Bytes at higher speed (FAST_READ) instruction sequence
and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 16. Dual Output Fast Read instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17. Read Lock Register (RDLR) instruction sequence and data-out sequence . . . . . . . . . . . . 36
Figure 18. Read OTP (ROTP) instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 19. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 20. Dual Input Fast Program (DIFP) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 21. Program OTP (POTP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 22. How to permanently lock the 64 OTP bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 23. Write to Lock Register (WRLR) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 24. Subsector Erase (SSE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 25. Sector Erase (SE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 26. Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 27. Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 28. Release from Deep Power-down (RDP) instruction sequence. . . . . . . . . . . . . . . . . . . . . . 49
Figure 29. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 30. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 31. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 32. Write Protect Setup and Hold timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . 57
Figure 33. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 34. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 35. VPPH timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 36. VFQFPN8 (MLP8) 8-lead very thin fine pitch dual flat package no lead,
6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 37. SO8W 8-lead plastic small outline, 208 mils body width, package outline . . . . . . . . . . . . . 61
Figure 38. SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline . . . . . . . 62
Figure 39. TBGA, 6x8 mm, 24 ball package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5/68
Description
M25PX32
1
Description
The M25PX32 is a 32 Mbit (4 Mb x 8) serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus.
The M25PX32 supports two new, high-performance dual input/output instructions:
•
Dual Output Fast Read (DOFR) instruction used to read data at up to 75 MHz by using
both pin DQ1 and pin DQ0 as outputs
•
Dual Input Fast Program (DIFP) instruction used to program data at up to 75 MHz by
using both pin DQ1 and pin DQ0 as inputs
These new instructions double the transfer bandwidth for read and program operations.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
The memory is organized as 64 sectors that are further divided into 16 subsectors each
(1024 subsectors in total).
The memory can be erased a 4-Kbyte subsector at a time, a 64-Kbyte sector at a time, or as
a whole. It can be Write Protected by software using a mix of volatile and non-volatile
protection features, depending on the application needs. The protection granularity is of 64
Kbytes (sector granularity).
The M25PX32 has 64 one-time-programmable bytes (OTP bytes) that can be read and
programmed using two dedicated instructions, Read OTP (ROTP) and Program OTP
(POTP), respectively. These 64 bytes can be permanently locked by a particular Program
OTP (POTP) sequence. Once they have been locked, they become read-only and this state
cannot be reverted.
Further features are available as additional security options. More information on these
security features is available, upon completion of an NDA (nondisclosure agreement), and
are, therefore, not described in this datasheet. For more details of this option contact your
nearest Numonyx Sales office.
6/68
M25PX32
Description
Figure 1. Logic diagram
V
CC
DQ0
C
DQ1
M25PX32
S
W/V
PP
HOLD
V
SS
AI14228
Table 1.
Signal names
Signal name
Function
Direction
C
Serial Clock
Input
I/O(1)
I/O(2)
Input
Input
Input
DQ0
DQ1
S
Serial Data input
Serial Data output
Chip Select
W/VPP
HOLD
VCC
VSS
Write Protect/Enhanced Program supply voltage
Hold
Supply voltage
Ground
1. Serves as an output during Dual Output Fast Read (DOFR) instructions.
2. Serves as an input during Dual Input Fast Program (DIFP) instructions.
Figure 2. VFQFPN and SO8 connections
M25PX32
S
1
2
3
4
8
7
6
5
V
CC
HOLD
DQ1
W/V
C
PP
V
DQ0
SS
AI13720b
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Package mechanical section for package dimensions, and how to identify pin-1.
7/68
Description
M25PX32
Figure 3. SO16 connections
M25PX32
HOLD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C
V
DQ0
DU
DU
DU
DU
CC
DU
DU
DU
DU
S
V
SS
W/V
DQ1
PP
AI13721b
Note:
1
2
DU = Don’t use.
See Section 11: Package mechanical, and how to identify pin-1.
Figure 4. BGA 6x8 24 ball ballout
Note:
1
2
NC = No Connection
See Section 11: Package mechanical.
8/68
M25PX32
Signal descriptions
2
Signal descriptions
2.1
2.2
Serial Data output (DQ1)
This output signal is used to transfer data serially out of the device. Data are shifted out on
the falling edge of Serial Clock (C).
During the Dual Input Fast Program (DIFP) instruction, pin DQ1 is used as an input. It is
latched on the rising edge of the Serial Clock (C).
Serial Data input (DQ0)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
During the Dual Output Fast Read (DOFR) instruction, pin DQ0 is used as an output. Data
are shifted out on the falling edge of the Serial Clock (C).
2.3
2.4
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data input (DQ0) are latched on the rising edge of Serial Clock (C). Data
on Serial Data output (DQ1) changes after the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data output (DQ1) is at
high impedance. Unless an internal Program, Erase or Write Status Register cycle is in
progress, the device will be in the Standby Power mode (this is not the Deep Power-down
mode). Driving Chip Select (S) Low enables the device, placing it in the Active Power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data output (DQ1) is high impedance, and Serial Data
input (DQ0) and Serial Clock (C) are Don’t care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
9/68
Signal descriptions
M25PX32
2.6
Write Protect/Enhanced Program supply voltage (W/VPP)
W/VPP is both a control input and a power supply pin. The two functions are selected by the
voltage range applied to the pin.
If the W/VPP input is kept in a low voltage range (0 V to VCC) the pin is seen as a control
input. This input signal is used to freeze the size of the area of memory that is protected
against program or erase instructions (as specified by the values in the BP2, BP1 and BP0
bits of the Status Register. See Table 9).
If VPP is in the range of VPPH (as defined in Table 15) it acts as an additional power
supply.(1)
2.7
2.8
VCC supply voltage
VCC is the supply voltage.
VSS ground
VSS is the reference for the VCC supply voltage.
1. Avoid applying VPPH to the W/VPP pin during Bulk Erase.
10/68
M25PX32
SPI modes
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
•
•
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 6, is the clock polarity when the
bus master is in Standby mode and not transferring data:
•
•
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 5. Bus Master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C
VCC
VCC
VCC
C
C
VSS
VSS
VSS
SPI Bus Master
DQ1DQ0
DQ1 DQ0
DQ1DQ0
SPI memory
device
SPI memory
device
SPI memory
device
R
R
R
CS3 CS2 CS1
W
S
S
S
W
HOLD
HOLD
HOLD
W
AI13725b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 5 shows an example of three devices connected to an MCU, on an SPI bus. Only
one device is selected at a time, so only one device drives the Serial Data output (DQ1) line
at a time, the other devices are high impedance. Resistors R (represented in Figure 5)
ensure that the M25PX32 is not selected if the Bus Master leaves the S line in the high
impedance state. As the Bus Master may enter a state where all inputs/outputs are in high
impedance at the same time (for example, when the Bus Master is reset), the clock line (C)
must be connected to an external pull-down resistor so that, when all inputs/outputs become
high impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S
and C do not become High at the same time, and so, that the tSHCH requirement is met).
The typical value of R is 100 kΩ, assuming that the time constant R*Cp (Cp = parasitic
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
11/68
SPI modes
M25PX32
Example: Cp = 50 pF, that is R*Cp = 5 μs <=> the application must ensure that the Bus
Master never leaves the SPI bus in the high impedance state for a time period shorter than
5 μs.
Figure 6. SPI modes supported
CPOL CPHA
C
0
1
0
1
C
DQ0
DQ1
MSB
MSB
AI13730
12/68
M25PX32
Operating features
4
Operating features
4.1
Page programming
To program one data byte, two instructions are required: Write Enable (WREN), which is
one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This
is followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Page Program (PP)
and Table 18: AC characteristics).
4.2
4.3
Dual Input Fast Program
The Dual Input Fast Program (DIFP) instruction makes it possible to program up to 256
bytes using two input pins at the same time (by changing bits from 1 to 0).
For optimized timings, it is recommended to use the Dual Input Fast Program (DIFP)
instruction to program all consecutive targeted bytes in a single sequence rather to using
several Dual Input Fast Program (DIFP) sequences each containing only a few bytes (see
Section 6.12: Dual Input Fast Program (DIFP)).
Subsector Erase, Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a subsector at a time, using the Subsector Erase (SSE) instruction, a sector
at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using
the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration tSSE, tSE or
tBE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.4
Polling during a Write, Program or Erase cycle
A further improvement in the time to Write Status Register (WRSR), Program OTP (POTP),
Program (PP), Dual Input Fast Program (DIFP) or Erase (SSE, SE or BE) can be achieved
by not waiting for the worst case delay (tW, tPP, tSSE, tSE, or tBE). The Write In Progress
(WIP) bit is provided in the Status Register so that the application program can monitor its
value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is
complete.
13/68
Operating features
M25PX32
4.5
Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active
Power mode until all internal cycles have completed (Program, Erase, Write Status
Register). The device then goes in to the Standby Power mode. The device consumption
drops to ICC1
.
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to ICC2. The
device remains in this mode until another specific instruction (the Release from Deep
Power-down (RDP) instruction) is executed.
While in the Deep Power-down mode, the device ignores all Write, Program and Erase
instructions (see Deep Power-down (DP)), this can be used as an extra software protection
mechanism, when the device is not in active use, to protect the device from inadvertent
Write, Program or Erase instructions.
4.6
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.4: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
14/68
M25PX32
Operating features
4.7
Protection modes
There are protocol-related and specific hardware and software protection modes. They are
described below.
4.7.1
Protocol-related protections
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25PX32 features the following data protection mechanisms:
•
Power On Reset and an internal timer (tPUW) can provide protection against
inadvertent changes while the power supply is outside the operating specification
•
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution
•
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
–
–
–
–
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write to Lock Register (WRLR) instruction completion
Program OTP (POTP) instruction completion
Page Program (PP) instruction completion
Dual Input Fast Program (DIFP) instruction completion
Subsector Erase (SSE) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
•
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection, as all Write, Program and Erase instructions are ignored.
15/68
Operating features
M25PX32
4.7.2
Specific hardware and software protection
There are two software protected modes, SPM1 and SPM2, that can be combined to protect
the memory array as required. The SPM2 can be locked by hardware with the help of the W
input pin.
SPM1 and SPM2
•
The first software protected mode (SPM1) is managed by specific Lock Registers
assigned to each 64 Kbyte sector.
The Lock Registers can be read and written using the Read Lock Register (RDLR) and
Write to Lock Register (WRLR) instructions.
In each Lock Register two bits control the protection of each sector: the Write Lock bit
and the Lock Down bit.
–
Write Lock bit:
The Write Lock bit determines whether the contents of the sector can be modified
(using the Write, Program or Erase instructions). When the Write Lock bit is set to
‘1’, the sector is write protected – any operations that attempt to change the data
in the sector will fail. When the Write Lock bit is reset to ‘0’, the sector is not write
protected by the Lock Register, and may be modified.
–
Lock Down bit:
The Lock Down bit provides a mechanism for protecting software data from simple
hacking and malicious attack. When the Lock Down bit is set, ‘1’, further
modification to the Write Lock and Lock Down bits cannot be performed. A power-
up, is required before changes to these bits can be made. When the Lock Down
bit is reset, ‘0’, the Write Lock and Lock Down bits can be changed.
The definition of the Lock Register bits is given in Table 9: Lock Register out.
Table 2. Software protection truth table (Sectors 0 to 63, 64 Kbyte granularity)
Sector Lock
Register
Protection status
Lock
Write
Down bit Lock bit
Sector unprotected from Program/Erase/Write operations, protection status
reversible
0
0
1
1
0
1
0
1
Sector protected from Program/Erase/Write operations, protection status
reversible
Sector unprotected from Program/Erase/Write operations,
Sector protection status cannot be changed except by a power-up.
Sector protected from Program/Erase/Write operations,
Sector protection status cannot be changed except by a Power-up.
•
the second software protected mode (SPM2) uses the Block Protect bits (see
Section 6.4.3: BP2, BP1, BP0 bits) and the Top/Bottom bit (see Section 6.4.4: TB bit) to
allow part of the memory to be configured as read-only.
16/68
M25PX32
Operating features
Table 3.
Protected area sizes
Status Register
Memory content
contents
TB BP BP BP
bit bit 2 bit 1 bit 0
Protected area
Unprotected area
0
0
0
0
0
0
0
0
1
0
1
0
none
Upper 64th (Sector 63)
All sectors(1) (64 sectors: 0 to 63)
Lower 63/64ths (63 sectors: 0 to 62)
Upper 32nd (two sectors: 62 and 63) Lower 31/32nds (62 sectors: 0 to 61)
Upper sixteenth (four sectors: 60 to
Lower 15/16ths (60 sectors: 0 to 59)
63)
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
Lower seven-eighths (56 sectors: 0
Upper eighth (eight sectors: 56 to 63)
to 55)
Upper quarter (sixteen sectors: 48 to Lower three-quarters (48 sectors: 0
63)
to 47)
Upper half (thirty-two sectors: 32 to
63)
Lower half (32 sectors: 0 to 31)
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
All sectors (64 sectors: 0 to 63)
none
none
All sectors(1) (64 sectors: 0 to 63)
Upper 63/64ths (63 sectors: 1 to 63)
Upper 31/32ths (62 sectors: 2 to 63)
Upper 15/16ths (60 sectors: 4 to 63)
Upper 7/8ths (56 sectors: 8 to 63)
Upper 3/4ths (48 sectors: 16 to 63)
Lower 64th (sector 0)
Lower 32nd (two sectors: 0 and 1)
Lower 16th (four sectors: 0 to 3)
Lower 8th (eight sectors: 0 to 7)
Lower 4th (sixteen sectors: 0 to 15)
Lower half (thirty-two sectors: 0 to
31)
1
1
1
1
1
1
0
1
Upper half (32 sectors: 32 to 63)
none
All sectors (64 sectors: 0 to 63)
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are
0.
As a second level of protection, the Write Protect signal (applied on the W/VPP pin) can
freeze the Status Register in a read-only mode. In this mode, the Block Protect bits (BP2,
BP1, BP0) and the Status Register Write Disable bit (SRWD) are protected. For more
details, see Section 6.5: Write Status Register (WRSR).
17/68
Operating features
M25PX32
4.8
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in Figure 7).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in Figure 7).
During the Hold condition, the Serial Data output (DQ1) is high impedance, and Serial Data
input (DQ0) and Serial Clock (C) are Don’t care.
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
Figure 7. Hold condition activation
C
HOLD
Hold
Hold
Condition
Condition
(standard use)
(non-standard use)
AI02029D
18/68
M25PX32
Memory organization
5
Memory organization
The memory is organized as:
•
•
•
•
•
4 194 304 bytes (8 bits each)
1024 subsectors (4 Kbytes each)
64 sectors (64 Kbytes each)
16384 pages (256 bytes each)
64 OTP bytes located outside the main memory array
Each page can be individually programmed (bits are programmed from 1 to 0). The device is
Subsector, Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable.
Figure 8. Block diagram
HOLD
High Voltage
Generator
W/VPP
S
Control Logic
64 OTP bytes
C
DQ0
DQ1
I/O Shift Register
Status
Register
Address Register
and Counter
256 Byte
Data Buffer
3FFFFFh
Configurable OTP
area in main
memory array
00000h
000FFh
256 Bytes (Page Size)
X Decoder
AI13722
19/68
Memory organization
Table 4.
M25PX32
Memory organization
Sector Subsector
Address range
Sector Subsector
Address range
1023
3FF000h 3FFFFFh
847
34F000h
34FFFFh
63
62
61
60
59
58
57
56
55
54
53
52
1008
1007
3F0000h 3F0FFFh
3EF000h 3EFFFFh
832
831
51
340000h
33F000h
340FFFh
33FFFFh
992
991
3E0000h 3E0FFFh
3DF000h 3DFFFFh
816
815
50
330000h
32F000h
330FFFh
32FFFFh
976
975
3D0000h 3D0FFFh
3CF000h 3CFFFFh
800
799
49
320000h
31F000h
320FFFh
31FFFFh
960
959
3C0000h 3C0FFFh
3BF000h 3BFFFFh
784
783
48
310000h
30F000h
310FFFh
30FFFFh
944
943
3B0000h 3B0FFFh
3AF000g 3AFFFFh
768
767
47
300000h
2FF000h
300FFFh
2FFFFFh
928
927
3A0000h 3A0FFFh
39F000h 39FFFFh
752
751
46
2F0000h
2EF000h
2F0FFFh
2EFFFFh
912
911
390000h 390FFFh
38F000h 38FFFFh
736
735
45
2E0000h
2DF000h
2E0FFFh
2DFFFFh
896
895
380000h 380FFFh
37F000h 37FFFFh
720
719
44
2D0000h
2CF000h
2D0FFFh
2CFFFFh
880
879
370000h 370FFFh
36F000h 36FFFFh
704
703
43
2C0000h
2BF000h
2C0FFFh
2BFFFFh
864
863
360000h 360FFFh
35F000h 35FFFFh
688
687
42
2B0000h
2AF000h
2B0FFFh
2AFFFFh
848
350000h 350FFFh
672
2A0000h
2A0FFFh
20/68
M25PX32
Memory organization
Address range
Table 4.
Memory organization (continued)
Sector Subsector
Address range
Sector Subsector
671
29F000h 29FFFFh
495
1EF000h
1EFFFFh
41
30
656
655
40
290000h 290FFFh
28F000h 28FFFFh
480
479
29
1E0000h
1DF000h
1E0FFFh
1DFFFFh
640
639
39
280000h 280FFFh
27F000h 27FFFFh
464
463
28
1D0000h
1CF000h
1D0FFFh
1CFFFFh
624
623
38
270000h 270FFFh
26F000h 26FFFFh
448
447
27
1C0000h
1BF000h
1C0FFFh
1BFFFFh
608
607
37
260000h 260FFFh
25F000h 25FFFFh
432
431
26
1B0000h
1AF000h
1B0FFFh
1AFFFFh
592
591
36
250000h 250FFFh
24F000h 24FFFFh
416
415
25
1A0000h
19F000h
1A0FFFh
19FFFFh
576
575
35
240000h 240FFFh
23F000h 23FFFFh
400
399
24
190000h
18F000h
190FFFh
18FFFFh
560
559
34
230000h 230FFFh
22F000h 22FFFFh
384
383
23
180000h
17F000h
180FFFh
17FFFFh
544
543
33
220000h 220FFFh
21F000h 21FFFFh
368
367
22
170000h
16F000h
170FFFh
16FFFFh
528
527
32
210000h 210FFFh
20F000h 20FFFFh
352
351
21
160000h
15F000h
160FFFh
15FFFFh
512
511
31
200000h 200FFFh
1FF000h 1FFFFFh
336
335
20
150000h
14F000h
150FFFh
14FFFFh
496
1F0000h 1F0FFFh
320
140000h
140FFFh
21/68
Memory organization
Table 4.
M25PX32
Memory organization (continued)
Sector Subsector
Address range
Sector Subsector
Address range
319
13F000h 13FFFFh
143
8F000h
8FFFFh
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
304
303
130000h 130FFFh
12F000h 12FFFFh
128
127
80000h
7F000h
80FFFh
7FFFFh
288
287
120000h 120FFFh
11F000h 11FFFFh
112
111
70000h
6F000h
70FFFh
6FFFFh
272
271
110000h 110FFFh
10F000h 10FFFFh
96
95
60000h
5F000h
60FFFh
5FFFFh
256
255
100000h 100FFFh
80
79
50000h
4F000h
50FFFh
4FFFFh
FF000h
FFFFFh
240
239
F0000h
EF000h
F0FFFh
EFFFFh
64
63
40000h
3F000h
40FFFh
3FFFFh
224
223
E0000h
DF000h
E0FFFh
DFFFFh
48
47
30000h
2F000h
30FFFh
2FFFFh
208
207
D0000h
CF000h
D0FFFh
CFFFFh
32
31
20000h
1F000h
20FFFh
1FFFFh
192
191
C0000h
BF000h
C0FFFh
BFFFFh
16
15
10000h
0F000h
10FFFh
0FFFFh
176
175
B0000h
AF000h
B0FFFh
AFFFFh
4
3
2
1
0
04000h
03000h
02000h
01000h
00000h
04FFFh
03FFFh
02FFFh
01FFFh
00FFFh
0
160
159
A0000h
9F000h
A0FFFh
9FFFFh
144
90000h
90FFFh
22/68
M25PX32
Instructions
6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data input(s) DQ0 (DQ1) is (are) sampled on the first rising edge of Serial Clock (C)
after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to
the device, most significant bit first, on Serial Data input(s) DQ0 (DQ1), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 5.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at higher speed (FAST_READ),
Dual Output Fast Read (DOFR), Read OTP (ROTP), Read Lock Registers (RDLR), Read
Status Register (RDSR), Read Identification (RDID) or Release from Deep Power-down
(RDP) instruction, the shifted-in instruction sequence is followed by a data-out sequence.
Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted
out.
In the case of a Page Program (PP), Program OTP (POTP), Dual Input Fast Program
(DIFP), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Write Status Register
(WRSR), Write to Lock Register (WRLR), Write Enable (WREN), Write Disable (WRDI) or
Deep Power-down (DP) instruction, Chip Select (S) must be driven High exactly at a byte
boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S)
must driven High when the number of clock pulses after Chip Select (S) being driven Low is
an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
23/68
Instructions
M25PX32
Table 5.
Instruction set
One-byte instruction Address Dummy
Data
bytes
Instruction
Description
code
bytes
bytes
WREN
WRDI
Write Enable
Write Disable
0000 0110
0000 0100
1001 1111
1001 1110
0000 0101
0000 0001
1110 0101
1110 1000
0000 0011
06h
04h
9Fh
9Eh
05h
01h
E5h
E8h
03h
0
0
0
0
0
0
3
3
3
0
0
0
0
0
0
0
0
0
0
0
1 to 20
1 to 3
1 to ∞
1
RDID
Read Identification
RDSR
WRSR
WRLR
RDLR
READ
Read Status Register
Write Status Register
Write to Lock Register
Read Lock Register
Read Data Bytes
1
1
1 to ∞
Read Data Bytes at higher
speed
FAST_READ
DOFR
0000 1011
0011 1011
0100 1011
0Bh
3Bh
4Bh
3
3
3
1
1
1
1 to ∞
1 to ∞
1 to 65
Dual Output Fast Read
Read OTP (Read 64 bytes of
OTP area)
ROTP
Program OTP (Program 64
bytes of OTP area)
POTP
0100 0010
42h
3
0
1 to 65
PP
DIFP
SSE
SE
Page Program
0000 0010
1010 0010
0010 0000
1101 1000
1100 0111
1011 1001
02h
A2h
20h
D8h
C7h
B9h
3
3
3
3
0
0
0
0
0
0
0
0
1 to 256
Dual Input Fast Program
Subsector Erase
Sector Erase
1 to 256
0
0
0
0
BE
Bulk Erase
DP
Deep Power-down
Release from Deep Power-
down
RDP
1010 1011
ABh
0
0
0
24/68
M25PX32
Instructions
6.1
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 9) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Dual Input
Fast Program (DIFP), Program OTP (POTP), Write to Lock Register (WRLR), Subsector
Erase (SSE), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR)
instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 9. Write Enable (WREN) instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
DQ0
DQ1
High Impedance
AI13731
25/68
Instructions
M25PX32
6.2
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 10) resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
•
Power-up
•
•
•
•
•
•
•
•
•
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write lo Lock Register (WRLR) instruction completion
Page Program (PP) instruction completion
Dual Input Fast Program (DIFP) instruction completion
Program OTP (POTP) instruction completion
Subsector Erase (SSE) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Figure 10. Write Disable (WRDI) instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
DQ0
DQ1
High Impedance
AI13732
26/68
M25PX32
Instructions
6.3
Read Identification (RDID)
The Read Identification (RDID) instruction allows to read the device identification data:
•
•
•
Manufacturer identification (1 byte)
Device identification (2 bytes)
A Unique ID code (UID) (17 bytes, of which 16 available upon customer request).
The manufacturer identification is assigned by JEDEC, and has the value 20h. The device
identification is assigned by the device manufacturer, and indicates the memory type in the
first byte (71h), and the memory capacity of the device in the second byte (16h). The UID
contains the length of the following data in the first byte (set to 10h) and 16 bytes of the
optional Customized Factory Data (CFD) content. The CFD bytes are read-only and can be
programmed with customers data upon their demand. If the customers do not make
requests, the devices are shipped with all the CFD bytes programmed to zero (00h).
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is
not decoded, and has no effect on the cycle that is in progress.
The Read Identification (RDID) instruction should not be issued while the device is in Deep
Power-down mode.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. After this, the 24-bit device identification, stored in the
memory, the 8-bit CFD length followed by 16 bytes of CFD content will be shifted out on
Serial Data output (DQ1). Each bit is shifted out during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 11.
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Table 6.
Read Identification (RDID) data-out sequence
Device identification
UID
Manufacturer identification
Memory type
71h
Memory capacity
16h
CFD length
CFD content
20h
10h
16 bytes
27/68
Instructions
M25PX32
Figure 11. Read Identification (RDID) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16 17 18
28 29 30 31
C
Instruction
DQ0
Manufacturer identification
Device identification
UID
High Impedance
DQ1
15 14 13
MSB
3
2
1
0
MSB
MSB
AI06809d
28/68
M25PX32
Instructions
6.4
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as shown in Figure 12.
Table 7.
Status Register format
b7
b0
SRWD
0
TB
BP2
BP1
BP0
WEL
WIP
Status Register Write Protect
Top/Bottom bit
Block Protect bits
Write Enable Latch bit
Write In Progress bit
The status and control bits of the Status Register are as follows:
6.4.1
6.4.2
6.4.3
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
0 no such cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3) becomes
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
29/68
Instructions
M25PX32
6.4.4
TB bit
The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status Register
(WRSR) instruction provided that the Write Enable (WREN) instruction has been issued.
The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP0, BP1, BP2) bits
to determine if the protected area defined by the Block Protect bits starts from the top or the
bottom of the memory array:
•
When TB is reset to ‘0’ (default value), the area protected by the Block Protect bits
starts from the top of the memory array (see Table 3: Protected area sizes)
•
When TB is set to ‘1’, the area protected by the Block Protect bits starts from the
bottom of the memory array (see Table 3: Protected area sizes)
The TB bit cannot be written when the SRWD bit is set to ‘1’ and the W pin is driven Low.
6.4.5
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and the Write Protect
(W/VPP) signal allow the device to be put in the hardware protected mode (when the Status
Register Write Disable (SRWD) bit is set to ‘1’, and Write Protect (W/VPP) is driven Low). In
this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become
read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
Figure 12. Read Status Register (RDSR) instruction sequence and data-out
sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
DQ0
Status Register Out
Status Register Out
High Impedance
DQ1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI13734
30/68
M25PX32
Instructions
6.5
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data input (DQ0).
The instruction sequence is shown in Figure 13.
The Write Status Register (WRSR) instruction has no effect on b6, b1 and b0 of the Status
Register. b6 is always read as ‘0’.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in Table 3. The Write Status Register (WRSR) instruction also allows
the user to set and reset the Status Register Write Disable (SRWD) bit in accordance with
the Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write
Protect (W/VPP) signal allow the device to be put in the hardware protected mode (HPM).
The Write Status Register (WRSR) instruction is not executed once the hardware protected
mode (HPM) is entered.
Figure 13. Write Status Register (WRSR) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
DQ0
DQ1
High Impedance
MSB
AI13735
31/68
Instructions
M25PX32
Table 8.
Protection modes
Write Protection
of the Status
Register
Memory content
Protected area(1) Unprotected area(1)
W/VPP
signal
SRWD
Mode
bit
1
0
0
0
Status Register is
Writable (if the
WREN instruction
has set the WEL
bit)
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
Software
protected
(SPM)
The values in the
SRWD, BP2, BP1
and BP0 bits can be
changed
1
0
1
instructions
Status Register is
hardware write
protected
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
Hardware
protected
(HPM)
1
The values in the
SRWD, BP2, BP1
and BP0 bits
instructions
cannot be changed
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 3.
The protection features of the device are summarized in Table 8.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W/VPP) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W/VPP):
•
If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
•
If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register
even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected mode (HPM) can be
entered:
•
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/VPP) Low
•
or by driving Write Protect (W/VPP) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W/VPP) High.
If Write Protect (W/VPP) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
32/68
M25PX32
Instructions
6.6
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data output (DQ1), each bit being shifted out, at a
maximum frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 14. Read Data Bytes (READ) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address
23 22 21
MSB
3
2
1
0
DQ0
DQ1
Data Out 1
Data Out 2
7
High Impedance
2
7
6
5
4
3
1
0
MSB
AI13736
1. Address bits A23 to A22 are Don’t care.
33/68
Instructions
M25PX32
6.7
Read Data Bytes at higher speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, are shifted out on Serial Data output (DQ1) at a
maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 15.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at higher speed (FAST_READ) instruction.
When the highest address is reached, the address counter rolls over to 000000h, allowing
the read sequence to be continued indefinitely.
The Read Data Bytes at higher speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any
Read Data Bytes at higher speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 15. Read Data Bytes at higher speed (FAST_READ) instruction sequence
and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
Instruction
24-bit address
23 22 21
3
2
1
0
DQ0
DQ1
High Impedance
S
C
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Dummy byte
7
6
5
4
3
2
0
1
DQ0
DQ1
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
MSB
MSB
MSB
AI13737
1. Address bits A23 to A22 are Don’t care.
34/68
M25PX32
Instructions
6.8
Dual Output Fast Read (DOFR)
The Dual Output Fast Read (DOFR) instruction is very similar to the Read Data Bytes at
higher speed (FAST_READ) instruction, except that the data are shifted out on two pins (pin
DQ0 and pin DQ1) instead of only one. Outputting the data on two pins instead of one
doubles the data transfer bandwidth compared to the Read Data Bytes at higher speed
(FAST_READ) instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual
Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte,
each bit being latched-in during the rising edge of Serial Clock (C). Then the memory
contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency fC,
during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 16.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out on DQ0 and DQ1. The whole
memory can, therefore, be read with a single Dual Output Fast Read (DOFR) instruction.
When the highest address is reached, the address counter rolls over to 00 0000h, so that
the read sequence can be continued indefinitely.
Figure 16. Dual Output Fast Read instruction sequence
S
Mode 3
Mode 2
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
Instruction
24-bit address
DQ0
DQ1
23 22 21
3
2
1
0
High Impedance
S
C
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Dummy byte
DQ0
DQ1
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
DATA OUT 1 DATA OUT 2 DATA OUT 3
DATA OUT n
7
5
3
1
7
5
3
1
7
5
3
1
7
5
1
3
MSB
MSB
MSB
MSB
MSB
ai13574
1. A23 to A22 are Don't care.
35/68
Instructions
M25PX32
6.9
Read Lock Register (RDLR)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector. Each address bit is latched-in during the rising edge of
Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data output
(DQ1), each bit being shifted out, at a maximum frequency fC, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 17.
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Table 9.
Bit
Lock Register out(1)
Bit name
Value
Function
b7-b2
Reserved
The Write Lock and Lock Down bits cannot be changed.
Once a ‘1’ is written to the Lock Down bit it cannot be cleared
to ‘0’, except by a power-up.
‘1’
b1
Sector Lock Down
Sector Write Lock
The Write Lock and Lock Down bits can be changed by
writing new values to them.
‘0’
‘1’
‘0’
Write, Program and Erase operations in this sector will not be
executed. The memory contents will not be changed.
b0
Write, Program and Erase operations in this sector are
executed and will modify the sector contents.
1. Values of (b1, b0) after power-up are defined in Section 7: Power-up and power-down.
Figure 17. Read Lock Register (RDLR) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address
23 22 21
MSB
3
2
1
0
DQ0
DQ1
Lock Register Out
High Impedance
2
7
6
5
4
3
1
0
MSB
AI13738
36/68
M25PX32
Instructions
6.10
Read OTP (ROTP)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each
bit is latched in on the rising edge of Serial Clock (C).
Then the memory contents at that address are shifted out on Serial Data output (DQ1).
Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock
(C). The instruction sequence is shown in Figure 18.
The address is automatically incremented to the next higher address after each byte of data
is shifted out.
There is no rollover mechanism with the Read OTP (ROTP) instruction. This means that the
Read OTP (ROTP) instruction must be sent with a maximum of 65 bytes to read, since once
the 65th byte has been read, the same (65th) byte keeps being read on the DQ1 pin.
The Read OTP (ROTP) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read OTP (ROTP)
instruction issued while an Erase, Program or Write cycle is in progress, is rejected without
having any effect on the cycle that is in progress.
Figure 18. Read OTP (ROTP) instruction and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
Instruction
24-bit address
23 22 21
3
2
1
0
DQ0
DQ1
High Impedance
S
C
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Dummy byte
7
6
5
4
3
2
0
1
DQ0
DQ1
DATA OUT n
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
MSB
MSB
MSB
AI13573
1. A23 to A7 are Don't care.
2. 1 ≤ n ≤ 65.
37/68
Instructions
M25PX32
6.11
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address bytes and at least one data byte on Serial Data input
(DQ0). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that
goes beyond the end of the current page are programmed from the start address of the
same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip
Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 19.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Table 18: AC
characteristics).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 3 and Table 4) is not executed.
38/68
M25PX32
Instructions
Figure 19. Page Program (PP) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address
Data byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
DQ0
MSB
S
C
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data byte 2
Data byte 3
Data byte 256
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
DQ0
MSB
MSB
MSB
AI13739
1. Address bits A23 to A22 are Don’t care.
39/68
Instructions
M25PX32
6.12
Dual Input Fast Program (DIFP)
The Dual Input Fast Program (DIFP) instruction is very similar to the Page Program (PP)
instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of
only one. Inputting the data on two pins instead of one doubles the data transfer bandwidth
compared to the Page Program (PP) instruction.
The Dual Input Fast Program (DIFP) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes and at least one data byte on Serial
Data input (DQ0).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 20.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes in the same page.
For optimized timings, it is recommended to use the Dual Input Fast Program (DIFP)
instruction to program all consecutive targeted bytes in a single sequence rather to using
several Dual Input Fast Program (DIFP) sequences each containing only a few bytes (see
Table 18: AC characteristics).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Dual Input Fast Program (DIFP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Dual Input Fast Program (DIFP) cycle is in progress,
the Status Register may be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch
(WEL) bit is reset.
A Dual Input Fast Program (DIFP) instruction applied to a page that is protected by the
Block Protect (BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
40/68
M25PX32
Instructions
Figure 20. Dual Input Fast Program (DIFP) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
Instruction
24-bit address
23
22 21
3
2
1
0
DQ0
DQ1
High Impedance
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
6
4
0
2
6
4
2
0
1
6
4
0
1
6
4
2
0
1
6
4
0
1
6
4
2
0
1
2
2
DQ0
DQ1
DATA IN 1
DATA IN 2
DATA IN 3
DATA IN 4
DATA IN 5
DATA IN 256
7
5
3
7
7
5
3
7
5
3
5
3
7
5
1
7
5
3
3
MSB
MSB
MSB
MSB
MSB
MSB
AI14229
1. A23 to A22 are Don't care.
41/68
Instructions
M25PX32
6.13
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded, the device sets the Write Enable Latch (WEL) bit.
The Program OTP instruction is entered by driving Chip Select (S) Low, followed by the
instruction opcode, three address bytes and at least one data byte on Serial Data input
(DQ0).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Program OTP instruction is not executed.
There is no rollover mechanism with the Program OTP (POTP) instruction. This means that
the Program OTP (POTP) instruction must be sent with a maximum of 65 bytes to program,
once all 65 bytes have been latched in, any following byte will be discarded.
The instruction sequence is shown in Figure 21.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Program OTP cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Program OTP cycle, and it is 0 when it is completed. At
some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is
reset.
To lock the OTP memory:
Bit 0 of the OTP control byte, that is byte 64, (see Figure 22) is used to permanently lock the
OTP memory array.
•
When bit 0 of byte 64 = ’1’, the 64 bytes of the OTP memory array can be programmed.
•
When bit 0 of byte 64 = ‘0’, the 64 bytes of the OTP memory array are read-only and
cannot be programmed anymore.
Once a bit of the OTP memory has been programmed to ‘0’, it can no longer be set to ‘1’.
Therefore, as soon as bit 0 of byte 64 (control byte) is set to ‘0’, the 64 bytes of the OTP
memory array become read-only in a permanent way.
Any Program OTP (POTP) instruction issued while an Erase, Program or Write cycle is in
progress is rejected without having any effect on the cycle that is in progress.
42/68
M25PX32
Instructions
Figure 21. Program OTP (POTP) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address
Data byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
DQ0
S
MSB
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
Data byte 2
Data byte 3
Data byte n
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
DQ0
MSB
MSB
MSB
AI13575
1. A23 to A7 are Don't care.
2. 1 ≤ n ≤ 65
Figure 22. How to permanently lock the 64 OTP bytes
64 data bytes
OTP Control byte
ByteByteByte
ByteByte
63 64
0
1
2
X
X
X
X
X
X
X
bit 0 When bit 0 = 0
the 64 OTP bytes
become READ only
Bit 1 to bit 7 are NOT
programmable
ai13587
43/68
Instructions
M25PX32
6.14
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes (pointing to any address in the
targeted sector and one data byte on Serial Data input (DQ0). The instruction sequence is
shown in Figure 23. Chip Select (S) must be driven High after the eighth bit of the data byte
has been latched in, otherwise the Write to Lock Register (WRLR) instruction is not
executed.
Lock Register bits are volatile, and therefore do not require time to be written. When the
Write to Lock Register (WRLR) instruction has been successfully executed, the Write
Enable Latch (WEL) bit is reset after a delay time less than tSHSL minimum value.
Any Write to Lock Register (WRLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 23. Write to Lock Register (WRLR) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
Lock Register
C
Instruction
24-Bit Address
In
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
DQ0
MSB
AI13740
Table 10. Lock Register in(1)
Sector
Bit
Value
‘0’
b7-b2
b1
All sectors
Sector Lock Down bit value (refer to Table 9)
Sector Write Lock bit value (refer to Table 9)
b0
1. Values of (b1, b0) after power-up are defined in Section 7: Power-up and power-down.
44/68
M25PX32
Instructions
6.15
Subsector Erase (SSE)
The Subsector Erase (SSE) instruction sets to 1 (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been
executed. After the Write Enable (WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Subsector Erase (SSE) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code, and three address bytes on Serial Data input (DQ0). Any address
inside the Subsector (see Table 4) is a valid address for the Subsector Erase (SSE)
instruction. Chip Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 24.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Subsector Erase (SSE) instruction is not executed. As soon as
Chip Select (S) is driven High, the self-timed Subsector Erase cycle (whose duration is tSSE
)
is initiated. While the Subsector Erase cycle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Subsector Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Subsector Erase (SSE) instruction issued to a sector that is hardware or software
protected, is not executed.
Any Subsector Erase (SSE) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 24. Subsector Erase (SSE) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
Instruction
24 Bit Address
2
0
1
23 22
MSB
DQ0
AI13741
1. Address bits A23 to A22 are Don’t care.
45/68
Instructions
M25PX32
6.16
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data input (DQ0). Any address inside
the Sector (see Table 4) is a valid address for the Sector Erase (SE) instruction. Chip Select
(S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 25.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 3 and Table 4) is not executed.
Figure 25. Sector Erase (SE) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
Instruction
24 Bit Address
23 22
MSB
2
0
1
DQ1
AI13742
1. Address bits A23 to A22 are Don’t care.
46/68
M25PX32
Instructions
6.17
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 26.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits
are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 26. Bulk Erase (BE) instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
DQ0
AI13743
47/68
Instructions
M25PX32
6.18
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as a software
protection mechanism, while the device is not in active use, as in this mode, the device
ignores all Write, Program and Erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power
mode (if there is no internal cycle currently in progress). But this mode is not the Deep
Power-down mode. The Deep Power-down mode can only be entered by executing the
Deep Power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to
ICC2, as specified in Table 17).
To take the device out of Deep Power-down mode, the Release from Deep Power-down
(RDP) instruction must be issued. No other instruction must be issued while the device is in
Deep Power-down mode.
The Deep Power-down mode automatically stops at power-down, and the device always
powers up in the Standby Power mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for
the entire duration of the sequence.
The instruction sequence is shown in Figure 27.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced
to ICC2 and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 27. Deep Power-down (DP) instruction sequence
S
tDP
0
1
2
3
4
5
6
7
C
Instruction
DQ0
Standby mode
Deep Power-down mode
AI13744
48/68
M25PX32
Instructions
6.19
Release from Deep Power-down (RDP)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down (RDP) instruction. Executing this instruction
takes the device out of the Deep Power-down mode.
The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S)
Low, followed by the instruction code on Serial Data input (DQ0). Chip Select (S) must be
driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 28.
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select
(S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven
Low, cause the instruction to be rejected, and not executed.
After Chip Select (S) has been driven High, followed by a delay, tRDP, the device is put in the
Standby mode. Chip Select (S) must remain High at least until this period is over. The
device waits to be selected, so that it can receive, decode and execute instructions.
Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write
cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 28. Release from Deep Power-down (RDP) instruction sequence
S
t
RDP
0
1
2
3
4
5
6
7
C
Instruction
DQ0
High Impedance
DQ1
Deep Power-down mode
Standby mode
AI13745
49/68
Power-up and power-down
M25PX32
7
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
•
•
V
CC(min) at power-up, and then for a further delay of tVSL
VSS at power-down
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Dual Input Fast
Program (DIFP), Program OTP (POTP), Subsector Erase (SSE), Sector Erase (SE), Bulk
Erase (BE), Write Status Register (WRSR) and Write to Lock Register (WRLR) instructions
until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI
threshold. However, the correct operation of the device is not guaranteed if, by this time,
VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should
be sent until the later of:
•
•
tPUW after VCC has passed the VWI threshold
VSL after VCC has passed the VCC(min) level.
t
These values are specified in Table 11.
If the time, tVSL, has elapsed, after VCC rises above VCC(min), the device can be selected
for READ instructions even if the tPUW delay has not yet fully elapsed.
After power-up, the device is in the following state:
•
•
•
•
The device is in the Standby Power mode (not the Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
The Write In Progress (WIP) bit is reset.
The Lock Registers are configured as: (Write Lock bit, Lock Down bit) = (0,0)
Normal precautions must be taken for supply line decoupling, to stabilize the VCC supply.
Each device in a system should have the VCC line decoupled by a suitable capacitor close
to the package pins (generally, this capacitor is of the order of 100 nF).
At power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not respond
to any instruction. (The designer needs to be aware that if power-down occurs while a Write,
Program or Erase cycle is in progress, some data corruption may result.)
•
VPPH must be applied only when VCC is stable and in the VCCmin to VCCmax voltage
range.
50/68
M25PX32
Power-up and power-down
Figure 29. Power-up timing
V
CC
V
(max)
CC
Program, Erase and Write commands are rejected by the device
Chip Selection not allowed
V
(min)
CC
tVSL
Read Access allowed
Device fully
accessible
Reset state
of the
device
V
WI
tPUW
time
AI04009C
Table 11.
Symbol
Power-up timing and VWI threshold
Parameter
Min
Max
Unit
(1)
tVSL
VCC(min) to S low
30
1
μs
ms
V
(1)
tPUW
Time delay to write instruction
Write Inhibit voltage
10
(1)
VWI
1.5
2.5
1. These parameters are characterized only.
51/68
Initial delivery state
M25PX32
8
Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte
contains FFh). The Status Register contains 00h (all Status Register bits are 0).
9
Maximum rating
Stressing the device outside the ratings listed in Table 12: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these, or any other conditions outside those indicated in the operating sections of
this specification, is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 12. Absolute maximum ratings
Symbol
Parameter
Min
Max
Unit
TSTG
TLEAD
VIO
Storage temperature
–65
150
see(1)
VCC+0.6
4.0
°C
°C
V
Lead temperature during soldering
Input and output voltage (with respect to ground)
Supply voltage
–0.6
–0.6
VCC
V
VPP
Fast Program/Erase voltage(2)
–0.2
10.0
V
VESD
Electrostatic discharge voltage (Human Body model)(3)
–2000
2000
V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), and the European
directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
2. Avoid applying VPPH to the W/VPP pin during Bulk Erase.
3. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
52/68
M25PX32
DC and AC parameters
10
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 13. Operating conditions
Symbol
Vcc
Parameter
Min
2.7
Typ
Max
3.6
Unit
Supply Voltage
V
Vphh
Supply Voltage on Vpp
8.5
-40
-40
9.5
85
V
Ambient operating temperature (device grade 6)
Ambient operating temperature (device grade 3)
tA
C
125
Table 14. Data Retention and Endurance
Parameter
Condition
Min.
100000
Max.
Unit
Program/Erase
Cycles
Grade 3, Autograde 6,
Grade 6
Cycles per Sector
Data Retention
at 55°C
20
years
Table 15. AC measurement conditions
Symbol
Parameter
Min
Max
Unit
CL
Load capacitance
30
pF
ns
V
Input rise and fall times
5
Input pulse voltages
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
VCC / 2
Input timing reference voltages
Output timing reference voltages
V
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 30. AC measurement I/O waveform
Input levels
Input and output
timing reference levels
0.8V
CC
0.7V
0.5V
0.3V
CC
CC
CC
0.2V
CC
AI07455
53/68
DC and AC parameters
Table 16. Capacitance(1)
M25PX32
Unit
Symbol
CIN/OUT Input/output capacitance (DQ0/DQ1)
CIN Input capacitance (other pins)
Parameter
Test condition
Min
Max
VOUT = 0 V
VIN = 0 V
8
6
pF
pF
1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 33 MHz.
Table 17. DC characteristics
Test condition (in addition
Symbol
Parameter
Min
Max
Unit
to those in Table 13)
ILI
Input leakage current
Output leakage current
Standby current
± 2
± 2
50
μA
μA
μA
μA
ILO
ICC1
ICC2
S = VCC, VIN = VSS or VCC
S = VCC, VIN = VSS or VCC
Deep Power-down current
10
C = 0.1VCC / 0.9VCC at
75 MHz, DQ1 = open
12
4
mA
mA
mA
Operating current (READ)
C = 0.1VCC / 0.9VCC at
33 MHz, DQ1 = open
ICC3
C = 0.1VCC / 0.9VCC at
75 MHz, DQ1 = open
Operating current (DOFR)
15
Operating current (PP)
Operating current (DIFP)
Operating current (WRSR)
Operating current (SE)
Operating current (BE)
Input low voltage
S = VCC
S = VCC
S = VCC
S = VCC
S = VCC
15
15
15
15
15
mA
mA
mA
mA
mA
ICC4
ICC5
ICC6
ICC7
VIL
– 0.5
0.3VCC
V
V
V
V
VIH
Input high voltage
0.7VCC VCC+0.4
VOL
VOH
Output low voltage
IOL = 1.6 mA
0.4
Output high voltage
IOH = –100 μA
VCC–0.2
54/68
M25PX32
DC and AC parameters
Table 18. AC characteristics
Test conditions specified in Table 13 and Table 15
Symbol
Alt.
Parameter
Min
Typ(1)
Max Unit
Clock frequency for the following
instructions: DOFR, DIFP, FAST_READ,
fC
fC SSE, SE, BE, DP, WREN, WRDI, RDID,
RDSR, WRSR, ROTP, PP, POTP, WRLR,
RDLR, RDP
D.C.
75
33
MHz
fR
Clock frequency for READ instructions
tCLH Clock High time
D.C.
6
MHz
ns
(2)
tCH
(2)
tCL
tCLL Clock Low time
6
ns
(3)
tCLCH
Clock rise time(4) (peak to peak)
Clock fall time(4) (peak to peak)
tCSS S active setup time (relative to C)
S not active hold time (relative to C)
tDSU Data In setup time
0.1
0.1
5
V/ns
V/ns
ns
(3)
tCHCL
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
5
ns
2
ns
tDH Data In hold time
5
ns
S active hold time (relative to C)
S not active setup time (relative to C)
tCSH S deselect time
5
ns
5
ns
80
ns
(3)
tSHQZ
tDIS Output Disable time
8
8
6
ns
Clock Low to Output valid under 30 pF
ns
tCLQV
tV
Clock Low to Output valid under 10 pF
ns
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHO Output hold time
0
5
5
5
5
ns
HOLD setup time (relative to C)
HOLD hold time (relative to C)
HOLD setup time (relative to C)
HOLD hold time (relative to C)
tLZ HOLD to Output Low-Z
tHZ HOLD to Output High-Z
Write Protect setup time
ns
ns
ns
ns
(3)
tHHQX
8
8
ns
(3)
tHLQZ
ns
(5)
tWHSL
20
ns
(5)
tSHWL
Write Protect hold time
100
ns
Enhanced Program supply voltage High
(VPPH) to Chip Select Low
(6)
tVPPHSL
200
ns
(3)
tDP
S High to Deep Power-down mode
S High to Standby mode
3
μs
μs
(3)
tRDP
30
55/68
DC and AC parameters
M25PX32
Table 18. AC characteristics (continued)
Test conditions specified in Table 13 and Table 15
Typ(1)
Symbol Alt.
Parameter
Min
Max Unit
tW
Write Status Register cycle time
Page Program cycle time (256 bytes)
Page Program cycle time (n bytes)
Program OTP cycle time (64 bytes)
Subsector Erase cycle time
1.3
15
ms
ms
0.8
(7)
tPP
int(n/8) × 0.025(8)
5
0.2
70
1
ms
ms
s
tSSE
tSE
150
3
Sector Erase cycle time
tBE
Bulk Erase cycle time
34
80
s
1. Typical values given for TA = 25° C.
2. tCH + tCL must be greater than or equal to 1/ fC.
3. Value guaranteed by characterization, not 100% tested in production.
4. Expressed as a slew-rate.
5. Only applicable as a constraint for a WRSR instruction when SRWD is set at ‘1’.
6. PPH should be kept at a valid level until the program or erase operation has completed and its result
V
(success or failure) is known. Avoid applying VPPH to the W/VPP pin during Bulk Erase.
7. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are
obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤
256).
8. int(A) corresponds to the upper integer part of A. For example, int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
Figure 31. Serial input timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
DQ0
DQ1
High Impedance
AI13728
56/68
M25PX32
DC and AC parameters
Figure 32. Write Protect Setup and Hold timing during WRSR when SRWD=1
W/V
PP
tSHWL
tWHSL
S
C
DQ0
High Impedance
DQ1
AI07439c
Figure 33. Hold timing
S
tHLCH
tCHHH
tCHHL
tHLQZ
tHHCH
C
tHHQX
DQ1
DQ0
HOLD
AI13746
57/68
DC and AC parameters
M25PX32
Figure 34. Output timing
S
C
tCH
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
tCLQX
LSB OUT
DQ1
tQLQH
tQHQL
ADDR.
LSB IN
DQ0
AI13729
Figure 35. VPPH timing
End of command
(identi ed byWIPpolling)
S
C
DQ0
VPPH
VPP
ai13726-b
t VPPHSL
58/68
M25PX32
Package mechanical
11
Package mechanical
In order to meet environmental requirements, Numonyx offers these devices in RoHS
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
Figure 36. VFQFPN8 (MLP8) 8-lead very thin fine pitch dual flat package no lead,
6 × 5 mm, package outline
A
D
aaa C A
R1
D1
B
E
E1
E2
A2
e
b
2x
0.10 C
B
D2
0.10 C
A
θ
L
ddd
C
A
A1 A3
70-ME
1. Drawing is not to scale.
59/68
Package mechanical
M25PX32
Table 19. VFQFPN8 (MLP8) 8-lead very thin fine pitch dual flat package no lead,
6 × 5 mm, package mechanical data
Millimeters
Inches
Min
Symbol
Typ
Min
Max
Typ
Max
A
A1
A2
A3
b
0.85
0.80
0.00
1.00
0.05
0.0335
0.0315
0.0000
0.0394
0.0020
0.65
0.20
0.40
6.00
5.75
3.40
5.00
4.75
4.00
1.27
0.10
0.60
0.0256
0.0079
0.0157
0.2362
0.2264
0.1339
0.1969
0.1870
0.1575
0.0500
0.0039
0.0236
0.35
3.20
0.48
3.60
0.0138
0.1260
0.0189
0.1417
D
D1
D2
E
E1
E2
e
3.80
–
4.30
–
0.1496
–
0.1693
–
R1
L
0.00
0.50
0.0000
0.0197
0.75
12°
0.0295
12°
Θ
aaa
bbb
ddd
0.15
0.10
0.05
0.0059
0.0039
0.0020
60/68
M25PX32
Package mechanical
Figure 37. SO8W 8-lead plastic small outline, 208 mils body width, package outline
A2
A
c
b
CP
e
D
N
1
E E1
A1
k
L
6L_ME
1. Drawing is not to scale.
Table 20. SO8W 8-lead plastic small outline, 208 mils body width, package
mechanical data
Millimeters
Min
Inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
2.50
0.25
2.00
0.51
0.35
0.10
6.05
6.22
8.89
–
0.098
0.010
0.079
0.020
0.014
0.004
0.238
0.245
0.350
–
0.00
1.51
0.35
0.10
0.000
0.059
0.014
0.004
0.40
0.20
0.016
0.008
c
CP
D
E
5.02
7.62
–
0.198
0.300
–
E1
e
1.27
0.050
k
0°
10°
0°
10°
L
0.50
8
0.80
0.020
8
0.031
N
61/68
Package mechanical
M25PX32
Figure 38. SO16 wide - 16-lead plastic small outline, 300 mils body width, package
outline
D
h x 45˚
16
9
C
E
H
1
8
θ
A2
A
A1
L
ddd
B
e
SO-H
1. Drawing is not to scale.
Table 21. SO16 wide - 16-lead plastic small outline, 300 mils body width,
mechanical data
Millimeters
Min
Inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
B
2.35
0.10
0.33
0.23
10.10
7.40
–
2.65
0.30
0.51
0.32
10.50
7.60
–
0.093
0.004
0.013
0.009
0.398
0.291
–
0.104
0.012
0.020
0.013
0.413
0.299
–
C
D
E
e
1.27
0.050
H
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
0.394
0.010
0.016
0°
0.419
0.030
0.050
8°
h
L
θ
ddd
0.10
0.004
62/68
M25PX32
Package mechanical
Figure 39. TBGA, 6x8 mm, 24 ball package outline
63/68
Package mechanical
M25PX32
Table 22. TBGA 6x8 mm 24-ball package dimensions
MIN
NOM
MAX
A
1.20
A1
A2
Øb
D
0.20
0.79
0.40
6.00
4.00
8.00
4.00
1.00
1.00
1.00
2.00
0.35
5.90
0.45
6.10
D1
E
7.90
8.10
E1
eD
eE
FD
FE
MD
ME
n
5
5
24 balls
aaa
bbb
ddd
eee
fff
0.15
0.10
0.10
0.15
0.08
Control unit: mm
64/68
M25PX32
Ordering information
12
Ordering information
Table 23. Ordering information scheme
Example:
M25PX32
–
V MW
3
E
B
A
Device type
M25PX = serial Flash memory, 4-Kbyte and 64-Kbyte
erasable sectors, dual input/output
Device function
32 = 32 Mbit (4 Mb × 8)
Security features(1)
– = no extra security
SO = OTP configurable
ST = OTP configurable + protection at power_up
S = CFD programmed with UID
Operating voltage
V = VCC = 2.7 V to 3.6 V
Package
MW = SO8W (208 mils width)
MF = SO16 (300 mils width)
MP = VFQFPN 6 × 5 mm (MLP8)
ZM = TBGA24 6 x 8 mm
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3
(2) = Automotive temperature range, –40 to 125 °C.
Device tested with high reliability certified flow.
Option
E = Standard packing RoHS compliant
F = Tape and reel packing RoHS compliant
Lithography
B = 110nm, Fab.2 Diffusion Plant
blank = 110 nm
Automotive Grade
A
(2) = Automotive –40 to 125 °C Part.
Device tested with high reliability certified flow.
blank = standard –40 to 85 °C device
1. Secure options are available upon customer request.
65/68
Ordering information
M25PX32
2. Numonyx strongly recommends the use of the Automotive Grade devices(AutoGrade 6 and Grade 3) for
use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality
note QNEE9801.
Note:
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest Numonyx Sales Office.
66/68
M25PX32
Revision history
13
Revision history
Table 24. Document revision history
Date
Revision
Changes
19-Dec-2006
0.1
Initial release.
Document status promoted from Target Specification to Preliminary Data.
Added the SO16 (MF) package.
31-Jul-2007
1
Added specific hardware protection (see Section 4.7.2: Specific hardware and
software protection).
Modified the RDID instruction (see Section 6.3: Read Identification (RDID)).
Updated the typical value for the Deep Power-down current (ICC2).
20-Aug-2007
2
Modified Lock Registers’ configuration in Section 7: Power-up and power-down.
Added security features reference to Chapter 1: Description and added the
security features part number ordering information in Table 23.
05-Sep-2007
12-Sep-2007
3
4
Document status promoted from Preliminary Data to full Datasheet.
Section 6.3: Read Identification (RDID) and Figure 8: Block diagram updated.
Modified the minimum value for tSHSL in Table 18: AC characteristics.
Minor text changes.
16-Nov-2007
13-Dec-2007
24-Sept 2008
5
6
7
Applied Numonyx branding.
Corrected bulk erase specifications on the cover page;
Added the following information regarding bulk erase: Avoid applying VPPH to
the W/VPP pin during Bulk Erase.
04-February-2009
16-February-2009
6-March 2009
8
9
Added the TBGA package and accompanying informaiton.
Added Notes to the TBGA package and deleted a blank page.
Added “Automotive Certified Parts” information.
10
67/68
M25PX32
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2009, Numonyx, B.V., All Rights Reserved.
68/68
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